Pirama Arumuga Nainar | 494f645 | 2021-12-02 10:42:14 -0800 | [diff] [blame] | 1 | //===----------------------------------------------------------------------===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // Automatically generated file, do not edit! |
| 9 | //===----------------------------------------------------------------------===// |
| 10 | |
| 11 | |
| 12 | |
| 13 | #ifndef _HVX_HEXAGON_PROTOS_H_ |
| 14 | #define _HVX_HEXAGON_PROTOS_H_ 1 |
| 15 | |
| 16 | #ifdef __HVX__ |
| 17 | #if __HVX_LENGTH__ == 128 |
| 18 | #define __BUILTIN_VECTOR_WRAP(a) a ## _128B |
| 19 | #else |
| 20 | #define __BUILTIN_VECTOR_WRAP(a) a |
| 21 | #endif |
| 22 | |
| 23 | #if __HVX_ARCH__ >= 60 |
| 24 | /* ========================================================================== |
| 25 | Assembly Syntax: Rd32=vextract(Vu32,Rs32) |
| 26 | C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs) |
| 27 | Instruction Type: LD |
| 28 | Execution Slots: SLOT0 |
| 29 | ========================================================================== */ |
| 30 | |
| 31 | #define Q6_R_vextract_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw) |
| 32 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 33 | |
| 34 | #if __HVX_ARCH__ >= 60 |
| 35 | /* ========================================================================== |
| 36 | Assembly Syntax: Vd32=hi(Vss32) |
| 37 | C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss) |
| 38 | Instruction Type: CVI_VA |
| 39 | Execution Slots: SLOT0123 |
| 40 | ========================================================================== */ |
| 41 | |
| 42 | #define Q6_V_hi_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi) |
| 43 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 44 | |
| 45 | #if __HVX_ARCH__ >= 60 |
| 46 | /* ========================================================================== |
| 47 | Assembly Syntax: Vd32=lo(Vss32) |
| 48 | C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss) |
| 49 | Instruction Type: CVI_VA |
| 50 | Execution Slots: SLOT0123 |
| 51 | ========================================================================== */ |
| 52 | |
| 53 | #define Q6_V_lo_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo) |
| 54 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 55 | |
| 56 | #if __HVX_ARCH__ >= 60 |
| 57 | /* ========================================================================== |
| 58 | Assembly Syntax: Vd32=vsplat(Rt32) |
| 59 | C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt) |
| 60 | Instruction Type: CVI_VX_LATE |
| 61 | Execution Slots: SLOT23 |
| 62 | ========================================================================== */ |
| 63 | |
| 64 | #define Q6_V_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw) |
| 65 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 66 | |
| 67 | #if __HVX_ARCH__ >= 60 |
| 68 | /* ========================================================================== |
| 69 | Assembly Syntax: Qd4=and(Qs4,Qt4) |
| 70 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 71 | Instruction Type: CVI_VA_DV |
| 72 | Execution Slots: SLOT0123 |
| 73 | ========================================================================== */ |
| 74 | |
| 75 | #define Q6_Q_and_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and) |
| 76 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 77 | |
| 78 | #if __HVX_ARCH__ >= 60 |
| 79 | /* ========================================================================== |
| 80 | Assembly Syntax: Qd4=and(Qs4,!Qt4) |
| 81 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 82 | Instruction Type: CVI_VA_DV |
| 83 | Execution Slots: SLOT0123 |
| 84 | ========================================================================== */ |
| 85 | |
| 86 | #define Q6_Q_and_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n) |
| 87 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 88 | |
| 89 | #if __HVX_ARCH__ >= 60 |
| 90 | /* ========================================================================== |
| 91 | Assembly Syntax: Qd4=not(Qs4) |
| 92 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs) |
| 93 | Instruction Type: CVI_VA |
| 94 | Execution Slots: SLOT0123 |
| 95 | ========================================================================== */ |
| 96 | |
| 97 | #define Q6_Q_not_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not) |
| 98 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 99 | |
| 100 | #if __HVX_ARCH__ >= 60 |
| 101 | /* ========================================================================== |
| 102 | Assembly Syntax: Qd4=or(Qs4,Qt4) |
| 103 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 104 | Instruction Type: CVI_VA_DV |
| 105 | Execution Slots: SLOT0123 |
| 106 | ========================================================================== */ |
| 107 | |
| 108 | #define Q6_Q_or_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or) |
| 109 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 110 | |
| 111 | #if __HVX_ARCH__ >= 60 |
| 112 | /* ========================================================================== |
| 113 | Assembly Syntax: Qd4=or(Qs4,!Qt4) |
| 114 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 115 | Instruction Type: CVI_VA_DV |
| 116 | Execution Slots: SLOT0123 |
| 117 | ========================================================================== */ |
| 118 | |
| 119 | #define Q6_Q_or_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n) |
| 120 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 121 | |
| 122 | #if __HVX_ARCH__ >= 60 |
| 123 | /* ========================================================================== |
| 124 | Assembly Syntax: Qd4=vsetq(Rt32) |
| 125 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt) |
| 126 | Instruction Type: CVI_VP |
| 127 | Execution Slots: SLOT0123 |
| 128 | ========================================================================== */ |
| 129 | |
| 130 | #define Q6_Q_vsetq_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2) |
| 131 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 132 | |
| 133 | #if __HVX_ARCH__ >= 60 |
| 134 | /* ========================================================================== |
| 135 | Assembly Syntax: Qd4=xor(Qs4,Qt4) |
| 136 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 137 | Instruction Type: CVI_VA_DV |
| 138 | Execution Slots: SLOT0123 |
| 139 | ========================================================================== */ |
| 140 | |
| 141 | #define Q6_Q_xor_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor) |
| 142 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 143 | |
| 144 | #if __HVX_ARCH__ >= 60 |
| 145 | /* ========================================================================== |
| 146 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4)=Vs32 |
| 147 | C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 148 | Instruction Type: CVI_VM_ST |
| 149 | Execution Slots: SLOT0 |
| 150 | ========================================================================== */ |
| 151 | |
| 152 | #define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai) |
| 153 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 154 | |
| 155 | #if __HVX_ARCH__ >= 60 |
| 156 | /* ========================================================================== |
| 157 | Assembly Syntax: if (!Qv4) vmem(Rt32+#s4):nt=Vs32 |
| 158 | C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 159 | Instruction Type: CVI_VM_ST |
| 160 | Execution Slots: SLOT0 |
| 161 | ========================================================================== */ |
| 162 | |
| 163 | #define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai) |
| 164 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 165 | |
| 166 | #if __HVX_ARCH__ >= 60 |
| 167 | /* ========================================================================== |
| 168 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4):nt=Vs32 |
| 169 | C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 170 | Instruction Type: CVI_VM_ST |
| 171 | Execution Slots: SLOT0 |
| 172 | ========================================================================== */ |
| 173 | |
| 174 | #define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai) |
| 175 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 176 | |
| 177 | #if __HVX_ARCH__ >= 60 |
| 178 | /* ========================================================================== |
| 179 | Assembly Syntax: if (Qv4) vmem(Rt32+#s4)=Vs32 |
| 180 | C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs) |
| 181 | Instruction Type: CVI_VM_ST |
| 182 | Execution Slots: SLOT0 |
| 183 | ========================================================================== */ |
| 184 | |
| 185 | #define Q6_vmem_QRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai) |
| 186 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 187 | |
| 188 | #if __HVX_ARCH__ >= 60 |
| 189 | /* ========================================================================== |
| 190 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.h,Vv32.h) |
| 191 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 192 | Instruction Type: CVI_VX |
| 193 | Execution Slots: SLOT23 |
| 194 | ========================================================================== */ |
| 195 | |
| 196 | #define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh) |
| 197 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 198 | |
| 199 | #if __HVX_ARCH__ >= 60 |
| 200 | /* ========================================================================== |
| 201 | Assembly Syntax: Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub) |
| 202 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 203 | Instruction Type: CVI_VX |
| 204 | Execution Slots: SLOT23 |
| 205 | ========================================================================== */ |
| 206 | |
| 207 | #define Q6_Vub_vabsdiff_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub) |
| 208 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 209 | |
| 210 | #if __HVX_ARCH__ >= 60 |
| 211 | /* ========================================================================== |
| 212 | Assembly Syntax: Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh) |
| 213 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 214 | Instruction Type: CVI_VX |
| 215 | Execution Slots: SLOT23 |
| 216 | ========================================================================== */ |
| 217 | |
| 218 | #define Q6_Vuh_vabsdiff_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh) |
| 219 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 220 | |
| 221 | #if __HVX_ARCH__ >= 60 |
| 222 | /* ========================================================================== |
| 223 | Assembly Syntax: Vd32.uw=vabsdiff(Vu32.w,Vv32.w) |
| 224 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 225 | Instruction Type: CVI_VX |
| 226 | Execution Slots: SLOT23 |
| 227 | ========================================================================== */ |
| 228 | |
| 229 | #define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw) |
| 230 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 231 | |
| 232 | #if __HVX_ARCH__ >= 60 |
| 233 | /* ========================================================================== |
| 234 | Assembly Syntax: Vd32.h=vabs(Vu32.h) |
| 235 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu) |
| 236 | Instruction Type: CVI_VA |
| 237 | Execution Slots: SLOT0123 |
| 238 | ========================================================================== */ |
| 239 | |
| 240 | #define Q6_Vh_vabs_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh) |
| 241 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 242 | |
| 243 | #if __HVX_ARCH__ >= 60 |
| 244 | /* ========================================================================== |
| 245 | Assembly Syntax: Vd32.h=vabs(Vu32.h):sat |
| 246 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu) |
| 247 | Instruction Type: CVI_VA |
| 248 | Execution Slots: SLOT0123 |
| 249 | ========================================================================== */ |
| 250 | |
| 251 | #define Q6_Vh_vabs_Vh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat) |
| 252 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 253 | |
| 254 | #if __HVX_ARCH__ >= 60 |
| 255 | /* ========================================================================== |
| 256 | Assembly Syntax: Vd32.w=vabs(Vu32.w) |
| 257 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu) |
| 258 | Instruction Type: CVI_VA |
| 259 | Execution Slots: SLOT0123 |
| 260 | ========================================================================== */ |
| 261 | |
| 262 | #define Q6_Vw_vabs_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw) |
| 263 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 264 | |
| 265 | #if __HVX_ARCH__ >= 60 |
| 266 | /* ========================================================================== |
| 267 | Assembly Syntax: Vd32.w=vabs(Vu32.w):sat |
| 268 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu) |
| 269 | Instruction Type: CVI_VA |
| 270 | Execution Slots: SLOT0123 |
| 271 | ========================================================================== */ |
| 272 | |
| 273 | #define Q6_Vw_vabs_Vw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat) |
| 274 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 275 | |
| 276 | #if __HVX_ARCH__ >= 60 |
| 277 | /* ========================================================================== |
| 278 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b) |
| 279 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 280 | Instruction Type: CVI_VA |
| 281 | Execution Slots: SLOT0123 |
| 282 | ========================================================================== */ |
| 283 | |
| 284 | #define Q6_Vb_vadd_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb) |
| 285 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 286 | |
| 287 | #if __HVX_ARCH__ >= 60 |
| 288 | /* ========================================================================== |
| 289 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b) |
| 290 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 291 | Instruction Type: CVI_VA_DV |
| 292 | Execution Slots: SLOT0123 |
| 293 | ========================================================================== */ |
| 294 | |
| 295 | #define Q6_Wb_vadd_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv) |
| 296 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 297 | |
| 298 | #if __HVX_ARCH__ >= 60 |
| 299 | /* ========================================================================== |
| 300 | Assembly Syntax: if (!Qv4) Vx32.b+=Vu32.b |
| 301 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 302 | Instruction Type: CVI_VA |
| 303 | Execution Slots: SLOT0123 |
| 304 | ========================================================================== */ |
| 305 | |
| 306 | #define Q6_Vb_condacc_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq) |
| 307 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 308 | |
| 309 | #if __HVX_ARCH__ >= 60 |
| 310 | /* ========================================================================== |
| 311 | Assembly Syntax: if (Qv4) Vx32.b+=Vu32.b |
| 312 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 313 | Instruction Type: CVI_VA |
| 314 | Execution Slots: SLOT0123 |
| 315 | ========================================================================== */ |
| 316 | |
| 317 | #define Q6_Vb_condacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq) |
| 318 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 319 | |
| 320 | #if __HVX_ARCH__ >= 60 |
| 321 | /* ========================================================================== |
| 322 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h) |
| 323 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 324 | Instruction Type: CVI_VA |
| 325 | Execution Slots: SLOT0123 |
| 326 | ========================================================================== */ |
| 327 | |
| 328 | #define Q6_Vh_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh) |
| 329 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 330 | |
| 331 | #if __HVX_ARCH__ >= 60 |
| 332 | /* ========================================================================== |
| 333 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h) |
| 334 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 335 | Instruction Type: CVI_VA_DV |
| 336 | Execution Slots: SLOT0123 |
| 337 | ========================================================================== */ |
| 338 | |
| 339 | #define Q6_Wh_vadd_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv) |
| 340 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 341 | |
| 342 | #if __HVX_ARCH__ >= 60 |
| 343 | /* ========================================================================== |
| 344 | Assembly Syntax: if (!Qv4) Vx32.h+=Vu32.h |
| 345 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 346 | Instruction Type: CVI_VA |
| 347 | Execution Slots: SLOT0123 |
| 348 | ========================================================================== */ |
| 349 | |
| 350 | #define Q6_Vh_condacc_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq) |
| 351 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 352 | |
| 353 | #if __HVX_ARCH__ >= 60 |
| 354 | /* ========================================================================== |
| 355 | Assembly Syntax: if (Qv4) Vx32.h+=Vu32.h |
| 356 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 357 | Instruction Type: CVI_VA |
| 358 | Execution Slots: SLOT0123 |
| 359 | ========================================================================== */ |
| 360 | |
| 361 | #define Q6_Vh_condacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq) |
| 362 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 363 | |
| 364 | #if __HVX_ARCH__ >= 60 |
| 365 | /* ========================================================================== |
| 366 | Assembly Syntax: Vd32.h=vadd(Vu32.h,Vv32.h):sat |
| 367 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 368 | Instruction Type: CVI_VA |
| 369 | Execution Slots: SLOT0123 |
| 370 | ========================================================================== */ |
| 371 | |
| 372 | #define Q6_Vh_vadd_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat) |
| 373 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 374 | |
| 375 | #if __HVX_ARCH__ >= 60 |
| 376 | /* ========================================================================== |
| 377 | Assembly Syntax: Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat |
| 378 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 379 | Instruction Type: CVI_VA_DV |
| 380 | Execution Slots: SLOT0123 |
| 381 | ========================================================================== */ |
| 382 | |
| 383 | #define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv) |
| 384 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 385 | |
| 386 | #if __HVX_ARCH__ >= 60 |
| 387 | /* ========================================================================== |
| 388 | Assembly Syntax: Vdd32.w=vadd(Vu32.h,Vv32.h) |
| 389 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 390 | Instruction Type: CVI_VX_DV |
| 391 | Execution Slots: SLOT23 |
| 392 | ========================================================================== */ |
| 393 | |
| 394 | #define Q6_Ww_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw) |
| 395 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 396 | |
| 397 | #if __HVX_ARCH__ >= 60 |
| 398 | /* ========================================================================== |
| 399 | Assembly Syntax: Vdd32.h=vadd(Vu32.ub,Vv32.ub) |
| 400 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 401 | Instruction Type: CVI_VX_DV |
| 402 | Execution Slots: SLOT23 |
| 403 | ========================================================================== */ |
| 404 | |
| 405 | #define Q6_Wh_vadd_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh) |
| 406 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 407 | |
| 408 | #if __HVX_ARCH__ >= 60 |
| 409 | /* ========================================================================== |
| 410 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat |
| 411 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 412 | Instruction Type: CVI_VA |
| 413 | Execution Slots: SLOT0123 |
| 414 | ========================================================================== */ |
| 415 | |
| 416 | #define Q6_Vub_vadd_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat) |
| 417 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 418 | |
| 419 | #if __HVX_ARCH__ >= 60 |
| 420 | /* ========================================================================== |
| 421 | Assembly Syntax: Vdd32.ub=vadd(Vuu32.ub,Vvv32.ub):sat |
| 422 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vadd_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 423 | Instruction Type: CVI_VA_DV |
| 424 | Execution Slots: SLOT0123 |
| 425 | ========================================================================== */ |
| 426 | |
| 427 | #define Q6_Wub_vadd_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv) |
| 428 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 429 | |
| 430 | #if __HVX_ARCH__ >= 60 |
| 431 | /* ========================================================================== |
| 432 | Assembly Syntax: Vd32.uh=vadd(Vu32.uh,Vv32.uh):sat |
| 433 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vadd_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 434 | Instruction Type: CVI_VA |
| 435 | Execution Slots: SLOT0123 |
| 436 | ========================================================================== */ |
| 437 | |
| 438 | #define Q6_Vuh_vadd_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat) |
| 439 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 440 | |
| 441 | #if __HVX_ARCH__ >= 60 |
| 442 | /* ========================================================================== |
| 443 | Assembly Syntax: Vdd32.uh=vadd(Vuu32.uh,Vvv32.uh):sat |
| 444 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vadd_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 445 | Instruction Type: CVI_VA_DV |
| 446 | Execution Slots: SLOT0123 |
| 447 | ========================================================================== */ |
| 448 | |
| 449 | #define Q6_Wuh_vadd_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv) |
| 450 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 451 | |
| 452 | #if __HVX_ARCH__ >= 60 |
| 453 | /* ========================================================================== |
| 454 | Assembly Syntax: Vdd32.w=vadd(Vu32.uh,Vv32.uh) |
| 455 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 456 | Instruction Type: CVI_VX_DV |
| 457 | Execution Slots: SLOT23 |
| 458 | ========================================================================== */ |
| 459 | |
| 460 | #define Q6_Ww_vadd_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw) |
| 461 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 462 | |
| 463 | #if __HVX_ARCH__ >= 60 |
| 464 | /* ========================================================================== |
| 465 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w) |
| 466 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 467 | Instruction Type: CVI_VA |
| 468 | Execution Slots: SLOT0123 |
| 469 | ========================================================================== */ |
| 470 | |
| 471 | #define Q6_Vw_vadd_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw) |
| 472 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 473 | |
| 474 | #if __HVX_ARCH__ >= 60 |
| 475 | /* ========================================================================== |
| 476 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w) |
| 477 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 478 | Instruction Type: CVI_VA_DV |
| 479 | Execution Slots: SLOT0123 |
| 480 | ========================================================================== */ |
| 481 | |
| 482 | #define Q6_Ww_vadd_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv) |
| 483 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 484 | |
| 485 | #if __HVX_ARCH__ >= 60 |
| 486 | /* ========================================================================== |
| 487 | Assembly Syntax: if (!Qv4) Vx32.w+=Vu32.w |
| 488 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 489 | Instruction Type: CVI_VA |
| 490 | Execution Slots: SLOT0123 |
| 491 | ========================================================================== */ |
| 492 | |
| 493 | #define Q6_Vw_condacc_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq) |
| 494 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 495 | |
| 496 | #if __HVX_ARCH__ >= 60 |
| 497 | /* ========================================================================== |
| 498 | Assembly Syntax: if (Qv4) Vx32.w+=Vu32.w |
| 499 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condacc_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 500 | Instruction Type: CVI_VA |
| 501 | Execution Slots: SLOT0123 |
| 502 | ========================================================================== */ |
| 503 | |
| 504 | #define Q6_Vw_condacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq) |
| 505 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 506 | |
| 507 | #if __HVX_ARCH__ >= 60 |
| 508 | /* ========================================================================== |
| 509 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w):sat |
| 510 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 511 | Instruction Type: CVI_VA |
| 512 | Execution Slots: SLOT0123 |
| 513 | ========================================================================== */ |
| 514 | |
| 515 | #define Q6_Vw_vadd_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat) |
| 516 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 517 | |
| 518 | #if __HVX_ARCH__ >= 60 |
| 519 | /* ========================================================================== |
| 520 | Assembly Syntax: Vdd32.w=vadd(Vuu32.w,Vvv32.w):sat |
| 521 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 522 | Instruction Type: CVI_VA_DV |
| 523 | Execution Slots: SLOT0123 |
| 524 | ========================================================================== */ |
| 525 | |
| 526 | #define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv) |
| 527 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 528 | |
| 529 | #if __HVX_ARCH__ >= 60 |
| 530 | /* ========================================================================== |
| 531 | Assembly Syntax: Vd32=valign(Vu32,Vv32,Rt8) |
| 532 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 533 | Instruction Type: CVI_VP |
| 534 | Execution Slots: SLOT0123 |
| 535 | ========================================================================== */ |
| 536 | |
| 537 | #define Q6_V_valign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb) |
| 538 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 539 | |
| 540 | #if __HVX_ARCH__ >= 60 |
| 541 | /* ========================================================================== |
| 542 | Assembly Syntax: Vd32=valign(Vu32,Vv32,#u3) |
| 543 | C Intrinsic Prototype: HVX_Vector Q6_V_valign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 544 | Instruction Type: CVI_VP |
| 545 | Execution Slots: SLOT0123 |
| 546 | ========================================================================== */ |
| 547 | |
| 548 | #define Q6_V_valign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi) |
| 549 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 550 | |
| 551 | #if __HVX_ARCH__ >= 60 |
| 552 | /* ========================================================================== |
| 553 | Assembly Syntax: Vd32=vand(Vu32,Vv32) |
| 554 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 555 | Instruction Type: CVI_VA |
| 556 | Execution Slots: SLOT0123 |
| 557 | ========================================================================== */ |
| 558 | |
| 559 | #define Q6_V_vand_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand) |
| 560 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 561 | |
| 562 | #if __HVX_ARCH__ >= 60 |
| 563 | /* ========================================================================== |
| 564 | Assembly Syntax: Vd32=vand(Qu4,Rt32) |
| 565 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QR(HVX_VectorPred Qu, Word32 Rt) |
| 566 | Instruction Type: CVI_VX_LATE |
| 567 | Execution Slots: SLOT23 |
| 568 | ========================================================================== */ |
| 569 | |
| 570 | #define Q6_V_vand_QR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) |
| 571 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 572 | |
| 573 | #if __HVX_ARCH__ >= 60 |
| 574 | /* ========================================================================== |
| 575 | Assembly Syntax: Vx32|=vand(Qu4,Rt32) |
| 576 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
| 577 | Instruction Type: CVI_VX_LATE |
| 578 | Execution Slots: SLOT23 |
| 579 | ========================================================================== */ |
| 580 | |
| 581 | #define Q6_V_vandor_VQR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc) |
| 582 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 583 | |
| 584 | #if __HVX_ARCH__ >= 60 |
| 585 | /* ========================================================================== |
| 586 | Assembly Syntax: Qd4=vand(Vu32,Rt32) |
| 587 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vand_VR(HVX_Vector Vu, Word32 Rt) |
| 588 | Instruction Type: CVI_VX_LATE |
| 589 | Execution Slots: SLOT23 |
| 590 | ========================================================================== */ |
| 591 | |
| 592 | #define Q6_Q_vand_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt) |
| 593 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 594 | |
| 595 | #if __HVX_ARCH__ >= 60 |
| 596 | /* ========================================================================== |
| 597 | Assembly Syntax: Qx4|=vand(Vu32,Rt32) |
| 598 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vandor_QVR(HVX_VectorPred Qx, HVX_Vector Vu, Word32 Rt) |
| 599 | Instruction Type: CVI_VX_LATE |
| 600 | Execution Slots: SLOT23 |
| 601 | ========================================================================== */ |
| 602 | |
| 603 | #define Q6_Q_vandor_QVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc) |
| 604 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 605 | |
| 606 | #if __HVX_ARCH__ >= 60 |
| 607 | /* ========================================================================== |
| 608 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Rt32) |
| 609 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhR(HVX_Vector Vu, Word32 Rt) |
| 610 | Instruction Type: CVI_VS |
| 611 | Execution Slots: SLOT0123 |
| 612 | ========================================================================== */ |
| 613 | |
| 614 | #define Q6_Vh_vasl_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh) |
| 615 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 616 | |
| 617 | #if __HVX_ARCH__ >= 60 |
| 618 | /* ========================================================================== |
| 619 | Assembly Syntax: Vd32.h=vasl(Vu32.h,Vv32.h) |
| 620 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasl_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 621 | Instruction Type: CVI_VS |
| 622 | Execution Slots: SLOT0123 |
| 623 | ========================================================================== */ |
| 624 | |
| 625 | #define Q6_Vh_vasl_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv) |
| 626 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 627 | |
| 628 | #if __HVX_ARCH__ >= 60 |
| 629 | /* ========================================================================== |
| 630 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Rt32) |
| 631 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwR(HVX_Vector Vu, Word32 Rt) |
| 632 | Instruction Type: CVI_VS |
| 633 | Execution Slots: SLOT0123 |
| 634 | ========================================================================== */ |
| 635 | |
| 636 | #define Q6_Vw_vasl_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw) |
| 637 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 638 | |
| 639 | #if __HVX_ARCH__ >= 60 |
| 640 | /* ========================================================================== |
| 641 | Assembly Syntax: Vx32.w+=vasl(Vu32.w,Rt32) |
| 642 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vaslacc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 643 | Instruction Type: CVI_VS |
| 644 | Execution Slots: SLOT0123 |
| 645 | ========================================================================== */ |
| 646 | |
| 647 | #define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc) |
| 648 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 649 | |
| 650 | #if __HVX_ARCH__ >= 60 |
| 651 | /* ========================================================================== |
| 652 | Assembly Syntax: Vd32.w=vasl(Vu32.w,Vv32.w) |
| 653 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasl_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 654 | Instruction Type: CVI_VS |
| 655 | Execution Slots: SLOT0123 |
| 656 | ========================================================================== */ |
| 657 | |
| 658 | #define Q6_Vw_vasl_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv) |
| 659 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 660 | |
| 661 | #if __HVX_ARCH__ >= 60 |
| 662 | /* ========================================================================== |
| 663 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Rt32) |
| 664 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhR(HVX_Vector Vu, Word32 Rt) |
| 665 | Instruction Type: CVI_VS |
| 666 | Execution Slots: SLOT0123 |
| 667 | ========================================================================== */ |
| 668 | |
| 669 | #define Q6_Vh_vasr_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh) |
| 670 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 671 | |
| 672 | #if __HVX_ARCH__ >= 60 |
| 673 | /* ========================================================================== |
| 674 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
| 675 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 676 | Instruction Type: CVI_VS |
| 677 | Execution Slots: SLOT0123 |
| 678 | ========================================================================== */ |
| 679 | |
| 680 | #define Q6_Vb_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat) |
| 681 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 682 | |
| 683 | #if __HVX_ARCH__ >= 60 |
| 684 | /* ========================================================================== |
| 685 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):rnd:sat |
| 686 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 687 | Instruction Type: CVI_VS |
| 688 | Execution Slots: SLOT0123 |
| 689 | ========================================================================== */ |
| 690 | |
| 691 | #define Q6_Vub_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat) |
| 692 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 693 | |
| 694 | #if __HVX_ARCH__ >= 60 |
| 695 | /* ========================================================================== |
| 696 | Assembly Syntax: Vd32.ub=vasr(Vu32.h,Vv32.h,Rt8):sat |
| 697 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 698 | Instruction Type: CVI_VS |
| 699 | Execution Slots: SLOT0123 |
| 700 | ========================================================================== */ |
| 701 | |
| 702 | #define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat) |
| 703 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 704 | |
| 705 | #if __HVX_ARCH__ >= 60 |
| 706 | /* ========================================================================== |
| 707 | Assembly Syntax: Vd32.h=vasr(Vu32.h,Vv32.h) |
| 708 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 709 | Instruction Type: CVI_VS |
| 710 | Execution Slots: SLOT0123 |
| 711 | ========================================================================== */ |
| 712 | |
| 713 | #define Q6_Vh_vasr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv) |
| 714 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 715 | |
| 716 | #if __HVX_ARCH__ >= 60 |
| 717 | /* ========================================================================== |
| 718 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Rt32) |
| 719 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwR(HVX_Vector Vu, Word32 Rt) |
| 720 | Instruction Type: CVI_VS |
| 721 | Execution Slots: SLOT0123 |
| 722 | ========================================================================== */ |
| 723 | |
| 724 | #define Q6_Vw_vasr_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw) |
| 725 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 726 | |
| 727 | #if __HVX_ARCH__ >= 60 |
| 728 | /* ========================================================================== |
| 729 | Assembly Syntax: Vx32.w+=vasr(Vu32.w,Rt32) |
| 730 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasracc_VwVwR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 731 | Instruction Type: CVI_VS |
| 732 | Execution Slots: SLOT0123 |
| 733 | ========================================================================== */ |
| 734 | |
| 735 | #define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc) |
| 736 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 737 | |
| 738 | #if __HVX_ARCH__ >= 60 |
| 739 | /* ========================================================================== |
| 740 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8) |
| 741 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 742 | Instruction Type: CVI_VS |
| 743 | Execution Slots: SLOT0123 |
| 744 | ========================================================================== */ |
| 745 | |
| 746 | #define Q6_Vh_vasr_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh) |
| 747 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 748 | |
| 749 | #if __HVX_ARCH__ >= 60 |
| 750 | /* ========================================================================== |
| 751 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
| 752 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 753 | Instruction Type: CVI_VS |
| 754 | Execution Slots: SLOT0123 |
| 755 | ========================================================================== */ |
| 756 | |
| 757 | #define Q6_Vh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat) |
| 758 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 759 | |
| 760 | #if __HVX_ARCH__ >= 60 |
| 761 | /* ========================================================================== |
| 762 | Assembly Syntax: Vd32.h=vasr(Vu32.w,Vv32.w,Rt8):sat |
| 763 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 764 | Instruction Type: CVI_VS |
| 765 | Execution Slots: SLOT0123 |
| 766 | ========================================================================== */ |
| 767 | |
| 768 | #define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat) |
| 769 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 770 | |
| 771 | #if __HVX_ARCH__ >= 60 |
| 772 | /* ========================================================================== |
| 773 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):sat |
| 774 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 775 | Instruction Type: CVI_VS |
| 776 | Execution Slots: SLOT0123 |
| 777 | ========================================================================== */ |
| 778 | |
| 779 | #define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat) |
| 780 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 781 | |
| 782 | #if __HVX_ARCH__ >= 60 |
| 783 | /* ========================================================================== |
| 784 | Assembly Syntax: Vd32.w=vasr(Vu32.w,Vv32.w) |
| 785 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vasr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 786 | Instruction Type: CVI_VS |
| 787 | Execution Slots: SLOT0123 |
| 788 | ========================================================================== */ |
| 789 | |
| 790 | #define Q6_Vw_vasr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv) |
| 791 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 792 | |
| 793 | #if __HVX_ARCH__ >= 60 |
| 794 | /* ========================================================================== |
| 795 | Assembly Syntax: Vd32=Vu32 |
| 796 | C Intrinsic Prototype: HVX_Vector Q6_V_equals_V(HVX_Vector Vu) |
| 797 | Instruction Type: CVI_VA |
| 798 | Execution Slots: SLOT0123 |
| 799 | ========================================================================== */ |
| 800 | |
| 801 | #define Q6_V_equals_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign) |
| 802 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 803 | |
| 804 | #if __HVX_ARCH__ >= 60 |
| 805 | /* ========================================================================== |
| 806 | Assembly Syntax: Vdd32=Vuu32 |
| 807 | C Intrinsic Prototype: HVX_VectorPair Q6_W_equals_W(HVX_VectorPair Vuu) |
| 808 | Instruction Type: CVI_VA_DV |
| 809 | Execution Slots: SLOT0123 |
| 810 | ========================================================================== */ |
| 811 | |
| 812 | #define Q6_W_equals_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp) |
| 813 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 814 | |
| 815 | #if __HVX_ARCH__ >= 60 |
| 816 | /* ========================================================================== |
| 817 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h) |
| 818 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 819 | Instruction Type: CVI_VA |
| 820 | Execution Slots: SLOT0123 |
| 821 | ========================================================================== */ |
| 822 | |
| 823 | #define Q6_Vh_vavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh) |
| 824 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 825 | |
| 826 | #if __HVX_ARCH__ >= 60 |
| 827 | /* ========================================================================== |
| 828 | Assembly Syntax: Vd32.h=vavg(Vu32.h,Vv32.h):rnd |
| 829 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vavg_VhVh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 830 | Instruction Type: CVI_VA |
| 831 | Execution Slots: SLOT0123 |
| 832 | ========================================================================== */ |
| 833 | |
| 834 | #define Q6_Vh_vavg_VhVh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd) |
| 835 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 836 | |
| 837 | #if __HVX_ARCH__ >= 60 |
| 838 | /* ========================================================================== |
| 839 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub) |
| 840 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 841 | Instruction Type: CVI_VA |
| 842 | Execution Slots: SLOT0123 |
| 843 | ========================================================================== */ |
| 844 | |
| 845 | #define Q6_Vub_vavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub) |
| 846 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 847 | |
| 848 | #if __HVX_ARCH__ >= 60 |
| 849 | /* ========================================================================== |
| 850 | Assembly Syntax: Vd32.ub=vavg(Vu32.ub,Vv32.ub):rnd |
| 851 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vavg_VubVub_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 852 | Instruction Type: CVI_VA |
| 853 | Execution Slots: SLOT0123 |
| 854 | ========================================================================== */ |
| 855 | |
| 856 | #define Q6_Vub_vavg_VubVub_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd) |
| 857 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 858 | |
| 859 | #if __HVX_ARCH__ >= 60 |
| 860 | /* ========================================================================== |
| 861 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh) |
| 862 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 863 | Instruction Type: CVI_VA |
| 864 | Execution Slots: SLOT0123 |
| 865 | ========================================================================== */ |
| 866 | |
| 867 | #define Q6_Vuh_vavg_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh) |
| 868 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 869 | |
| 870 | #if __HVX_ARCH__ >= 60 |
| 871 | /* ========================================================================== |
| 872 | Assembly Syntax: Vd32.uh=vavg(Vu32.uh,Vv32.uh):rnd |
| 873 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vavg_VuhVuh_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 874 | Instruction Type: CVI_VA |
| 875 | Execution Slots: SLOT0123 |
| 876 | ========================================================================== */ |
| 877 | |
| 878 | #define Q6_Vuh_vavg_VuhVuh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd) |
| 879 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 880 | |
| 881 | #if __HVX_ARCH__ >= 60 |
| 882 | /* ========================================================================== |
| 883 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w) |
| 884 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 885 | Instruction Type: CVI_VA |
| 886 | Execution Slots: SLOT0123 |
| 887 | ========================================================================== */ |
| 888 | |
| 889 | #define Q6_Vw_vavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw) |
| 890 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 891 | |
| 892 | #if __HVX_ARCH__ >= 60 |
| 893 | /* ========================================================================== |
| 894 | Assembly Syntax: Vd32.w=vavg(Vu32.w,Vv32.w):rnd |
| 895 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vavg_VwVw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 896 | Instruction Type: CVI_VA |
| 897 | Execution Slots: SLOT0123 |
| 898 | ========================================================================== */ |
| 899 | |
| 900 | #define Q6_Vw_vavg_VwVw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd) |
| 901 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 902 | |
| 903 | #if __HVX_ARCH__ >= 60 |
| 904 | /* ========================================================================== |
| 905 | Assembly Syntax: Vd32.uh=vcl0(Vu32.uh) |
| 906 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vcl0_Vuh(HVX_Vector Vu) |
| 907 | Instruction Type: CVI_VS |
| 908 | Execution Slots: SLOT0123 |
| 909 | ========================================================================== */ |
| 910 | |
| 911 | #define Q6_Vuh_vcl0_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h) |
| 912 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 913 | |
| 914 | #if __HVX_ARCH__ >= 60 |
| 915 | /* ========================================================================== |
| 916 | Assembly Syntax: Vd32.uw=vcl0(Vu32.uw) |
| 917 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vcl0_Vuw(HVX_Vector Vu) |
| 918 | Instruction Type: CVI_VS |
| 919 | Execution Slots: SLOT0123 |
| 920 | ========================================================================== */ |
| 921 | |
| 922 | #define Q6_Vuw_vcl0_Vuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w) |
| 923 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 924 | |
| 925 | #if __HVX_ARCH__ >= 60 |
| 926 | /* ========================================================================== |
| 927 | Assembly Syntax: Vdd32=vcombine(Vu32,Vv32) |
| 928 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vcombine_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 929 | Instruction Type: CVI_VA_DV |
| 930 | Execution Slots: SLOT0123 |
| 931 | ========================================================================== */ |
| 932 | |
| 933 | #define Q6_W_vcombine_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine) |
| 934 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 935 | |
| 936 | #if __HVX_ARCH__ >= 60 |
| 937 | /* ========================================================================== |
| 938 | Assembly Syntax: Vd32=#0 |
| 939 | C Intrinsic Prototype: HVX_Vector Q6_V_vzero() |
| 940 | Instruction Type: CVI_VA |
| 941 | Execution Slots: SLOT0123 |
| 942 | ========================================================================== */ |
| 943 | |
| 944 | #define Q6_V_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0) |
| 945 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 946 | |
| 947 | #if __HVX_ARCH__ >= 60 |
| 948 | /* ========================================================================== |
| 949 | Assembly Syntax: Vd32.b=vdeal(Vu32.b) |
| 950 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeal_Vb(HVX_Vector Vu) |
| 951 | Instruction Type: CVI_VP |
| 952 | Execution Slots: SLOT0123 |
| 953 | ========================================================================== */ |
| 954 | |
| 955 | #define Q6_Vb_vdeal_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb) |
| 956 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 957 | |
| 958 | #if __HVX_ARCH__ >= 60 |
| 959 | /* ========================================================================== |
| 960 | Assembly Syntax: Vd32.b=vdeale(Vu32.b,Vv32.b) |
| 961 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vdeale_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 962 | Instruction Type: CVI_VP |
| 963 | Execution Slots: SLOT0123 |
| 964 | ========================================================================== */ |
| 965 | |
| 966 | #define Q6_Vb_vdeale_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w) |
| 967 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 968 | |
| 969 | #if __HVX_ARCH__ >= 60 |
| 970 | /* ========================================================================== |
| 971 | Assembly Syntax: Vd32.h=vdeal(Vu32.h) |
| 972 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdeal_Vh(HVX_Vector Vu) |
| 973 | Instruction Type: CVI_VP |
| 974 | Execution Slots: SLOT0123 |
| 975 | ========================================================================== */ |
| 976 | |
| 977 | #define Q6_Vh_vdeal_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh) |
| 978 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 979 | |
| 980 | #if __HVX_ARCH__ >= 60 |
| 981 | /* ========================================================================== |
| 982 | Assembly Syntax: Vdd32=vdeal(Vu32,Vv32,Rt8) |
| 983 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vdeal_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 984 | Instruction Type: CVI_VP_VS |
| 985 | Execution Slots: SLOT0123 |
| 986 | ========================================================================== */ |
| 987 | |
| 988 | #define Q6_W_vdeal_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd) |
| 989 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 990 | |
| 991 | #if __HVX_ARCH__ >= 60 |
| 992 | /* ========================================================================== |
| 993 | Assembly Syntax: Vd32=vdelta(Vu32,Vv32) |
| 994 | C Intrinsic Prototype: HVX_Vector Q6_V_vdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 995 | Instruction Type: CVI_VP |
| 996 | Execution Slots: SLOT0123 |
| 997 | ========================================================================== */ |
| 998 | |
| 999 | #define Q6_V_vdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta) |
| 1000 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1001 | |
| 1002 | #if __HVX_ARCH__ >= 60 |
| 1003 | /* ========================================================================== |
| 1004 | Assembly Syntax: Vd32.h=vdmpy(Vu32.ub,Rt32.b) |
| 1005 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 1006 | Instruction Type: CVI_VX |
| 1007 | Execution Slots: SLOT23 |
| 1008 | ========================================================================== */ |
| 1009 | |
| 1010 | #define Q6_Vh_vdmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus) |
| 1011 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1012 | |
| 1013 | #if __HVX_ARCH__ >= 60 |
| 1014 | /* ========================================================================== |
| 1015 | Assembly Syntax: Vx32.h+=vdmpy(Vu32.ub,Rt32.b) |
| 1016 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vdmpyacc_VhVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1017 | Instruction Type: CVI_VX |
| 1018 | Execution Slots: SLOT23 |
| 1019 | ========================================================================== */ |
| 1020 | |
| 1021 | #define Q6_Vh_vdmpyacc_VhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc) |
| 1022 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1023 | |
| 1024 | #if __HVX_ARCH__ >= 60 |
| 1025 | /* ========================================================================== |
| 1026 | Assembly Syntax: Vdd32.h=vdmpy(Vuu32.ub,Rt32.b) |
| 1027 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1028 | Instruction Type: CVI_VX_DV |
| 1029 | Execution Slots: SLOT23 |
| 1030 | ========================================================================== */ |
| 1031 | |
| 1032 | #define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv) |
| 1033 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1034 | |
| 1035 | #if __HVX_ARCH__ >= 60 |
| 1036 | /* ========================================================================== |
| 1037 | Assembly Syntax: Vxx32.h+=vdmpy(Vuu32.ub,Rt32.b) |
| 1038 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vdmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1039 | Instruction Type: CVI_VX_DV |
| 1040 | Execution Slots: SLOT23 |
| 1041 | ========================================================================== */ |
| 1042 | |
| 1043 | #define Q6_Wh_vdmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc) |
| 1044 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1045 | |
| 1046 | #if __HVX_ARCH__ >= 60 |
| 1047 | /* ========================================================================== |
| 1048 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.b) |
| 1049 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRb(HVX_Vector Vu, Word32 Rt) |
| 1050 | Instruction Type: CVI_VX |
| 1051 | Execution Slots: SLOT23 |
| 1052 | ========================================================================== */ |
| 1053 | |
| 1054 | #define Q6_Vw_vdmpy_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb) |
| 1055 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1056 | |
| 1057 | #if __HVX_ARCH__ >= 60 |
| 1058 | /* ========================================================================== |
| 1059 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.b) |
| 1060 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1061 | Instruction Type: CVI_VX |
| 1062 | Execution Slots: SLOT23 |
| 1063 | ========================================================================== */ |
| 1064 | |
| 1065 | #define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc) |
| 1066 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1067 | |
| 1068 | #if __HVX_ARCH__ >= 60 |
| 1069 | /* ========================================================================== |
| 1070 | Assembly Syntax: Vdd32.w=vdmpy(Vuu32.h,Rt32.b) |
| 1071 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1072 | Instruction Type: CVI_VX_DV |
| 1073 | Execution Slots: SLOT23 |
| 1074 | ========================================================================== */ |
| 1075 | |
| 1076 | #define Q6_Ww_vdmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv) |
| 1077 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1078 | |
| 1079 | #if __HVX_ARCH__ >= 60 |
| 1080 | /* ========================================================================== |
| 1081 | Assembly Syntax: Vxx32.w+=vdmpy(Vuu32.h,Rt32.b) |
| 1082 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vdmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1083 | Instruction Type: CVI_VX_DV |
| 1084 | Execution Slots: SLOT23 |
| 1085 | ========================================================================== */ |
| 1086 | |
| 1087 | #define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc) |
| 1088 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1089 | |
| 1090 | #if __HVX_ARCH__ >= 60 |
| 1091 | /* ========================================================================== |
| 1092 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.h):sat |
| 1093 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRh_sat(HVX_VectorPair Vuu, Word32 Rt) |
| 1094 | Instruction Type: CVI_VX_DV |
| 1095 | Execution Slots: SLOT23 |
| 1096 | ========================================================================== */ |
| 1097 | |
| 1098 | #define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat) |
| 1099 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1100 | |
| 1101 | #if __HVX_ARCH__ >= 60 |
| 1102 | /* ========================================================================== |
| 1103 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.h):sat |
| 1104 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
| 1105 | Instruction Type: CVI_VX_DV |
| 1106 | Execution Slots: SLOT23 |
| 1107 | ========================================================================== */ |
| 1108 | |
| 1109 | #define Q6_Vw_vdmpyacc_VwWhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc) |
| 1110 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1111 | |
| 1112 | #if __HVX_ARCH__ >= 60 |
| 1113 | /* ========================================================================== |
| 1114 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.h):sat |
| 1115 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRh_sat(HVX_Vector Vu, Word32 Rt) |
| 1116 | Instruction Type: CVI_VX_DV |
| 1117 | Execution Slots: SLOT23 |
| 1118 | ========================================================================== */ |
| 1119 | |
| 1120 | #define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat) |
| 1121 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1122 | |
| 1123 | #if __HVX_ARCH__ >= 60 |
| 1124 | /* ========================================================================== |
| 1125 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.h):sat |
| 1126 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1127 | Instruction Type: CVI_VX_DV |
| 1128 | Execution Slots: SLOT23 |
| 1129 | ========================================================================== */ |
| 1130 | |
| 1131 | #define Q6_Vw_vdmpyacc_VwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc) |
| 1132 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1133 | |
| 1134 | #if __HVX_ARCH__ >= 60 |
| 1135 | /* ========================================================================== |
| 1136 | Assembly Syntax: Vd32.w=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
| 1137 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_WhRuh_sat(HVX_VectorPair Vuu, Word32 Rt) |
| 1138 | Instruction Type: CVI_VX_DV |
| 1139 | Execution Slots: SLOT23 |
| 1140 | ========================================================================== */ |
| 1141 | |
| 1142 | #define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat) |
| 1143 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1144 | |
| 1145 | #if __HVX_ARCH__ >= 60 |
| 1146 | /* ========================================================================== |
| 1147 | Assembly Syntax: Vx32.w+=vdmpy(Vuu32.h,Rt32.uh,#1):sat |
| 1148 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwWhRuh_sat(HVX_Vector Vx, HVX_VectorPair Vuu, Word32 Rt) |
| 1149 | Instruction Type: CVI_VX_DV |
| 1150 | Execution Slots: SLOT23 |
| 1151 | ========================================================================== */ |
| 1152 | |
| 1153 | #define Q6_Vw_vdmpyacc_VwWhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc) |
| 1154 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1155 | |
| 1156 | #if __HVX_ARCH__ >= 60 |
| 1157 | /* ========================================================================== |
| 1158 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Rt32.uh):sat |
| 1159 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhRuh_sat(HVX_Vector Vu, Word32 Rt) |
| 1160 | Instruction Type: CVI_VX_DV |
| 1161 | Execution Slots: SLOT23 |
| 1162 | ========================================================================== */ |
| 1163 | |
| 1164 | #define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat) |
| 1165 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1166 | |
| 1167 | #if __HVX_ARCH__ >= 60 |
| 1168 | /* ========================================================================== |
| 1169 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Rt32.uh):sat |
| 1170 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhRuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 1171 | Instruction Type: CVI_VX_DV |
| 1172 | Execution Slots: SLOT23 |
| 1173 | ========================================================================== */ |
| 1174 | |
| 1175 | #define Q6_Vw_vdmpyacc_VwVhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc) |
| 1176 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1177 | |
| 1178 | #if __HVX_ARCH__ >= 60 |
| 1179 | /* ========================================================================== |
| 1180 | Assembly Syntax: Vd32.w=vdmpy(Vu32.h,Vv32.h):sat |
| 1181 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpy_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 1182 | Instruction Type: CVI_VX_DV |
| 1183 | Execution Slots: SLOT23 |
| 1184 | ========================================================================== */ |
| 1185 | |
| 1186 | #define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat) |
| 1187 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1188 | |
| 1189 | #if __HVX_ARCH__ >= 60 |
| 1190 | /* ========================================================================== |
| 1191 | Assembly Syntax: Vx32.w+=vdmpy(Vu32.h,Vv32.h):sat |
| 1192 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vdmpyacc_VwVhVh_sat(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 1193 | Instruction Type: CVI_VX_DV |
| 1194 | Execution Slots: SLOT23 |
| 1195 | ========================================================================== */ |
| 1196 | |
| 1197 | #define Q6_Vw_vdmpyacc_VwVhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc) |
| 1198 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1199 | |
| 1200 | #if __HVX_ARCH__ >= 60 |
| 1201 | /* ========================================================================== |
| 1202 | Assembly Syntax: Vdd32.uw=vdsad(Vuu32.uh,Rt32.uh) |
| 1203 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsad_WuhRuh(HVX_VectorPair Vuu, Word32 Rt) |
| 1204 | Instruction Type: CVI_VX_DV |
| 1205 | Execution Slots: SLOT23 |
| 1206 | ========================================================================== */ |
| 1207 | |
| 1208 | #define Q6_Wuw_vdsad_WuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh) |
| 1209 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1210 | |
| 1211 | #if __HVX_ARCH__ >= 60 |
| 1212 | /* ========================================================================== |
| 1213 | Assembly Syntax: Vxx32.uw+=vdsad(Vuu32.uh,Rt32.uh) |
| 1214 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vdsadacc_WuwWuhRuh(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1215 | Instruction Type: CVI_VX_DV |
| 1216 | Execution Slots: SLOT23 |
| 1217 | ========================================================================== */ |
| 1218 | |
| 1219 | #define Q6_Wuw_vdsadacc_WuwWuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc) |
| 1220 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1221 | |
| 1222 | #if __HVX_ARCH__ >= 60 |
| 1223 | /* ========================================================================== |
| 1224 | Assembly Syntax: Qd4=vcmp.eq(Vu32.b,Vv32.b) |
| 1225 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1226 | Instruction Type: CVI_VA |
| 1227 | Execution Slots: SLOT0123 |
| 1228 | ========================================================================== */ |
| 1229 | |
| 1230 | #define Q6_Q_vcmp_eq_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb) |
| 1231 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1232 | |
| 1233 | #if __HVX_ARCH__ >= 60 |
| 1234 | /* ========================================================================== |
| 1235 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.b,Vv32.b) |
| 1236 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1237 | Instruction Type: CVI_VA |
| 1238 | Execution Slots: SLOT0123 |
| 1239 | ========================================================================== */ |
| 1240 | |
| 1241 | #define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and) |
| 1242 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1243 | |
| 1244 | #if __HVX_ARCH__ >= 60 |
| 1245 | /* ========================================================================== |
| 1246 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.b,Vv32.b) |
| 1247 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1248 | Instruction Type: CVI_VA |
| 1249 | Execution Slots: SLOT0123 |
| 1250 | ========================================================================== */ |
| 1251 | |
| 1252 | #define Q6_Q_vcmp_eqor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or) |
| 1253 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1254 | |
| 1255 | #if __HVX_ARCH__ >= 60 |
| 1256 | /* ========================================================================== |
| 1257 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.b,Vv32.b) |
| 1258 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1259 | Instruction Type: CVI_VA |
| 1260 | Execution Slots: SLOT0123 |
| 1261 | ========================================================================== */ |
| 1262 | |
| 1263 | #define Q6_Q_vcmp_eqxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor) |
| 1264 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1265 | |
| 1266 | #if __HVX_ARCH__ >= 60 |
| 1267 | /* ========================================================================== |
| 1268 | Assembly Syntax: Qd4=vcmp.eq(Vu32.h,Vv32.h) |
| 1269 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1270 | Instruction Type: CVI_VA |
| 1271 | Execution Slots: SLOT0123 |
| 1272 | ========================================================================== */ |
| 1273 | |
| 1274 | #define Q6_Q_vcmp_eq_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh) |
| 1275 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1276 | |
| 1277 | #if __HVX_ARCH__ >= 60 |
| 1278 | /* ========================================================================== |
| 1279 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.h,Vv32.h) |
| 1280 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1281 | Instruction Type: CVI_VA |
| 1282 | Execution Slots: SLOT0123 |
| 1283 | ========================================================================== */ |
| 1284 | |
| 1285 | #define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and) |
| 1286 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1287 | |
| 1288 | #if __HVX_ARCH__ >= 60 |
| 1289 | /* ========================================================================== |
| 1290 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.h,Vv32.h) |
| 1291 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1292 | Instruction Type: CVI_VA |
| 1293 | Execution Slots: SLOT0123 |
| 1294 | ========================================================================== */ |
| 1295 | |
| 1296 | #define Q6_Q_vcmp_eqor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or) |
| 1297 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1298 | |
| 1299 | #if __HVX_ARCH__ >= 60 |
| 1300 | /* ========================================================================== |
| 1301 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.h,Vv32.h) |
| 1302 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1303 | Instruction Type: CVI_VA |
| 1304 | Execution Slots: SLOT0123 |
| 1305 | ========================================================================== */ |
| 1306 | |
| 1307 | #define Q6_Q_vcmp_eqxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor) |
| 1308 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1309 | |
| 1310 | #if __HVX_ARCH__ >= 60 |
| 1311 | /* ========================================================================== |
| 1312 | Assembly Syntax: Qd4=vcmp.eq(Vu32.w,Vv32.w) |
| 1313 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eq_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1314 | Instruction Type: CVI_VA |
| 1315 | Execution Slots: SLOT0123 |
| 1316 | ========================================================================== */ |
| 1317 | |
| 1318 | #define Q6_Q_vcmp_eq_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw) |
| 1319 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1320 | |
| 1321 | #if __HVX_ARCH__ >= 60 |
| 1322 | /* ========================================================================== |
| 1323 | Assembly Syntax: Qx4&=vcmp.eq(Vu32.w,Vv32.w) |
| 1324 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1325 | Instruction Type: CVI_VA |
| 1326 | Execution Slots: SLOT0123 |
| 1327 | ========================================================================== */ |
| 1328 | |
| 1329 | #define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and) |
| 1330 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1331 | |
| 1332 | #if __HVX_ARCH__ >= 60 |
| 1333 | /* ========================================================================== |
| 1334 | Assembly Syntax: Qx4|=vcmp.eq(Vu32.w,Vv32.w) |
| 1335 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1336 | Instruction Type: CVI_VA |
| 1337 | Execution Slots: SLOT0123 |
| 1338 | ========================================================================== */ |
| 1339 | |
| 1340 | #define Q6_Q_vcmp_eqor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or) |
| 1341 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1342 | |
| 1343 | #if __HVX_ARCH__ >= 60 |
| 1344 | /* ========================================================================== |
| 1345 | Assembly Syntax: Qx4^=vcmp.eq(Vu32.w,Vv32.w) |
| 1346 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_eqxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1347 | Instruction Type: CVI_VA |
| 1348 | Execution Slots: SLOT0123 |
| 1349 | ========================================================================== */ |
| 1350 | |
| 1351 | #define Q6_Q_vcmp_eqxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor) |
| 1352 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1353 | |
| 1354 | #if __HVX_ARCH__ >= 60 |
| 1355 | /* ========================================================================== |
| 1356 | Assembly Syntax: Qd4=vcmp.gt(Vu32.b,Vv32.b) |
| 1357 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1358 | Instruction Type: CVI_VA |
| 1359 | Execution Slots: SLOT0123 |
| 1360 | ========================================================================== */ |
| 1361 | |
| 1362 | #define Q6_Q_vcmp_gt_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb) |
| 1363 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1364 | |
| 1365 | #if __HVX_ARCH__ >= 60 |
| 1366 | /* ========================================================================== |
| 1367 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.b,Vv32.b) |
| 1368 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1369 | Instruction Type: CVI_VA |
| 1370 | Execution Slots: SLOT0123 |
| 1371 | ========================================================================== */ |
| 1372 | |
| 1373 | #define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and) |
| 1374 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1375 | |
| 1376 | #if __HVX_ARCH__ >= 60 |
| 1377 | /* ========================================================================== |
| 1378 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.b,Vv32.b) |
| 1379 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1380 | Instruction Type: CVI_VA |
| 1381 | Execution Slots: SLOT0123 |
| 1382 | ========================================================================== */ |
| 1383 | |
| 1384 | #define Q6_Q_vcmp_gtor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or) |
| 1385 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1386 | |
| 1387 | #if __HVX_ARCH__ >= 60 |
| 1388 | /* ========================================================================== |
| 1389 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.b,Vv32.b) |
| 1390 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVbVb(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1391 | Instruction Type: CVI_VA |
| 1392 | Execution Slots: SLOT0123 |
| 1393 | ========================================================================== */ |
| 1394 | |
| 1395 | #define Q6_Q_vcmp_gtxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor) |
| 1396 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1397 | |
| 1398 | #if __HVX_ARCH__ >= 60 |
| 1399 | /* ========================================================================== |
| 1400 | Assembly Syntax: Qd4=vcmp.gt(Vu32.h,Vv32.h) |
| 1401 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1402 | Instruction Type: CVI_VA |
| 1403 | Execution Slots: SLOT0123 |
| 1404 | ========================================================================== */ |
| 1405 | |
| 1406 | #define Q6_Q_vcmp_gt_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth) |
| 1407 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1408 | |
| 1409 | #if __HVX_ARCH__ >= 60 |
| 1410 | /* ========================================================================== |
| 1411 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.h,Vv32.h) |
| 1412 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1413 | Instruction Type: CVI_VA |
| 1414 | Execution Slots: SLOT0123 |
| 1415 | ========================================================================== */ |
| 1416 | |
| 1417 | #define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and) |
| 1418 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1419 | |
| 1420 | #if __HVX_ARCH__ >= 60 |
| 1421 | /* ========================================================================== |
| 1422 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.h,Vv32.h) |
| 1423 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1424 | Instruction Type: CVI_VA |
| 1425 | Execution Slots: SLOT0123 |
| 1426 | ========================================================================== */ |
| 1427 | |
| 1428 | #define Q6_Q_vcmp_gtor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or) |
| 1429 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1430 | |
| 1431 | #if __HVX_ARCH__ >= 60 |
| 1432 | /* ========================================================================== |
| 1433 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.h,Vv32.h) |
| 1434 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVhVh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1435 | Instruction Type: CVI_VA |
| 1436 | Execution Slots: SLOT0123 |
| 1437 | ========================================================================== */ |
| 1438 | |
| 1439 | #define Q6_Q_vcmp_gtxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor) |
| 1440 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1441 | |
| 1442 | #if __HVX_ARCH__ >= 60 |
| 1443 | /* ========================================================================== |
| 1444 | Assembly Syntax: Qd4=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1445 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1446 | Instruction Type: CVI_VA |
| 1447 | Execution Slots: SLOT0123 |
| 1448 | ========================================================================== */ |
| 1449 | |
| 1450 | #define Q6_Q_vcmp_gt_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub) |
| 1451 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1452 | |
| 1453 | #if __HVX_ARCH__ >= 60 |
| 1454 | /* ========================================================================== |
| 1455 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1456 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1457 | Instruction Type: CVI_VA |
| 1458 | Execution Slots: SLOT0123 |
| 1459 | ========================================================================== */ |
| 1460 | |
| 1461 | #define Q6_Q_vcmp_gtand_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and) |
| 1462 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1463 | |
| 1464 | #if __HVX_ARCH__ >= 60 |
| 1465 | /* ========================================================================== |
| 1466 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1467 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1468 | Instruction Type: CVI_VA |
| 1469 | Execution Slots: SLOT0123 |
| 1470 | ========================================================================== */ |
| 1471 | |
| 1472 | #define Q6_Q_vcmp_gtor_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or) |
| 1473 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1474 | |
| 1475 | #if __HVX_ARCH__ >= 60 |
| 1476 | /* ========================================================================== |
| 1477 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.ub,Vv32.ub) |
| 1478 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVubVub(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1479 | Instruction Type: CVI_VA |
| 1480 | Execution Slots: SLOT0123 |
| 1481 | ========================================================================== */ |
| 1482 | |
| 1483 | #define Q6_Q_vcmp_gtxacc_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor) |
| 1484 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1485 | |
| 1486 | #if __HVX_ARCH__ >= 60 |
| 1487 | /* ========================================================================== |
| 1488 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1489 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1490 | Instruction Type: CVI_VA |
| 1491 | Execution Slots: SLOT0123 |
| 1492 | ========================================================================== */ |
| 1493 | |
| 1494 | #define Q6_Q_vcmp_gt_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh) |
| 1495 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1496 | |
| 1497 | #if __HVX_ARCH__ >= 60 |
| 1498 | /* ========================================================================== |
| 1499 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1500 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1501 | Instruction Type: CVI_VA |
| 1502 | Execution Slots: SLOT0123 |
| 1503 | ========================================================================== */ |
| 1504 | |
| 1505 | #define Q6_Q_vcmp_gtand_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and) |
| 1506 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1507 | |
| 1508 | #if __HVX_ARCH__ >= 60 |
| 1509 | /* ========================================================================== |
| 1510 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1511 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1512 | Instruction Type: CVI_VA |
| 1513 | Execution Slots: SLOT0123 |
| 1514 | ========================================================================== */ |
| 1515 | |
| 1516 | #define Q6_Q_vcmp_gtor_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or) |
| 1517 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1518 | |
| 1519 | #if __HVX_ARCH__ >= 60 |
| 1520 | /* ========================================================================== |
| 1521 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uh,Vv32.uh) |
| 1522 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuhVuh(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1523 | Instruction Type: CVI_VA |
| 1524 | Execution Slots: SLOT0123 |
| 1525 | ========================================================================== */ |
| 1526 | |
| 1527 | #define Q6_Q_vcmp_gtxacc_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor) |
| 1528 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1529 | |
| 1530 | #if __HVX_ARCH__ >= 60 |
| 1531 | /* ========================================================================== |
| 1532 | Assembly Syntax: Qd4=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1533 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 1534 | Instruction Type: CVI_VA |
| 1535 | Execution Slots: SLOT0123 |
| 1536 | ========================================================================== */ |
| 1537 | |
| 1538 | #define Q6_Q_vcmp_gt_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw) |
| 1539 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1540 | |
| 1541 | #if __HVX_ARCH__ >= 60 |
| 1542 | /* ========================================================================== |
| 1543 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1544 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1545 | Instruction Type: CVI_VA |
| 1546 | Execution Slots: SLOT0123 |
| 1547 | ========================================================================== */ |
| 1548 | |
| 1549 | #define Q6_Q_vcmp_gtand_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and) |
| 1550 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1551 | |
| 1552 | #if __HVX_ARCH__ >= 60 |
| 1553 | /* ========================================================================== |
| 1554 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1555 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1556 | Instruction Type: CVI_VA |
| 1557 | Execution Slots: SLOT0123 |
| 1558 | ========================================================================== */ |
| 1559 | |
| 1560 | #define Q6_Q_vcmp_gtor_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or) |
| 1561 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1562 | |
| 1563 | #if __HVX_ARCH__ >= 60 |
| 1564 | /* ========================================================================== |
| 1565 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.uw,Vv32.uw) |
| 1566 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVuwVuw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1567 | Instruction Type: CVI_VA |
| 1568 | Execution Slots: SLOT0123 |
| 1569 | ========================================================================== */ |
| 1570 | |
| 1571 | #define Q6_Q_vcmp_gtxacc_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor) |
| 1572 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1573 | |
| 1574 | #if __HVX_ARCH__ >= 60 |
| 1575 | /* ========================================================================== |
| 1576 | Assembly Syntax: Qd4=vcmp.gt(Vu32.w,Vv32.w) |
| 1577 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gt_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1578 | Instruction Type: CVI_VA |
| 1579 | Execution Slots: SLOT0123 |
| 1580 | ========================================================================== */ |
| 1581 | |
| 1582 | #define Q6_Q_vcmp_gt_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw) |
| 1583 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1584 | |
| 1585 | #if __HVX_ARCH__ >= 60 |
| 1586 | /* ========================================================================== |
| 1587 | Assembly Syntax: Qx4&=vcmp.gt(Vu32.w,Vv32.w) |
| 1588 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtand_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1589 | Instruction Type: CVI_VA |
| 1590 | Execution Slots: SLOT0123 |
| 1591 | ========================================================================== */ |
| 1592 | |
| 1593 | #define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and) |
| 1594 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1595 | |
| 1596 | #if __HVX_ARCH__ >= 60 |
| 1597 | /* ========================================================================== |
| 1598 | Assembly Syntax: Qx4|=vcmp.gt(Vu32.w,Vv32.w) |
| 1599 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtor_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1600 | Instruction Type: CVI_VA |
| 1601 | Execution Slots: SLOT0123 |
| 1602 | ========================================================================== */ |
| 1603 | |
| 1604 | #define Q6_Q_vcmp_gtor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or) |
| 1605 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1606 | |
| 1607 | #if __HVX_ARCH__ >= 60 |
| 1608 | /* ========================================================================== |
| 1609 | Assembly Syntax: Qx4^=vcmp.gt(Vu32.w,Vv32.w) |
| 1610 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vcmp_gtxacc_QVwVw(HVX_VectorPred Qx, HVX_Vector Vu, HVX_Vector Vv) |
| 1611 | Instruction Type: CVI_VA |
| 1612 | Execution Slots: SLOT0123 |
| 1613 | ========================================================================== */ |
| 1614 | |
| 1615 | #define Q6_Q_vcmp_gtxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor) |
| 1616 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1617 | |
| 1618 | #if __HVX_ARCH__ >= 60 |
| 1619 | /* ========================================================================== |
| 1620 | Assembly Syntax: Vx32.w=vinsert(Rt32) |
| 1621 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vinsert_VwR(HVX_Vector Vx, Word32 Rt) |
| 1622 | Instruction Type: CVI_VX_LATE |
| 1623 | Execution Slots: SLOT23 |
| 1624 | ========================================================================== */ |
| 1625 | |
| 1626 | #define Q6_Vw_vinsert_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr) |
| 1627 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1628 | |
| 1629 | #if __HVX_ARCH__ >= 60 |
| 1630 | /* ========================================================================== |
| 1631 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,Rt8) |
| 1632 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1633 | Instruction Type: CVI_VP |
| 1634 | Execution Slots: SLOT0123 |
| 1635 | ========================================================================== */ |
| 1636 | |
| 1637 | #define Q6_V_vlalign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb) |
| 1638 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1639 | |
| 1640 | #if __HVX_ARCH__ >= 60 |
| 1641 | /* ========================================================================== |
| 1642 | Assembly Syntax: Vd32=vlalign(Vu32,Vv32,#u3) |
| 1643 | C Intrinsic Prototype: HVX_Vector Q6_V_vlalign_VVI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 1644 | Instruction Type: CVI_VP |
| 1645 | Execution Slots: SLOT0123 |
| 1646 | ========================================================================== */ |
| 1647 | |
| 1648 | #define Q6_V_vlalign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi) |
| 1649 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1650 | |
| 1651 | #if __HVX_ARCH__ >= 60 |
| 1652 | /* ========================================================================== |
| 1653 | Assembly Syntax: Vd32.uh=vlsr(Vu32.uh,Rt32) |
| 1654 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vlsr_VuhR(HVX_Vector Vu, Word32 Rt) |
| 1655 | Instruction Type: CVI_VS |
| 1656 | Execution Slots: SLOT0123 |
| 1657 | ========================================================================== */ |
| 1658 | |
| 1659 | #define Q6_Vuh_vlsr_VuhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh) |
| 1660 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1661 | |
| 1662 | #if __HVX_ARCH__ >= 60 |
| 1663 | /* ========================================================================== |
| 1664 | Assembly Syntax: Vd32.h=vlsr(Vu32.h,Vv32.h) |
| 1665 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlsr_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1666 | Instruction Type: CVI_VS |
| 1667 | Execution Slots: SLOT0123 |
| 1668 | ========================================================================== */ |
| 1669 | |
| 1670 | #define Q6_Vh_vlsr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv) |
| 1671 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1672 | |
| 1673 | #if __HVX_ARCH__ >= 60 |
| 1674 | /* ========================================================================== |
| 1675 | Assembly Syntax: Vd32.uw=vlsr(Vu32.uw,Rt32) |
| 1676 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vlsr_VuwR(HVX_Vector Vu, Word32 Rt) |
| 1677 | Instruction Type: CVI_VS |
| 1678 | Execution Slots: SLOT0123 |
| 1679 | ========================================================================== */ |
| 1680 | |
| 1681 | #define Q6_Vuw_vlsr_VuwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw) |
| 1682 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1683 | |
| 1684 | #if __HVX_ARCH__ >= 60 |
| 1685 | /* ========================================================================== |
| 1686 | Assembly Syntax: Vd32.w=vlsr(Vu32.w,Vv32.w) |
| 1687 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vlsr_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1688 | Instruction Type: CVI_VS |
| 1689 | Execution Slots: SLOT0123 |
| 1690 | ========================================================================== */ |
| 1691 | |
| 1692 | #define Q6_Vw_vlsr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv) |
| 1693 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1694 | |
| 1695 | #if __HVX_ARCH__ >= 60 |
| 1696 | /* ========================================================================== |
| 1697 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8) |
| 1698 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1699 | Instruction Type: CVI_VP |
| 1700 | Execution Slots: SLOT0123 |
| 1701 | ========================================================================== */ |
| 1702 | |
| 1703 | #define Q6_Vb_vlut32_VbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb) |
| 1704 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1705 | |
| 1706 | #if __HVX_ARCH__ >= 60 |
| 1707 | /* ========================================================================== |
| 1708 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,Rt8) |
| 1709 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbR(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1710 | Instruction Type: CVI_VP_VS |
| 1711 | Execution Slots: SLOT0123 |
| 1712 | ========================================================================== */ |
| 1713 | |
| 1714 | #define Q6_Vb_vlut32or_VbVbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc) |
| 1715 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1716 | |
| 1717 | #if __HVX_ARCH__ >= 60 |
| 1718 | /* ========================================================================== |
| 1719 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8) |
| 1720 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1721 | Instruction Type: CVI_VP_VS |
| 1722 | Execution Slots: SLOT0123 |
| 1723 | ========================================================================== */ |
| 1724 | |
| 1725 | #define Q6_Wh_vlut16_VbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh) |
| 1726 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1727 | |
| 1728 | #if __HVX_ARCH__ >= 60 |
| 1729 | /* ========================================================================== |
| 1730 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,Rt8) |
| 1731 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhR(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 1732 | Instruction Type: CVI_VP_VS |
| 1733 | Execution Slots: SLOT0123 |
| 1734 | ========================================================================== */ |
| 1735 | |
| 1736 | #define Q6_Wh_vlut16or_WhVbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc) |
| 1737 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1738 | |
| 1739 | #if __HVX_ARCH__ >= 60 |
| 1740 | /* ========================================================================== |
| 1741 | Assembly Syntax: Vd32.h=vmax(Vu32.h,Vv32.h) |
| 1742 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmax_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1743 | Instruction Type: CVI_VA |
| 1744 | Execution Slots: SLOT0123 |
| 1745 | ========================================================================== */ |
| 1746 | |
| 1747 | #define Q6_Vh_vmax_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh) |
| 1748 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1749 | |
| 1750 | #if __HVX_ARCH__ >= 60 |
| 1751 | /* ========================================================================== |
| 1752 | Assembly Syntax: Vd32.ub=vmax(Vu32.ub,Vv32.ub) |
| 1753 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmax_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1754 | Instruction Type: CVI_VA |
| 1755 | Execution Slots: SLOT0123 |
| 1756 | ========================================================================== */ |
| 1757 | |
| 1758 | #define Q6_Vub_vmax_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub) |
| 1759 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1760 | |
| 1761 | #if __HVX_ARCH__ >= 60 |
| 1762 | /* ========================================================================== |
| 1763 | Assembly Syntax: Vd32.uh=vmax(Vu32.uh,Vv32.uh) |
| 1764 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmax_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1765 | Instruction Type: CVI_VA |
| 1766 | Execution Slots: SLOT0123 |
| 1767 | ========================================================================== */ |
| 1768 | |
| 1769 | #define Q6_Vuh_vmax_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh) |
| 1770 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1771 | |
| 1772 | #if __HVX_ARCH__ >= 60 |
| 1773 | /* ========================================================================== |
| 1774 | Assembly Syntax: Vd32.w=vmax(Vu32.w,Vv32.w) |
| 1775 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmax_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1776 | Instruction Type: CVI_VA |
| 1777 | Execution Slots: SLOT0123 |
| 1778 | ========================================================================== */ |
| 1779 | |
| 1780 | #define Q6_Vw_vmax_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw) |
| 1781 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1782 | |
| 1783 | #if __HVX_ARCH__ >= 60 |
| 1784 | /* ========================================================================== |
| 1785 | Assembly Syntax: Vd32.h=vmin(Vu32.h,Vv32.h) |
| 1786 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmin_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 1787 | Instruction Type: CVI_VA |
| 1788 | Execution Slots: SLOT0123 |
| 1789 | ========================================================================== */ |
| 1790 | |
| 1791 | #define Q6_Vh_vmin_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh) |
| 1792 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1793 | |
| 1794 | #if __HVX_ARCH__ >= 60 |
| 1795 | /* ========================================================================== |
| 1796 | Assembly Syntax: Vd32.ub=vmin(Vu32.ub,Vv32.ub) |
| 1797 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vmin_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 1798 | Instruction Type: CVI_VA |
| 1799 | Execution Slots: SLOT0123 |
| 1800 | ========================================================================== */ |
| 1801 | |
| 1802 | #define Q6_Vub_vmin_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub) |
| 1803 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1804 | |
| 1805 | #if __HVX_ARCH__ >= 60 |
| 1806 | /* ========================================================================== |
| 1807 | Assembly Syntax: Vd32.uh=vmin(Vu32.uh,Vv32.uh) |
| 1808 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vmin_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1809 | Instruction Type: CVI_VA |
| 1810 | Execution Slots: SLOT0123 |
| 1811 | ========================================================================== */ |
| 1812 | |
| 1813 | #define Q6_Vuh_vmin_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh) |
| 1814 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1815 | |
| 1816 | #if __HVX_ARCH__ >= 60 |
| 1817 | /* ========================================================================== |
| 1818 | Assembly Syntax: Vd32.w=vmin(Vu32.w,Vv32.w) |
| 1819 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmin_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 1820 | Instruction Type: CVI_VA |
| 1821 | Execution Slots: SLOT0123 |
| 1822 | ========================================================================== */ |
| 1823 | |
| 1824 | #define Q6_Vw_vmin_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw) |
| 1825 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1826 | |
| 1827 | #if __HVX_ARCH__ >= 60 |
| 1828 | /* ========================================================================== |
| 1829 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.b) |
| 1830 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1831 | Instruction Type: CVI_VX_DV |
| 1832 | Execution Slots: SLOT23 |
| 1833 | ========================================================================== */ |
| 1834 | |
| 1835 | #define Q6_Wh_vmpa_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus) |
| 1836 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1837 | |
| 1838 | #if __HVX_ARCH__ >= 60 |
| 1839 | /* ========================================================================== |
| 1840 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.b) |
| 1841 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1842 | Instruction Type: CVI_VX_DV |
| 1843 | Execution Slots: SLOT23 |
| 1844 | ========================================================================== */ |
| 1845 | |
| 1846 | #define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc) |
| 1847 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1848 | |
| 1849 | #if __HVX_ARCH__ >= 60 |
| 1850 | /* ========================================================================== |
| 1851 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.b) |
| 1852 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 1853 | Instruction Type: CVI_VX_DV |
| 1854 | Execution Slots: SLOT23 |
| 1855 | ========================================================================== */ |
| 1856 | |
| 1857 | #define Q6_Wh_vmpa_WubWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv) |
| 1858 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1859 | |
| 1860 | #if __HVX_ARCH__ >= 60 |
| 1861 | /* ========================================================================== |
| 1862 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Vvv32.ub) |
| 1863 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubWub(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 1864 | Instruction Type: CVI_VX_DV |
| 1865 | Execution Slots: SLOT23 |
| 1866 | ========================================================================== */ |
| 1867 | |
| 1868 | #define Q6_Wh_vmpa_WubWub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv) |
| 1869 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1870 | |
| 1871 | #if __HVX_ARCH__ >= 60 |
| 1872 | /* ========================================================================== |
| 1873 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.h,Rt32.b) |
| 1874 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 1875 | Instruction Type: CVI_VX_DV |
| 1876 | Execution Slots: SLOT23 |
| 1877 | ========================================================================== */ |
| 1878 | |
| 1879 | #define Q6_Ww_vmpa_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb) |
| 1880 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1881 | |
| 1882 | #if __HVX_ARCH__ >= 60 |
| 1883 | /* ========================================================================== |
| 1884 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.h,Rt32.b) |
| 1885 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 1886 | Instruction Type: CVI_VX_DV |
| 1887 | Execution Slots: SLOT23 |
| 1888 | ========================================================================== */ |
| 1889 | |
| 1890 | #define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc) |
| 1891 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1892 | |
| 1893 | #if __HVX_ARCH__ >= 60 |
| 1894 | /* ========================================================================== |
| 1895 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Rt32.b) |
| 1896 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 1897 | Instruction Type: CVI_VX_DV |
| 1898 | Execution Slots: SLOT23 |
| 1899 | ========================================================================== */ |
| 1900 | |
| 1901 | #define Q6_Wh_vmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus) |
| 1902 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1903 | |
| 1904 | #if __HVX_ARCH__ >= 60 |
| 1905 | /* ========================================================================== |
| 1906 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Rt32.b) |
| 1907 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubRb(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1908 | Instruction Type: CVI_VX_DV |
| 1909 | Execution Slots: SLOT23 |
| 1910 | ========================================================================== */ |
| 1911 | |
| 1912 | #define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc) |
| 1913 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1914 | |
| 1915 | #if __HVX_ARCH__ >= 60 |
| 1916 | /* ========================================================================== |
| 1917 | Assembly Syntax: Vdd32.h=vmpy(Vu32.ub,Vv32.b) |
| 1918 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1919 | Instruction Type: CVI_VX_DV |
| 1920 | Execution Slots: SLOT23 |
| 1921 | ========================================================================== */ |
| 1922 | |
| 1923 | #define Q6_Wh_vmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv) |
| 1924 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1925 | |
| 1926 | #if __HVX_ARCH__ >= 60 |
| 1927 | /* ========================================================================== |
| 1928 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.ub,Vv32.b) |
| 1929 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVubVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1930 | Instruction Type: CVI_VX_DV |
| 1931 | Execution Slots: SLOT23 |
| 1932 | ========================================================================== */ |
| 1933 | |
| 1934 | #define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc) |
| 1935 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1936 | |
| 1937 | #if __HVX_ARCH__ >= 60 |
| 1938 | /* ========================================================================== |
| 1939 | Assembly Syntax: Vdd32.h=vmpy(Vu32.b,Vv32.b) |
| 1940 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 1941 | Instruction Type: CVI_VX_DV |
| 1942 | Execution Slots: SLOT23 |
| 1943 | ========================================================================== */ |
| 1944 | |
| 1945 | #define Q6_Wh_vmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv) |
| 1946 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1947 | |
| 1948 | #if __HVX_ARCH__ >= 60 |
| 1949 | /* ========================================================================== |
| 1950 | Assembly Syntax: Vxx32.h+=vmpy(Vu32.b,Vv32.b) |
| 1951 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpyacc_WhVbVb(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 1952 | Instruction Type: CVI_VX_DV |
| 1953 | Execution Slots: SLOT23 |
| 1954 | ========================================================================== */ |
| 1955 | |
| 1956 | #define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc) |
| 1957 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1958 | |
| 1959 | #if __HVX_ARCH__ >= 60 |
| 1960 | /* ========================================================================== |
| 1961 | Assembly Syntax: Vd32.w=vmpye(Vu32.w,Vv32.uh) |
| 1962 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 1963 | Instruction Type: CVI_VX_DV |
| 1964 | Execution Slots: SLOT23 |
| 1965 | ========================================================================== */ |
| 1966 | |
| 1967 | #define Q6_Vw_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh) |
| 1968 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1969 | |
| 1970 | #if __HVX_ARCH__ >= 60 |
| 1971 | /* ========================================================================== |
| 1972 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Rt32.h) |
| 1973 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhRh(HVX_Vector Vu, Word32 Rt) |
| 1974 | Instruction Type: CVI_VX_DV |
| 1975 | Execution Slots: SLOT23 |
| 1976 | ========================================================================== */ |
| 1977 | |
| 1978 | #define Q6_Ww_vmpy_VhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh) |
| 1979 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1980 | |
| 1981 | #if __HVX_ARCH__ >= 60 |
| 1982 | /* ========================================================================== |
| 1983 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h):sat |
| 1984 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh_sat(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 1985 | Instruction Type: CVI_VX_DV |
| 1986 | Execution Slots: SLOT23 |
| 1987 | ========================================================================== */ |
| 1988 | |
| 1989 | #define Q6_Ww_vmpyacc_WwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc) |
| 1990 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 1991 | |
| 1992 | #if __HVX_ARCH__ >= 60 |
| 1993 | /* ========================================================================== |
| 1994 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:rnd:sat |
| 1995 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_rnd_sat(HVX_Vector Vu, Word32 Rt) |
| 1996 | Instruction Type: CVI_VX_DV |
| 1997 | Execution Slots: SLOT23 |
| 1998 | ========================================================================== */ |
| 1999 | |
| 2000 | #define Q6_Vh_vmpy_VhRh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs) |
| 2001 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2002 | |
| 2003 | #if __HVX_ARCH__ >= 60 |
| 2004 | /* ========================================================================== |
| 2005 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Rt32.h):<<1:sat |
| 2006 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhRh_s1_sat(HVX_Vector Vu, Word32 Rt) |
| 2007 | Instruction Type: CVI_VX_DV |
| 2008 | Execution Slots: SLOT23 |
| 2009 | ========================================================================== */ |
| 2010 | |
| 2011 | #define Q6_Vh_vmpy_VhRh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss) |
| 2012 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2013 | |
| 2014 | #if __HVX_ARCH__ >= 60 |
| 2015 | /* ========================================================================== |
| 2016 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.uh) |
| 2017 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 2018 | Instruction Type: CVI_VX_DV |
| 2019 | Execution Slots: SLOT23 |
| 2020 | ========================================================================== */ |
| 2021 | |
| 2022 | #define Q6_Ww_vmpy_VhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus) |
| 2023 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2024 | |
| 2025 | #if __HVX_ARCH__ >= 60 |
| 2026 | /* ========================================================================== |
| 2027 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.uh) |
| 2028 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2029 | Instruction Type: CVI_VX_DV |
| 2030 | Execution Slots: SLOT23 |
| 2031 | ========================================================================== */ |
| 2032 | |
| 2033 | #define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc) |
| 2034 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2035 | |
| 2036 | #if __HVX_ARCH__ >= 60 |
| 2037 | /* ========================================================================== |
| 2038 | Assembly Syntax: Vdd32.w=vmpy(Vu32.h,Vv32.h) |
| 2039 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpy_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2040 | Instruction Type: CVI_VX_DV |
| 2041 | Execution Slots: SLOT23 |
| 2042 | ========================================================================== */ |
| 2043 | |
| 2044 | #define Q6_Ww_vmpy_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv) |
| 2045 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2046 | |
| 2047 | #if __HVX_ARCH__ >= 60 |
| 2048 | /* ========================================================================== |
| 2049 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Vv32.h) |
| 2050 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2051 | Instruction Type: CVI_VX_DV |
| 2052 | Execution Slots: SLOT23 |
| 2053 | ========================================================================== */ |
| 2054 | |
| 2055 | #define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc) |
| 2056 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2057 | |
| 2058 | #if __HVX_ARCH__ >= 60 |
| 2059 | /* ========================================================================== |
| 2060 | Assembly Syntax: Vd32.h=vmpy(Vu32.h,Vv32.h):<<1:rnd:sat |
| 2061 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpy_VhVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2062 | Instruction Type: CVI_VX_DV |
| 2063 | Execution Slots: SLOT23 |
| 2064 | ========================================================================== */ |
| 2065 | |
| 2066 | #define Q6_Vh_vmpy_VhVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs) |
| 2067 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2068 | |
| 2069 | #if __HVX_ARCH__ >= 60 |
| 2070 | /* ========================================================================== |
| 2071 | Assembly Syntax: Vd32.w=vmpyieo(Vu32.h,Vv32.h) |
| 2072 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2073 | Instruction Type: CVI_VX |
| 2074 | Execution Slots: SLOT23 |
| 2075 | ========================================================================== */ |
| 2076 | |
| 2077 | #define Q6_Vw_vmpyieo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh) |
| 2078 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2079 | |
| 2080 | #if __HVX_ARCH__ >= 60 |
| 2081 | /* ========================================================================== |
| 2082 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.h) |
| 2083 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2084 | Instruction Type: CVI_VX_DV |
| 2085 | Execution Slots: SLOT23 |
| 2086 | ========================================================================== */ |
| 2087 | |
| 2088 | #define Q6_Vw_vmpyieacc_VwVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc) |
| 2089 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2090 | |
| 2091 | #if __HVX_ARCH__ >= 60 |
| 2092 | /* ========================================================================== |
| 2093 | Assembly Syntax: Vd32.w=vmpyie(Vu32.w,Vv32.uh) |
| 2094 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyie_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 2095 | Instruction Type: CVI_VX_DV |
| 2096 | Execution Slots: SLOT23 |
| 2097 | ========================================================================== */ |
| 2098 | |
| 2099 | #define Q6_Vw_vmpyie_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh) |
| 2100 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2101 | |
| 2102 | #if __HVX_ARCH__ >= 60 |
| 2103 | /* ========================================================================== |
| 2104 | Assembly Syntax: Vx32.w+=vmpyie(Vu32.w,Vv32.uh) |
| 2105 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyieacc_VwVwVuh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2106 | Instruction Type: CVI_VX_DV |
| 2107 | Execution Slots: SLOT23 |
| 2108 | ========================================================================== */ |
| 2109 | |
| 2110 | #define Q6_Vw_vmpyieacc_VwVwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc) |
| 2111 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2112 | |
| 2113 | #if __HVX_ARCH__ >= 60 |
| 2114 | /* ========================================================================== |
| 2115 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Vv32.h) |
| 2116 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2117 | Instruction Type: CVI_VX_DV |
| 2118 | Execution Slots: SLOT23 |
| 2119 | ========================================================================== */ |
| 2120 | |
| 2121 | #define Q6_Vh_vmpyi_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih) |
| 2122 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2123 | |
| 2124 | #if __HVX_ARCH__ >= 60 |
| 2125 | /* ========================================================================== |
| 2126 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Vv32.h) |
| 2127 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhVh(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2128 | Instruction Type: CVI_VX_DV |
| 2129 | Execution Slots: SLOT23 |
| 2130 | ========================================================================== */ |
| 2131 | |
| 2132 | #define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc) |
| 2133 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2134 | |
| 2135 | #if __HVX_ARCH__ >= 60 |
| 2136 | /* ========================================================================== |
| 2137 | Assembly Syntax: Vd32.h=vmpyi(Vu32.h,Rt32.b) |
| 2138 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyi_VhRb(HVX_Vector Vu, Word32 Rt) |
| 2139 | Instruction Type: CVI_VX |
| 2140 | Execution Slots: SLOT23 |
| 2141 | ========================================================================== */ |
| 2142 | |
| 2143 | #define Q6_Vh_vmpyi_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb) |
| 2144 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2145 | |
| 2146 | #if __HVX_ARCH__ >= 60 |
| 2147 | /* ========================================================================== |
| 2148 | Assembly Syntax: Vx32.h+=vmpyi(Vu32.h,Rt32.b) |
| 2149 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpyiacc_VhVhRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2150 | Instruction Type: CVI_VX |
| 2151 | Execution Slots: SLOT23 |
| 2152 | ========================================================================== */ |
| 2153 | |
| 2154 | #define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc) |
| 2155 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2156 | |
| 2157 | #if __HVX_ARCH__ >= 60 |
| 2158 | /* ========================================================================== |
| 2159 | Assembly Syntax: Vd32.w=vmpyio(Vu32.w,Vv32.h) |
| 2160 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyio_VwVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2161 | Instruction Type: CVI_VX_DV |
| 2162 | Execution Slots: SLOT23 |
| 2163 | ========================================================================== */ |
| 2164 | |
| 2165 | #define Q6_Vw_vmpyio_VwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh) |
| 2166 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2167 | |
| 2168 | #if __HVX_ARCH__ >= 60 |
| 2169 | /* ========================================================================== |
| 2170 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.b) |
| 2171 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRb(HVX_Vector Vu, Word32 Rt) |
| 2172 | Instruction Type: CVI_VX |
| 2173 | Execution Slots: SLOT23 |
| 2174 | ========================================================================== */ |
| 2175 | |
| 2176 | #define Q6_Vw_vmpyi_VwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb) |
| 2177 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2178 | |
| 2179 | #if __HVX_ARCH__ >= 60 |
| 2180 | /* ========================================================================== |
| 2181 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.b) |
| 2182 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2183 | Instruction Type: CVI_VX |
| 2184 | Execution Slots: SLOT23 |
| 2185 | ========================================================================== */ |
| 2186 | |
| 2187 | #define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc) |
| 2188 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2189 | |
| 2190 | #if __HVX_ARCH__ >= 60 |
| 2191 | /* ========================================================================== |
| 2192 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.h) |
| 2193 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRh(HVX_Vector Vu, Word32 Rt) |
| 2194 | Instruction Type: CVI_VX_DV |
| 2195 | Execution Slots: SLOT23 |
| 2196 | ========================================================================== */ |
| 2197 | |
| 2198 | #define Q6_Vw_vmpyi_VwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh) |
| 2199 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2200 | |
| 2201 | #if __HVX_ARCH__ >= 60 |
| 2202 | /* ========================================================================== |
| 2203 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.h) |
| 2204 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2205 | Instruction Type: CVI_VX_DV |
| 2206 | Execution Slots: SLOT23 |
| 2207 | ========================================================================== */ |
| 2208 | |
| 2209 | #define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc) |
| 2210 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2211 | |
| 2212 | #if __HVX_ARCH__ >= 60 |
| 2213 | /* ========================================================================== |
| 2214 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:sat |
| 2215 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2216 | Instruction Type: CVI_VX_DV |
| 2217 | Execution Slots: SLOT23 |
| 2218 | ========================================================================== */ |
| 2219 | |
| 2220 | #define Q6_Vw_vmpyo_VwVh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh) |
| 2221 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2222 | |
| 2223 | #if __HVX_ARCH__ >= 60 |
| 2224 | /* ========================================================================== |
| 2225 | Assembly Syntax: Vd32.w=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat |
| 2226 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyo_VwVh_s1_rnd_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2227 | Instruction Type: CVI_VX_DV |
| 2228 | Execution Slots: SLOT23 |
| 2229 | ========================================================================== */ |
| 2230 | |
| 2231 | #define Q6_Vw_vmpyo_VwVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd) |
| 2232 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2233 | |
| 2234 | #if __HVX_ARCH__ >= 60 |
| 2235 | /* ========================================================================== |
| 2236 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:rnd:sat:shift |
| 2237 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2238 | Instruction Type: CVI_VX_DV |
| 2239 | Execution Slots: SLOT23 |
| 2240 | ========================================================================== */ |
| 2241 | |
| 2242 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc) |
| 2243 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2244 | |
| 2245 | #if __HVX_ARCH__ >= 60 |
| 2246 | /* ========================================================================== |
| 2247 | Assembly Syntax: Vx32.w+=vmpyo(Vu32.w,Vv32.h):<<1:sat:shift |
| 2248 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2249 | Instruction Type: CVI_VX_DV |
| 2250 | Execution Slots: SLOT23 |
| 2251 | ========================================================================== */ |
| 2252 | |
| 2253 | #define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc) |
| 2254 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2255 | |
| 2256 | #if __HVX_ARCH__ >= 60 |
| 2257 | /* ========================================================================== |
| 2258 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Rt32.ub) |
| 2259 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
| 2260 | Instruction Type: CVI_VX_DV |
| 2261 | Execution Slots: SLOT23 |
| 2262 | ========================================================================== */ |
| 2263 | |
| 2264 | #define Q6_Wuh_vmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub) |
| 2265 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2266 | |
| 2267 | #if __HVX_ARCH__ >= 60 |
| 2268 | /* ========================================================================== |
| 2269 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Rt32.ub) |
| 2270 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubRub(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 2271 | Instruction Type: CVI_VX_DV |
| 2272 | Execution Slots: SLOT23 |
| 2273 | ========================================================================== */ |
| 2274 | |
| 2275 | #define Q6_Wuh_vmpyacc_WuhVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc) |
| 2276 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2277 | |
| 2278 | #if __HVX_ARCH__ >= 60 |
| 2279 | /* ========================================================================== |
| 2280 | Assembly Syntax: Vdd32.uh=vmpy(Vu32.ub,Vv32.ub) |
| 2281 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 2282 | Instruction Type: CVI_VX_DV |
| 2283 | Execution Slots: SLOT23 |
| 2284 | ========================================================================== */ |
| 2285 | |
| 2286 | #define Q6_Wuh_vmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv) |
| 2287 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2288 | |
| 2289 | #if __HVX_ARCH__ >= 60 |
| 2290 | /* ========================================================================== |
| 2291 | Assembly Syntax: Vxx32.uh+=vmpy(Vu32.ub,Vv32.ub) |
| 2292 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vmpyacc_WuhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2293 | Instruction Type: CVI_VX_DV |
| 2294 | Execution Slots: SLOT23 |
| 2295 | ========================================================================== */ |
| 2296 | |
| 2297 | #define Q6_Wuh_vmpyacc_WuhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc) |
| 2298 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2299 | |
| 2300 | #if __HVX_ARCH__ >= 60 |
| 2301 | /* ========================================================================== |
| 2302 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Rt32.uh) |
| 2303 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhRuh(HVX_Vector Vu, Word32 Rt) |
| 2304 | Instruction Type: CVI_VX_DV |
| 2305 | Execution Slots: SLOT23 |
| 2306 | ========================================================================== */ |
| 2307 | |
| 2308 | #define Q6_Wuw_vmpy_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh) |
| 2309 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2310 | |
| 2311 | #if __HVX_ARCH__ >= 60 |
| 2312 | /* ========================================================================== |
| 2313 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Rt32.uh) |
| 2314 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhRuh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 2315 | Instruction Type: CVI_VX_DV |
| 2316 | Execution Slots: SLOT23 |
| 2317 | ========================================================================== */ |
| 2318 | |
| 2319 | #define Q6_Wuw_vmpyacc_WuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc) |
| 2320 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2321 | |
| 2322 | #if __HVX_ARCH__ >= 60 |
| 2323 | /* ========================================================================== |
| 2324 | Assembly Syntax: Vdd32.uw=vmpy(Vu32.uh,Vv32.uh) |
| 2325 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpy_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 2326 | Instruction Type: CVI_VX_DV |
| 2327 | Execution Slots: SLOT23 |
| 2328 | ========================================================================== */ |
| 2329 | |
| 2330 | #define Q6_Wuw_vmpy_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv) |
| 2331 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2332 | |
| 2333 | #if __HVX_ARCH__ >= 60 |
| 2334 | /* ========================================================================== |
| 2335 | Assembly Syntax: Vxx32.uw+=vmpy(Vu32.uh,Vv32.uh) |
| 2336 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vmpyacc_WuwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 2337 | Instruction Type: CVI_VX_DV |
| 2338 | Execution Slots: SLOT23 |
| 2339 | ========================================================================== */ |
| 2340 | |
| 2341 | #define Q6_Wuw_vmpyacc_WuwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc) |
| 2342 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2343 | |
| 2344 | #if __HVX_ARCH__ >= 60 |
| 2345 | /* ========================================================================== |
| 2346 | Assembly Syntax: Vd32=vmux(Qt4,Vu32,Vv32) |
| 2347 | C Intrinsic Prototype: HVX_Vector Q6_V_vmux_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
| 2348 | Instruction Type: CVI_VA |
| 2349 | Execution Slots: SLOT0123 |
| 2350 | ========================================================================== */ |
| 2351 | |
| 2352 | #define Q6_V_vmux_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux) |
| 2353 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2354 | |
| 2355 | #if __HVX_ARCH__ >= 60 |
| 2356 | /* ========================================================================== |
| 2357 | Assembly Syntax: Vd32.h=vnavg(Vu32.h,Vv32.h) |
| 2358 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnavg_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2359 | Instruction Type: CVI_VA |
| 2360 | Execution Slots: SLOT0123 |
| 2361 | ========================================================================== */ |
| 2362 | |
| 2363 | #define Q6_Vh_vnavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh) |
| 2364 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2365 | |
| 2366 | #if __HVX_ARCH__ >= 60 |
| 2367 | /* ========================================================================== |
| 2368 | Assembly Syntax: Vd32.b=vnavg(Vu32.ub,Vv32.ub) |
| 2369 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 2370 | Instruction Type: CVI_VA |
| 2371 | Execution Slots: SLOT0123 |
| 2372 | ========================================================================== */ |
| 2373 | |
| 2374 | #define Q6_Vb_vnavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub) |
| 2375 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2376 | |
| 2377 | #if __HVX_ARCH__ >= 60 |
| 2378 | /* ========================================================================== |
| 2379 | Assembly Syntax: Vd32.w=vnavg(Vu32.w,Vv32.w) |
| 2380 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnavg_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2381 | Instruction Type: CVI_VA |
| 2382 | Execution Slots: SLOT0123 |
| 2383 | ========================================================================== */ |
| 2384 | |
| 2385 | #define Q6_Vw_vnavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw) |
| 2386 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2387 | |
| 2388 | #if __HVX_ARCH__ >= 60 |
| 2389 | /* ========================================================================== |
| 2390 | Assembly Syntax: Vd32.h=vnormamt(Vu32.h) |
| 2391 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vnormamt_Vh(HVX_Vector Vu) |
| 2392 | Instruction Type: CVI_VS |
| 2393 | Execution Slots: SLOT0123 |
| 2394 | ========================================================================== */ |
| 2395 | |
| 2396 | #define Q6_Vh_vnormamt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth) |
| 2397 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2398 | |
| 2399 | #if __HVX_ARCH__ >= 60 |
| 2400 | /* ========================================================================== |
| 2401 | Assembly Syntax: Vd32.w=vnormamt(Vu32.w) |
| 2402 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vnormamt_Vw(HVX_Vector Vu) |
| 2403 | Instruction Type: CVI_VS |
| 2404 | Execution Slots: SLOT0123 |
| 2405 | ========================================================================== */ |
| 2406 | |
| 2407 | #define Q6_Vw_vnormamt_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw) |
| 2408 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2409 | |
| 2410 | #if __HVX_ARCH__ >= 60 |
| 2411 | /* ========================================================================== |
| 2412 | Assembly Syntax: Vd32=vnot(Vu32) |
| 2413 | C Intrinsic Prototype: HVX_Vector Q6_V_vnot_V(HVX_Vector Vu) |
| 2414 | Instruction Type: CVI_VA |
| 2415 | Execution Slots: SLOT0123 |
| 2416 | ========================================================================== */ |
| 2417 | |
| 2418 | #define Q6_V_vnot_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot) |
| 2419 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2420 | |
| 2421 | #if __HVX_ARCH__ >= 60 |
| 2422 | /* ========================================================================== |
| 2423 | Assembly Syntax: Vd32=vor(Vu32,Vv32) |
| 2424 | C Intrinsic Prototype: HVX_Vector Q6_V_vor_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 2425 | Instruction Type: CVI_VA |
| 2426 | Execution Slots: SLOT0123 |
| 2427 | ========================================================================== */ |
| 2428 | |
| 2429 | #define Q6_V_vor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor) |
| 2430 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2431 | |
| 2432 | #if __HVX_ARCH__ >= 60 |
| 2433 | /* ========================================================================== |
| 2434 | Assembly Syntax: Vd32.b=vpacke(Vu32.h,Vv32.h) |
| 2435 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacke_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2436 | Instruction Type: CVI_VP |
| 2437 | Execution Slots: SLOT0123 |
| 2438 | ========================================================================== */ |
| 2439 | |
| 2440 | #define Q6_Vb_vpacke_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb) |
| 2441 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2442 | |
| 2443 | #if __HVX_ARCH__ >= 60 |
| 2444 | /* ========================================================================== |
| 2445 | Assembly Syntax: Vd32.h=vpacke(Vu32.w,Vv32.w) |
| 2446 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacke_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2447 | Instruction Type: CVI_VP |
| 2448 | Execution Slots: SLOT0123 |
| 2449 | ========================================================================== */ |
| 2450 | |
| 2451 | #define Q6_Vh_vpacke_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh) |
| 2452 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2453 | |
| 2454 | #if __HVX_ARCH__ >= 60 |
| 2455 | /* ========================================================================== |
| 2456 | Assembly Syntax: Vd32.b=vpack(Vu32.h,Vv32.h):sat |
| 2457 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2458 | Instruction Type: CVI_VP |
| 2459 | Execution Slots: SLOT0123 |
| 2460 | ========================================================================== */ |
| 2461 | |
| 2462 | #define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat) |
| 2463 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2464 | |
| 2465 | #if __HVX_ARCH__ >= 60 |
| 2466 | /* ========================================================================== |
| 2467 | Assembly Syntax: Vd32.ub=vpack(Vu32.h,Vv32.h):sat |
| 2468 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vpack_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2469 | Instruction Type: CVI_VP |
| 2470 | Execution Slots: SLOT0123 |
| 2471 | ========================================================================== */ |
| 2472 | |
| 2473 | #define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat) |
| 2474 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2475 | |
| 2476 | #if __HVX_ARCH__ >= 60 |
| 2477 | /* ========================================================================== |
| 2478 | Assembly Syntax: Vd32.b=vpacko(Vu32.h,Vv32.h) |
| 2479 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vpacko_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2480 | Instruction Type: CVI_VP |
| 2481 | Execution Slots: SLOT0123 |
| 2482 | ========================================================================== */ |
| 2483 | |
| 2484 | #define Q6_Vb_vpacko_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob) |
| 2485 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2486 | |
| 2487 | #if __HVX_ARCH__ >= 60 |
| 2488 | /* ========================================================================== |
| 2489 | Assembly Syntax: Vd32.h=vpacko(Vu32.w,Vv32.w) |
| 2490 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpacko_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2491 | Instruction Type: CVI_VP |
| 2492 | Execution Slots: SLOT0123 |
| 2493 | ========================================================================== */ |
| 2494 | |
| 2495 | #define Q6_Vh_vpacko_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh) |
| 2496 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2497 | |
| 2498 | #if __HVX_ARCH__ >= 60 |
| 2499 | /* ========================================================================== |
| 2500 | Assembly Syntax: Vd32.h=vpack(Vu32.w,Vv32.w):sat |
| 2501 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2502 | Instruction Type: CVI_VP |
| 2503 | Execution Slots: SLOT0123 |
| 2504 | ========================================================================== */ |
| 2505 | |
| 2506 | #define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat) |
| 2507 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2508 | |
| 2509 | #if __HVX_ARCH__ >= 60 |
| 2510 | /* ========================================================================== |
| 2511 | Assembly Syntax: Vd32.uh=vpack(Vu32.w,Vv32.w):sat |
| 2512 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vpack_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2513 | Instruction Type: CVI_VP |
| 2514 | Execution Slots: SLOT0123 |
| 2515 | ========================================================================== */ |
| 2516 | |
| 2517 | #define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat) |
| 2518 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2519 | |
| 2520 | #if __HVX_ARCH__ >= 60 |
| 2521 | /* ========================================================================== |
| 2522 | Assembly Syntax: Vd32.h=vpopcount(Vu32.h) |
| 2523 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vpopcount_Vh(HVX_Vector Vu) |
| 2524 | Instruction Type: CVI_VS |
| 2525 | Execution Slots: SLOT0123 |
| 2526 | ========================================================================== */ |
| 2527 | |
| 2528 | #define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth) |
| 2529 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2530 | |
| 2531 | #if __HVX_ARCH__ >= 60 |
| 2532 | /* ========================================================================== |
| 2533 | Assembly Syntax: Vd32=vrdelta(Vu32,Vv32) |
| 2534 | C Intrinsic Prototype: HVX_Vector Q6_V_vrdelta_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 2535 | Instruction Type: CVI_VP |
| 2536 | Execution Slots: SLOT0123 |
| 2537 | ========================================================================== */ |
| 2538 | |
| 2539 | #define Q6_V_vrdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta) |
| 2540 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2541 | |
| 2542 | #if __HVX_ARCH__ >= 60 |
| 2543 | /* ========================================================================== |
| 2544 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Rt32.b) |
| 2545 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubRb(HVX_Vector Vu, Word32 Rt) |
| 2546 | Instruction Type: CVI_VX |
| 2547 | Execution Slots: SLOT23 |
| 2548 | ========================================================================== */ |
| 2549 | |
| 2550 | #define Q6_Vw_vrmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus) |
| 2551 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2552 | |
| 2553 | #if __HVX_ARCH__ >= 60 |
| 2554 | /* ========================================================================== |
| 2555 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Rt32.b) |
| 2556 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubRb(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2557 | Instruction Type: CVI_VX |
| 2558 | Execution Slots: SLOT23 |
| 2559 | ========================================================================== */ |
| 2560 | |
| 2561 | #define Q6_Vw_vrmpyacc_VwVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc) |
| 2562 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2563 | |
| 2564 | #if __HVX_ARCH__ >= 60 |
| 2565 | /* ========================================================================== |
| 2566 | Assembly Syntax: Vdd32.w=vrmpy(Vuu32.ub,Rt32.b,#u1) |
| 2567 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpy_WubRbI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2568 | Instruction Type: CVI_VX_DV |
| 2569 | Execution Slots: SLOT23 |
| 2570 | ========================================================================== */ |
| 2571 | |
| 2572 | #define Q6_Ww_vrmpy_WubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi) |
| 2573 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2574 | |
| 2575 | #if __HVX_ARCH__ >= 60 |
| 2576 | /* ========================================================================== |
| 2577 | Assembly Syntax: Vxx32.w+=vrmpy(Vuu32.ub,Rt32.b,#u1) |
| 2578 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vrmpyacc_WwWubRbI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2579 | Instruction Type: CVI_VX_DV |
| 2580 | Execution Slots: SLOT23 |
| 2581 | ========================================================================== */ |
| 2582 | |
| 2583 | #define Q6_Ww_vrmpyacc_WwWubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc) |
| 2584 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2585 | |
| 2586 | #if __HVX_ARCH__ >= 60 |
| 2587 | /* ========================================================================== |
| 2588 | Assembly Syntax: Vd32.w=vrmpy(Vu32.ub,Vv32.b) |
| 2589 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VubVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2590 | Instruction Type: CVI_VX |
| 2591 | Execution Slots: SLOT23 |
| 2592 | ========================================================================== */ |
| 2593 | |
| 2594 | #define Q6_Vw_vrmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv) |
| 2595 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2596 | |
| 2597 | #if __HVX_ARCH__ >= 60 |
| 2598 | /* ========================================================================== |
| 2599 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.ub,Vv32.b) |
| 2600 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVubVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2601 | Instruction Type: CVI_VX_DV |
| 2602 | Execution Slots: SLOT23 |
| 2603 | ========================================================================== */ |
| 2604 | |
| 2605 | #define Q6_Vw_vrmpyacc_VwVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc) |
| 2606 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2607 | |
| 2608 | #if __HVX_ARCH__ >= 60 |
| 2609 | /* ========================================================================== |
| 2610 | Assembly Syntax: Vd32.w=vrmpy(Vu32.b,Vv32.b) |
| 2611 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpy_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2612 | Instruction Type: CVI_VX |
| 2613 | Execution Slots: SLOT23 |
| 2614 | ========================================================================== */ |
| 2615 | |
| 2616 | #define Q6_Vw_vrmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv) |
| 2617 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2618 | |
| 2619 | #if __HVX_ARCH__ >= 60 |
| 2620 | /* ========================================================================== |
| 2621 | Assembly Syntax: Vx32.w+=vrmpy(Vu32.b,Vv32.b) |
| 2622 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vrmpyacc_VwVbVb(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2623 | Instruction Type: CVI_VX_DV |
| 2624 | Execution Slots: SLOT23 |
| 2625 | ========================================================================== */ |
| 2626 | |
| 2627 | #define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc) |
| 2628 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2629 | |
| 2630 | #if __HVX_ARCH__ >= 60 |
| 2631 | /* ========================================================================== |
| 2632 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Rt32.ub) |
| 2633 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubRub(HVX_Vector Vu, Word32 Rt) |
| 2634 | Instruction Type: CVI_VX |
| 2635 | Execution Slots: SLOT23 |
| 2636 | ========================================================================== */ |
| 2637 | |
| 2638 | #define Q6_Vuw_vrmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub) |
| 2639 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2640 | |
| 2641 | #if __HVX_ARCH__ >= 60 |
| 2642 | /* ========================================================================== |
| 2643 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Rt32.ub) |
| 2644 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 2645 | Instruction Type: CVI_VX |
| 2646 | Execution Slots: SLOT23 |
| 2647 | ========================================================================== */ |
| 2648 | |
| 2649 | #define Q6_Vuw_vrmpyacc_VuwVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc) |
| 2650 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2651 | |
| 2652 | #if __HVX_ARCH__ >= 60 |
| 2653 | /* ========================================================================== |
| 2654 | Assembly Syntax: Vdd32.uw=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
| 2655 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpy_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2656 | Instruction Type: CVI_VX_DV |
| 2657 | Execution Slots: SLOT23 |
| 2658 | ========================================================================== */ |
| 2659 | |
| 2660 | #define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi) |
| 2661 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2662 | |
| 2663 | #if __HVX_ARCH__ >= 60 |
| 2664 | /* ========================================================================== |
| 2665 | Assembly Syntax: Vxx32.uw+=vrmpy(Vuu32.ub,Rt32.ub,#u1) |
| 2666 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrmpyacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2667 | Instruction Type: CVI_VX_DV |
| 2668 | Execution Slots: SLOT23 |
| 2669 | ========================================================================== */ |
| 2670 | |
| 2671 | #define Q6_Wuw_vrmpyacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc) |
| 2672 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2673 | |
| 2674 | #if __HVX_ARCH__ >= 60 |
| 2675 | /* ========================================================================== |
| 2676 | Assembly Syntax: Vd32.uw=vrmpy(Vu32.ub,Vv32.ub) |
| 2677 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpy_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 2678 | Instruction Type: CVI_VX |
| 2679 | Execution Slots: SLOT23 |
| 2680 | ========================================================================== */ |
| 2681 | |
| 2682 | #define Q6_Vuw_vrmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv) |
| 2683 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2684 | |
| 2685 | #if __HVX_ARCH__ >= 60 |
| 2686 | /* ========================================================================== |
| 2687 | Assembly Syntax: Vx32.uw+=vrmpy(Vu32.ub,Vv32.ub) |
| 2688 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrmpyacc_VuwVubVub(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv) |
| 2689 | Instruction Type: CVI_VX_DV |
| 2690 | Execution Slots: SLOT23 |
| 2691 | ========================================================================== */ |
| 2692 | |
| 2693 | #define Q6_Vuw_vrmpyacc_VuwVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc) |
| 2694 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2695 | |
| 2696 | #if __HVX_ARCH__ >= 60 |
| 2697 | /* ========================================================================== |
| 2698 | Assembly Syntax: Vd32=vror(Vu32,Rt32) |
| 2699 | C Intrinsic Prototype: HVX_Vector Q6_V_vror_VR(HVX_Vector Vu, Word32 Rt) |
| 2700 | Instruction Type: CVI_VP |
| 2701 | Execution Slots: SLOT0123 |
| 2702 | ========================================================================== */ |
| 2703 | |
| 2704 | #define Q6_V_vror_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror) |
| 2705 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2706 | |
| 2707 | #if __HVX_ARCH__ >= 60 |
| 2708 | /* ========================================================================== |
| 2709 | Assembly Syntax: Vd32.b=vround(Vu32.h,Vv32.h):sat |
| 2710 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2711 | Instruction Type: CVI_VS |
| 2712 | Execution Slots: SLOT0123 |
| 2713 | ========================================================================== */ |
| 2714 | |
| 2715 | #define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb) |
| 2716 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2717 | |
| 2718 | #if __HVX_ARCH__ >= 60 |
| 2719 | /* ========================================================================== |
| 2720 | Assembly Syntax: Vd32.ub=vround(Vu32.h,Vv32.h):sat |
| 2721 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2722 | Instruction Type: CVI_VS |
| 2723 | Execution Slots: SLOT0123 |
| 2724 | ========================================================================== */ |
| 2725 | |
| 2726 | #define Q6_Vub_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub) |
| 2727 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2728 | |
| 2729 | #if __HVX_ARCH__ >= 60 |
| 2730 | /* ========================================================================== |
| 2731 | Assembly Syntax: Vd32.h=vround(Vu32.w,Vv32.w):sat |
| 2732 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2733 | Instruction Type: CVI_VS |
| 2734 | Execution Slots: SLOT0123 |
| 2735 | ========================================================================== */ |
| 2736 | |
| 2737 | #define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh) |
| 2738 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2739 | |
| 2740 | #if __HVX_ARCH__ >= 60 |
| 2741 | /* ========================================================================== |
| 2742 | Assembly Syntax: Vd32.uh=vround(Vu32.w,Vv32.w):sat |
| 2743 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 2744 | Instruction Type: CVI_VS |
| 2745 | Execution Slots: SLOT0123 |
| 2746 | ========================================================================== */ |
| 2747 | |
| 2748 | #define Q6_Vuh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh) |
| 2749 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2750 | |
| 2751 | #if __HVX_ARCH__ >= 60 |
| 2752 | /* ========================================================================== |
| 2753 | Assembly Syntax: Vdd32.uw=vrsad(Vuu32.ub,Rt32.ub,#u1) |
| 2754 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsad_WubRubI(HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2755 | Instruction Type: CVI_VX_DV |
| 2756 | Execution Slots: SLOT23 |
| 2757 | ========================================================================== */ |
| 2758 | |
| 2759 | #define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi) |
| 2760 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2761 | |
| 2762 | #if __HVX_ARCH__ >= 60 |
| 2763 | /* ========================================================================== |
| 2764 | Assembly Syntax: Vxx32.uw+=vrsad(Vuu32.ub,Rt32.ub,#u1) |
| 2765 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vrsadacc_WuwWubRubI(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt, Word32 Iu1) |
| 2766 | Instruction Type: CVI_VX_DV |
| 2767 | Execution Slots: SLOT23 |
| 2768 | ========================================================================== */ |
| 2769 | |
| 2770 | #define Q6_Wuw_vrsadacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc) |
| 2771 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2772 | |
| 2773 | #if __HVX_ARCH__ >= 60 |
| 2774 | /* ========================================================================== |
| 2775 | Assembly Syntax: Vd32.ub=vsat(Vu32.h,Vv32.h) |
| 2776 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsat_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2777 | Instruction Type: CVI_VA |
| 2778 | Execution Slots: SLOT0123 |
| 2779 | ========================================================================== */ |
| 2780 | |
| 2781 | #define Q6_Vub_vsat_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub) |
| 2782 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2783 | |
| 2784 | #if __HVX_ARCH__ >= 60 |
| 2785 | /* ========================================================================== |
| 2786 | Assembly Syntax: Vd32.h=vsat(Vu32.w,Vv32.w) |
| 2787 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsat_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 2788 | Instruction Type: CVI_VA |
| 2789 | Execution Slots: SLOT0123 |
| 2790 | ========================================================================== */ |
| 2791 | |
| 2792 | #define Q6_Vh_vsat_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh) |
| 2793 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2794 | |
| 2795 | #if __HVX_ARCH__ >= 60 |
| 2796 | /* ========================================================================== |
| 2797 | Assembly Syntax: Vdd32.h=vsxt(Vu32.b) |
| 2798 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsxt_Vb(HVX_Vector Vu) |
| 2799 | Instruction Type: CVI_VA_DV |
| 2800 | Execution Slots: SLOT0123 |
| 2801 | ========================================================================== */ |
| 2802 | |
| 2803 | #define Q6_Wh_vsxt_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb) |
| 2804 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2805 | |
| 2806 | #if __HVX_ARCH__ >= 60 |
| 2807 | /* ========================================================================== |
| 2808 | Assembly Syntax: Vdd32.w=vsxt(Vu32.h) |
| 2809 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsxt_Vh(HVX_Vector Vu) |
| 2810 | Instruction Type: CVI_VA_DV |
| 2811 | Execution Slots: SLOT0123 |
| 2812 | ========================================================================== */ |
| 2813 | |
| 2814 | #define Q6_Ww_vsxt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh) |
| 2815 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2816 | |
| 2817 | #if __HVX_ARCH__ >= 60 |
| 2818 | /* ========================================================================== |
| 2819 | Assembly Syntax: Vd32.h=vshuffe(Vu32.h,Vv32.h) |
| 2820 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2821 | Instruction Type: CVI_VA |
| 2822 | Execution Slots: SLOT0123 |
| 2823 | ========================================================================== */ |
| 2824 | |
| 2825 | #define Q6_Vh_vshuffe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh) |
| 2826 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2827 | |
| 2828 | #if __HVX_ARCH__ >= 60 |
| 2829 | /* ========================================================================== |
| 2830 | Assembly Syntax: Vd32.b=vshuff(Vu32.b) |
| 2831 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuff_Vb(HVX_Vector Vu) |
| 2832 | Instruction Type: CVI_VP |
| 2833 | Execution Slots: SLOT0123 |
| 2834 | ========================================================================== */ |
| 2835 | |
| 2836 | #define Q6_Vb_vshuff_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb) |
| 2837 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2838 | |
| 2839 | #if __HVX_ARCH__ >= 60 |
| 2840 | /* ========================================================================== |
| 2841 | Assembly Syntax: Vd32.b=vshuffe(Vu32.b,Vv32.b) |
| 2842 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2843 | Instruction Type: CVI_VA |
| 2844 | Execution Slots: SLOT0123 |
| 2845 | ========================================================================== */ |
| 2846 | |
| 2847 | #define Q6_Vb_vshuffe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb) |
| 2848 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2849 | |
| 2850 | #if __HVX_ARCH__ >= 60 |
| 2851 | /* ========================================================================== |
| 2852 | Assembly Syntax: Vd32.h=vshuff(Vu32.h) |
| 2853 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuff_Vh(HVX_Vector Vu) |
| 2854 | Instruction Type: CVI_VP |
| 2855 | Execution Slots: SLOT0123 |
| 2856 | ========================================================================== */ |
| 2857 | |
| 2858 | #define Q6_Vh_vshuff_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh) |
| 2859 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2860 | |
| 2861 | #if __HVX_ARCH__ >= 60 |
| 2862 | /* ========================================================================== |
| 2863 | Assembly Syntax: Vd32.b=vshuffo(Vu32.b,Vv32.b) |
| 2864 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vshuffo_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2865 | Instruction Type: CVI_VA |
| 2866 | Execution Slots: SLOT0123 |
| 2867 | ========================================================================== */ |
| 2868 | |
| 2869 | #define Q6_Vb_vshuffo_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob) |
| 2870 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2871 | |
| 2872 | #if __HVX_ARCH__ >= 60 |
| 2873 | /* ========================================================================== |
| 2874 | Assembly Syntax: Vdd32=vshuff(Vu32,Vv32,Rt8) |
| 2875 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vshuff_VVR(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 2876 | Instruction Type: CVI_VP_VS |
| 2877 | Execution Slots: SLOT0123 |
| 2878 | ========================================================================== */ |
| 2879 | |
| 2880 | #define Q6_W_vshuff_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd) |
| 2881 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2882 | |
| 2883 | #if __HVX_ARCH__ >= 60 |
| 2884 | /* ========================================================================== |
| 2885 | Assembly Syntax: Vdd32.b=vshuffoe(Vu32.b,Vv32.b) |
| 2886 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vshuffoe_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2887 | Instruction Type: CVI_VA_DV |
| 2888 | Execution Slots: SLOT0123 |
| 2889 | ========================================================================== */ |
| 2890 | |
| 2891 | #define Q6_Wb_vshuffoe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb) |
| 2892 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2893 | |
| 2894 | #if __HVX_ARCH__ >= 60 |
| 2895 | /* ========================================================================== |
| 2896 | Assembly Syntax: Vdd32.h=vshuffoe(Vu32.h,Vv32.h) |
| 2897 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vshuffoe_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2898 | Instruction Type: CVI_VA_DV |
| 2899 | Execution Slots: SLOT0123 |
| 2900 | ========================================================================== */ |
| 2901 | |
| 2902 | #define Q6_Wh_vshuffoe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh) |
| 2903 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2904 | |
| 2905 | #if __HVX_ARCH__ >= 60 |
| 2906 | /* ========================================================================== |
| 2907 | Assembly Syntax: Vd32.h=vshuffo(Vu32.h,Vv32.h) |
| 2908 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vshuffo_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2909 | Instruction Type: CVI_VA |
| 2910 | Execution Slots: SLOT0123 |
| 2911 | ========================================================================== */ |
| 2912 | |
| 2913 | #define Q6_Vh_vshuffo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh) |
| 2914 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2915 | |
| 2916 | #if __HVX_ARCH__ >= 60 |
| 2917 | /* ========================================================================== |
| 2918 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b) |
| 2919 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 2920 | Instruction Type: CVI_VA |
| 2921 | Execution Slots: SLOT0123 |
| 2922 | ========================================================================== */ |
| 2923 | |
| 2924 | #define Q6_Vb_vsub_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb) |
| 2925 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2926 | |
| 2927 | #if __HVX_ARCH__ >= 60 |
| 2928 | /* ========================================================================== |
| 2929 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b) |
| 2930 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2931 | Instruction Type: CVI_VA_DV |
| 2932 | Execution Slots: SLOT0123 |
| 2933 | ========================================================================== */ |
| 2934 | |
| 2935 | #define Q6_Wb_vsub_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv) |
| 2936 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2937 | |
| 2938 | #if __HVX_ARCH__ >= 60 |
| 2939 | /* ========================================================================== |
| 2940 | Assembly Syntax: if (!Qv4) Vx32.b-=Vu32.b |
| 2941 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2942 | Instruction Type: CVI_VA |
| 2943 | Execution Slots: SLOT0123 |
| 2944 | ========================================================================== */ |
| 2945 | |
| 2946 | #define Q6_Vb_condnac_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq) |
| 2947 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2948 | |
| 2949 | #if __HVX_ARCH__ >= 60 |
| 2950 | /* ========================================================================== |
| 2951 | Assembly Syntax: if (Qv4) Vx32.b-=Vu32.b |
| 2952 | C Intrinsic Prototype: HVX_Vector Q6_Vb_condnac_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2953 | Instruction Type: CVI_VA |
| 2954 | Execution Slots: SLOT0123 |
| 2955 | ========================================================================== */ |
| 2956 | |
| 2957 | #define Q6_Vb_condnac_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq) |
| 2958 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2959 | |
| 2960 | #if __HVX_ARCH__ >= 60 |
| 2961 | /* ========================================================================== |
| 2962 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h) |
| 2963 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 2964 | Instruction Type: CVI_VA |
| 2965 | Execution Slots: SLOT0123 |
| 2966 | ========================================================================== */ |
| 2967 | |
| 2968 | #define Q6_Vh_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh) |
| 2969 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2970 | |
| 2971 | #if __HVX_ARCH__ >= 60 |
| 2972 | /* ========================================================================== |
| 2973 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h) |
| 2974 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 2975 | Instruction Type: CVI_VA_DV |
| 2976 | Execution Slots: SLOT0123 |
| 2977 | ========================================================================== */ |
| 2978 | |
| 2979 | #define Q6_Wh_vsub_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv) |
| 2980 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2981 | |
| 2982 | #if __HVX_ARCH__ >= 60 |
| 2983 | /* ========================================================================== |
| 2984 | Assembly Syntax: if (!Qv4) Vx32.h-=Vu32.h |
| 2985 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2986 | Instruction Type: CVI_VA |
| 2987 | Execution Slots: SLOT0123 |
| 2988 | ========================================================================== */ |
| 2989 | |
| 2990 | #define Q6_Vh_condnac_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq) |
| 2991 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 2992 | |
| 2993 | #if __HVX_ARCH__ >= 60 |
| 2994 | /* ========================================================================== |
| 2995 | Assembly Syntax: if (Qv4) Vx32.h-=Vu32.h |
| 2996 | C Intrinsic Prototype: HVX_Vector Q6_Vh_condnac_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 2997 | Instruction Type: CVI_VA |
| 2998 | Execution Slots: SLOT0123 |
| 2999 | ========================================================================== */ |
| 3000 | |
| 3001 | #define Q6_Vh_condnac_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq) |
| 3002 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3003 | |
| 3004 | #if __HVX_ARCH__ >= 60 |
| 3005 | /* ========================================================================== |
| 3006 | Assembly Syntax: Vd32.h=vsub(Vu32.h,Vv32.h):sat |
| 3007 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsub_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3008 | Instruction Type: CVI_VA |
| 3009 | Execution Slots: SLOT0123 |
| 3010 | ========================================================================== */ |
| 3011 | |
| 3012 | #define Q6_Vh_vsub_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat) |
| 3013 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3014 | |
| 3015 | #if __HVX_ARCH__ >= 60 |
| 3016 | /* ========================================================================== |
| 3017 | Assembly Syntax: Vdd32.h=vsub(Vuu32.h,Vvv32.h):sat |
| 3018 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3019 | Instruction Type: CVI_VA_DV |
| 3020 | Execution Slots: SLOT0123 |
| 3021 | ========================================================================== */ |
| 3022 | |
| 3023 | #define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv) |
| 3024 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3025 | |
| 3026 | #if __HVX_ARCH__ >= 60 |
| 3027 | /* ========================================================================== |
| 3028 | Assembly Syntax: Vdd32.w=vsub(Vu32.h,Vv32.h) |
| 3029 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 3030 | Instruction Type: CVI_VX_DV |
| 3031 | Execution Slots: SLOT23 |
| 3032 | ========================================================================== */ |
| 3033 | |
| 3034 | #define Q6_Ww_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw) |
| 3035 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3036 | |
| 3037 | #if __HVX_ARCH__ >= 60 |
| 3038 | /* ========================================================================== |
| 3039 | Assembly Syntax: Vdd32.h=vsub(Vu32.ub,Vv32.ub) |
| 3040 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vsub_VubVub(HVX_Vector Vu, HVX_Vector Vv) |
| 3041 | Instruction Type: CVI_VX_DV |
| 3042 | Execution Slots: SLOT23 |
| 3043 | ========================================================================== */ |
| 3044 | |
| 3045 | #define Q6_Wh_vsub_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh) |
| 3046 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3047 | |
| 3048 | #if __HVX_ARCH__ >= 60 |
| 3049 | /* ========================================================================== |
| 3050 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.ub):sat |
| 3051 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3052 | Instruction Type: CVI_VA |
| 3053 | Execution Slots: SLOT0123 |
| 3054 | ========================================================================== */ |
| 3055 | |
| 3056 | #define Q6_Vub_vsub_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat) |
| 3057 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3058 | |
| 3059 | #if __HVX_ARCH__ >= 60 |
| 3060 | /* ========================================================================== |
| 3061 | Assembly Syntax: Vdd32.ub=vsub(Vuu32.ub,Vvv32.ub):sat |
| 3062 | C Intrinsic Prototype: HVX_VectorPair Q6_Wub_vsub_WubWub_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3063 | Instruction Type: CVI_VA_DV |
| 3064 | Execution Slots: SLOT0123 |
| 3065 | ========================================================================== */ |
| 3066 | |
| 3067 | #define Q6_Wub_vsub_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv) |
| 3068 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3069 | |
| 3070 | #if __HVX_ARCH__ >= 60 |
| 3071 | /* ========================================================================== |
| 3072 | Assembly Syntax: Vd32.uh=vsub(Vu32.uh,Vv32.uh):sat |
| 3073 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsub_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3074 | Instruction Type: CVI_VA |
| 3075 | Execution Slots: SLOT0123 |
| 3076 | ========================================================================== */ |
| 3077 | |
| 3078 | #define Q6_Vuh_vsub_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat) |
| 3079 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3080 | |
| 3081 | #if __HVX_ARCH__ >= 60 |
| 3082 | /* ========================================================================== |
| 3083 | Assembly Syntax: Vdd32.uh=vsub(Vuu32.uh,Vvv32.uh):sat |
| 3084 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vsub_WuhWuh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3085 | Instruction Type: CVI_VA_DV |
| 3086 | Execution Slots: SLOT0123 |
| 3087 | ========================================================================== */ |
| 3088 | |
| 3089 | #define Q6_Wuh_vsub_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv) |
| 3090 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3091 | |
| 3092 | #if __HVX_ARCH__ >= 60 |
| 3093 | /* ========================================================================== |
| 3094 | Assembly Syntax: Vdd32.w=vsub(Vu32.uh,Vv32.uh) |
| 3095 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_VuhVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 3096 | Instruction Type: CVI_VX_DV |
| 3097 | Execution Slots: SLOT23 |
| 3098 | ========================================================================== */ |
| 3099 | |
| 3100 | #define Q6_Ww_vsub_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw) |
| 3101 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3102 | |
| 3103 | #if __HVX_ARCH__ >= 60 |
| 3104 | /* ========================================================================== |
| 3105 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w) |
| 3106 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 3107 | Instruction Type: CVI_VA |
| 3108 | Execution Slots: SLOT0123 |
| 3109 | ========================================================================== */ |
| 3110 | |
| 3111 | #define Q6_Vw_vsub_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw) |
| 3112 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3113 | |
| 3114 | #if __HVX_ARCH__ >= 60 |
| 3115 | /* ========================================================================== |
| 3116 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w) |
| 3117 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3118 | Instruction Type: CVI_VA_DV |
| 3119 | Execution Slots: SLOT0123 |
| 3120 | ========================================================================== */ |
| 3121 | |
| 3122 | #define Q6_Ww_vsub_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv) |
| 3123 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3124 | |
| 3125 | #if __HVX_ARCH__ >= 60 |
| 3126 | /* ========================================================================== |
| 3127 | Assembly Syntax: if (!Qv4) Vx32.w-=Vu32.w |
| 3128 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QnVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 3129 | Instruction Type: CVI_VA |
| 3130 | Execution Slots: SLOT0123 |
| 3131 | ========================================================================== */ |
| 3132 | |
| 3133 | #define Q6_Vw_condnac_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq) |
| 3134 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3135 | |
| 3136 | #if __HVX_ARCH__ >= 60 |
| 3137 | /* ========================================================================== |
| 3138 | Assembly Syntax: if (Qv4) Vx32.w-=Vu32.w |
| 3139 | C Intrinsic Prototype: HVX_Vector Q6_Vw_condnac_QVwVw(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu) |
| 3140 | Instruction Type: CVI_VA |
| 3141 | Execution Slots: SLOT0123 |
| 3142 | ========================================================================== */ |
| 3143 | |
| 3144 | #define Q6_Vw_condnac_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq) |
| 3145 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3146 | |
| 3147 | #if __HVX_ARCH__ >= 60 |
| 3148 | /* ========================================================================== |
| 3149 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w):sat |
| 3150 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3151 | Instruction Type: CVI_VA |
| 3152 | Execution Slots: SLOT0123 |
| 3153 | ========================================================================== */ |
| 3154 | |
| 3155 | #define Q6_Vw_vsub_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat) |
| 3156 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3157 | |
| 3158 | #if __HVX_ARCH__ >= 60 |
| 3159 | /* ========================================================================== |
| 3160 | Assembly Syntax: Vdd32.w=vsub(Vuu32.w,Vvv32.w):sat |
| 3161 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vsub_WwWw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3162 | Instruction Type: CVI_VA_DV |
| 3163 | Execution Slots: SLOT0123 |
| 3164 | ========================================================================== */ |
| 3165 | |
| 3166 | #define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv) |
| 3167 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3168 | |
| 3169 | #if __HVX_ARCH__ >= 60 |
| 3170 | /* ========================================================================== |
| 3171 | Assembly Syntax: Vdd32=vswap(Qt4,Vu32,Vv32) |
| 3172 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vswap_QVV(HVX_VectorPred Qt, HVX_Vector Vu, HVX_Vector Vv) |
| 3173 | Instruction Type: CVI_VA_DV |
| 3174 | Execution Slots: SLOT0123 |
| 3175 | ========================================================================== */ |
| 3176 | |
| 3177 | #define Q6_W_vswap_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap) |
| 3178 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3179 | |
| 3180 | #if __HVX_ARCH__ >= 60 |
| 3181 | /* ========================================================================== |
| 3182 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.b,Rt32.b) |
| 3183 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WbRb(HVX_VectorPair Vuu, Word32 Rt) |
| 3184 | Instruction Type: CVI_VX_DV |
| 3185 | Execution Slots: SLOT23 |
| 3186 | ========================================================================== */ |
| 3187 | |
| 3188 | #define Q6_Wh_vtmpy_WbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb) |
| 3189 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3190 | |
| 3191 | #if __HVX_ARCH__ >= 60 |
| 3192 | /* ========================================================================== |
| 3193 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.b,Rt32.b) |
| 3194 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWbRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3195 | Instruction Type: CVI_VX_DV |
| 3196 | Execution Slots: SLOT23 |
| 3197 | ========================================================================== */ |
| 3198 | |
| 3199 | #define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc) |
| 3200 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3201 | |
| 3202 | #if __HVX_ARCH__ >= 60 |
| 3203 | /* ========================================================================== |
| 3204 | Assembly Syntax: Vdd32.h=vtmpy(Vuu32.ub,Rt32.b) |
| 3205 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpy_WubRb(HVX_VectorPair Vuu, Word32 Rt) |
| 3206 | Instruction Type: CVI_VX_DV |
| 3207 | Execution Slots: SLOT23 |
| 3208 | ========================================================================== */ |
| 3209 | |
| 3210 | #define Q6_Wh_vtmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus) |
| 3211 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3212 | |
| 3213 | #if __HVX_ARCH__ >= 60 |
| 3214 | /* ========================================================================== |
| 3215 | Assembly Syntax: Vxx32.h+=vtmpy(Vuu32.ub,Rt32.b) |
| 3216 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vtmpyacc_WhWubRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3217 | Instruction Type: CVI_VX_DV |
| 3218 | Execution Slots: SLOT23 |
| 3219 | ========================================================================== */ |
| 3220 | |
| 3221 | #define Q6_Wh_vtmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc) |
| 3222 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3223 | |
| 3224 | #if __HVX_ARCH__ >= 60 |
| 3225 | /* ========================================================================== |
| 3226 | Assembly Syntax: Vdd32.w=vtmpy(Vuu32.h,Rt32.b) |
| 3227 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpy_WhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 3228 | Instruction Type: CVI_VX_DV |
| 3229 | Execution Slots: SLOT23 |
| 3230 | ========================================================================== */ |
| 3231 | |
| 3232 | #define Q6_Ww_vtmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb) |
| 3233 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3234 | |
| 3235 | #if __HVX_ARCH__ >= 60 |
| 3236 | /* ========================================================================== |
| 3237 | Assembly Syntax: Vxx32.w+=vtmpy(Vuu32.h,Rt32.b) |
| 3238 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vtmpyacc_WwWhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3239 | Instruction Type: CVI_VX_DV |
| 3240 | Execution Slots: SLOT23 |
| 3241 | ========================================================================== */ |
| 3242 | |
| 3243 | #define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc) |
| 3244 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3245 | |
| 3246 | #if __HVX_ARCH__ >= 60 |
| 3247 | /* ========================================================================== |
| 3248 | Assembly Syntax: Vdd32.h=vunpack(Vu32.b) |
| 3249 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpack_Vb(HVX_Vector Vu) |
| 3250 | Instruction Type: CVI_VP_VS |
| 3251 | Execution Slots: SLOT0123 |
| 3252 | ========================================================================== */ |
| 3253 | |
| 3254 | #define Q6_Wh_vunpack_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb) |
| 3255 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3256 | |
| 3257 | #if __HVX_ARCH__ >= 60 |
| 3258 | /* ========================================================================== |
| 3259 | Assembly Syntax: Vdd32.w=vunpack(Vu32.h) |
| 3260 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpack_Vh(HVX_Vector Vu) |
| 3261 | Instruction Type: CVI_VP_VS |
| 3262 | Execution Slots: SLOT0123 |
| 3263 | ========================================================================== */ |
| 3264 | |
| 3265 | #define Q6_Ww_vunpack_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh) |
| 3266 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3267 | |
| 3268 | #if __HVX_ARCH__ >= 60 |
| 3269 | /* ========================================================================== |
| 3270 | Assembly Syntax: Vxx32.h|=vunpacko(Vu32.b) |
| 3271 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vunpackoor_WhVb(HVX_VectorPair Vxx, HVX_Vector Vu) |
| 3272 | Instruction Type: CVI_VP_VS |
| 3273 | Execution Slots: SLOT0123 |
| 3274 | ========================================================================== */ |
| 3275 | |
| 3276 | #define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob) |
| 3277 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3278 | |
| 3279 | #if __HVX_ARCH__ >= 60 |
| 3280 | /* ========================================================================== |
| 3281 | Assembly Syntax: Vxx32.w|=vunpacko(Vu32.h) |
| 3282 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vunpackoor_WwVh(HVX_VectorPair Vxx, HVX_Vector Vu) |
| 3283 | Instruction Type: CVI_VP_VS |
| 3284 | Execution Slots: SLOT0123 |
| 3285 | ========================================================================== */ |
| 3286 | |
| 3287 | #define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh) |
| 3288 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3289 | |
| 3290 | #if __HVX_ARCH__ >= 60 |
| 3291 | /* ========================================================================== |
| 3292 | Assembly Syntax: Vdd32.uh=vunpack(Vu32.ub) |
| 3293 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vunpack_Vub(HVX_Vector Vu) |
| 3294 | Instruction Type: CVI_VP_VS |
| 3295 | Execution Slots: SLOT0123 |
| 3296 | ========================================================================== */ |
| 3297 | |
| 3298 | #define Q6_Wuh_vunpack_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub) |
| 3299 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3300 | |
| 3301 | #if __HVX_ARCH__ >= 60 |
| 3302 | /* ========================================================================== |
| 3303 | Assembly Syntax: Vdd32.uw=vunpack(Vu32.uh) |
| 3304 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vunpack_Vuh(HVX_Vector Vu) |
| 3305 | Instruction Type: CVI_VP_VS |
| 3306 | Execution Slots: SLOT0123 |
| 3307 | ========================================================================== */ |
| 3308 | |
| 3309 | #define Q6_Wuw_vunpack_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh) |
| 3310 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3311 | |
| 3312 | #if __HVX_ARCH__ >= 60 |
| 3313 | /* ========================================================================== |
| 3314 | Assembly Syntax: Vd32=vxor(Vu32,Vv32) |
| 3315 | C Intrinsic Prototype: HVX_Vector Q6_V_vxor_VV(HVX_Vector Vu, HVX_Vector Vv) |
| 3316 | Instruction Type: CVI_VA |
| 3317 | Execution Slots: SLOT0123 |
| 3318 | ========================================================================== */ |
| 3319 | |
| 3320 | #define Q6_V_vxor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor) |
| 3321 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3322 | |
| 3323 | #if __HVX_ARCH__ >= 60 |
| 3324 | /* ========================================================================== |
| 3325 | Assembly Syntax: Vdd32.uh=vzxt(Vu32.ub) |
| 3326 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuh_vzxt_Vub(HVX_Vector Vu) |
| 3327 | Instruction Type: CVI_VA_DV |
| 3328 | Execution Slots: SLOT0123 |
| 3329 | ========================================================================== */ |
| 3330 | |
| 3331 | #define Q6_Wuh_vzxt_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb) |
| 3332 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3333 | |
| 3334 | #if __HVX_ARCH__ >= 60 |
| 3335 | /* ========================================================================== |
| 3336 | Assembly Syntax: Vdd32.uw=vzxt(Vu32.uh) |
| 3337 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vzxt_Vuh(HVX_Vector Vu) |
| 3338 | Instruction Type: CVI_VA_DV |
| 3339 | Execution Slots: SLOT0123 |
| 3340 | ========================================================================== */ |
| 3341 | |
| 3342 | #define Q6_Wuw_vzxt_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh) |
| 3343 | #endif /* __HEXAGON_ARCH___ >= 60 */ |
| 3344 | |
| 3345 | #if __HVX_ARCH__ >= 62 |
| 3346 | /* ========================================================================== |
| 3347 | Assembly Syntax: Vd32.b=vsplat(Rt32) |
| 3348 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsplat_R(Word32 Rt) |
| 3349 | Instruction Type: CVI_VX_LATE |
| 3350 | Execution Slots: SLOT23 |
| 3351 | ========================================================================== */ |
| 3352 | |
| 3353 | #define Q6_Vb_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb) |
| 3354 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3355 | |
| 3356 | #if __HVX_ARCH__ >= 62 |
| 3357 | /* ========================================================================== |
| 3358 | Assembly Syntax: Vd32.h=vsplat(Rt32) |
| 3359 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vsplat_R(Word32 Rt) |
| 3360 | Instruction Type: CVI_VX_LATE |
| 3361 | Execution Slots: SLOT23 |
| 3362 | ========================================================================== */ |
| 3363 | |
| 3364 | #define Q6_Vh_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath) |
| 3365 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3366 | |
| 3367 | #if __HVX_ARCH__ >= 62 |
| 3368 | /* ========================================================================== |
| 3369 | Assembly Syntax: Qd4=vsetq2(Rt32) |
| 3370 | C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq2_R(Word32 Rt) |
| 3371 | Instruction Type: CVI_VP |
| 3372 | Execution Slots: SLOT0123 |
| 3373 | ========================================================================== */ |
| 3374 | |
| 3375 | #define Q6_Q_vsetq2_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2) |
| 3376 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3377 | |
| 3378 | #if __HVX_ARCH__ >= 62 |
| 3379 | /* ========================================================================== |
| 3380 | Assembly Syntax: Qd4.b=vshuffe(Qs4.h,Qt4.h) |
| 3381 | C Intrinsic Prototype: HVX_VectorPred Q6_Qb_vshuffe_QhQh(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 3382 | Instruction Type: CVI_VA_DV |
| 3383 | Execution Slots: SLOT0123 |
| 3384 | ========================================================================== */ |
| 3385 | |
| 3386 | #define Q6_Qb_vshuffe_QhQh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh) |
| 3387 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3388 | |
| 3389 | #if __HVX_ARCH__ >= 62 |
| 3390 | /* ========================================================================== |
| 3391 | Assembly Syntax: Qd4.h=vshuffe(Qs4.w,Qt4.w) |
| 3392 | C Intrinsic Prototype: HVX_VectorPred Q6_Qh_vshuffe_QwQw(HVX_VectorPred Qs, HVX_VectorPred Qt) |
| 3393 | Instruction Type: CVI_VA_DV |
| 3394 | Execution Slots: SLOT0123 |
| 3395 | ========================================================================== */ |
| 3396 | |
| 3397 | #define Q6_Qh_vshuffe_QwQw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw) |
| 3398 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3399 | |
| 3400 | #if __HVX_ARCH__ >= 62 |
| 3401 | /* ========================================================================== |
| 3402 | Assembly Syntax: Vd32.b=vadd(Vu32.b,Vv32.b):sat |
| 3403 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3404 | Instruction Type: CVI_VA |
| 3405 | Execution Slots: SLOT0123 |
| 3406 | ========================================================================== */ |
| 3407 | |
| 3408 | #define Q6_Vb_vadd_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat) |
| 3409 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3410 | |
| 3411 | #if __HVX_ARCH__ >= 62 |
| 3412 | /* ========================================================================== |
| 3413 | Assembly Syntax: Vdd32.b=vadd(Vuu32.b,Vvv32.b):sat |
| 3414 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3415 | Instruction Type: CVI_VA_DV |
| 3416 | Execution Slots: SLOT0123 |
| 3417 | ========================================================================== */ |
| 3418 | |
| 3419 | #define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv) |
| 3420 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3421 | |
| 3422 | #if __HVX_ARCH__ >= 62 |
| 3423 | /* ========================================================================== |
| 3424 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qx4):carry |
| 3425 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
| 3426 | Instruction Type: CVI_VA |
| 3427 | Execution Slots: SLOT0123 |
| 3428 | ========================================================================== */ |
| 3429 | |
| 3430 | #define Q6_Vw_vadd_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry) |
| 3431 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3432 | |
| 3433 | #if __HVX_ARCH__ >= 62 |
| 3434 | /* ========================================================================== |
| 3435 | Assembly Syntax: Vd32.h=vadd(vclb(Vu32.h),Vv32.h) |
| 3436 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_vclb_VhVh(HVX_Vector Vu, HVX_Vector Vv) |
| 3437 | Instruction Type: CVI_VS |
| 3438 | Execution Slots: SLOT0123 |
| 3439 | ========================================================================== */ |
| 3440 | |
| 3441 | #define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh) |
| 3442 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3443 | |
| 3444 | #if __HVX_ARCH__ >= 62 |
| 3445 | /* ========================================================================== |
| 3446 | Assembly Syntax: Vd32.w=vadd(vclb(Vu32.w),Vv32.w) |
| 3447 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_vclb_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 3448 | Instruction Type: CVI_VS |
| 3449 | Execution Slots: SLOT0123 |
| 3450 | ========================================================================== */ |
| 3451 | |
| 3452 | #define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw) |
| 3453 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3454 | |
| 3455 | #if __HVX_ARCH__ >= 62 |
| 3456 | /* ========================================================================== |
| 3457 | Assembly Syntax: Vxx32.w+=vadd(Vu32.h,Vv32.h) |
| 3458 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVhVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3459 | Instruction Type: CVI_VX_DV |
| 3460 | Execution Slots: SLOT23 |
| 3461 | ========================================================================== */ |
| 3462 | |
| 3463 | #define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc) |
| 3464 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3465 | |
| 3466 | #if __HVX_ARCH__ >= 62 |
| 3467 | /* ========================================================================== |
| 3468 | Assembly Syntax: Vxx32.h+=vadd(Vu32.ub,Vv32.ub) |
| 3469 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vaddacc_WhVubVub(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3470 | Instruction Type: CVI_VX_DV |
| 3471 | Execution Slots: SLOT23 |
| 3472 | ========================================================================== */ |
| 3473 | |
| 3474 | #define Q6_Wh_vaddacc_WhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc) |
| 3475 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3476 | |
| 3477 | #if __HVX_ARCH__ >= 62 |
| 3478 | /* ========================================================================== |
| 3479 | Assembly Syntax: Vd32.ub=vadd(Vu32.ub,Vv32.b):sat |
| 3480 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3481 | Instruction Type: CVI_VA |
| 3482 | Execution Slots: SLOT0123 |
| 3483 | ========================================================================== */ |
| 3484 | |
| 3485 | #define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat) |
| 3486 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3487 | |
| 3488 | #if __HVX_ARCH__ >= 62 |
| 3489 | /* ========================================================================== |
| 3490 | Assembly Syntax: Vxx32.w+=vadd(Vu32.uh,Vv32.uh) |
| 3491 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vaddacc_WwVuhVuh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3492 | Instruction Type: CVI_VX_DV |
| 3493 | Execution Slots: SLOT23 |
| 3494 | ========================================================================== */ |
| 3495 | |
| 3496 | #define Q6_Ww_vaddacc_WwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc) |
| 3497 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3498 | |
| 3499 | #if __HVX_ARCH__ >= 62 |
| 3500 | /* ========================================================================== |
| 3501 | Assembly Syntax: Vd32.uw=vadd(Vu32.uw,Vv32.uw):sat |
| 3502 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vadd_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3503 | Instruction Type: CVI_VA |
| 3504 | Execution Slots: SLOT0123 |
| 3505 | ========================================================================== */ |
| 3506 | |
| 3507 | #define Q6_Vuw_vadd_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat) |
| 3508 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3509 | |
| 3510 | #if __HVX_ARCH__ >= 62 |
| 3511 | /* ========================================================================== |
| 3512 | Assembly Syntax: Vdd32.uw=vadd(Vuu32.uw,Vvv32.uw):sat |
| 3513 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vadd_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3514 | Instruction Type: CVI_VA_DV |
| 3515 | Execution Slots: SLOT0123 |
| 3516 | ========================================================================== */ |
| 3517 | |
| 3518 | #define Q6_Wuw_vadd_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv) |
| 3519 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3520 | |
| 3521 | #if __HVX_ARCH__ >= 62 |
| 3522 | /* ========================================================================== |
| 3523 | Assembly Syntax: Vd32=vand(!Qu4,Rt32) |
| 3524 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnR(HVX_VectorPred Qu, Word32 Rt) |
| 3525 | Instruction Type: CVI_VX_LATE |
| 3526 | Execution Slots: SLOT23 |
| 3527 | ========================================================================== */ |
| 3528 | |
| 3529 | #define Q6_V_vand_QnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt) |
| 3530 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3531 | |
| 3532 | #if __HVX_ARCH__ >= 62 |
| 3533 | /* ========================================================================== |
| 3534 | Assembly Syntax: Vx32|=vand(!Qu4,Rt32) |
| 3535 | C Intrinsic Prototype: HVX_Vector Q6_V_vandor_VQnR(HVX_Vector Vx, HVX_VectorPred Qu, Word32 Rt) |
| 3536 | Instruction Type: CVI_VX_LATE |
| 3537 | Execution Slots: SLOT23 |
| 3538 | ========================================================================== */ |
| 3539 | |
| 3540 | #define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc) |
| 3541 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3542 | |
| 3543 | #if __HVX_ARCH__ >= 62 |
| 3544 | /* ========================================================================== |
| 3545 | Assembly Syntax: Vd32=vand(!Qv4,Vu32) |
| 3546 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QnV(HVX_VectorPred Qv, HVX_Vector Vu) |
| 3547 | Instruction Type: CVI_VA |
| 3548 | Execution Slots: SLOT0123 |
| 3549 | ========================================================================== */ |
| 3550 | |
| 3551 | #define Q6_V_vand_QnV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv) |
| 3552 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3553 | |
| 3554 | #if __HVX_ARCH__ >= 62 |
| 3555 | /* ========================================================================== |
| 3556 | Assembly Syntax: Vd32=vand(Qv4,Vu32) |
| 3557 | C Intrinsic Prototype: HVX_Vector Q6_V_vand_QV(HVX_VectorPred Qv, HVX_Vector Vu) |
| 3558 | Instruction Type: CVI_VA |
| 3559 | Execution Slots: SLOT0123 |
| 3560 | ========================================================================== */ |
| 3561 | |
| 3562 | #define Q6_V_vand_QV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv) |
| 3563 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3564 | |
| 3565 | #if __HVX_ARCH__ >= 62 |
| 3566 | /* ========================================================================== |
| 3567 | Assembly Syntax: Vd32.b=vasr(Vu32.h,Vv32.h,Rt8):sat |
| 3568 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vasr_VhVhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3569 | Instruction Type: CVI_VS |
| 3570 | Execution Slots: SLOT0123 |
| 3571 | ========================================================================== */ |
| 3572 | |
| 3573 | #define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat) |
| 3574 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3575 | |
| 3576 | #if __HVX_ARCH__ >= 62 |
| 3577 | /* ========================================================================== |
| 3578 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):rnd:sat |
| 3579 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3580 | Instruction Type: CVI_VS |
| 3581 | Execution Slots: SLOT0123 |
| 3582 | ========================================================================== */ |
| 3583 | |
| 3584 | #define Q6_Vuh_vasr_VuwVuwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat) |
| 3585 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3586 | |
| 3587 | #if __HVX_ARCH__ >= 62 |
| 3588 | /* ========================================================================== |
| 3589 | Assembly Syntax: Vd32.uh=vasr(Vu32.w,Vv32.w,Rt8):rnd:sat |
| 3590 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VwVwR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3591 | Instruction Type: CVI_VS |
| 3592 | Execution Slots: SLOT0123 |
| 3593 | ========================================================================== */ |
| 3594 | |
| 3595 | #define Q6_Vuh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat) |
| 3596 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3597 | |
| 3598 | #if __HVX_ARCH__ >= 62 |
| 3599 | /* ========================================================================== |
| 3600 | Assembly Syntax: Vd32.ub=vlsr(Vu32.ub,Rt32) |
| 3601 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vlsr_VubR(HVX_Vector Vu, Word32 Rt) |
| 3602 | Instruction Type: CVI_VS |
| 3603 | Execution Slots: SLOT0123 |
| 3604 | ========================================================================== */ |
| 3605 | |
| 3606 | #define Q6_Vub_vlsr_VubR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb) |
| 3607 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3608 | |
| 3609 | #if __HVX_ARCH__ >= 62 |
| 3610 | /* ========================================================================== |
| 3611 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,Rt8):nomatch |
| 3612 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3613 | Instruction Type: CVI_VP |
| 3614 | Execution Slots: SLOT0123 |
| 3615 | ========================================================================== */ |
| 3616 | |
| 3617 | #define Q6_Vb_vlut32_VbVbR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm) |
| 3618 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3619 | |
| 3620 | #if __HVX_ARCH__ >= 62 |
| 3621 | /* ========================================================================== |
| 3622 | Assembly Syntax: Vx32.b|=vlut32(Vu32.b,Vv32.b,#u3) |
| 3623 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32or_VbVbVbI(HVX_Vector Vx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3624 | Instruction Type: CVI_VP_VS |
| 3625 | Execution Slots: SLOT0123 |
| 3626 | ========================================================================== */ |
| 3627 | |
| 3628 | #define Q6_Vb_vlut32or_VbVbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci) |
| 3629 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3630 | |
| 3631 | #if __HVX_ARCH__ >= 62 |
| 3632 | /* ========================================================================== |
| 3633 | Assembly Syntax: Vd32.b=vlut32(Vu32.b,Vv32.b,#u3) |
| 3634 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vlut32_VbVbI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3635 | Instruction Type: CVI_VP |
| 3636 | Execution Slots: SLOT0123 |
| 3637 | ========================================================================== */ |
| 3638 | |
| 3639 | #define Q6_Vb_vlut32_VbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi) |
| 3640 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3641 | |
| 3642 | #if __HVX_ARCH__ >= 62 |
| 3643 | /* ========================================================================== |
| 3644 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,Rt8):nomatch |
| 3645 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhR_nomatch(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3646 | Instruction Type: CVI_VP_VS |
| 3647 | Execution Slots: SLOT0123 |
| 3648 | ========================================================================== */ |
| 3649 | |
| 3650 | #define Q6_Wh_vlut16_VbVhR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm) |
| 3651 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3652 | |
| 3653 | #if __HVX_ARCH__ >= 62 |
| 3654 | /* ========================================================================== |
| 3655 | Assembly Syntax: Vxx32.h|=vlut16(Vu32.b,Vv32.h,#u3) |
| 3656 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16or_WhVbVhI(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3657 | Instruction Type: CVI_VP_VS |
| 3658 | Execution Slots: SLOT0123 |
| 3659 | ========================================================================== */ |
| 3660 | |
| 3661 | #define Q6_Wh_vlut16or_WhVbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci) |
| 3662 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3663 | |
| 3664 | #if __HVX_ARCH__ >= 62 |
| 3665 | /* ========================================================================== |
| 3666 | Assembly Syntax: Vdd32.h=vlut16(Vu32.b,Vv32.h,#u3) |
| 3667 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vlut16_VbVhI(HVX_Vector Vu, HVX_Vector Vv, Word32 Iu3) |
| 3668 | Instruction Type: CVI_VP_VS |
| 3669 | Execution Slots: SLOT0123 |
| 3670 | ========================================================================== */ |
| 3671 | |
| 3672 | #define Q6_Wh_vlut16_VbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi) |
| 3673 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3674 | |
| 3675 | #if __HVX_ARCH__ >= 62 |
| 3676 | /* ========================================================================== |
| 3677 | Assembly Syntax: Vd32.b=vmax(Vu32.b,Vv32.b) |
| 3678 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmax_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3679 | Instruction Type: CVI_VA |
| 3680 | Execution Slots: SLOT0123 |
| 3681 | ========================================================================== */ |
| 3682 | |
| 3683 | #define Q6_Vb_vmax_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb) |
| 3684 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3685 | |
| 3686 | #if __HVX_ARCH__ >= 62 |
| 3687 | /* ========================================================================== |
| 3688 | Assembly Syntax: Vd32.b=vmin(Vu32.b,Vv32.b) |
| 3689 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vmin_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3690 | Instruction Type: CVI_VA |
| 3691 | Execution Slots: SLOT0123 |
| 3692 | ========================================================================== */ |
| 3693 | |
| 3694 | #define Q6_Vb_vmin_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb) |
| 3695 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3696 | |
| 3697 | #if __HVX_ARCH__ >= 62 |
| 3698 | /* ========================================================================== |
| 3699 | Assembly Syntax: Vdd32.w=vmpa(Vuu32.uh,Rt32.b) |
| 3700 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpa_WuhRb(HVX_VectorPair Vuu, Word32 Rt) |
| 3701 | Instruction Type: CVI_VX_DV |
| 3702 | Execution Slots: SLOT23 |
| 3703 | ========================================================================== */ |
| 3704 | |
| 3705 | #define Q6_Ww_vmpa_WuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb) |
| 3706 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3707 | |
| 3708 | #if __HVX_ARCH__ >= 62 |
| 3709 | /* ========================================================================== |
| 3710 | Assembly Syntax: Vxx32.w+=vmpa(Vuu32.uh,Rt32.b) |
| 3711 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpaacc_WwWuhRb(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 3712 | Instruction Type: CVI_VX_DV |
| 3713 | Execution Slots: SLOT23 |
| 3714 | ========================================================================== */ |
| 3715 | |
| 3716 | #define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc) |
| 3717 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3718 | |
| 3719 | #if __HVX_ARCH__ >= 62 |
| 3720 | /* ========================================================================== |
| 3721 | Assembly Syntax: Vdd32=vmpye(Vu32.w,Vv32.uh) |
| 3722 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpye_VwVuh(HVX_Vector Vu, HVX_Vector Vv) |
| 3723 | Instruction Type: CVI_VX_DV |
| 3724 | Execution Slots: SLOT23 |
| 3725 | ========================================================================== */ |
| 3726 | |
| 3727 | #define Q6_W_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64) |
| 3728 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3729 | |
| 3730 | #if __HVX_ARCH__ >= 62 |
| 3731 | /* ========================================================================== |
| 3732 | Assembly Syntax: Vd32.w=vmpyi(Vu32.w,Rt32.ub) |
| 3733 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyi_VwRub(HVX_Vector Vu, Word32 Rt) |
| 3734 | Instruction Type: CVI_VX |
| 3735 | Execution Slots: SLOT23 |
| 3736 | ========================================================================== */ |
| 3737 | |
| 3738 | #define Q6_Vw_vmpyi_VwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub) |
| 3739 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3740 | |
| 3741 | #if __HVX_ARCH__ >= 62 |
| 3742 | /* ========================================================================== |
| 3743 | Assembly Syntax: Vx32.w+=vmpyi(Vu32.w,Rt32.ub) |
| 3744 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vmpyiacc_VwVwRub(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3745 | Instruction Type: CVI_VX |
| 3746 | Execution Slots: SLOT23 |
| 3747 | ========================================================================== */ |
| 3748 | |
| 3749 | #define Q6_Vw_vmpyiacc_VwVwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc) |
| 3750 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3751 | |
| 3752 | #if __HVX_ARCH__ >= 62 |
| 3753 | /* ========================================================================== |
| 3754 | Assembly Syntax: Vxx32+=vmpyo(Vu32.w,Vv32.h) |
| 3755 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vmpyoacc_WVwVh(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 3756 | Instruction Type: CVI_VX_DV |
| 3757 | Execution Slots: SLOT23 |
| 3758 | ========================================================================== */ |
| 3759 | |
| 3760 | #define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc) |
| 3761 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3762 | |
| 3763 | #if __HVX_ARCH__ >= 62 |
| 3764 | /* ========================================================================== |
| 3765 | Assembly Syntax: Vd32.ub=vround(Vu32.uh,Vv32.uh):sat |
| 3766 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vround_VuhVuh_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3767 | Instruction Type: CVI_VS |
| 3768 | Execution Slots: SLOT0123 |
| 3769 | ========================================================================== */ |
| 3770 | |
| 3771 | #define Q6_Vub_vround_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub) |
| 3772 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3773 | |
| 3774 | #if __HVX_ARCH__ >= 62 |
| 3775 | /* ========================================================================== |
| 3776 | Assembly Syntax: Vd32.uh=vround(Vu32.uw,Vv32.uw):sat |
| 3777 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vround_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3778 | Instruction Type: CVI_VS |
| 3779 | Execution Slots: SLOT0123 |
| 3780 | ========================================================================== */ |
| 3781 | |
| 3782 | #define Q6_Vuh_vround_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh) |
| 3783 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3784 | |
| 3785 | #if __HVX_ARCH__ >= 62 |
| 3786 | /* ========================================================================== |
| 3787 | Assembly Syntax: Vd32.uh=vsat(Vu32.uw,Vv32.uw) |
| 3788 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vsat_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 3789 | Instruction Type: CVI_VA |
| 3790 | Execution Slots: SLOT0123 |
| 3791 | ========================================================================== */ |
| 3792 | |
| 3793 | #define Q6_Vuh_vsat_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh) |
| 3794 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3795 | |
| 3796 | #if __HVX_ARCH__ >= 62 |
| 3797 | /* ========================================================================== |
| 3798 | Assembly Syntax: Vd32.b=vsub(Vu32.b,Vv32.b):sat |
| 3799 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vsub_VbVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3800 | Instruction Type: CVI_VA |
| 3801 | Execution Slots: SLOT0123 |
| 3802 | ========================================================================== */ |
| 3803 | |
| 3804 | #define Q6_Vb_vsub_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat) |
| 3805 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3806 | |
| 3807 | #if __HVX_ARCH__ >= 62 |
| 3808 | /* ========================================================================== |
| 3809 | Assembly Syntax: Vdd32.b=vsub(Vuu32.b,Vvv32.b):sat |
| 3810 | C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vsub_WbWb_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3811 | Instruction Type: CVI_VA_DV |
| 3812 | Execution Slots: SLOT0123 |
| 3813 | ========================================================================== */ |
| 3814 | |
| 3815 | #define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv) |
| 3816 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3817 | |
| 3818 | #if __HVX_ARCH__ >= 62 |
| 3819 | /* ========================================================================== |
| 3820 | Assembly Syntax: Vd32.w=vsub(Vu32.w,Vv32.w,Qx4):carry |
| 3821 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsub_VwVwQ_carry(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred* Qx) |
| 3822 | Instruction Type: CVI_VA |
| 3823 | Execution Slots: SLOT0123 |
| 3824 | ========================================================================== */ |
| 3825 | |
| 3826 | #define Q6_Vw_vsub_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry) |
| 3827 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3828 | |
| 3829 | #if __HVX_ARCH__ >= 62 |
| 3830 | /* ========================================================================== |
| 3831 | Assembly Syntax: Vd32.ub=vsub(Vu32.ub,Vv32.b):sat |
| 3832 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vsub_VubVb_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3833 | Instruction Type: CVI_VA |
| 3834 | Execution Slots: SLOT0123 |
| 3835 | ========================================================================== */ |
| 3836 | |
| 3837 | #define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat) |
| 3838 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3839 | |
| 3840 | #if __HVX_ARCH__ >= 62 |
| 3841 | /* ========================================================================== |
| 3842 | Assembly Syntax: Vd32.uw=vsub(Vu32.uw,Vv32.uw):sat |
| 3843 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vsub_VuwVuw_sat(HVX_Vector Vu, HVX_Vector Vv) |
| 3844 | Instruction Type: CVI_VA |
| 3845 | Execution Slots: SLOT0123 |
| 3846 | ========================================================================== */ |
| 3847 | |
| 3848 | #define Q6_Vuw_vsub_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat) |
| 3849 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3850 | |
| 3851 | #if __HVX_ARCH__ >= 62 |
| 3852 | /* ========================================================================== |
| 3853 | Assembly Syntax: Vdd32.uw=vsub(Vuu32.uw,Vvv32.uw):sat |
| 3854 | C Intrinsic Prototype: HVX_VectorPair Q6_Wuw_vsub_WuwWuw_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv) |
| 3855 | Instruction Type: CVI_VA_DV |
| 3856 | Execution Slots: SLOT0123 |
| 3857 | ========================================================================== */ |
| 3858 | |
| 3859 | #define Q6_Wuw_vsub_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv) |
| 3860 | #endif /* __HEXAGON_ARCH___ >= 62 */ |
| 3861 | |
| 3862 | #if __HVX_ARCH__ >= 65 |
| 3863 | /* ========================================================================== |
| 3864 | Assembly Syntax: Vd32.b=vabs(Vu32.b) |
| 3865 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb(HVX_Vector Vu) |
| 3866 | Instruction Type: CVI_VA |
| 3867 | Execution Slots: SLOT0123 |
| 3868 | ========================================================================== */ |
| 3869 | |
| 3870 | #define Q6_Vb_vabs_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb) |
| 3871 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3872 | |
| 3873 | #if __HVX_ARCH__ >= 65 |
| 3874 | /* ========================================================================== |
| 3875 | Assembly Syntax: Vd32.b=vabs(Vu32.b):sat |
| 3876 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vabs_Vb_sat(HVX_Vector Vu) |
| 3877 | Instruction Type: CVI_VA |
| 3878 | Execution Slots: SLOT0123 |
| 3879 | ========================================================================== */ |
| 3880 | |
| 3881 | #define Q6_Vb_vabs_Vb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat) |
| 3882 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3883 | |
| 3884 | #if __HVX_ARCH__ >= 65 |
| 3885 | /* ========================================================================== |
| 3886 | Assembly Syntax: Vx32.h+=vasl(Vu32.h,Rt32) |
| 3887 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vaslacc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3888 | Instruction Type: CVI_VS |
| 3889 | Execution Slots: SLOT0123 |
| 3890 | ========================================================================== */ |
| 3891 | |
| 3892 | #define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc) |
| 3893 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3894 | |
| 3895 | #if __HVX_ARCH__ >= 65 |
| 3896 | /* ========================================================================== |
| 3897 | Assembly Syntax: Vx32.h+=vasr(Vu32.h,Rt32) |
| 3898 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vasracc_VhVhR(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 3899 | Instruction Type: CVI_VS |
| 3900 | Execution Slots: SLOT0123 |
| 3901 | ========================================================================== */ |
| 3902 | |
| 3903 | #define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc) |
| 3904 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3905 | |
| 3906 | #if __HVX_ARCH__ >= 65 |
| 3907 | /* ========================================================================== |
| 3908 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):rnd:sat |
| 3909 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_rnd_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3910 | Instruction Type: CVI_VS |
| 3911 | Execution Slots: SLOT0123 |
| 3912 | ========================================================================== */ |
| 3913 | |
| 3914 | #define Q6_Vub_vasr_VuhVuhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat) |
| 3915 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3916 | |
| 3917 | #if __HVX_ARCH__ >= 65 |
| 3918 | /* ========================================================================== |
| 3919 | Assembly Syntax: Vd32.ub=vasr(Vu32.uh,Vv32.uh,Rt8):sat |
| 3920 | C Intrinsic Prototype: HVX_Vector Q6_Vub_vasr_VuhVuhR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3921 | Instruction Type: CVI_VS |
| 3922 | Execution Slots: SLOT0123 |
| 3923 | ========================================================================== */ |
| 3924 | |
| 3925 | #define Q6_Vub_vasr_VuhVuhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat) |
| 3926 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3927 | |
| 3928 | #if __HVX_ARCH__ >= 65 |
| 3929 | /* ========================================================================== |
| 3930 | Assembly Syntax: Vd32.uh=vasr(Vu32.uw,Vv32.uw,Rt8):sat |
| 3931 | C Intrinsic Prototype: HVX_Vector Q6_Vuh_vasr_VuwVuwR_sat(HVX_Vector Vu, HVX_Vector Vv, Word32 Rt) |
| 3932 | Instruction Type: CVI_VS |
| 3933 | Execution Slots: SLOT0123 |
| 3934 | ========================================================================== */ |
| 3935 | |
| 3936 | #define Q6_Vuh_vasr_VuwVuwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat) |
| 3937 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3938 | |
| 3939 | #if __HVX_ARCH__ >= 65 |
| 3940 | /* ========================================================================== |
| 3941 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b) |
| 3942 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 3943 | Instruction Type: CVI_VA |
| 3944 | Execution Slots: SLOT0123 |
| 3945 | ========================================================================== */ |
| 3946 | |
| 3947 | #define Q6_Vb_vavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb) |
| 3948 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3949 | |
| 3950 | #if __HVX_ARCH__ >= 65 |
| 3951 | /* ========================================================================== |
| 3952 | Assembly Syntax: Vd32.b=vavg(Vu32.b,Vv32.b):rnd |
| 3953 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vavg_VbVb_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 3954 | Instruction Type: CVI_VA |
| 3955 | Execution Slots: SLOT0123 |
| 3956 | ========================================================================== */ |
| 3957 | |
| 3958 | #define Q6_Vb_vavg_VbVb_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd) |
| 3959 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3960 | |
| 3961 | #if __HVX_ARCH__ >= 65 |
| 3962 | /* ========================================================================== |
| 3963 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw) |
| 3964 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 3965 | Instruction Type: CVI_VA |
| 3966 | Execution Slots: SLOT0123 |
| 3967 | ========================================================================== */ |
| 3968 | |
| 3969 | #define Q6_Vuw_vavg_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw) |
| 3970 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3971 | |
| 3972 | #if __HVX_ARCH__ >= 65 |
| 3973 | /* ========================================================================== |
| 3974 | Assembly Syntax: Vd32.uw=vavg(Vu32.uw,Vv32.uw):rnd |
| 3975 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vavg_VuwVuw_rnd(HVX_Vector Vu, HVX_Vector Vv) |
| 3976 | Instruction Type: CVI_VA |
| 3977 | Execution Slots: SLOT0123 |
| 3978 | ========================================================================== */ |
| 3979 | |
| 3980 | #define Q6_Vuw_vavg_VuwVuw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd) |
| 3981 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3982 | |
| 3983 | #if __HVX_ARCH__ >= 65 |
| 3984 | /* ========================================================================== |
| 3985 | Assembly Syntax: Vdd32=#0 |
| 3986 | C Intrinsic Prototype: HVX_VectorPair Q6_W_vzero() |
| 3987 | Instruction Type: MAPPING |
| 3988 | Execution Slots: SLOT0123 |
| 3989 | ========================================================================== */ |
| 3990 | |
| 3991 | #define Q6_W_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0) |
| 3992 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 3993 | |
| 3994 | #if __HVX_ARCH__ >= 65 |
| 3995 | /* ========================================================================== |
| 3996 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
| 3997 | C Intrinsic Prototype: void Q6_vgather_ARMVh(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 3998 | Instruction Type: CVI_GATHER |
| 3999 | Execution Slots: SLOT01 |
| 4000 | ========================================================================== */ |
| 4001 | |
| 4002 | #define Q6_vgather_ARMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh) |
| 4003 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4004 | |
| 4005 | #if __HVX_ARCH__ >= 65 |
| 4006 | /* ========================================================================== |
| 4007 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vv32.h).h |
| 4008 | C Intrinsic Prototype: void Q6_vgather_AQRMVh(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 4009 | Instruction Type: CVI_GATHER |
| 4010 | Execution Slots: SLOT01 |
| 4011 | ========================================================================== */ |
| 4012 | |
| 4013 | #define Q6_vgather_AQRMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq) |
| 4014 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4015 | |
| 4016 | #if __HVX_ARCH__ >= 65 |
| 4017 | /* ========================================================================== |
| 4018 | Assembly Syntax: vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
| 4019 | C Intrinsic Prototype: void Q6_vgather_ARMWw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
| 4020 | Instruction Type: CVI_GATHER_DV |
| 4021 | Execution Slots: SLOT01 |
| 4022 | ========================================================================== */ |
| 4023 | |
| 4024 | #define Q6_vgather_ARMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw) |
| 4025 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4026 | |
| 4027 | #if __HVX_ARCH__ >= 65 |
| 4028 | /* ========================================================================== |
| 4029 | Assembly Syntax: if (Qs4) vtmp.h=vgather(Rt32,Mu2,Vvv32.w).h |
| 4030 | C Intrinsic Prototype: void Q6_vgather_AQRMWw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv) |
| 4031 | Instruction Type: CVI_GATHER_DV |
| 4032 | Execution Slots: SLOT01 |
| 4033 | ========================================================================== */ |
| 4034 | |
| 4035 | #define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq) |
| 4036 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4037 | |
| 4038 | #if __HVX_ARCH__ >= 65 |
| 4039 | /* ========================================================================== |
| 4040 | Assembly Syntax: vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
| 4041 | C Intrinsic Prototype: void Q6_vgather_ARMVw(HVX_Vector* Rs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 4042 | Instruction Type: CVI_GATHER |
| 4043 | Execution Slots: SLOT01 |
| 4044 | ========================================================================== */ |
| 4045 | |
| 4046 | #define Q6_vgather_ARMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw) |
| 4047 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4048 | |
| 4049 | #if __HVX_ARCH__ >= 65 |
| 4050 | /* ========================================================================== |
| 4051 | Assembly Syntax: if (Qs4) vtmp.w=vgather(Rt32,Mu2,Vv32.w).w |
| 4052 | C Intrinsic Prototype: void Q6_vgather_AQRMVw(HVX_Vector* Rs, HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv) |
| 4053 | Instruction Type: CVI_GATHER |
| 4054 | Execution Slots: SLOT01 |
| 4055 | ========================================================================== */ |
| 4056 | |
| 4057 | #define Q6_vgather_AQRMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq) |
| 4058 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4059 | |
| 4060 | #if __HVX_ARCH__ >= 65 |
| 4061 | /* ========================================================================== |
| 4062 | Assembly Syntax: Vd32.h=vlut4(Vu32.uh,Rtt32.h) |
| 4063 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vlut4_VuhPh(HVX_Vector Vu, Word64 Rtt) |
| 4064 | Instruction Type: CVI_VX_DV |
| 4065 | Execution Slots: SLOT2 |
| 4066 | ========================================================================== */ |
| 4067 | |
| 4068 | #define Q6_Vh_vlut4_VuhPh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4) |
| 4069 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4070 | |
| 4071 | #if __HVX_ARCH__ >= 65 |
| 4072 | /* ========================================================================== |
| 4073 | Assembly Syntax: Vdd32.h=vmpa(Vuu32.ub,Rt32.ub) |
| 4074 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpa_WubRub(HVX_VectorPair Vuu, Word32 Rt) |
| 4075 | Instruction Type: CVI_VX_DV |
| 4076 | Execution Slots: SLOT23 |
| 4077 | ========================================================================== */ |
| 4078 | |
| 4079 | #define Q6_Wh_vmpa_WubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu) |
| 4080 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4081 | |
| 4082 | #if __HVX_ARCH__ >= 65 |
| 4083 | /* ========================================================================== |
| 4084 | Assembly Syntax: Vxx32.h+=vmpa(Vuu32.ub,Rt32.ub) |
| 4085 | C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vmpaacc_WhWubRub(HVX_VectorPair Vxx, HVX_VectorPair Vuu, Word32 Rt) |
| 4086 | Instruction Type: CVI_VX_DV |
| 4087 | Execution Slots: SLOT23 |
| 4088 | ========================================================================== */ |
| 4089 | |
| 4090 | #define Q6_Wh_vmpaacc_WhWubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc) |
| 4091 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4092 | |
| 4093 | #if __HVX_ARCH__ >= 65 |
| 4094 | /* ========================================================================== |
| 4095 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.h,Rtt32.h):sat |
| 4096 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVhPh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 4097 | Instruction Type: CVI_VX_DV |
| 4098 | Execution Slots: SLOT2 |
| 4099 | ========================================================================== */ |
| 4100 | |
| 4101 | #define Q6_Vh_vmpa_VhVhVhPh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat) |
| 4102 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4103 | |
| 4104 | #if __HVX_ARCH__ >= 65 |
| 4105 | /* ========================================================================== |
| 4106 | Assembly Syntax: Vx32.h=vmpa(Vx32.h,Vu32.uh,Rtt32.uh):sat |
| 4107 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmpa_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 4108 | Instruction Type: CVI_VX_DV |
| 4109 | Execution Slots: SLOT2 |
| 4110 | ========================================================================== */ |
| 4111 | |
| 4112 | #define Q6_Vh_vmpa_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat) |
| 4113 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4114 | |
| 4115 | #if __HVX_ARCH__ >= 65 |
| 4116 | /* ========================================================================== |
| 4117 | Assembly Syntax: Vx32.h=vmps(Vx32.h,Vu32.uh,Rtt32.uh):sat |
| 4118 | C Intrinsic Prototype: HVX_Vector Q6_Vh_vmps_VhVhVuhPuh_sat(HVX_Vector Vx, HVX_Vector Vu, Word64 Rtt) |
| 4119 | Instruction Type: CVI_VX_DV |
| 4120 | Execution Slots: SLOT2 |
| 4121 | ========================================================================== */ |
| 4122 | |
| 4123 | #define Q6_Vh_vmps_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat) |
| 4124 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4125 | |
| 4126 | #if __HVX_ARCH__ >= 65 |
| 4127 | /* ========================================================================== |
| 4128 | Assembly Syntax: Vxx32.w+=vmpy(Vu32.h,Rt32.h) |
| 4129 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vmpyacc_WwVhRh(HVX_VectorPair Vxx, HVX_Vector Vu, Word32 Rt) |
| 4130 | Instruction Type: CVI_VX_DV |
| 4131 | Execution Slots: SLOT23 |
| 4132 | ========================================================================== */ |
| 4133 | |
| 4134 | #define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc) |
| 4135 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4136 | |
| 4137 | #if __HVX_ARCH__ >= 65 |
| 4138 | /* ========================================================================== |
| 4139 | Assembly Syntax: Vd32.uw=vmpye(Vu32.uh,Rt32.uh) |
| 4140 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpye_VuhRuh(HVX_Vector Vu, Word32 Rt) |
| 4141 | Instruction Type: CVI_VX |
| 4142 | Execution Slots: SLOT23 |
| 4143 | ========================================================================== */ |
| 4144 | |
| 4145 | #define Q6_Vuw_vmpye_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe) |
| 4146 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4147 | |
| 4148 | #if __HVX_ARCH__ >= 65 |
| 4149 | /* ========================================================================== |
| 4150 | Assembly Syntax: Vx32.uw+=vmpye(Vu32.uh,Rt32.uh) |
| 4151 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vmpyeacc_VuwVuhRuh(HVX_Vector Vx, HVX_Vector Vu, Word32 Rt) |
| 4152 | Instruction Type: CVI_VX |
| 4153 | Execution Slots: SLOT23 |
| 4154 | ========================================================================== */ |
| 4155 | |
| 4156 | #define Q6_Vuw_vmpyeacc_VuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc) |
| 4157 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4158 | |
| 4159 | #if __HVX_ARCH__ >= 65 |
| 4160 | /* ========================================================================== |
| 4161 | Assembly Syntax: Vd32.b=vnavg(Vu32.b,Vv32.b) |
| 4162 | C Intrinsic Prototype: HVX_Vector Q6_Vb_vnavg_VbVb(HVX_Vector Vu, HVX_Vector Vv) |
| 4163 | Instruction Type: CVI_VA |
| 4164 | Execution Slots: SLOT0123 |
| 4165 | ========================================================================== */ |
| 4166 | |
| 4167 | #define Q6_Vb_vnavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb) |
| 4168 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4169 | |
| 4170 | #if __HVX_ARCH__ >= 65 |
| 4171 | /* ========================================================================== |
| 4172 | Assembly Syntax: Vd32.b=prefixsum(Qv4) |
| 4173 | C Intrinsic Prototype: HVX_Vector Q6_Vb_prefixsum_Q(HVX_VectorPred Qv) |
| 4174 | Instruction Type: CVI_VS |
| 4175 | Execution Slots: SLOT0123 |
| 4176 | ========================================================================== */ |
| 4177 | |
| 4178 | #define Q6_Vb_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb) |
| 4179 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4180 | |
| 4181 | #if __HVX_ARCH__ >= 65 |
| 4182 | /* ========================================================================== |
| 4183 | Assembly Syntax: Vd32.h=prefixsum(Qv4) |
| 4184 | C Intrinsic Prototype: HVX_Vector Q6_Vh_prefixsum_Q(HVX_VectorPred Qv) |
| 4185 | Instruction Type: CVI_VS |
| 4186 | Execution Slots: SLOT0123 |
| 4187 | ========================================================================== */ |
| 4188 | |
| 4189 | #define Q6_Vh_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh) |
| 4190 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4191 | |
| 4192 | #if __HVX_ARCH__ >= 65 |
| 4193 | /* ========================================================================== |
| 4194 | Assembly Syntax: Vd32.w=prefixsum(Qv4) |
| 4195 | C Intrinsic Prototype: HVX_Vector Q6_Vw_prefixsum_Q(HVX_VectorPred Qv) |
| 4196 | Instruction Type: CVI_VS |
| 4197 | Execution Slots: SLOT0123 |
| 4198 | ========================================================================== */ |
| 4199 | |
| 4200 | #define Q6_Vw_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw) |
| 4201 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4202 | |
| 4203 | #if __HVX_ARCH__ >= 65 |
| 4204 | /* ========================================================================== |
| 4205 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
| 4206 | C Intrinsic Prototype: void Q6_vscatter_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4207 | Instruction Type: CVI_SCATTER |
| 4208 | Execution Slots: SLOT0 |
| 4209 | ========================================================================== */ |
| 4210 | |
| 4211 | #define Q6_vscatter_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh) |
| 4212 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4213 | |
| 4214 | #if __HVX_ARCH__ >= 65 |
| 4215 | /* ========================================================================== |
| 4216 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.h).h+=Vw32 |
| 4217 | C Intrinsic Prototype: void Q6_vscatteracc_RMVhV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4218 | Instruction Type: CVI_SCATTER |
| 4219 | Execution Slots: SLOT0 |
| 4220 | ========================================================================== */ |
| 4221 | |
| 4222 | #define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add) |
| 4223 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4224 | |
| 4225 | #if __HVX_ARCH__ >= 65 |
| 4226 | /* ========================================================================== |
| 4227 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.h).h=Vw32 |
| 4228 | C Intrinsic Prototype: void Q6_vscatter_QRMVhV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4229 | Instruction Type: CVI_SCATTER |
| 4230 | Execution Slots: SLOT0 |
| 4231 | ========================================================================== */ |
| 4232 | |
| 4233 | #define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq) |
| 4234 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4235 | |
| 4236 | #if __HVX_ARCH__ >= 65 |
| 4237 | /* ========================================================================== |
| 4238 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
| 4239 | C Intrinsic Prototype: void Q6_vscatter_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 4240 | Instruction Type: CVI_SCATTER_DV |
| 4241 | Execution Slots: SLOT0 |
| 4242 | ========================================================================== */ |
| 4243 | |
| 4244 | #define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw) |
| 4245 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4246 | |
| 4247 | #if __HVX_ARCH__ >= 65 |
| 4248 | /* ========================================================================== |
| 4249 | Assembly Syntax: vscatter(Rt32,Mu2,Vvv32.w).h+=Vw32 |
| 4250 | C Intrinsic Prototype: void Q6_vscatteracc_RMWwV(Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 4251 | Instruction Type: CVI_SCATTER_DV |
| 4252 | Execution Slots: SLOT0 |
| 4253 | ========================================================================== */ |
| 4254 | |
| 4255 | #define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add) |
| 4256 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4257 | |
| 4258 | #if __HVX_ARCH__ >= 65 |
| 4259 | /* ========================================================================== |
| 4260 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vvv32.w).h=Vw32 |
| 4261 | C Intrinsic Prototype: void Q6_vscatter_QRMWwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_VectorPair Vvv, HVX_Vector Vw) |
| 4262 | Instruction Type: CVI_SCATTER_DV |
| 4263 | Execution Slots: SLOT0 |
| 4264 | ========================================================================== */ |
| 4265 | |
| 4266 | #define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq) |
| 4267 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4268 | |
| 4269 | #if __HVX_ARCH__ >= 65 |
| 4270 | /* ========================================================================== |
| 4271 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
| 4272 | C Intrinsic Prototype: void Q6_vscatter_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4273 | Instruction Type: CVI_SCATTER |
| 4274 | Execution Slots: SLOT0 |
| 4275 | ========================================================================== */ |
| 4276 | |
| 4277 | #define Q6_vscatter_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw) |
| 4278 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4279 | |
| 4280 | #if __HVX_ARCH__ >= 65 |
| 4281 | /* ========================================================================== |
| 4282 | Assembly Syntax: vscatter(Rt32,Mu2,Vv32.w).w+=Vw32 |
| 4283 | C Intrinsic Prototype: void Q6_vscatteracc_RMVwV(Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4284 | Instruction Type: CVI_SCATTER |
| 4285 | Execution Slots: SLOT0 |
| 4286 | ========================================================================== */ |
| 4287 | |
| 4288 | #define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add) |
| 4289 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4290 | |
| 4291 | #if __HVX_ARCH__ >= 65 |
| 4292 | /* ========================================================================== |
| 4293 | Assembly Syntax: if (Qs4) vscatter(Rt32,Mu2,Vv32.w).w=Vw32 |
| 4294 | C Intrinsic Prototype: void Q6_vscatter_QRMVwV(HVX_VectorPred Qs, Word32 Rt, Word32 Mu, HVX_Vector Vv, HVX_Vector Vw) |
| 4295 | Instruction Type: CVI_SCATTER |
| 4296 | Execution Slots: SLOT0 |
| 4297 | ========================================================================== */ |
| 4298 | |
| 4299 | #define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq) |
| 4300 | #endif /* __HEXAGON_ARCH___ >= 65 */ |
| 4301 | |
| 4302 | #if __HVX_ARCH__ >= 66 |
| 4303 | /* ========================================================================== |
| 4304 | Assembly Syntax: Vd32.w=vadd(Vu32.w,Vv32.w,Qs4):carry:sat |
| 4305 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vadd_VwVwQ_carry_sat(HVX_Vector Vu, HVX_Vector Vv, HVX_VectorPred Qs) |
| 4306 | Instruction Type: CVI_VA |
| 4307 | Execution Slots: SLOT0123 |
| 4308 | ========================================================================== */ |
| 4309 | |
| 4310 | #define Q6_Vw_vadd_VwVwQ_carry_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat) |
| 4311 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
| 4312 | |
| 4313 | #if __HVX_ARCH__ >= 66 |
| 4314 | /* ========================================================================== |
| 4315 | Assembly Syntax: Vxx32.w=vasrinto(Vu32.w,Vv32.w) |
| 4316 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vasrinto_WwVwVw(HVX_VectorPair Vxx, HVX_Vector Vu, HVX_Vector Vv) |
| 4317 | Instruction Type: CVI_VP_VS |
| 4318 | Execution Slots: SLOT0123 |
| 4319 | ========================================================================== */ |
| 4320 | |
| 4321 | #define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into) |
| 4322 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
| 4323 | |
| 4324 | #if __HVX_ARCH__ >= 66 |
| 4325 | /* ========================================================================== |
| 4326 | Assembly Syntax: Vd32.uw=vrotr(Vu32.uw,Vv32.uw) |
| 4327 | C Intrinsic Prototype: HVX_Vector Q6_Vuw_vrotr_VuwVuw(HVX_Vector Vu, HVX_Vector Vv) |
| 4328 | Instruction Type: CVI_VS |
| 4329 | Execution Slots: SLOT0123 |
| 4330 | ========================================================================== */ |
| 4331 | |
| 4332 | #define Q6_Vuw_vrotr_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr) |
| 4333 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
| 4334 | |
| 4335 | #if __HVX_ARCH__ >= 66 |
| 4336 | /* ========================================================================== |
| 4337 | Assembly Syntax: Vd32.w=vsatdw(Vu32.w,Vv32.w) |
| 4338 | C Intrinsic Prototype: HVX_Vector Q6_Vw_vsatdw_VwVw(HVX_Vector Vu, HVX_Vector Vv) |
| 4339 | Instruction Type: CVI_VA |
| 4340 | Execution Slots: SLOT0123 |
| 4341 | ========================================================================== */ |
| 4342 | |
| 4343 | #define Q6_Vw_vsatdw_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw) |
| 4344 | #endif /* __HEXAGON_ARCH___ >= 66 */ |
| 4345 | |
| 4346 | #if __HVX_ARCH__ >= 68 |
| 4347 | /* ========================================================================== |
| 4348 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
| 4349 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_h(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 4350 | Instruction Type: CVI_VX_DV |
| 4351 | Execution Slots: SLOT23 |
| 4352 | ========================================================================== */ |
| 4353 | |
| 4354 | #define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10) |
| 4355 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
| 4356 | |
| 4357 | #if __HVX_ARCH__ >= 68 |
| 4358 | /* ========================================================================== |
| 4359 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):h |
| 4360 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_h(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 4361 | Instruction Type: CVI_VX_DV |
| 4362 | Execution Slots: SLOT23 |
| 4363 | ========================================================================== */ |
| 4364 | |
| 4365 | #define Q6_Ww_v6mpyacc_WwWubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx) |
| 4366 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
| 4367 | |
| 4368 | #if __HVX_ARCH__ >= 68 |
| 4369 | /* ========================================================================== |
| 4370 | Assembly Syntax: Vdd32.w=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
| 4371 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpy_WubWbI_v(HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 4372 | Instruction Type: CVI_VX_DV |
| 4373 | Execution Slots: SLOT23 |
| 4374 | ========================================================================== */ |
| 4375 | |
| 4376 | #define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10) |
| 4377 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
| 4378 | |
| 4379 | #if __HVX_ARCH__ >= 68 |
| 4380 | /* ========================================================================== |
| 4381 | Assembly Syntax: Vxx32.w+=v6mpy(Vuu32.ub,Vvv32.b,#u2):v |
| 4382 | C Intrinsic Prototype: HVX_VectorPair Q6_Ww_v6mpyacc_WwWubWbI_v(HVX_VectorPair Vxx, HVX_VectorPair Vuu, HVX_VectorPair Vvv, Word32 Iu2) |
| 4383 | Instruction Type: CVI_VX_DV |
| 4384 | Execution Slots: SLOT23 |
| 4385 | ========================================================================== */ |
| 4386 | |
| 4387 | #define Q6_Ww_v6mpyacc_WwWubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx) |
| 4388 | #endif /* __HEXAGON_ARCH___ >= 68 */ |
| 4389 | |
| 4390 | #endif /* __HVX__ */ |
| 4391 | |
| 4392 | #endif |