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Doug Horn1427b6a2018-12-11 13:19:16 -08001// Copyright 2017 The Fuchsia Authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
Adam Barth57eacf52020-11-04 00:38:09 +00005#ifndef SYSROOT_ZIRCON_SYSCALLS_HYPERVISOR_H_
6#define SYSROOT_ZIRCON_SYSCALLS_HYPERVISOR_H_
Doug Horn1427b6a2018-12-11 13:19:16 -08007
8#include <assert.h>
9
10#include <zircon/compiler.h>
11#include <zircon/types.h>
12
13__BEGIN_CDECLS
14
15// clang-format off
16typedef uint32_t zx_guest_trap_t;
17
18#define ZX_GUEST_TRAP_BELL ((zx_guest_trap_t) 0u)
19#define ZX_GUEST_TRAP_MEM ((zx_guest_trap_t) 1u)
20#define ZX_GUEST_TRAP_IO ((zx_guest_trap_t) 2u)
21
22typedef uint32_t zx_vcpu_t;
23
24#define ZX_VCPU_STATE ((zx_vcpu_t) 0u)
25#define ZX_VCPU_IO ((zx_vcpu_t) 1u)
26// clang-format on
27
28// Structure to read and write VCPU state.
29typedef struct zx_vcpu_state {
30#if __aarch64__
Adam Barth57eacf52020-11-04 00:38:09 +000031 uint64_t x[31];
32 uint64_t sp;
33 // Contains only the user-controllable upper 4-bits (NZCV).
34 uint32_t cpsr;
35 uint8_t padding1[4];
Doug Horn1427b6a2018-12-11 13:19:16 -080036#elif __x86_64__
Adam Barth57eacf52020-11-04 00:38:09 +000037 uint64_t rax;
38 uint64_t rcx;
39 uint64_t rdx;
40 uint64_t rbx;
41 uint64_t rsp;
42 uint64_t rbp;
43 uint64_t rsi;
44 uint64_t rdi;
45 uint64_t r8;
46 uint64_t r9;
47 uint64_t r10;
48 uint64_t r11;
49 uint64_t r12;
50 uint64_t r13;
51 uint64_t r14;
52 uint64_t r15;
53 // Contains only the user-controllable lower 32-bits.
54 uint64_t rflags;
Doug Horn1427b6a2018-12-11 13:19:16 -080055#endif
56} zx_vcpu_state_t;
57
58// Structure to read and write VCPU state for IO ports.
59typedef struct zx_vcpu_io {
Adam Barth57eacf52020-11-04 00:38:09 +000060 uint8_t access_size;
61 uint8_t padding1[3];
62 union {
63 struct {
64 uint8_t u8;
65 uint8_t padding2[3];
Doug Horn1427b6a2018-12-11 13:19:16 -080066 };
Adam Barth57eacf52020-11-04 00:38:09 +000067 struct {
68 uint16_t u16;
69 uint8_t padding3[2];
70 };
71 uint32_t u32;
72 uint8_t data[4];
73 };
Doug Horn1427b6a2018-12-11 13:19:16 -080074} zx_vcpu_io_t;
75
76__END_CDECLS
Adam Barth57eacf52020-11-04 00:38:09 +000077
78#endif // SYSROOT_ZIRCON_SYSCALLS_HYPERVISOR_H_