The Android Open Source Project | e9df6ba | 2012-12-13 14:55:37 -0800 | [diff] [blame^] | 1 | ## this file is used by Broadcom's Hardware Abstraction Layer at external/libnfc-nci/halimpl/ |
| 2 | |
| 3 | ############################################################################### |
| 4 | # Application options |
| 5 | APPL_TRACE_LEVEL=0xFF |
| 6 | PROTOCOL_TRACE_LEVEL=0xFFFFFFFF |
| 7 | |
| 8 | ############################################################################### |
| 9 | # performance measurement |
| 10 | # Change this setting to control how often USERIAL log the performance (throughput) |
| 11 | # data on read/write/poll |
| 12 | # defailt is to log performance dara for every 100 read or write |
| 13 | #REPORT_PERFORMANCE_MEASURE=100 |
| 14 | |
| 15 | ############################################################################### |
| 16 | # File used for NFA storage |
| 17 | NFA_STORAGE="/data/nfc" |
| 18 | |
| 19 | ############################################################################### |
| 20 | # Snooze Mode Settings |
| 21 | # |
| 22 | # By default snooze mode is enabled. Set SNOOZE_MODE_CFG byte[0] to 0 |
| 23 | # to disable. |
| 24 | # |
| 25 | # If SNOOZE_MODE_CFG is not provided, the default settings are used: |
| 26 | # They are as follows: |
| 27 | # 8 Sleep Mode (0=Disabled 1=UART 8=SPI/I2C) |
| 28 | # 0 Idle Threshold Host |
| 29 | # 0 Idle Threshold HC |
| 30 | # 0 NFC Wake active mode (0=ActiveLow 1=ActiveHigh) |
| 31 | # 1 Host Wake active mode (0=ActiveLow 1=ActiveHigh) |
| 32 | # |
| 33 | #SNOOZE_MODE_CFG={08:00:00:00:01} |
| 34 | |
| 35 | ############################################################################### |
| 36 | # Insert a delay in milliseconds after NFC_WAKE and before write to NFCC |
| 37 | NFC_WAKE_DELAY=20 |
| 38 | |
| 39 | ############################################################################### |
| 40 | # Various Delay settings (in ms) used in USERIAL |
| 41 | # POWER_ON_DELAY |
| 42 | # Delay after turning on chip, before writing to transport (default 300) |
| 43 | # PRE_POWER_OFF_DELAY |
| 44 | # Delay after deasserting NFC-Wake before turn off chip (default 0) |
| 45 | # POST_POWER_OFF_DELAY |
| 46 | # Delay after turning off chip, before USERIAL_close returns (default 0) |
| 47 | # |
| 48 | #POWER_ON_DELAY=300 |
| 49 | #PRE_POWER_OFF_DELAY=0 |
| 50 | #POST_POWER_OFF_DELAY=0 |
| 51 | |
| 52 | ############################################################################### |
| 53 | # LPTD mode configuration |
| 54 | # byte[0] is the length of the remaining bytes in this value |
| 55 | # if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled). |
| 56 | # byte[1] is the param id it should be set to B9. |
| 57 | # byte[2] is the length of the LPTD parameters |
| 58 | # byte[3] indicates if LPTD is enabled |
| 59 | # if set to 0, LPTD will be disabled (parameters will still be sent). |
| 60 | # byte[4-n] are the LPTD parameters. |
| 61 | # By default, LPTD is enabled and default settings are used. |
| 62 | # See nfc_hal_dm_cfg.c for defaults |
| 63 | LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00} |
| 64 | |
| 65 | ############################################################################### |
| 66 | # Startup Configuration (100 bytes maximum) |
| 67 | # |
| 68 | # For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is |
| 69 | # for UICC1. The values are defined as: |
| 70 | # 0 : UICCx only supports ISO_DEP in low power mode. |
| 71 | # 2 : UICCx only supports Mifare in low power mode. |
| 72 | # 3 : UICCx supports both ISO_DEP and Mifare in low power mode. |
| 73 | # |
| 74 | # AA BB |
| 75 | NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:28:01:01} |
| 76 | |
| 77 | ############################################################################### |
| 78 | # Startup Vendor Specific Configuration (100 bytes maximum); |
| 79 | # byte[0] TLV total len = 0x5 |
| 80 | # byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f |
| 81 | # byte[2] NCI_MSG_FRAME_LOG = 0x9 |
| 82 | # byte[3] 2 |
| 83 | # byte[4] 0=turn off RF frame logging; 1=turn on |
| 84 | # byte[5] 0=turn off SWP frame logging; 1=turn on |
| 85 | # NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01} |
| 86 | |
| 87 | ############################################################################### |
| 88 | # Configure crystal frequency when internal LPO can't detect the frequency. |
| 89 | #XTAL_FREQUENCY=0 |
| 90 | |
| 91 | ############################################################################### |
| 92 | # Firmware patch file |
| 93 | # If the value is not set then patch download is disabled. |
| 94 | FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd" |
| 95 | |
| 96 | ############################################################################### |
| 97 | # Firmware pre-patch file (sent before the above patch file) |
| 98 | # If the value is not set then pre-patch is not used. |
| 99 | FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd" |
| 100 | |
| 101 | ############################################################################### |
| 102 | # Firmware patch format |
| 103 | # 1 = HCD |
| 104 | # 2 = NCD (default) |
| 105 | #NFA_CONFIG_FORMAT=2 |
| 106 | |
| 107 | ############################################################################### |
| 108 | # SPD Debug mode |
| 109 | # If set to 1, any failure of downloading a patch will trigger a hard-stop |
| 110 | #SPD_DEBUG=0 |
| 111 | |
| 112 | ############################################################################### |
| 113 | # SPD Max Retry Count |
| 114 | # The number of attempts to download a patch before giving up (defualt is 3). |
| 115 | # Note, this resets after a power-cycle. |
| 116 | #SPD_MAX_RETRY_COUNT=3 |
| 117 | |
| 118 | ############################################################################### |
| 119 | # transport driver |
| 120 | # |
| 121 | # TRANSPORT_DRIVER=<driver> |
| 122 | # |
| 123 | # where <driver> can be, for example: |
| 124 | # "/dev/ttyS" (UART) |
| 125 | # "/dev/bcmi2cnfc" (I2C) |
| 126 | # "hwtun" (HW Tunnel) |
| 127 | # "/dev/bcmspinfc" (SPI) |
| 128 | # "/dev/btusb0" (BT USB) |
| 129 | TRANSPORT_DRIVER="/dev/bcm2079x" |
| 130 | |
| 131 | ############################################################################### |
| 132 | # power control driver |
| 133 | # Specify a kernel driver that support ioctl commands to control NFC_EN and |
| 134 | # NFC_WAKE gpio signals. |
| 135 | # |
| 136 | # POWER_CONTRL_DRIVER=<driver> |
| 137 | # where <driver> can be, for example: |
| 138 | # "/dev/nfcpower" |
| 139 | # "/dev/bcmi2cnfc" (I2C) |
| 140 | # "/dev/bcmspinfc" (SPI) |
| 141 | # i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal |
| 142 | POWER_CONTROL_DRIVER="/dev/bcm2079x" |
| 143 | |
| 144 | ############################################################################### |
| 145 | # I2C transport driver options |
| 146 | # |
| 147 | BCMI2CNFC_ADDRESS=0 |
| 148 | |
| 149 | ############################################################################### |
| 150 | # I2C transport driver try to read multiple packets in read() if data is available |
| 151 | # remove the comment below to enable this feature |
| 152 | #READ_MULTIPLE_PACKETS=1 |
| 153 | |
| 154 | ############################################################################### |
| 155 | # SPI transport driver options |
| 156 | #SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00} |
| 157 | |
| 158 | ############################################################################### |
| 159 | # UART transport driver options |
| 160 | # |
| 161 | # PORT=1,2,3,... |
| 162 | # BAUD=115200, 19200, 9600, 4800, |
| 163 | # DATABITS=8, 7, 6, 5 |
| 164 | # PARITY="even" | "odd" | "none" |
| 165 | # STOPBITS="0" | "1" | "1.5" | "2" |
| 166 | |
| 167 | #UART_PORT=2 |
| 168 | #UART_BAUD=115200 |
| 169 | #UART_DATABITS=8 |
| 170 | #UART_PARITY="none" |
| 171 | #UART_STOPBITS="1" |
| 172 | |
| 173 | ############################################################################### |
| 174 | # Insert a delay in microseconds per byte after a write to NFCC. |
| 175 | # after writing a block of data to the NFCC, delay this an amopunt of time before |
| 176 | # writing next block of data. the delay is calculated as below |
| 177 | # NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds |
| 178 | # e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write |
| 179 | NFC_WRITE_DELAY=20 |
| 180 | |
| 181 | ############################################################################### |
| 182 | # Maximum Number of Credits to be allowed by the NFCC |
| 183 | # This value overrides what the NFCC specifices allowing the host to have |
| 184 | # the control to work-around transport limitations. If this value does |
| 185 | # not exist or is set to 0, the NFCC will provide the number of credits. |
| 186 | MAX_RF_DATA_CREDITS=1 |
| 187 | |
| 188 | ############################################################################### |
| 189 | # Allow UICC to be powered off if there is no traffic. |
| 190 | # Timeout is in ms. If set to 0, then UICC will not be powered off. |
| 191 | UICC_IDLE_TIMEOUT=30000 |
| 192 | |
| 193 | |
| 194 | ############################################################################### |
| 195 | # Antenna Configuration - This data is used when setting 0xC8 config item |
| 196 | # at startup (before discovery is started). If not used, no value is sent. |
| 197 | # |
| 198 | # The settings for this value are documented here: |
| 199 | # http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/ |
| 200 | # Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx |
| 201 | # This document is maintained by Paul Forshaw. |
| 202 | # |
| 203 | # The values marked as ?? should be tweaked per antenna or customer/app: |
| 204 | # {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04} |
| 205 | # array[0] = 0x20 is length of the payload from array[1] to the end |
| 206 | # array[1] = 0xC8 is PREINIT_DSP_CFG |
| 207 | #PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04} |
| 208 | |