Merge "asoc: codecs: bolero: toggle zero gate for first hpf update"
diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c
index 33cc87f..d27a5cf 100644
--- a/asoc/codecs/bolero/tx-macro.c
+++ b/asoc/codecs/bolero/tx-macro.c
@@ -463,10 +463,10 @@
snd_soc_component_update_bits(component,
dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5);
- snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);
+ snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);
/* Minimum 1 clk cycle delay is required as per HW spec */
usleep_range(1000, 1010);
- snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);
+ snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);
}
static void tx_macro_mute_update_callback(struct work_struct *work)
@@ -878,6 +878,10 @@
tx_vol_ctl_reg, 0x20, 0x20);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00);
+ /*
+ * Minimum 1 clk cycle delay is required as per HW spec
+ */
+ usleep_range(1000, 1010);
hpf_cut_off_freq = (
snd_soc_component_read32(component, dec_cfg_reg) &
@@ -900,7 +904,7 @@
&tx_priv->tx_hpf_work[decimator].dwork,
msecs_to_jiffies(300));
snd_soc_component_update_bits(component,
- hpf_gate_reg, 0x02, 0x02);
+ hpf_gate_reg, 0x03, 0x03);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/
diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c
index 2150d28..494a951 100644
--- a/asoc/codecs/bolero/va-macro.c
+++ b/asoc/codecs/bolero/va-macro.c
@@ -717,10 +717,10 @@
snd_soc_component_update_bits(component,
dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
hpf_cut_off_freq << 5);
- snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);
+ snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);
/* Minimum 1 clk cycle delay is required as per HW spec */
usleep_range(1000, 1010);
- snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);
+ snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);
}
static void va_macro_mute_update_callback(struct work_struct *work)
@@ -1012,6 +1012,10 @@
tx_vol_ctl_reg, 0x20, 0x20);
snd_soc_component_update_bits(component,
hpf_gate_reg, 0x01, 0x00);
+ /*
+ * Minimum 1 clk cycle delay is required as per HW spec
+ */
+ usleep_range(1000, 1010);
hpf_cut_off_freq = (snd_soc_component_read32(
component, dec_cfg_reg) &
@@ -1024,7 +1028,7 @@
TX_HPF_CUT_OFF_FREQ_MASK,
CF_MIN_3DB_150HZ << 5);
snd_soc_component_update_bits(component,
- hpf_gate_reg, 0x02, 0x02);
+ hpf_gate_reg, 0x03, 0x03);
/*
* Minimum 1 clk cycle delay is required as per HW spec
*/