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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / 02bee73b77181f2e4d7a215bfa036d99328b9951 / . / asoc / sa6155.c
blob: 68117e56b7c1735b51bc55f6c7c3e3a87ab1f6be [file] [log] [blame]
Rahul Sharma02bee732018-12-20 18:48:34 +0530[diff] [blame^]1/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12/*
13 * Copyright 2011, The Android Open Source Project
14
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are met:
17 * Redistributions of source code must retain the above copyright
18 notice, this list of conditions and the following disclaimer.
19 * Redistributions in binary form must reproduce the above copyright
20 notice, this list of conditions and the following disclaimer in the
21 documentation and/or other materials provided with the distribution.
22 * Neither the name of The Android Open Source Project nor the names of
23 its contributors may be used to endorse or promote products derived
24 from this software without specific prior written permission.
25
26 * THIS SOFTWARE IS PROVIDED BY The Android Open Source Project ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL The Android Open Source Project BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
33 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
36 * DAMAGE.
37 */
38
39#include <linux/clk.h>
40#include <linux/delay.h>
41#include <linux/gpio.h>
42#include <linux/of_gpio.h>
43#include <linux/platform_device.h>
44#include <linux/slab.h>
45#include <linux/io.h>
46#include <linux/module.h>
47#include <linux/input.h>
48#include <linux/of_device.h>
49#include <linux/pm_qos.h>
50#include <sound/core.h>
51#include <sound/soc.h>
52#include <sound/soc-dapm.h>
53#include <sound/pcm.h>
54#include <sound/pcm_params.h>
55#include <sound/info.h>
56#include <dsp/audio_notifier.h>
57#include <dsp/q6afe-v2.h>
58#include <dsp/q6core.h>
59#include "device_event.h"
60#include "msm-pcm-routing-v2.h"
61
62#define DRV_NAME "sa6155-asoc-snd"
63
64#define __CHIPSET__ "SA6155 "
65#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
66
67#define DEV_NAME_STR_LEN 32
68
69#define SAMPLING_RATE_8KHZ 8000
70#define SAMPLING_RATE_11P025KHZ 11025
71#define SAMPLING_RATE_16KHZ 16000
72#define SAMPLING_RATE_22P05KHZ 22050
73#define SAMPLING_RATE_32KHZ 32000
74#define SAMPLING_RATE_44P1KHZ 44100
75#define SAMPLING_RATE_48KHZ 48000
76#define SAMPLING_RATE_88P2KHZ 88200
77#define SAMPLING_RATE_96KHZ 96000
78#define SAMPLING_RATE_176P4KHZ 176400
79#define SAMPLING_RATE_192KHZ 192000
80#define SAMPLING_RATE_352P8KHZ 352800
81#define SAMPLING_RATE_384KHZ 384000
82
83#define ADSP_STATE_READY_TIMEOUT_MS 3000
84#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
85
86enum {
87 PRIM_MI2S = 0,
88 SEC_MI2S,
89 TERT_MI2S,
90 QUAT_MI2S,
91 QUIN_MI2S,
92 MI2S_MAX,
93};
94
95enum {
96 PRIM_AUX_PCM = 0,
97 SEC_AUX_PCM,
98 TERT_AUX_PCM,
99 QUAT_AUX_PCM,
100 QUIN_AUX_PCM,
101 AUX_PCM_MAX,
102};
103
104struct mi2s_conf {
105 struct mutex lock;
106 u32 ref_cnt;
107 u32 msm_is_mi2s_master;
108};
109
110static u32 mi2s_ebit_clk[MI2S_MAX] = {
111 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
112 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
113 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
114 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
115 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
116};
117
118struct dev_config {
119 u32 sample_rate;
120 u32 bit_format;
121 u32 channels;
122};
123
124enum {
125 DP_RX_IDX = 0,
126 EXT_DISP_RX_IDX_MAX,
127};
128
129enum pinctrl_pin_state {
130 STATE_DISABLE = 0, /* All pins are in sleep state */
131 STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
132 STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
133};
134
135struct msm_pinctrl_info {
136 struct pinctrl *pinctrl;
137 struct pinctrl_state *mi2s_disable;
138 struct pinctrl_state *tdm_disable;
139 struct pinctrl_state *mi2s_active;
140 struct pinctrl_state *tdm_active;
141 enum pinctrl_pin_state curr_state;
142};
143
144struct msm_asoc_mach_data {
145 struct msm_pinctrl_info pinctrl_info;
146};
147
148static const char *const pin_states[] = {"sleep", "i2s-active",
149 "tdm-active"};
150
151enum {
152 TDM_0 = 0,
153 TDM_1,
154 TDM_2,
155 TDM_3,
156 TDM_4,
157 TDM_5,
158 TDM_6,
159 TDM_7,
160 TDM_PORT_MAX,
161};
162
163enum {
164 TDM_PRI = 0,
165 TDM_SEC,
166 TDM_TERT,
167 TDM_QUAT,
168 TDM_QUIN,
169 TDM_INTERFACE_MAX,
170};
171
172struct tdm_port {
173 u32 mode;
174 u32 channel;
175};
176
177/* TDM default config */
178static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
179 { /* PRI TDM */
180 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
181 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
182 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
183 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
184 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
185 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
186 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
187 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
188 },
189 { /* SEC TDM */
190 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_0 */
191 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_1 */
192 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_2 */
193 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* RX_3 */
194 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
195 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
196 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
197 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
198 },
199 { /* TERT TDM */
200 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* RX_0 */
201 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
202 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
203 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
204 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
205 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
206 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
207 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
208 },
209 { /* QUAT TDM */
210 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
211 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
212 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
213 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
214 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
215 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
216 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
217 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
218 },
219 { /* QUIN TDM */
220 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
221 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
222 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
223 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
224 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
225 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
226 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
227 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
228 }
229};
230
231/* TDM default config */
232static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
233 { /* PRI TDM */
234 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_0 */
235 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
236 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
237 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_3 */
238 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
239 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
240 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
241 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
242 },
243 { /* SEC TDM */
244 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 6}, /* TX_0 */
245 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
246 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
247 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
248 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
249 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
250 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
251 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
252 },
253 { /* TERT TDM */
254 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 4}, /* TX_0 */
255 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_1 */
256 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, /* TX_2 */
257 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
258 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
259 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
260 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
261 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
262 },
263 { /* QUAT TDM */
264 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
265 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
266 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
267 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
268 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
269 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
270 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
271 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
272 },
273 { /* QUIN TDM */
274 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
275 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
276 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
277 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
278 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
279 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
280 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
281 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
282 }
283};
284
285/* Default configuration of external display BE */
286static struct dev_config ext_disp_rx_cfg[] = {
287 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
288};
289
290static struct dev_config usb_rx_cfg = {
291 .sample_rate = SAMPLING_RATE_48KHZ,
292 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
293 .channels = 2,
294};
295
296static struct dev_config usb_tx_cfg = {
297 .sample_rate = SAMPLING_RATE_48KHZ,
298 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
299 .channels = 1,
300};
301
302static struct dev_config proxy_rx_cfg = {
303 .sample_rate = SAMPLING_RATE_48KHZ,
304 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
305 .channels = 2,
306};
307
308/* Default configuration of MI2S channels */
309static struct dev_config mi2s_rx_cfg[] = {
310 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
311 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
312 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
313 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
314 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
315};
316
317static struct dev_config mi2s_tx_cfg[] = {
318 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
319 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
320 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
321 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
322 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
323};
324
325static struct dev_config aux_pcm_rx_cfg[] = {
326 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
327 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
328 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
329 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
330 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
331};
332
333static struct dev_config aux_pcm_tx_cfg[] = {
334 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
335 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
336 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
337 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
338 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
339};
340
341/* TDM default slot config */
342struct tdm_slot_cfg {
343 u32 width;
344 u32 num;
345};
346
347static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = {
348 /* PRI TDM */
349 {32, 8},
350 /* SEC TDM */
351 {32, 8},
352 /* TERT TDM */
353 {32, 8},
354 /* QUAT TDM */
355 {32, 8},
356 /* QUIN TDM */
357 {32, 8}
358};
359
360/*****************************************************************************
361* TO BE UPDATED: Codec/Platform specific tdm slot table
362*****************************************************************************/
363static struct tdm_slot_cfg tdm_slot_custom[TDM_INTERFACE_MAX] = {
364 /* PRI TDM */
365 {16, 16},
366 /* SEC TDM */
367 {16, 16},
368 /* TERT TDM */
369 {16, 16},
370 /* QUAT TDM */
371 {16, 16},
372 /* QUIN TDM */
373 {16, 16}
374};
375
376
377/* TDM default slot offset config */
378#define TDM_SLOT_OFFSET_MAX 32
379
380static unsigned int tdm_rx_slot_offset
381 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
382 {/* PRI TDM */
383 {0, 4, 0xFFFF},
384 {8, 12, 0xFFFF},
385 {16, 20, 0xFFFF},
386 {24, 28, 0xFFFF},
387 {0xFFFF}, /* not used */
388 {0xFFFF}, /* not used */
389 {0xFFFF}, /* not used */
390 {0xFFFF}, /* not used */
391 },
392 {/* SEC TDM */
393 {0, 4, 0xFFFF},
394 {8, 12, 0xFFFF},
395 {16, 20, 0xFFFF},
396 {24, 28, 0xFFFF},
397 {0xFFFF}, /* not used */
398 {0xFFFF}, /* not used */
399 {0xFFFF}, /* not used */
400 {0xFFFF}, /* not used */
401 },
402 {/* TERT TDM */
403 {0, 4, 8, 12, 16, 20, 0xFFFF},
404 {24, 0xFFFF},
405 {28, 0xFFFF},
406 {0xFFFF}, /* not used */
407 {0xFFFF}, /* not used */
408 {0xFFFF}, /* not used */
409 {0xFFFF}, /* not used */
410 {0xFFFF}, /* not used */
411 },
412 {/* QUAT TDM */
413 {0xFFFF}, /* not used */
414 {0xFFFF}, /* not used */
415 {0xFFFF}, /* not used */
416 {0xFFFF}, /* not used */
417 {0xFFFF}, /* not used */
418 {0xFFFF}, /* not used */
419 {0xFFFF}, /* not used */
420 {0xFFFF}, /* not used */
421 },
422 {/* QUIN TDM */
423 {0xFFFF}, /* not used */
424 {0xFFFF}, /* not used */
425 {0xFFFF}, /* not used */
426 {0xFFFF}, /* not used */
427 {0xFFFF}, /* not used */
428 {0xFFFF}, /* not used */
429 {0xFFFF}, /* not used */
430 {0xFFFF}, /* not used */
431 }
432};
433
434static unsigned int tdm_tx_slot_offset
435 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
436 {/* PRI TDM */
437 {0, 4, 0xFFFF},
438 {8, 12, 0xFFFF},
439 {16, 20, 0xFFFF},
440 {24, 28, 0xFFFF},
441 {0xFFFF}, /* not used */
442 {0xFFFF}, /* not used */
443 {0xFFFF}, /* not used */
444 {0xFFFF}, /* not used */
445 },
446 {/* SEC TDM */
447 {0, 4, 8, 12, 16, 20, 0xFFFF},
448 {24, 0xFFFF},
449 {28, 0xFFFF},
450 {0xFFFF}, /* not used */
451 {0xFFFF}, /* not used */
452 {0xFFFF}, /* not used */
453 {0xFFFF}, /* not used */
454 {0xFFFF}, /* not used */
455 },
456 {/* TERT TDM */
457 {0, 4, 8, 12, 0xFFFF},
458 {16, 20, 0xFFFF},
459 {24, 28, 0xFFFF},
460 {0xFFFF}, /* not used */
461 {0xFFFF}, /* not used */
462 {0xFFFF}, /* not used */
463 {0xFFFF}, /* not used */
464 {0xFFFF}, /* not used */
465 },
466 {/* QUAT TDM */
467 {0xFFFF}, /* not used */
468 {0xFFFF}, /* not used */
469 {0xFFFF}, /* not used */
470 {0xFFFF}, /* not used */
471 {0xFFFF}, /* not used */
472 {0xFFFF}, /* not used */
473 {0xFFFF}, /* not used */
474 {0xFFFF}, /* not used */
475 },
476 {/* QUIN TDM */
477 {0xFFFF}, /* not used */
478 {0xFFFF}, /* not used */
479 {0xFFFF}, /* not used */
480 {0xFFFF}, /* not used */
481 {0xFFFF}, /* not used */
482 {0xFFFF}, /* not used */
483 {0xFFFF}, /* not used */
484 {0xFFFF}, /* not used */
485 }
486};
487
488/*****************************************************************************
489* NOTE:
490* Each entry represents the slot offset array of one backend tdm device
491* valid offset represents the starting offset in byte for the channel
492* use 0xFFFF for end or unused slot offset entry.
493*****************************************************************************/
494static unsigned int tdm_rx_slot_offset_custom
495 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
496 {/* PRI TDM */
497 {0xFFFF}, /* not used */
498 {0xFFFF}, /* not used */
499 {0xFFFF}, /* not used */
500 {0xFFFF}, /* not used */
501 {0xFFFF}, /* not used */
502 {0xFFFF}, /* not used */
503 {0xFFFF}, /* not used */
504 {0xFFFF}, /* not used */
505 },
506 {/* SEC TDM */
507 {0, 2, 0xFFFF},
508 {4, 0xFFFF},
509 {6, 0xFFFF},
510 {8, 0xFFFF},
511 {10, 0xFFFF},
512 {12, 14, 16, 18, 20, 22, 24, 26, 0xFFFF},
513 {28, 30, 0xFFFF},
514 {0xFFFF}, /* not used */
515 },
516 {/* TERT TDM */
517 {0, 2, 0xFFFF},
518 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
519 {20, 22, 24, 26, 28, 30, 0xFFFF},
520 {0xFFFF}, /* not used */
521 {0xFFFF}, /* not used */
522 {0xFFFF}, /* not used */
523 {0xFFFF}, /* not used */
524 {0xFFFF}, /* not used */
525 },
526 {/* QUAT TDM */
527 {0xFFFF}, /* not used */
528 {0xFFFF}, /* not used */
529 {0xFFFF}, /* not used */
530 {0xFFFF}, /* not used */
531 {0xFFFF}, /* not used */
532 {0xFFFF}, /* not used */
533 {0xFFFF}, /* not used */
534 {0xFFFF}, /* not used */
535 },
536 {/* QUIN TDM */
537 {0xFFFF}, /* not used */
538 {0xFFFF}, /* not used */
539 {0xFFFF}, /* not used */
540 {0xFFFF}, /* not used */
541 {0xFFFF}, /* not used */
542 {0xFFFF}, /* not used */
543 {0xFFFF}, /* not used */
544 {0xFFFF}, /* not used */
545 }
546};
547
548static unsigned int tdm_tx_slot_offset_custom
549 [TDM_INTERFACE_MAX][TDM_PORT_MAX][TDM_SLOT_OFFSET_MAX] = {
550 {/* PRI TDM */
551 {0xFFFF}, /* not used */
552 {0xFFFF}, /* not used */
553 {0xFFFF}, /* not used */
554 {0xFFFF}, /* not used */
555 {0xFFFF}, /* not used */
556 {0xFFFF}, /* not used */
557 {0xFFFF}, /* not used */
558 {0xFFFF}, /* not used */
559 },
560 {/* SEC TDM */
561 {0, 2, 0xFFFF},
562 {4, 6, 8, 10, 12, 14, 16, 18, 0xFFFF},
563 {20, 22, 24, 26, 28, 30, 0xFFFF},
564 {0xFFFF}, /* not used */
565 {0xFFFF}, /* not used */
566 {0xFFFF}, /* not used */
567 {0xFFFF}, /* not used */
568 {0xFFFF}, /* not used */
569 },
570 {/* TERT TDM */
571 {0, 2, 4, 6, 8, 10, 12, 0xFFFF},
572 {14, 16, 0xFFFF},
573 {18, 20, 22, 24, 26, 28, 30, 0xFFFF},
574 {0xFFFF}, /* not used */
575 {0xFFFF}, /* not used */
576 {0xFFFF}, /* not used */
577 {0xFFFF}, /* not used */
578 {0xFFFF}, /* not used */
579 },
580 {/* QUAT TDM */
581 {0xFFFF}, /* not used */
582 {0xFFFF}, /* not used */
583 {0xFFFF}, /* not used */
584 {0xFFFF}, /* not used */
585 {0xFFFF}, /* not used */
586 {0xFFFF}, /* not used */
587 {0xFFFF}, /* not used */
588 {0xFFFF}, /* not used */
589 },
590 {/* QUIN TDM */
591 {0xFFFF}, /* not used */
592 {0xFFFF}, /* not used */
593 {0xFFFF}, /* not used */
594 {0xFFFF}, /* not used */
595 {0xFFFF}, /* not used */
596 {0xFFFF}, /* not used */
597 {0xFFFF}, /* not used */
598 {0xFFFF}, /* not used */
599 }
600};
601
602
603static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
604 "S32_LE"};
605static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
606 "S24_3LE"};
607static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
608 "Five", "Six", "Seven",
609 "Eight"};
610static char const *ch_text[] = {"Two", "Three", "Four", "Five",
611 "Six", "Seven", "Eight"};
612static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
613 "KHZ_16", "KHZ_22P05",
614 "KHZ_32", "KHZ_44P1", "KHZ_48",
615 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
616 "KHZ_192", "KHZ_352P8", "KHZ_384"};
617static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
618 "KHZ_192", "KHZ_32", "KHZ_44P1",
619 "KHZ_88P2", "KHZ_176P4"};
620static char const *tdm_ch_text[] = {
621 "One", "Two", "Three", "Four",
622 "Five", "Six", "Seven", "Eight",
623 "Nine", "Ten", "Eleven", "Twelve",
624 "Thirteen", "Fourteen", "Fifteen", "Sixteen",
625 "Seventeen", "Eighteen", "Nineteen", "Twenty",
626 "TwentyOne", "TwentyTwo", "TwentyThree", "TwentyFour",
627 "TwentyFive", "TwentySix", "TwentySeven", "TwentyEight",
628 "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo"};
629static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
630static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
631 "KHZ_48", "KHZ_176P4",
632 "KHZ_352P8"};
633static const char *const tdm_slot_num_text[] = {"One", "Two", "Four",
634 "Eight", "Sixteen", "ThirtyTwo"};
635static const char *const tdm_slot_width_text[] = {"16", "24", "32"};
636static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
637static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
638 "KHZ_22P05", "KHZ_32", "KHZ_44P1",
639 "KHZ_48", "KHZ_96", "KHZ_192"};
640static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
641 "Five", "Six", "Seven",
642 "Eight"};
643static const char *const qos_text[] = {"Disable", "Enable"};
644
645static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
646static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
647static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
648static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
649static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
650static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
651static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
652static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
653static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
654static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
655 ext_disp_sample_rate_text);
656static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
657static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
658static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
659static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
660static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
661static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
662static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text);
663static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text);
664static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
665static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
666static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
667static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
668static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
669static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
670static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
671static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
672static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
673static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
674static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
675static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
676static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
677static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
678static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
679static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
680static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
681static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
682static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
683static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
684static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
685static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
686static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
687static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
688static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
689static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
690static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
691static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
692static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
693static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
694static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
695static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
696static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
697static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
698
699static bool is_initial_boot = true;
700
701static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
702 {
703 AFE_API_VERSION_I2S_CONFIG,
704 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
705 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
706 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
707 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
708 0,
709 },
710 {
711 AFE_API_VERSION_I2S_CONFIG,
712 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
713 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
714 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
715 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
716 0,
717 },
718 {
719 AFE_API_VERSION_I2S_CONFIG,
720 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
721 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
722 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
723 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
724 0,
725 },
726 {
727 AFE_API_VERSION_I2S_CONFIG,
728 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
729 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
730 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
731 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
732 0,
733 },
734 {
735 AFE_API_VERSION_I2S_CONFIG,
736 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
737 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
738 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
739 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
740 0,
741 }
742
743};
744
745static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
746
747static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
748 struct snd_ctl_elem_value *ucontrol)
749{
750 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
751 usb_rx_cfg.channels);
752 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
753 return 0;
754}
755
756static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
757 struct snd_ctl_elem_value *ucontrol)
758{
759 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
760
761 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
762 return 1;
763}
764
765static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
766 struct snd_ctl_elem_value *ucontrol)
767{
768 int sample_rate_val;
769
770 switch (usb_rx_cfg.sample_rate) {
771 case SAMPLING_RATE_384KHZ:
772 sample_rate_val = 12;
773 break;
774 case SAMPLING_RATE_352P8KHZ:
775 sample_rate_val = 11;
776 break;
777 case SAMPLING_RATE_192KHZ:
778 sample_rate_val = 10;
779 break;
780 case SAMPLING_RATE_176P4KHZ:
781 sample_rate_val = 9;
782 break;
783 case SAMPLING_RATE_96KHZ:
784 sample_rate_val = 8;
785 break;
786 case SAMPLING_RATE_88P2KHZ:
787 sample_rate_val = 7;
788 break;
789 case SAMPLING_RATE_48KHZ:
790 sample_rate_val = 6;
791 break;
792 case SAMPLING_RATE_44P1KHZ:
793 sample_rate_val = 5;
794 break;
795 case SAMPLING_RATE_32KHZ:
796 sample_rate_val = 4;
797 break;
798 case SAMPLING_RATE_22P05KHZ:
799 sample_rate_val = 3;
800 break;
801 case SAMPLING_RATE_16KHZ:
802 sample_rate_val = 2;
803 break;
804 case SAMPLING_RATE_11P025KHZ:
805 sample_rate_val = 1;
806 break;
807 case SAMPLING_RATE_8KHZ:
808 default:
809 sample_rate_val = 0;
810 break;
811 }
812
813 ucontrol->value.integer.value[0] = sample_rate_val;
814 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
815 usb_rx_cfg.sample_rate);
816 return 0;
817}
818
819static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
820 struct snd_ctl_elem_value *ucontrol)
821{
822 switch (ucontrol->value.integer.value[0]) {
823 case 12:
824 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
825 break;
826 case 11:
827 usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
828 break;
829 case 10:
830 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
831 break;
832 case 9:
833 usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
834 break;
835 case 8:
836 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
837 break;
838 case 7:
839 usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
840 break;
841 case 6:
842 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
843 break;
844 case 5:
845 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
846 break;
847 case 4:
848 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
849 break;
850 case 3:
851 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
852 break;
853 case 2:
854 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
855 break;
856 case 1:
857 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
858 break;
859 case 0:
860 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
861 break;
862 default:
863 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
864 break;
865 }
866
867 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
868 __func__, ucontrol->value.integer.value[0],
869 usb_rx_cfg.sample_rate);
870 return 0;
871}
872
873static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
874 struct snd_ctl_elem_value *ucontrol)
875{
876 switch (usb_rx_cfg.bit_format) {
877 case SNDRV_PCM_FORMAT_S32_LE:
878 ucontrol->value.integer.value[0] = 3;
879 break;
880 case SNDRV_PCM_FORMAT_S24_3LE:
881 ucontrol->value.integer.value[0] = 2;
882 break;
883 case SNDRV_PCM_FORMAT_S24_LE:
884 ucontrol->value.integer.value[0] = 1;
885 break;
886 case SNDRV_PCM_FORMAT_S16_LE:
887 default:
888 ucontrol->value.integer.value[0] = 0;
889 break;
890 }
891
892 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
893 __func__, usb_rx_cfg.bit_format,
894 ucontrol->value.integer.value[0]);
895 return 0;
896}
897
898static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
899 struct snd_ctl_elem_value *ucontrol)
900{
901 int rc = 0;
902
903 switch (ucontrol->value.integer.value[0]) {
904 case 3:
905 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
906 break;
907 case 2:
908 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
909 break;
910 case 1:
911 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
912 break;
913 case 0:
914 default:
915 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
916 break;
917 }
918 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
919 __func__, usb_rx_cfg.bit_format,
920 ucontrol->value.integer.value[0]);
921
922 return rc;
923}
924
925static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
926 struct snd_ctl_elem_value *ucontrol)
927{
928 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
929 usb_tx_cfg.channels);
930 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
931 return 0;
932}
933
934static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936{
937 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
938
939 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
940 return 1;
941}
942
943static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
944 struct snd_ctl_elem_value *ucontrol)
945{
946 int sample_rate_val;
947
948 switch (usb_tx_cfg.sample_rate) {
949 case SAMPLING_RATE_384KHZ:
950 sample_rate_val = 12;
951 break;
952 case SAMPLING_RATE_352P8KHZ:
953 sample_rate_val = 11;
954 break;
955 case SAMPLING_RATE_192KHZ:
956 sample_rate_val = 10;
957 break;
958 case SAMPLING_RATE_176P4KHZ:
959 sample_rate_val = 9;
960 break;
961 case SAMPLING_RATE_96KHZ:
962 sample_rate_val = 8;
963 break;
964 case SAMPLING_RATE_88P2KHZ:
965 sample_rate_val = 7;
966 break;
967 case SAMPLING_RATE_48KHZ:
968 sample_rate_val = 6;
969 break;
970 case SAMPLING_RATE_44P1KHZ:
971 sample_rate_val = 5;
972 break;
973 case SAMPLING_RATE_32KHZ:
974 sample_rate_val = 4;
975 break;
976 case SAMPLING_RATE_22P05KHZ:
977 sample_rate_val = 3;
978 break;
979 case SAMPLING_RATE_16KHZ:
980 sample_rate_val = 2;
981 break;
982 case SAMPLING_RATE_11P025KHZ:
983 sample_rate_val = 1;
984 break;
985 case SAMPLING_RATE_8KHZ:
986 sample_rate_val = 0;
987 break;
988 default:
989 sample_rate_val = 6;
990 break;
991 }
992
993 ucontrol->value.integer.value[0] = sample_rate_val;
994 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
995 usb_tx_cfg.sample_rate);
996 return 0;
997}
998
999static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1000 struct snd_ctl_elem_value *ucontrol)
1001{
1002 switch (ucontrol->value.integer.value[0]) {
1003 case 12:
1004 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
1005 break;
1006 case 11:
1007 usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
1008 break;
1009 case 10:
1010 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
1011 break;
1012 case 9:
1013 usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
1014 break;
1015 case 8:
1016 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
1017 break;
1018 case 7:
1019 usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
1020 break;
1021 case 6:
1022 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1023 break;
1024 case 5:
1025 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
1026 break;
1027 case 4:
1028 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
1029 break;
1030 case 3:
1031 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
1032 break;
1033 case 2:
1034 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
1035 break;
1036 case 1:
1037 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
1038 break;
1039 case 0:
1040 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
1041 break;
1042 default:
1043 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1044 break;
1045 }
1046
1047 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
1048 __func__, ucontrol->value.integer.value[0],
1049 usb_tx_cfg.sample_rate);
1050 return 0;
1051}
1052
1053static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
1054 struct snd_ctl_elem_value *ucontrol)
1055{
1056 switch (usb_tx_cfg.bit_format) {
1057 case SNDRV_PCM_FORMAT_S32_LE:
1058 ucontrol->value.integer.value[0] = 3;
1059 break;
1060 case SNDRV_PCM_FORMAT_S24_3LE:
1061 ucontrol->value.integer.value[0] = 2;
1062 break;
1063 case SNDRV_PCM_FORMAT_S24_LE:
1064 ucontrol->value.integer.value[0] = 1;
1065 break;
1066 case SNDRV_PCM_FORMAT_S16_LE:
1067 default:
1068 ucontrol->value.integer.value[0] = 0;
1069 break;
1070 }
1071
1072 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1073 __func__, usb_tx_cfg.bit_format,
1074 ucontrol->value.integer.value[0]);
1075 return 0;
1076}
1077
1078static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
1079 struct snd_ctl_elem_value *ucontrol)
1080{
1081 int rc = 0;
1082
1083 switch (ucontrol->value.integer.value[0]) {
1084 case 3:
1085 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
1086 break;
1087 case 2:
1088 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1089 break;
1090 case 1:
1091 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
1092 break;
1093 case 0:
1094 default:
1095 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
1096 break;
1097 }
1098 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
1099 __func__, usb_tx_cfg.bit_format,
1100 ucontrol->value.integer.value[0]);
1101
1102 return rc;
1103}
1104
1105static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
1106{
1107 int idx = 0;
1108
1109 if (strnstr(kcontrol->id.name, "Display Port RX",
1110 sizeof("Display Port RX"))) {
1111 idx = DP_RX_IDX;
1112 } else {
1113 pr_err("%s: unsupported BE: %s\n",
1114 __func__, kcontrol->id.name);
1115 idx = -EINVAL;
1116 }
1117
1118 return idx;
1119}
1120
1121static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
1122 struct snd_ctl_elem_value *ucontrol)
1123{
1124 int idx = ext_disp_get_port_idx(kcontrol);
1125
1126 if (idx < 0)
1127 return idx;
1128
1129 switch (ext_disp_rx_cfg[idx].bit_format) {
1130 case SNDRV_PCM_FORMAT_S24_3LE:
1131 ucontrol->value.integer.value[0] = 2;
1132 break;
1133 case SNDRV_PCM_FORMAT_S24_LE:
1134 ucontrol->value.integer.value[0] = 1;
1135 break;
1136 case SNDRV_PCM_FORMAT_S16_LE:
1137 default:
1138 ucontrol->value.integer.value[0] = 0;
1139 break;
1140 }
1141
1142 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1143 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1144 ucontrol->value.integer.value[0]);
1145 return 0;
1146}
1147
1148static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
1149 struct snd_ctl_elem_value *ucontrol)
1150{
1151 int idx = ext_disp_get_port_idx(kcontrol);
1152
1153 if (idx < 0)
1154 return idx;
1155
1156 switch (ucontrol->value.integer.value[0]) {
1157 case 2:
1158 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1159 break;
1160 case 1:
1161 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1162 break;
1163 case 0:
1164 default:
1165 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1166 break;
1167 }
1168 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
1169 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
1170 ucontrol->value.integer.value[0]);
1171
1172 return 0;
1173}
1174
1175static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
1176 struct snd_ctl_elem_value *ucontrol)
1177{
1178 int idx = ext_disp_get_port_idx(kcontrol);
1179
1180 if (idx < 0)
1181 return idx;
1182
1183 ucontrol->value.integer.value[0] =
1184 ext_disp_rx_cfg[idx].channels - 2;
1185
1186 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1187 idx, ext_disp_rx_cfg[idx].channels);
1188
1189 return 0;
1190}
1191
1192static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
1193 struct snd_ctl_elem_value *ucontrol)
1194{
1195 int idx = ext_disp_get_port_idx(kcontrol);
1196
1197 if (idx < 0)
1198 return idx;
1199
1200 ext_disp_rx_cfg[idx].channels =
1201 ucontrol->value.integer.value[0] + 2;
1202
1203 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
1204 idx, ext_disp_rx_cfg[idx].channels);
1205 return 1;
1206}
1207
1208static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1209 struct snd_ctl_elem_value *ucontrol)
1210{
1211 int sample_rate_val;
1212 int idx = ext_disp_get_port_idx(kcontrol);
1213
1214 if (idx < 0)
1215 return idx;
1216
1217 switch (ext_disp_rx_cfg[idx].sample_rate) {
1218 case SAMPLING_RATE_176P4KHZ:
1219 sample_rate_val = 6;
1220 break;
1221
1222 case SAMPLING_RATE_88P2KHZ:
1223 sample_rate_val = 5;
1224 break;
1225
1226 case SAMPLING_RATE_44P1KHZ:
1227 sample_rate_val = 4;
1228 break;
1229
1230 case SAMPLING_RATE_32KHZ:
1231 sample_rate_val = 3;
1232 break;
1233
1234 case SAMPLING_RATE_192KHZ:
1235 sample_rate_val = 2;
1236 break;
1237
1238 case SAMPLING_RATE_96KHZ:
1239 sample_rate_val = 1;
1240 break;
1241
1242 case SAMPLING_RATE_48KHZ:
1243 default:
1244 sample_rate_val = 0;
1245 break;
1246 }
1247
1248 ucontrol->value.integer.value[0] = sample_rate_val;
1249 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
1250 idx, ext_disp_rx_cfg[idx].sample_rate);
1251
1252 return 0;
1253}
1254
1255static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1256 struct snd_ctl_elem_value *ucontrol)
1257{
1258 int idx = ext_disp_get_port_idx(kcontrol);
1259
1260 if (idx < 0)
1261 return idx;
1262
1263 switch (ucontrol->value.integer.value[0]) {
1264 case 6:
1265 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
1266 break;
1267 case 5:
1268 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
1269 break;
1270 case 4:
1271 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
1272 break;
1273 case 3:
1274 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
1275 break;
1276 case 2:
1277 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
1278 break;
1279 case 1:
1280 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
1281 break;
1282 case 0:
1283 default:
1284 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
1285 break;
1286 }
1287
1288 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
1289 __func__, ucontrol->value.integer.value[0], idx,
1290 ext_disp_rx_cfg[idx].sample_rate);
1291 return 0;
1292}
1293
1294static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
1295 struct snd_ctl_elem_value *ucontrol)
1296{
1297 pr_debug("%s: proxy_rx channels = %d\n",
1298 __func__, proxy_rx_cfg.channels);
1299 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
1300
1301 return 0;
1302}
1303
1304static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
1305 struct snd_ctl_elem_value *ucontrol)
1306{
1307 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
1308 pr_debug("%s: proxy_rx channels = %d\n",
1309 __func__, proxy_rx_cfg.channels);
1310
1311 return 1;
1312}
1313
1314static int tdm_get_sample_rate(int value)
1315{
1316 int sample_rate = 0;
1317
1318 switch (value) {
1319 case 0:
1320 sample_rate = SAMPLING_RATE_8KHZ;
1321 break;
1322 case 1:
1323 sample_rate = SAMPLING_RATE_16KHZ;
1324 break;
1325 case 2:
1326 sample_rate = SAMPLING_RATE_32KHZ;
1327 break;
1328 case 3:
1329 sample_rate = SAMPLING_RATE_48KHZ;
1330 break;
1331 case 4:
1332 sample_rate = SAMPLING_RATE_176P4KHZ;
1333 break;
1334 case 5:
1335 sample_rate = SAMPLING_RATE_352P8KHZ;
1336 break;
1337 default:
1338 sample_rate = SAMPLING_RATE_48KHZ;
1339 break;
1340 }
1341 return sample_rate;
1342}
1343
1344static int aux_pcm_get_sample_rate(int value)
1345{
1346 int sample_rate;
1347
1348 switch (value) {
1349 case 1:
1350 sample_rate = SAMPLING_RATE_16KHZ;
1351 break;
1352 case 0:
1353 default:
1354 sample_rate = SAMPLING_RATE_8KHZ;
1355 break;
1356 }
1357 return sample_rate;
1358}
1359
1360static int tdm_get_sample_rate_val(int sample_rate)
1361{
1362 int sample_rate_val = 0;
1363
1364 switch (sample_rate) {
1365 case SAMPLING_RATE_8KHZ:
1366 sample_rate_val = 0;
1367 break;
1368 case SAMPLING_RATE_16KHZ:
1369 sample_rate_val = 1;
1370 break;
1371 case SAMPLING_RATE_32KHZ:
1372 sample_rate_val = 2;
1373 break;
1374 case SAMPLING_RATE_48KHZ:
1375 sample_rate_val = 3;
1376 break;
1377 case SAMPLING_RATE_176P4KHZ:
1378 sample_rate_val = 4;
1379 break;
1380 case SAMPLING_RATE_352P8KHZ:
1381 sample_rate_val = 5;
1382 break;
1383 default:
1384 sample_rate_val = 3;
1385 break;
1386 }
1387 return sample_rate_val;
1388}
1389
1390static int aux_pcm_get_sample_rate_val(int sample_rate)
1391{
1392 int sample_rate_val = 0;
1393
1394 switch (sample_rate) {
1395 case SAMPLING_RATE_16KHZ:
1396 sample_rate_val = 1;
1397 break;
1398 case SAMPLING_RATE_8KHZ:
1399 default:
1400 sample_rate_val = 0;
1401 break;
1402 }
1403 return sample_rate_val;
1404}
1405
1406static int tdm_get_mode(struct snd_kcontrol *kcontrol)
1407{
1408 int mode = TDM_PRI;
1409
1410 if (strnstr(kcontrol->id.name, "PRI",
1411 sizeof(kcontrol->id.name))) {
1412 mode = TDM_PRI;
1413 } else if (strnstr(kcontrol->id.name, "SEC",
1414 sizeof(kcontrol->id.name))) {
1415 mode = TDM_SEC;
1416 } else if (strnstr(kcontrol->id.name, "TERT",
1417 sizeof(kcontrol->id.name))) {
1418 mode = TDM_TERT;
1419 } else if (strnstr(kcontrol->id.name, "QUAT",
1420 sizeof(kcontrol->id.name))) {
1421 mode = TDM_QUAT;
1422 } else if (strnstr(kcontrol->id.name, "QUIN",
1423 sizeof(kcontrol->id.name))) {
1424 mode = TDM_QUIN;
1425 } else {
1426 pr_err("%s: unsupported mode in: %s",
1427 __func__, kcontrol->id.name);
1428 mode = -EINVAL;
1429 }
1430
1431 return mode;
1432}
1433
1434static int tdm_get_channel(struct snd_kcontrol *kcontrol)
1435{
1436 int channel = TDM_0;
1437
1438 if (strnstr(kcontrol->id.name, "RX_0",
1439 sizeof(kcontrol->id.name)) ||
1440 strnstr(kcontrol->id.name, "TX_0",
1441 sizeof(kcontrol->id.name))) {
1442 channel = TDM_0;
1443 } else if (strnstr(kcontrol->id.name, "RX_1",
1444 sizeof(kcontrol->id.name)) ||
1445 strnstr(kcontrol->id.name, "TX_1",
1446 sizeof(kcontrol->id.name))) {
1447 channel = TDM_1;
1448 } else if (strnstr(kcontrol->id.name, "RX_2",
1449 sizeof(kcontrol->id.name)) ||
1450 strnstr(kcontrol->id.name, "TX_2",
1451 sizeof(kcontrol->id.name))) {
1452 channel = TDM_2;
1453 } else if (strnstr(kcontrol->id.name, "RX_3",
1454 sizeof(kcontrol->id.name)) ||
1455 strnstr(kcontrol->id.name, "TX_3",
1456 sizeof(kcontrol->id.name))) {
1457 channel = TDM_3;
1458 } else if (strnstr(kcontrol->id.name, "RX_4",
1459 sizeof(kcontrol->id.name)) ||
1460 strnstr(kcontrol->id.name, "TX_4",
1461 sizeof(kcontrol->id.name))) {
1462 channel = TDM_4;
1463 } else if (strnstr(kcontrol->id.name, "RX_5",
1464 sizeof(kcontrol->id.name)) ||
1465 strnstr(kcontrol->id.name, "TX_5",
1466 sizeof(kcontrol->id.name))) {
1467 channel = TDM_5;
1468 } else if (strnstr(kcontrol->id.name, "RX_6",
1469 sizeof(kcontrol->id.name)) ||
1470 strnstr(kcontrol->id.name, "TX_6",
1471 sizeof(kcontrol->id.name))) {
1472 channel = TDM_6;
1473 } else if (strnstr(kcontrol->id.name, "RX_7",
1474 sizeof(kcontrol->id.name)) ||
1475 strnstr(kcontrol->id.name, "TX_7",
1476 sizeof(kcontrol->id.name))) {
1477 channel = TDM_7;
1478 } else {
1479 pr_err("%s: unsupported channel in: %s",
1480 __func__, kcontrol->id.name);
1481 channel = -EINVAL;
1482 }
1483
1484 return channel;
1485}
1486
1487static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
1488 struct tdm_port *port)
1489{
1490 if (port) {
1491 port->mode = tdm_get_mode(kcontrol);
1492 if (port->mode < 0)
1493 return port->mode;
1494
1495 port->channel = tdm_get_channel(kcontrol);
1496 if (port->channel < 0)
1497 return port->channel;
1498 } else {
1499 return -EINVAL;
1500 }
1501 return 0;
1502}
1503
1504static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1505 struct snd_ctl_elem_value *ucontrol)
1506{
1507 struct tdm_port port;
1508 int ret = tdm_get_port_idx(kcontrol, &port);
1509
1510 if (ret) {
1511 pr_err("%s: unsupported control: %s\n",
1512 __func__, kcontrol->id.name);
1513 } else {
1514 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1515 tdm_rx_cfg[port.mode][port.channel].sample_rate);
1516
1517 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1518 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1519 ucontrol->value.enumerated.item[0]);
1520 }
1521 return ret;
1522}
1523
1524static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1525 struct snd_ctl_elem_value *ucontrol)
1526{
1527 struct tdm_port port;
1528 int ret = tdm_get_port_idx(kcontrol, &port);
1529
1530 if (ret) {
1531 pr_err("%s: unsupported control: %s\n",
1532 __func__, kcontrol->id.name);
1533 } else {
1534 tdm_rx_cfg[port.mode][port.channel].sample_rate =
1535 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1536
1537 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
1538 tdm_rx_cfg[port.mode][port.channel].sample_rate,
1539 ucontrol->value.enumerated.item[0]);
1540 }
1541 return ret;
1542}
1543
1544static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1545 struct snd_ctl_elem_value *ucontrol)
1546{
1547 struct tdm_port port;
1548 int ret = tdm_get_port_idx(kcontrol, &port);
1549
1550 if (ret) {
1551 pr_err("%s: unsupported control: %s",
1552 __func__, kcontrol->id.name);
1553 } else {
1554 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
1555 tdm_tx_cfg[port.mode][port.channel].sample_rate);
1556
1557 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1558 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1559 ucontrol->value.enumerated.item[0]);
1560 }
1561 return ret;
1562}
1563
1564static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1565 struct snd_ctl_elem_value *ucontrol)
1566{
1567 struct tdm_port port;
1568 int ret = tdm_get_port_idx(kcontrol, &port);
1569
1570 if (ret) {
1571 pr_err("%s: unsupported control: %s\n",
1572 __func__, kcontrol->id.name);
1573 } else {
1574 tdm_tx_cfg[port.mode][port.channel].sample_rate =
1575 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
1576
1577 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
1578 tdm_tx_cfg[port.mode][port.channel].sample_rate,
1579 ucontrol->value.enumerated.item[0]);
1580 }
1581 return ret;
1582}
1583
1584static int tdm_get_format(int value)
1585{
1586 int format = 0;
1587
1588 switch (value) {
1589 case 0:
1590 format = SNDRV_PCM_FORMAT_S16_LE;
1591 break;
1592 case 1:
1593 format = SNDRV_PCM_FORMAT_S24_LE;
1594 break;
1595 case 2:
1596 format = SNDRV_PCM_FORMAT_S32_LE;
1597 break;
1598 default:
1599 format = SNDRV_PCM_FORMAT_S16_LE;
1600 break;
1601 }
1602 return format;
1603}
1604
1605static int tdm_get_format_val(int format)
1606{
1607 int value = 0;
1608
1609 switch (format) {
1610 case SNDRV_PCM_FORMAT_S16_LE:
1611 value = 0;
1612 break;
1613 case SNDRV_PCM_FORMAT_S24_LE:
1614 value = 1;
1615 break;
1616 case SNDRV_PCM_FORMAT_S32_LE:
1617 value = 2;
1618 break;
1619 default:
1620 value = 0;
1621 break;
1622 }
1623 return value;
1624}
1625
1626static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
1627 struct snd_ctl_elem_value *ucontrol)
1628{
1629 struct tdm_port port;
1630 int ret = tdm_get_port_idx(kcontrol, &port);
1631
1632 if (ret) {
1633 pr_err("%s: unsupported control: %s\n",
1634 __func__, kcontrol->id.name);
1635 } else {
1636 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1637 tdm_rx_cfg[port.mode][port.channel].bit_format);
1638
1639 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1640 tdm_rx_cfg[port.mode][port.channel].bit_format,
1641 ucontrol->value.enumerated.item[0]);
1642 }
1643 return ret;
1644}
1645
1646static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
1647 struct snd_ctl_elem_value *ucontrol)
1648{
1649 struct tdm_port port;
1650 int ret = tdm_get_port_idx(kcontrol, &port);
1651
1652 if (ret) {
1653 pr_err("%s: unsupported control: %s\n",
1654 __func__, kcontrol->id.name);
1655 } else {
1656 tdm_rx_cfg[port.mode][port.channel].bit_format =
1657 tdm_get_format(ucontrol->value.enumerated.item[0]);
1658
1659 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
1660 tdm_rx_cfg[port.mode][port.channel].bit_format,
1661 ucontrol->value.enumerated.item[0]);
1662 }
1663 return ret;
1664}
1665
1666static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
1667 struct snd_ctl_elem_value *ucontrol)
1668{
1669 struct tdm_port port;
1670 int ret = tdm_get_port_idx(kcontrol, &port);
1671
1672 if (ret) {
1673 pr_err("%s: unsupported control: %s\n",
1674 __func__, kcontrol->id.name);
1675 } else {
1676 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
1677 tdm_tx_cfg[port.mode][port.channel].bit_format);
1678
1679 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1680 tdm_tx_cfg[port.mode][port.channel].bit_format,
1681 ucontrol->value.enumerated.item[0]);
1682 }
1683 return ret;
1684}
1685
1686static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
1687 struct snd_ctl_elem_value *ucontrol)
1688{
1689 struct tdm_port port;
1690 int ret = tdm_get_port_idx(kcontrol, &port);
1691
1692 if (ret) {
1693 pr_err("%s: unsupported control: %s\n",
1694 __func__, kcontrol->id.name);
1695 } else {
1696 tdm_tx_cfg[port.mode][port.channel].bit_format =
1697 tdm_get_format(ucontrol->value.enumerated.item[0]);
1698
1699 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
1700 tdm_tx_cfg[port.mode][port.channel].bit_format,
1701 ucontrol->value.enumerated.item[0]);
1702 }
1703 return ret;
1704}
1705
1706static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
1707 struct snd_ctl_elem_value *ucontrol)
1708{
1709 struct tdm_port port;
1710 int ret = tdm_get_port_idx(kcontrol, &port);
1711
1712 if (ret) {
1713 pr_err("%s: unsupported control: %s\n",
1714 __func__, kcontrol->id.name);
1715 } else {
1716
1717 ucontrol->value.enumerated.item[0] =
1718 tdm_rx_cfg[port.mode][port.channel].channels - 1;
1719
1720 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1721 tdm_rx_cfg[port.mode][port.channel].channels - 1,
1722 ucontrol->value.enumerated.item[0]);
1723 }
1724 return ret;
1725}
1726
1727static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
1728 struct snd_ctl_elem_value *ucontrol)
1729{
1730 struct tdm_port port;
1731 int ret = tdm_get_port_idx(kcontrol, &port);
1732
1733 if (ret) {
1734 pr_err("%s: unsupported control: %s\n",
1735 __func__, kcontrol->id.name);
1736 } else {
1737 tdm_rx_cfg[port.mode][port.channel].channels =
1738 ucontrol->value.enumerated.item[0] + 1;
1739
1740 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
1741 tdm_rx_cfg[port.mode][port.channel].channels,
1742 ucontrol->value.enumerated.item[0] + 1);
1743 }
1744 return ret;
1745}
1746
1747static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
1748 struct snd_ctl_elem_value *ucontrol)
1749{
1750 struct tdm_port port;
1751 int ret = tdm_get_port_idx(kcontrol, &port);
1752
1753 if (ret) {
1754 pr_err("%s: unsupported control: %s\n",
1755 __func__, kcontrol->id.name);
1756 } else {
1757 ucontrol->value.enumerated.item[0] =
1758 tdm_tx_cfg[port.mode][port.channel].channels - 1;
1759
1760 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1761 tdm_tx_cfg[port.mode][port.channel].channels - 1,
1762 ucontrol->value.enumerated.item[0]);
1763 }
1764 return ret;
1765}
1766
1767static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
1768 struct snd_ctl_elem_value *ucontrol)
1769{
1770 struct tdm_port port;
1771 int ret = tdm_get_port_idx(kcontrol, &port);
1772
1773 if (ret) {
1774 pr_err("%s: unsupported control: %s\n",
1775 __func__, kcontrol->id.name);
1776 } else {
1777 tdm_tx_cfg[port.mode][port.channel].channels =
1778 ucontrol->value.enumerated.item[0] + 1;
1779
1780 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
1781 tdm_tx_cfg[port.mode][port.channel].channels,
1782 ucontrol->value.enumerated.item[0] + 1);
1783 }
1784 return ret;
1785}
1786
1787static int tdm_get_slot_num_val(int slot_num)
1788{
1789 int slot_num_val = 0;
1790
1791 switch (slot_num) {
1792 case 1:
1793 slot_num_val = 0;
1794 break;
1795 case 2:
1796 slot_num_val = 1;
1797 break;
1798 case 4:
1799 slot_num_val = 2;
1800 break;
1801 case 8:
1802 slot_num_val = 3;
1803 break;
1804 case 16:
1805 slot_num_val = 4;
1806 break;
1807 case 32:
1808 slot_num_val = 5;
1809 break;
1810 default:
1811 slot_num_val = 5;
1812 break;
1813 }
1814 return slot_num_val;
1815}
1816
1817static int tdm_slot_num_get(struct snd_kcontrol *kcontrol,
1818 struct snd_ctl_elem_value *ucontrol)
1819{
1820 int mode = tdm_get_mode(kcontrol);
1821
1822 if (mode < 0) {
1823 pr_err("%s: unsupported control: %s\n",
1824 __func__, kcontrol->id.name);
1825 return mode;
1826 }
1827
1828 ucontrol->value.enumerated.item[0] =
1829 tdm_get_slot_num_val(tdm_slot[mode].num);
1830
1831 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1832 mode, tdm_slot[mode].num,
1833 ucontrol->value.enumerated.item[0]);
1834
1835 return 0;
1836}
1837
1838static int tdm_get_slot_num(int value)
1839{
1840 int slot_num = 0;
1841
1842 switch (value) {
1843 case 0:
1844 slot_num = 1;
1845 break;
1846 case 1:
1847 slot_num = 2;
1848 break;
1849 case 2:
1850 slot_num = 4;
1851 break;
1852 case 3:
1853 slot_num = 8;
1854 break;
1855 case 4:
1856 slot_num = 16;
1857 break;
1858 case 5:
1859 slot_num = 32;
1860 break;
1861 default:
1862 slot_num = 8;
1863 break;
1864 }
1865 return slot_num;
1866}
1867
1868static int tdm_slot_num_put(struct snd_kcontrol *kcontrol,
1869 struct snd_ctl_elem_value *ucontrol)
1870{
1871 int mode = tdm_get_mode(kcontrol);
1872
1873 if (mode < 0) {
1874 pr_err("%s: unsupported control: %s\n",
1875 __func__, kcontrol->id.name);
1876 return mode;
1877 }
1878
1879 tdm_slot[mode].num =
1880 tdm_get_slot_num(ucontrol->value.enumerated.item[0]);
1881
1882 pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__,
1883 mode, tdm_slot[mode].num,
1884 ucontrol->value.enumerated.item[0]);
1885
1886 return 0;
1887}
1888
1889static int tdm_get_slot_width_val(int slot_width)
1890{
1891 int slot_width_val = 2;
1892
1893 switch (slot_width) {
1894 case 16:
1895 slot_width_val = 0;
1896 break;
1897 case 24:
1898 slot_width_val = 1;
1899 break;
1900 case 32:
1901 slot_width_val = 2;
1902 break;
1903 default:
1904 slot_width_val = 2;
1905 break;
1906 }
1907 return slot_width_val;
1908}
1909
1910static int tdm_slot_width_get(struct snd_kcontrol *kcontrol,
1911 struct snd_ctl_elem_value *ucontrol)
1912{
1913 int mode = tdm_get_mode(kcontrol);
1914
1915 if (mode < 0) {
1916 pr_err("%s: unsupported control: %s\n",
1917 __func__, kcontrol->id.name);
1918 return mode;
1919 }
1920
1921 ucontrol->value.enumerated.item[0] =
1922 tdm_get_slot_width_val(tdm_slot[mode].width);
1923
1924 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1925 mode, tdm_slot[mode].width,
1926 ucontrol->value.enumerated.item[0]);
1927
1928 return 0;
1929}
1930
1931static int tdm_get_slot_width(int value)
1932{
1933 int slot_width = 32;
1934
1935 switch (value) {
1936 case 0:
1937 slot_width = 16;
1938 break;
1939 case 1:
1940 slot_width = 24;
1941 break;
1942 case 2:
1943 slot_width = 32;
1944 break;
1945 default:
1946 slot_width = 32;
1947 break;
1948 }
1949 return slot_width;
1950}
1951
1952static int tdm_slot_width_put(struct snd_kcontrol *kcontrol,
1953 struct snd_ctl_elem_value *ucontrol)
1954{
1955 int mode = tdm_get_mode(kcontrol);
1956
1957 if (mode < 0) {
1958 pr_err("%s: unsupported control: %s\n",
1959 __func__, kcontrol->id.name);
1960 return mode;
1961 }
1962
1963 tdm_slot[mode].width =
1964 tdm_get_slot_width(ucontrol->value.enumerated.item[0]);
1965
1966 pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__,
1967 mode, tdm_slot[mode].width,
1968 ucontrol->value.enumerated.item[0]);
1969
1970 return 0;
1971}
1972
1973static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol,
1974 struct snd_ctl_elem_value *ucontrol)
1975{
1976 unsigned int *slot_offset;
1977 int i;
1978 struct tdm_port port;
1979 int ret = tdm_get_port_idx(kcontrol, &port);
1980
1981 if (ret) {
1982 pr_err("%s: unsupported control: %s\n",
1983 __func__, kcontrol->id.name);
1984 } else {
1985 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
1986 pr_debug("%s: mode = %d, channel = %d\n",
1987 __func__, port.mode, port.channel);
1988 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
1989 ucontrol->value.integer.value[i] = slot_offset[i];
1990 pr_debug("%s: offset %d, value %d\n",
1991 __func__, i, slot_offset[i]);
1992 }
1993 }
1994 return ret;
1995}
1996
1997static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol,
1998 struct snd_ctl_elem_value *ucontrol)
1999{
2000 unsigned int *slot_offset;
2001 int i;
2002 struct tdm_port port;
2003 int ret = tdm_get_port_idx(kcontrol, &port);
2004
2005 if (ret) {
2006 pr_err("%s: unsupported control: %s\n",
2007 __func__, kcontrol->id.name);
2008 } else {
2009 slot_offset = tdm_rx_slot_offset[port.mode][port.channel];
2010 pr_debug("%s: mode = %d, channel = %d\n",
2011 __func__, port.mode, port.channel);
2012 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2013 slot_offset[i] = ucontrol->value.integer.value[i];
2014 pr_debug("%s: offset %d, value %d\n",
2015 __func__, i, slot_offset[i]);
2016 }
2017 }
2018 return ret;
2019}
2020
2021static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol,
2022 struct snd_ctl_elem_value *ucontrol)
2023{
2024 unsigned int *slot_offset;
2025 int i;
2026 struct tdm_port port;
2027 int ret = tdm_get_port_idx(kcontrol, &port);
2028
2029 if (ret) {
2030 pr_err("%s: unsupported control: %s\n",
2031 __func__, kcontrol->id.name);
2032 } else {
2033 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2034 pr_debug("%s: mode = %d, channel = %d\n",
2035 __func__, port.mode, port.channel);
2036 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2037 ucontrol->value.integer.value[i] = slot_offset[i];
2038 pr_debug("%s: offset %d, value %d\n",
2039 __func__, i, slot_offset[i]);
2040 }
2041 }
2042 return ret;
2043}
2044
2045static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol,
2046 struct snd_ctl_elem_value *ucontrol)
2047{
2048 unsigned int *slot_offset;
2049 int i;
2050 struct tdm_port port;
2051 int ret = tdm_get_port_idx(kcontrol, &port);
2052
2053 if (ret) {
2054 pr_err("%s: unsupported control: %s\n",
2055 __func__, kcontrol->id.name);
2056 } else {
2057 slot_offset = tdm_tx_slot_offset[port.mode][port.channel];
2058 pr_debug("%s: mode = %d, channel = %d\n",
2059 __func__, port.mode, port.channel);
2060 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
2061 slot_offset[i] = ucontrol->value.integer.value[i];
2062 pr_debug("%s: offset %d, value %d\n",
2063 __func__, i, slot_offset[i]);
2064 }
2065 }
2066 return ret;
2067}
2068
2069static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2070{
2071 int idx;
2072
2073 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2074 sizeof("PRIM_AUX_PCM")))
2075 idx = PRIM_AUX_PCM;
2076 else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2077 sizeof("SEC_AUX_PCM")))
2078 idx = SEC_AUX_PCM;
2079 else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2080 sizeof("TERT_AUX_PCM")))
2081 idx = TERT_AUX_PCM;
2082 else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2083 sizeof("QUAT_AUX_PCM")))
2084 idx = QUAT_AUX_PCM;
2085 else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2086 sizeof("QUIN_AUX_PCM")))
2087 idx = QUIN_AUX_PCM;
2088 else {
2089 pr_err("%s: unsupported port: %s\n",
2090 __func__, kcontrol->id.name);
2091 idx = -EINVAL;
2092 }
2093
2094 return idx;
2095}
2096
2097static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2098 struct snd_ctl_elem_value *ucontrol)
2099{
2100 int idx = aux_pcm_get_port_idx(kcontrol);
2101
2102 if (idx < 0)
2103 return idx;
2104
2105 aux_pcm_rx_cfg[idx].sample_rate =
2106 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2107
2108 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2109 idx, aux_pcm_rx_cfg[idx].sample_rate,
2110 ucontrol->value.enumerated.item[0]);
2111
2112 return 0;
2113}
2114
2115static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2116 struct snd_ctl_elem_value *ucontrol)
2117{
2118 int idx = aux_pcm_get_port_idx(kcontrol);
2119
2120 if (idx < 0)
2121 return idx;
2122
2123 ucontrol->value.enumerated.item[0] =
2124 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2125
2126 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2127 idx, aux_pcm_rx_cfg[idx].sample_rate,
2128 ucontrol->value.enumerated.item[0]);
2129
2130 return 0;
2131}
2132
2133static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2134 struct snd_ctl_elem_value *ucontrol)
2135{
2136 int idx = aux_pcm_get_port_idx(kcontrol);
2137
2138 if (idx < 0)
2139 return idx;
2140
2141 aux_pcm_tx_cfg[idx].sample_rate =
2142 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2143
2144 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2145 idx, aux_pcm_tx_cfg[idx].sample_rate,
2146 ucontrol->value.enumerated.item[0]);
2147
2148 return 0;
2149}
2150
2151static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2152 struct snd_ctl_elem_value *ucontrol)
2153{
2154 int idx = aux_pcm_get_port_idx(kcontrol);
2155
2156 if (idx < 0)
2157 return idx;
2158
2159 ucontrol->value.enumerated.item[0] =
2160 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2161
2162 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2163 idx, aux_pcm_tx_cfg[idx].sample_rate,
2164 ucontrol->value.enumerated.item[0]);
2165
2166 return 0;
2167}
2168
2169static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2170{
2171 int idx;
2172
2173 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2174 sizeof("PRIM_MI2S_RX")))
2175 idx = PRIM_MI2S;
2176 else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2177 sizeof("SEC_MI2S_RX")))
2178 idx = SEC_MI2S;
2179 else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2180 sizeof("TERT_MI2S_RX")))
2181 idx = TERT_MI2S;
2182 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2183 sizeof("QUAT_MI2S_RX")))
2184 idx = QUAT_MI2S;
2185 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2186 sizeof("QUIN_MI2S_RX")))
2187 idx = QUIN_MI2S;
2188 else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2189 sizeof("PRIM_MI2S_TX")))
2190 idx = PRIM_MI2S;
2191 else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2192 sizeof("SEC_MI2S_TX")))
2193 idx = SEC_MI2S;
2194 else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2195 sizeof("TERT_MI2S_TX")))
2196 idx = TERT_MI2S;
2197 else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2198 sizeof("QUAT_MI2S_TX")))
2199 idx = QUAT_MI2S;
2200 else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2201 sizeof("QUIN_MI2S_TX")))
2202 idx = QUIN_MI2S;
2203 else {
2204 pr_err("%s: unsupported channel: %s\n",
2205 __func__, kcontrol->id.name);
2206 idx = -EINVAL;
2207 }
2208
2209 return idx;
2210}
2211
2212static int mi2s_get_sample_rate_val(int sample_rate)
2213{
2214 int sample_rate_val;
2215
2216 switch (sample_rate) {
2217 case SAMPLING_RATE_8KHZ:
2218 sample_rate_val = 0;
2219 break;
2220 case SAMPLING_RATE_11P025KHZ:
2221 sample_rate_val = 1;
2222 break;
2223 case SAMPLING_RATE_16KHZ:
2224 sample_rate_val = 2;
2225 break;
2226 case SAMPLING_RATE_22P05KHZ:
2227 sample_rate_val = 3;
2228 break;
2229 case SAMPLING_RATE_32KHZ:
2230 sample_rate_val = 4;
2231 break;
2232 case SAMPLING_RATE_44P1KHZ:
2233 sample_rate_val = 5;
2234 break;
2235 case SAMPLING_RATE_48KHZ:
2236 sample_rate_val = 6;
2237 break;
2238 case SAMPLING_RATE_96KHZ:
2239 sample_rate_val = 7;
2240 break;
2241 case SAMPLING_RATE_192KHZ:
2242 sample_rate_val = 8;
2243 break;
2244 default:
2245 sample_rate_val = 6;
2246 break;
2247 }
2248 return sample_rate_val;
2249}
2250
2251static int mi2s_get_sample_rate(int value)
2252{
2253 int sample_rate;
2254
2255 switch (value) {
2256 case 0:
2257 sample_rate = SAMPLING_RATE_8KHZ;
2258 break;
2259 case 1:
2260 sample_rate = SAMPLING_RATE_11P025KHZ;
2261 break;
2262 case 2:
2263 sample_rate = SAMPLING_RATE_16KHZ;
2264 break;
2265 case 3:
2266 sample_rate = SAMPLING_RATE_22P05KHZ;
2267 break;
2268 case 4:
2269 sample_rate = SAMPLING_RATE_32KHZ;
2270 break;
2271 case 5:
2272 sample_rate = SAMPLING_RATE_44P1KHZ;
2273 break;
2274 case 6:
2275 sample_rate = SAMPLING_RATE_48KHZ;
2276 break;
2277 case 7:
2278 sample_rate = SAMPLING_RATE_96KHZ;
2279 break;
2280 case 8:
2281 sample_rate = SAMPLING_RATE_192KHZ;
2282 break;
2283 default:
2284 sample_rate = SAMPLING_RATE_48KHZ;
2285 break;
2286 }
2287 return sample_rate;
2288}
2289
2290static int mi2s_auxpcm_get_format(int value)
2291{
2292 int format;
2293
2294 switch (value) {
2295 case 0:
2296 format = SNDRV_PCM_FORMAT_S16_LE;
2297 break;
2298 case 1:
2299 format = SNDRV_PCM_FORMAT_S24_LE;
2300 break;
2301 case 2:
2302 format = SNDRV_PCM_FORMAT_S24_3LE;
2303 break;
2304 case 3:
2305 format = SNDRV_PCM_FORMAT_S32_LE;
2306 break;
2307 default:
2308 format = SNDRV_PCM_FORMAT_S16_LE;
2309 break;
2310 }
2311 return format;
2312}
2313
2314static int mi2s_auxpcm_get_format_value(int format)
2315{
2316 int value;
2317
2318 switch (format) {
2319 case SNDRV_PCM_FORMAT_S16_LE:
2320 value = 0;
2321 break;
2322 case SNDRV_PCM_FORMAT_S24_LE:
2323 value = 1;
2324 break;
2325 case SNDRV_PCM_FORMAT_S24_3LE:
2326 value = 2;
2327 break;
2328 case SNDRV_PCM_FORMAT_S32_LE:
2329 value = 3;
2330 break;
2331 default:
2332 value = 0;
2333 break;
2334 }
2335 return value;
2336}
2337
2338static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2339 struct snd_ctl_elem_value *ucontrol)
2340{
2341 int idx = mi2s_get_port_idx(kcontrol);
2342
2343 if (idx < 0)
2344 return idx;
2345
2346 mi2s_rx_cfg[idx].sample_rate =
2347 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2348
2349 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2350 idx, mi2s_rx_cfg[idx].sample_rate,
2351 ucontrol->value.enumerated.item[0]);
2352
2353 return 0;
2354}
2355
2356static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2357 struct snd_ctl_elem_value *ucontrol)
2358{
2359 int idx = mi2s_get_port_idx(kcontrol);
2360
2361 if (idx < 0)
2362 return idx;
2363
2364 ucontrol->value.enumerated.item[0] =
2365 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
2366
2367 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2368 idx, mi2s_rx_cfg[idx].sample_rate,
2369 ucontrol->value.enumerated.item[0]);
2370
2371 return 0;
2372}
2373
2374static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2375 struct snd_ctl_elem_value *ucontrol)
2376{
2377 int idx = mi2s_get_port_idx(kcontrol);
2378
2379 if (idx < 0)
2380 return idx;
2381
2382 mi2s_tx_cfg[idx].sample_rate =
2383 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
2384
2385 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2386 idx, mi2s_tx_cfg[idx].sample_rate,
2387 ucontrol->value.enumerated.item[0]);
2388
2389 return 0;
2390}
2391
2392static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2393 struct snd_ctl_elem_value *ucontrol)
2394{
2395 int idx = mi2s_get_port_idx(kcontrol);
2396
2397 if (idx < 0)
2398 return idx;
2399
2400 ucontrol->value.enumerated.item[0] =
2401 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
2402
2403 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2404 idx, mi2s_tx_cfg[idx].sample_rate,
2405 ucontrol->value.enumerated.item[0]);
2406
2407 return 0;
2408}
2409
2410static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
2411 struct snd_ctl_elem_value *ucontrol)
2412{
2413 int idx = mi2s_get_port_idx(kcontrol);
2414
2415 if (idx < 0)
2416 return idx;
2417
2418 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2419 idx, mi2s_rx_cfg[idx].channels);
2420 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
2421
2422 return 0;
2423}
2424
2425static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
2426 struct snd_ctl_elem_value *ucontrol)
2427{
2428 int idx = mi2s_get_port_idx(kcontrol);
2429
2430 if (idx < 0)
2431 return idx;
2432
2433 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2434 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
2435 idx, mi2s_rx_cfg[idx].channels);
2436
2437 return 1;
2438}
2439
2440static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
2441 struct snd_ctl_elem_value *ucontrol)
2442{
2443 int idx = mi2s_get_port_idx(kcontrol);
2444
2445 if (idx < 0)
2446 return idx;
2447
2448 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2449 idx, mi2s_tx_cfg[idx].channels);
2450 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
2451
2452 return 0;
2453}
2454
2455static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
2456 struct snd_ctl_elem_value *ucontrol)
2457{
2458 int idx = mi2s_get_port_idx(kcontrol);
2459
2460 if (idx < 0)
2461 return idx;
2462
2463 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
2464 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
2465 idx, mi2s_tx_cfg[idx].channels);
2466
2467 return 1;
2468}
2469
2470static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
2471 struct snd_ctl_elem_value *ucontrol)
2472{
2473 int idx = mi2s_get_port_idx(kcontrol);
2474
2475 if (idx < 0)
2476 return idx;
2477
2478 ucontrol->value.enumerated.item[0] =
2479 mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
2480
2481 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2482 idx, mi2s_rx_cfg[idx].bit_format,
2483 ucontrol->value.enumerated.item[0]);
2484
2485 return 0;
2486}
2487
2488static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
2489 struct snd_ctl_elem_value *ucontrol)
2490{
2491 int idx = mi2s_get_port_idx(kcontrol);
2492
2493 if (idx < 0)
2494 return idx;
2495
2496 mi2s_rx_cfg[idx].bit_format =
2497 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2498
2499 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2500 idx, mi2s_rx_cfg[idx].bit_format,
2501 ucontrol->value.enumerated.item[0]);
2502
2503 return 0;
2504}
2505
2506static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
2507 struct snd_ctl_elem_value *ucontrol)
2508{
2509 int idx = mi2s_get_port_idx(kcontrol);
2510
2511 if (idx < 0)
2512 return idx;
2513
2514 ucontrol->value.enumerated.item[0] =
2515 mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
2516
2517 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2518 idx, mi2s_tx_cfg[idx].bit_format,
2519 ucontrol->value.enumerated.item[0]);
2520
2521 return 0;
2522}
2523
2524static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
2525 struct snd_ctl_elem_value *ucontrol)
2526{
2527 int idx = mi2s_get_port_idx(kcontrol);
2528
2529 if (idx < 0)
2530 return idx;
2531
2532 mi2s_tx_cfg[idx].bit_format =
2533 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2534
2535 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2536 idx, mi2s_tx_cfg[idx].bit_format,
2537 ucontrol->value.enumerated.item[0]);
2538
2539 return 0;
2540}
2541
2542static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
2543 struct snd_ctl_elem_value *ucontrol)
2544{
2545 int idx = aux_pcm_get_port_idx(kcontrol);
2546
2547 if (idx < 0)
2548 return idx;
2549
2550 ucontrol->value.enumerated.item[0] =
2551 mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
2552
2553 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2554 idx, aux_pcm_rx_cfg[idx].bit_format,
2555 ucontrol->value.enumerated.item[0]);
2556
2557 return 0;
2558}
2559
2560static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
2561 struct snd_ctl_elem_value *ucontrol)
2562{
2563 int idx = aux_pcm_get_port_idx(kcontrol);
2564
2565 if (idx < 0)
2566 return idx;
2567
2568 aux_pcm_rx_cfg[idx].bit_format =
2569 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2570
2571 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
2572 idx, aux_pcm_rx_cfg[idx].bit_format,
2573 ucontrol->value.enumerated.item[0]);
2574
2575 return 0;
2576}
2577
2578static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
2579 struct snd_ctl_elem_value *ucontrol)
2580{
2581 int idx = aux_pcm_get_port_idx(kcontrol);
2582
2583 if (idx < 0)
2584 return idx;
2585
2586 ucontrol->value.enumerated.item[0] =
2587 mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
2588
2589 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2590 idx, aux_pcm_tx_cfg[idx].bit_format,
2591 ucontrol->value.enumerated.item[0]);
2592
2593 return 0;
2594}
2595
2596static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
2597 struct snd_ctl_elem_value *ucontrol)
2598{
2599 int idx = aux_pcm_get_port_idx(kcontrol);
2600
2601 if (idx < 0)
2602 return idx;
2603
2604 aux_pcm_tx_cfg[idx].bit_format =
2605 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
2606
2607 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
2608 idx, aux_pcm_tx_cfg[idx].bit_format,
2609 ucontrol->value.enumerated.item[0]);
2610
2611 return 0;
2612}
2613
2614static const struct snd_kcontrol_new msm_snd_controls[] = {
2615 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
2616 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
2617 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
2618 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
2619 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
2620 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
2621 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
2622 proxy_rx_ch_get, proxy_rx_ch_put),
2623 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
2624 usb_audio_rx_format_get, usb_audio_rx_format_put),
2625 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
2626 usb_audio_tx_format_get, usb_audio_tx_format_put),
2627 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
2628 ext_disp_rx_format_get, ext_disp_rx_format_put),
2629 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
2630 usb_audio_rx_sample_rate_get,
2631 usb_audio_rx_sample_rate_put),
2632 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
2633 usb_audio_tx_sample_rate_get,
2634 usb_audio_tx_sample_rate_put),
2635 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
2636 ext_disp_rx_sample_rate_get,
2637 ext_disp_rx_sample_rate_put),
2638 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2639 tdm_rx_sample_rate_get,
2640 tdm_rx_sample_rate_put),
2641 SOC_ENUM_EXT("PRI_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2642 tdm_rx_sample_rate_get,
2643 tdm_rx_sample_rate_put),
2644 SOC_ENUM_EXT("PRI_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2645 tdm_rx_sample_rate_get,
2646 tdm_rx_sample_rate_put),
2647 SOC_ENUM_EXT("PRI_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2648 tdm_rx_sample_rate_get,
2649 tdm_rx_sample_rate_put),
2650 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2651 tdm_tx_sample_rate_get,
2652 tdm_tx_sample_rate_put),
2653 SOC_ENUM_EXT("PRI_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2654 tdm_tx_sample_rate_get,
2655 tdm_tx_sample_rate_put),
2656 SOC_ENUM_EXT("PRI_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2657 tdm_tx_sample_rate_get,
2658 tdm_tx_sample_rate_put),
2659 SOC_ENUM_EXT("PRI_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2660 tdm_tx_sample_rate_get,
2661 tdm_tx_sample_rate_put),
2662 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
2663 tdm_rx_format_get,
2664 tdm_rx_format_put),
2665 SOC_ENUM_EXT("PRI_TDM_RX_1 Format", tdm_rx_format,
2666 tdm_rx_format_get,
2667 tdm_rx_format_put),
2668 SOC_ENUM_EXT("PRI_TDM_RX_2 Format", tdm_rx_format,
2669 tdm_rx_format_get,
2670 tdm_rx_format_put),
2671 SOC_ENUM_EXT("PRI_TDM_RX_3 Format", tdm_rx_format,
2672 tdm_rx_format_get,
2673 tdm_rx_format_put),
2674 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
2675 tdm_tx_format_get,
2676 tdm_tx_format_put),
2677 SOC_ENUM_EXT("PRI_TDM_TX_1 Format", tdm_tx_format,
2678 tdm_tx_format_get,
2679 tdm_tx_format_put),
2680 SOC_ENUM_EXT("PRI_TDM_TX_2 Format", tdm_tx_format,
2681 tdm_tx_format_get,
2682 tdm_tx_format_put),
2683 SOC_ENUM_EXT("PRI_TDM_TX_3 Format", tdm_tx_format,
2684 tdm_tx_format_get,
2685 tdm_tx_format_put),
2686 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
2687 tdm_rx_ch_get,
2688 tdm_rx_ch_put),
2689 SOC_ENUM_EXT("PRI_TDM_RX_1 Channels", tdm_rx_chs,
2690 tdm_rx_ch_get,
2691 tdm_rx_ch_put),
2692 SOC_ENUM_EXT("PRI_TDM_RX_2 Channels", tdm_rx_chs,
2693 tdm_rx_ch_get,
2694 tdm_rx_ch_put),
2695 SOC_ENUM_EXT("PRI_TDM_RX_3 Channels", tdm_rx_chs,
2696 tdm_rx_ch_get,
2697 tdm_rx_ch_put),
2698 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
2699 tdm_tx_ch_get,
2700 tdm_tx_ch_put),
2701 SOC_ENUM_EXT("PRI_TDM_TX_1 Channels", tdm_tx_chs,
2702 tdm_tx_ch_get,
2703 tdm_tx_ch_put),
2704 SOC_ENUM_EXT("PRI_TDM_TX_2 Channels", tdm_tx_chs,
2705 tdm_tx_ch_get,
2706 tdm_tx_ch_put),
2707 SOC_ENUM_EXT("PRI_TDM_TX_3 Channels", tdm_tx_chs,
2708 tdm_tx_ch_get,
2709 tdm_tx_ch_put),
2710 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2711 tdm_rx_sample_rate_get,
2712 tdm_rx_sample_rate_put),
2713 SOC_ENUM_EXT("SEC_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2714 tdm_rx_sample_rate_get,
2715 tdm_rx_sample_rate_put),
2716 SOC_ENUM_EXT("SEC_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2717 tdm_rx_sample_rate_get,
2718 tdm_rx_sample_rate_put),
2719 SOC_ENUM_EXT("SEC_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2720 tdm_rx_sample_rate_get,
2721 tdm_rx_sample_rate_put),
2722 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2723 tdm_tx_sample_rate_get,
2724 tdm_tx_sample_rate_put),
2725 SOC_ENUM_EXT("SEC_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2726 tdm_tx_sample_rate_get,
2727 tdm_tx_sample_rate_put),
2728 SOC_ENUM_EXT("SEC_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2729 tdm_tx_sample_rate_get,
2730 tdm_tx_sample_rate_put),
2731 SOC_ENUM_EXT("SEC_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2732 tdm_tx_sample_rate_get,
2733 tdm_tx_sample_rate_put),
2734 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
2735 tdm_rx_format_get,
2736 tdm_rx_format_put),
2737 SOC_ENUM_EXT("SEC_TDM_RX_1 Format", tdm_rx_format,
2738 tdm_rx_format_get,
2739 tdm_rx_format_put),
2740 SOC_ENUM_EXT("SEC_TDM_RX_2 Format", tdm_rx_format,
2741 tdm_rx_format_get,
2742 tdm_rx_format_put),
2743 SOC_ENUM_EXT("SEC_TDM_RX_3 Format", tdm_rx_format,
2744 tdm_rx_format_get,
2745 tdm_rx_format_put),
2746 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
2747 tdm_tx_format_get,
2748 tdm_tx_format_put),
2749 SOC_ENUM_EXT("SEC_TDM_TX_1 Format", tdm_tx_format,
2750 tdm_tx_format_get,
2751 tdm_tx_format_put),
2752 SOC_ENUM_EXT("SEC_TDM_TX_2 Format", tdm_tx_format,
2753 tdm_tx_format_get,
2754 tdm_tx_format_put),
2755 SOC_ENUM_EXT("SEC_TDM_TX_3 Format", tdm_tx_format,
2756 tdm_tx_format_get,
2757 tdm_tx_format_put),
2758 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
2759 tdm_rx_ch_get,
2760 tdm_rx_ch_put),
2761 SOC_ENUM_EXT("SEC_TDM_RX_1 Channels", tdm_rx_chs,
2762 tdm_rx_ch_get,
2763 tdm_rx_ch_put),
2764 SOC_ENUM_EXT("SEC_TDM_RX_2 Channels", tdm_rx_chs,
2765 tdm_rx_ch_get,
2766 tdm_rx_ch_put),
2767 SOC_ENUM_EXT("SEC_TDM_RX_3 Channels", tdm_rx_chs,
2768 tdm_rx_ch_get,
2769 tdm_rx_ch_put),
2770 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
2771 tdm_tx_ch_get,
2772 tdm_tx_ch_put),
2773 SOC_ENUM_EXT("SEC_TDM_TX_1 Channels", tdm_tx_chs,
2774 tdm_tx_ch_get,
2775 tdm_tx_ch_put),
2776 SOC_ENUM_EXT("SEC_TDM_TX_2 Channels", tdm_tx_chs,
2777 tdm_tx_ch_get,
2778 tdm_tx_ch_put),
2779 SOC_ENUM_EXT("SEC_TDM_TX_3 Channels", tdm_tx_chs,
2780 tdm_tx_ch_get,
2781 tdm_tx_ch_put),
2782 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2783 tdm_rx_sample_rate_get,
2784 tdm_rx_sample_rate_put),
2785 SOC_ENUM_EXT("TERT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2786 tdm_rx_sample_rate_get,
2787 tdm_rx_sample_rate_put),
2788 SOC_ENUM_EXT("TERT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2789 tdm_rx_sample_rate_get,
2790 tdm_rx_sample_rate_put),
2791 SOC_ENUM_EXT("TERT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2792 tdm_rx_sample_rate_get,
2793 tdm_rx_sample_rate_put),
2794 SOC_ENUM_EXT("TERT_TDM_RX_4 SampleRate", tdm_rx_sample_rate,
2795 tdm_rx_sample_rate_get,
2796 tdm_rx_sample_rate_put),
2797 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2798 tdm_tx_sample_rate_get,
2799 tdm_tx_sample_rate_put),
2800 SOC_ENUM_EXT("TERT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2801 tdm_tx_sample_rate_get,
2802 tdm_tx_sample_rate_put),
2803 SOC_ENUM_EXT("TERT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2804 tdm_tx_sample_rate_get,
2805 tdm_tx_sample_rate_put),
2806 SOC_ENUM_EXT("TERT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2807 tdm_tx_sample_rate_get,
2808 tdm_tx_sample_rate_put),
2809 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
2810 tdm_rx_format_get,
2811 tdm_rx_format_put),
2812 SOC_ENUM_EXT("TERT_TDM_RX_1 Format", tdm_rx_format,
2813 tdm_rx_format_get,
2814 tdm_rx_format_put),
2815 SOC_ENUM_EXT("TERT_TDM_RX_2 Format", tdm_rx_format,
2816 tdm_rx_format_get,
2817 tdm_rx_format_put),
2818 SOC_ENUM_EXT("TERT_TDM_RX_3 Format", tdm_rx_format,
2819 tdm_rx_format_get,
2820 tdm_rx_format_put),
2821 SOC_ENUM_EXT("TERT_TDM_RX_4 Format", tdm_rx_format,
2822 tdm_rx_format_get,
2823 tdm_rx_format_put),
2824 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
2825 tdm_tx_format_get,
2826 tdm_tx_format_put),
2827 SOC_ENUM_EXT("TERT_TDM_TX_1 Format", tdm_tx_format,
2828 tdm_tx_format_get,
2829 tdm_tx_format_put),
2830 SOC_ENUM_EXT("TERT_TDM_TX_2 Format", tdm_tx_format,
2831 tdm_tx_format_get,
2832 tdm_tx_format_put),
2833 SOC_ENUM_EXT("TERT_TDM_TX_3 Format", tdm_tx_format,
2834 tdm_tx_format_get,
2835 tdm_tx_format_put),
2836 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
2837 tdm_rx_ch_get,
2838 tdm_rx_ch_put),
2839 SOC_ENUM_EXT("TERT_TDM_RX_1 Channels", tdm_rx_chs,
2840 tdm_rx_ch_get,
2841 tdm_rx_ch_put),
2842 SOC_ENUM_EXT("TERT_TDM_RX_2 Channels", tdm_rx_chs,
2843 tdm_rx_ch_get,
2844 tdm_rx_ch_put),
2845 SOC_ENUM_EXT("TERT_TDM_RX_3 Channels", tdm_rx_chs,
2846 tdm_rx_ch_get,
2847 tdm_rx_ch_put),
2848 SOC_ENUM_EXT("TERT_TDM_RX_4 Channels", tdm_rx_chs,
2849 tdm_rx_ch_get,
2850 tdm_rx_ch_put),
2851 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
2852 tdm_tx_ch_get,
2853 tdm_tx_ch_put),
2854 SOC_ENUM_EXT("TERT_TDM_TX_1 Channels", tdm_tx_chs,
2855 tdm_tx_ch_get,
2856 tdm_tx_ch_put),
2857 SOC_ENUM_EXT("TERT_TDM_TX_2 Channels", tdm_tx_chs,
2858 tdm_tx_ch_get,
2859 tdm_tx_ch_put),
2860 SOC_ENUM_EXT("TERT_TDM_TX_3 Channels", tdm_tx_chs,
2861 tdm_tx_ch_get,
2862 tdm_tx_ch_put),
2863 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2864 tdm_rx_sample_rate_get,
2865 tdm_rx_sample_rate_put),
2866 SOC_ENUM_EXT("QUAT_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2867 tdm_rx_sample_rate_get,
2868 tdm_rx_sample_rate_put),
2869 SOC_ENUM_EXT("QUAT_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2870 tdm_rx_sample_rate_get,
2871 tdm_rx_sample_rate_put),
2872 SOC_ENUM_EXT("QUAT_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2873 tdm_rx_sample_rate_get,
2874 tdm_rx_sample_rate_put),
2875 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2876 tdm_tx_sample_rate_get,
2877 tdm_tx_sample_rate_put),
2878 SOC_ENUM_EXT("QUAT_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2879 tdm_tx_sample_rate_get,
2880 tdm_tx_sample_rate_put),
2881 SOC_ENUM_EXT("QUAT_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2882 tdm_tx_sample_rate_get,
2883 tdm_tx_sample_rate_put),
2884 SOC_ENUM_EXT("QUAT_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2885 tdm_tx_sample_rate_get,
2886 tdm_tx_sample_rate_put),
2887 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
2888 tdm_rx_format_get,
2889 tdm_rx_format_put),
2890 SOC_ENUM_EXT("QUAT_TDM_RX_1 Format", tdm_rx_format,
2891 tdm_rx_format_get,
2892 tdm_rx_format_put),
2893 SOC_ENUM_EXT("QUAT_TDM_RX_2 Format", tdm_rx_format,
2894 tdm_rx_format_get,
2895 tdm_rx_format_put),
2896 SOC_ENUM_EXT("QUAT_TDM_RX_3 Format", tdm_rx_format,
2897 tdm_rx_format_get,
2898 tdm_rx_format_put),
2899 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
2900 tdm_tx_format_get,
2901 tdm_tx_format_put),
2902 SOC_ENUM_EXT("QUAT_TDM_TX_1 Format", tdm_tx_format,
2903 tdm_tx_format_get,
2904 tdm_tx_format_put),
2905 SOC_ENUM_EXT("QUAT_TDM_TX_2 Format", tdm_tx_format,
2906 tdm_tx_format_get,
2907 tdm_tx_format_put),
2908 SOC_ENUM_EXT("QUAT_TDM_TX_3 Format", tdm_tx_format,
2909 tdm_tx_format_get,
2910 tdm_tx_format_put),
2911 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
2912 tdm_rx_ch_get,
2913 tdm_rx_ch_put),
2914 SOC_ENUM_EXT("QUAT_TDM_RX_1 Channels", tdm_rx_chs,
2915 tdm_rx_ch_get,
2916 tdm_rx_ch_put),
2917 SOC_ENUM_EXT("QUAT_TDM_RX_2 Channels", tdm_rx_chs,
2918 tdm_rx_ch_get,
2919 tdm_rx_ch_put),
2920 SOC_ENUM_EXT("QUAT_TDM_RX_3 Channels", tdm_rx_chs,
2921 tdm_rx_ch_get,
2922 tdm_rx_ch_put),
2923 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
2924 tdm_tx_ch_get,
2925 tdm_tx_ch_put),
2926 SOC_ENUM_EXT("QUAT_TDM_TX_1 Channels", tdm_tx_chs,
2927 tdm_tx_ch_get,
2928 tdm_tx_ch_put),
2929 SOC_ENUM_EXT("QUAT_TDM_TX_2 Channels", tdm_tx_chs,
2930 tdm_tx_ch_get,
2931 tdm_tx_ch_put),
2932 SOC_ENUM_EXT("QUAT_TDM_TX_3 Channels", tdm_tx_chs,
2933 tdm_tx_ch_get,
2934 tdm_tx_ch_put),
2935 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
2936 tdm_rx_sample_rate_get,
2937 tdm_rx_sample_rate_put),
2938 SOC_ENUM_EXT("QUIN_TDM_RX_1 SampleRate", tdm_rx_sample_rate,
2939 tdm_rx_sample_rate_get,
2940 tdm_rx_sample_rate_put),
2941 SOC_ENUM_EXT("QUIN_TDM_RX_2 SampleRate", tdm_rx_sample_rate,
2942 tdm_rx_sample_rate_get,
2943 tdm_rx_sample_rate_put),
2944 SOC_ENUM_EXT("QUIN_TDM_RX_3 SampleRate", tdm_rx_sample_rate,
2945 tdm_rx_sample_rate_get,
2946 tdm_rx_sample_rate_put),
2947 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
2948 tdm_tx_sample_rate_get,
2949 tdm_tx_sample_rate_put),
2950 SOC_ENUM_EXT("QUIN_TDM_TX_1 SampleRate", tdm_tx_sample_rate,
2951 tdm_tx_sample_rate_get,
2952 tdm_tx_sample_rate_put),
2953 SOC_ENUM_EXT("QUIN_TDM_TX_2 SampleRate", tdm_tx_sample_rate,
2954 tdm_tx_sample_rate_get,
2955 tdm_tx_sample_rate_put),
2956 SOC_ENUM_EXT("QUIN_TDM_TX_3 SampleRate", tdm_tx_sample_rate,
2957 tdm_tx_sample_rate_get,
2958 tdm_tx_sample_rate_put),
2959 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
2960 tdm_rx_format_get,
2961 tdm_rx_format_put),
2962 SOC_ENUM_EXT("QUIN_TDM_RX_1 Format", tdm_rx_format,
2963 tdm_rx_format_get,
2964 tdm_rx_format_put),
2965 SOC_ENUM_EXT("QUIN_TDM_RX_2 Format", tdm_rx_format,
2966 tdm_rx_format_get,
2967 tdm_rx_format_put),
2968 SOC_ENUM_EXT("QUIN_TDM_RX_3 Format", tdm_rx_format,
2969 tdm_rx_format_get,
2970 tdm_rx_format_put),
2971 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
2972 tdm_tx_format_get,
2973 tdm_tx_format_put),
2974 SOC_ENUM_EXT("QUIN_TDM_TX_1 Format", tdm_tx_format,
2975 tdm_tx_format_get,
2976 tdm_tx_format_put),
2977 SOC_ENUM_EXT("QUIN_TDM_TX_2 Format", tdm_tx_format,
2978 tdm_tx_format_get,
2979 tdm_tx_format_put),
2980 SOC_ENUM_EXT("QUIN_TDM_TX_3 Format", tdm_tx_format,
2981 tdm_tx_format_get,
2982 tdm_tx_format_put),
2983 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
2984 tdm_rx_ch_get,
2985 tdm_rx_ch_put),
2986 SOC_ENUM_EXT("QUIN_TDM_RX_1 Channels", tdm_rx_chs,
2987 tdm_rx_ch_get,
2988 tdm_rx_ch_put),
2989 SOC_ENUM_EXT("QUIN_TDM_RX_2 Channels", tdm_rx_chs,
2990 tdm_rx_ch_get,
2991 tdm_rx_ch_put),
2992 SOC_ENUM_EXT("QUIN_TDM_RX_3 Channels", tdm_rx_chs,
2993 tdm_rx_ch_get,
2994 tdm_rx_ch_put),
2995 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
2996 tdm_tx_ch_get,
2997 tdm_tx_ch_put),
2998 SOC_ENUM_EXT("QUIN_TDM_TX_1 Channels", tdm_tx_chs,
2999 tdm_tx_ch_get,
3000 tdm_tx_ch_put),
3001 SOC_ENUM_EXT("QUIN_TDM_TX_2 Channels", tdm_tx_chs,
3002 tdm_tx_ch_get,
3003 tdm_tx_ch_put),
3004 SOC_ENUM_EXT("QUIN_TDM_TX_3 Channels", tdm_tx_chs,
3005 tdm_tx_ch_get,
3006 tdm_tx_ch_put),
3007 SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num,
3008 tdm_slot_num_get, tdm_slot_num_put),
3009 SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width,
3010 tdm_slot_width_get, tdm_slot_width_put),
3011 SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num,
3012 tdm_slot_num_get, tdm_slot_num_put),
3013 SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width,
3014 tdm_slot_width_get, tdm_slot_width_put),
3015 SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num,
3016 tdm_slot_num_get, tdm_slot_num_put),
3017 SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width,
3018 tdm_slot_width_get, tdm_slot_width_put),
3019 SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num,
3020 tdm_slot_num_get, tdm_slot_num_put),
3021 SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width,
3022 tdm_slot_width_get, tdm_slot_width_put),
3023 SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num,
3024 tdm_slot_num_get, tdm_slot_num_put),
3025 SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width,
3026 tdm_slot_width_get, tdm_slot_width_put),
3027 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_0 SlotMapping",
3028 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3029 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3030 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_1 SlotMapping",
3031 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3032 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3033 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_2 SlotMapping",
3034 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3035 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3036 SOC_SINGLE_MULTI_EXT("PRI_TDM_RX_3 SlotMapping",
3037 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3038 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3039 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_0 SlotMapping",
3040 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3041 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3042 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_1 SlotMapping",
3043 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3044 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3045 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_2 SlotMapping",
3046 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3047 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3048 SOC_SINGLE_MULTI_EXT("PRI_TDM_TX_3 SlotMapping",
3049 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3050 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3051 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_0 SlotMapping",
3052 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3053 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3054 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_1 SlotMapping",
3055 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3056 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3057 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_2 SlotMapping",
3058 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3059 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3060 SOC_SINGLE_MULTI_EXT("SEC_TDM_RX_3 SlotMapping",
3061 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3062 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3063 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_0 SlotMapping",
3064 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3065 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3066 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_1 SlotMapping",
3067 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3068 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3069 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_2 SlotMapping",
3070 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3071 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3072 SOC_SINGLE_MULTI_EXT("SEC_TDM_TX_3 SlotMapping",
3073 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3074 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3075 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_0 SlotMapping",
3076 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3077 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3078 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_1 SlotMapping",
3079 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3080 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3081 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_2 SlotMapping",
3082 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3083 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3084 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_3 SlotMapping",
3085 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3086 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3087 SOC_SINGLE_MULTI_EXT("TERT_TDM_RX_4 SlotMapping",
3088 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3089 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3090 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_0 SlotMapping",
3091 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3092 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3093 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_1 SlotMapping",
3094 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3095 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3096 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_2 SlotMapping",
3097 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3098 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3099 SOC_SINGLE_MULTI_EXT("TERT_TDM_TX_3 SlotMapping",
3100 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3101 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3102 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_0 SlotMapping",
3103 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3104 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3105 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_1 SlotMapping",
3106 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3107 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3108 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_2 SlotMapping",
3109 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3110 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3111 SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX_3 SlotMapping",
3112 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3113 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3114 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_0 SlotMapping",
3115 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3116 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3117 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_1 SlotMapping",
3118 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3119 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3120 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_2 SlotMapping",
3121 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3122 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3123 SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX_3 SlotMapping",
3124 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3125 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3126 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_0 SlotMapping",
3127 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3128 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3129 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_1 SlotMapping",
3130 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3131 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3132 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_2 SlotMapping",
3133 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3134 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3135 SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX_3 SlotMapping",
3136 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3137 tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put),
3138 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_0 SlotMapping",
3139 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3140 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3141 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_1 SlotMapping",
3142 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3143 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3144 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_2 SlotMapping",
3145 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3146 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3147 SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX_3 SlotMapping",
3148 SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX,
3149 tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put),
3150 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3151 aux_pcm_rx_sample_rate_get,
3152 aux_pcm_rx_sample_rate_put),
3153 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3154 aux_pcm_rx_sample_rate_get,
3155 aux_pcm_rx_sample_rate_put),
3156 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3157 aux_pcm_rx_sample_rate_get,
3158 aux_pcm_rx_sample_rate_put),
3159 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3160 aux_pcm_rx_sample_rate_get,
3161 aux_pcm_rx_sample_rate_put),
3162 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3163 aux_pcm_rx_sample_rate_get,
3164 aux_pcm_rx_sample_rate_put),
3165 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3166 aux_pcm_tx_sample_rate_get,
3167 aux_pcm_tx_sample_rate_put),
3168 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3169 aux_pcm_tx_sample_rate_get,
3170 aux_pcm_tx_sample_rate_put),
3171 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3172 aux_pcm_tx_sample_rate_get,
3173 aux_pcm_tx_sample_rate_put),
3174 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3175 aux_pcm_tx_sample_rate_get,
3176 aux_pcm_tx_sample_rate_put),
3177 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3178 aux_pcm_tx_sample_rate_get,
3179 aux_pcm_tx_sample_rate_put),
3180 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3181 mi2s_rx_sample_rate_get,
3182 mi2s_rx_sample_rate_put),
3183 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3184 mi2s_rx_sample_rate_get,
3185 mi2s_rx_sample_rate_put),
3186 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3187 mi2s_rx_sample_rate_get,
3188 mi2s_rx_sample_rate_put),
3189 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3190 mi2s_rx_sample_rate_get,
3191 mi2s_rx_sample_rate_put),
3192 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3193 mi2s_rx_sample_rate_get,
3194 mi2s_rx_sample_rate_put),
3195 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3196 mi2s_tx_sample_rate_get,
3197 mi2s_tx_sample_rate_put),
3198 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3199 mi2s_tx_sample_rate_get,
3200 mi2s_tx_sample_rate_put),
3201 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3202 mi2s_tx_sample_rate_get,
3203 mi2s_tx_sample_rate_put),
3204 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3205 mi2s_tx_sample_rate_get,
3206 mi2s_tx_sample_rate_put),
3207 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3208 mi2s_tx_sample_rate_get,
3209 mi2s_tx_sample_rate_put),
3210 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3211 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3212 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3213 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3214 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3215 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3216 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3217 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3218 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3219 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3220 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3221 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3222 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3223 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3224 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3225 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3226 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3227 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3228 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3229 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3230 SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
3231 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3232 SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
3233 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3234 SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
3235 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3236 SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
3237 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3238 SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
3239 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3240 SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
3241 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3242 SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
3243 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3244 SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
3245 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3246 SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
3247 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3248 SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
3249 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3250 SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
3251 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3252 SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
3253 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3254 SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
3255 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3256 SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
3257 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3258 SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
3259 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3260 SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
3261 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3262 SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
3263 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3264 SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
3265 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3266 SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
3267 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3268 SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
3269 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3270};
3271
3272static inline int param_is_mask(int p)
3273{
3274 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
3275 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
3276}
3277
3278static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
3279 int n)
3280{
3281 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
3282}
3283
3284static void param_set_mask(struct snd_pcm_hw_params *p, int n,
3285 unsigned int bit)
3286{
3287 if (bit >= SNDRV_MASK_MAX)
3288 return;
3289 if (param_is_mask(n)) {
3290 struct snd_mask *m = param_to_mask(p, n);
3291
3292 m->bits[0] = 0;
3293 m->bits[1] = 0;
3294 m->bits[bit >> 5] |= (1 << (bit & 31));
3295 }
3296}
3297
3298static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
3299{
3300 int idx;
3301
3302 switch (be_id) {
3303 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3304 idx = DP_RX_IDX;
3305 break;
3306 default:
3307 pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
3308 idx = -EINVAL;
3309 break;
3310 }
3311
3312 return idx;
3313}
3314
3315static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3316 struct snd_pcm_hw_params *params)
3317{
3318 struct snd_soc_dai_link *dai_link = rtd->dai_link;
3319 struct snd_interval *rate = hw_param_interval(params,
3320 SNDRV_PCM_HW_PARAM_RATE);
3321 struct snd_interval *channels = hw_param_interval(params,
3322 SNDRV_PCM_HW_PARAM_CHANNELS);
3323 int rc = 0;
3324 int idx;
3325
3326 pr_debug("%s: format = %d, rate = %d\n",
3327 __func__, params_format(params), params_rate(params));
3328
3329 switch (dai_link->id) {
3330 case MSM_BACKEND_DAI_USB_RX:
3331 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3332 usb_rx_cfg.bit_format);
3333 rate->min = rate->max = usb_rx_cfg.sample_rate;
3334 channels->min = channels->max = usb_rx_cfg.channels;
3335 break;
3336
3337 case MSM_BACKEND_DAI_USB_TX:
3338 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3339 usb_tx_cfg.bit_format);
3340 rate->min = rate->max = usb_tx_cfg.sample_rate;
3341 channels->min = channels->max = usb_tx_cfg.channels;
3342 break;
3343
3344 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
3345 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
3346 if (idx < 0) {
3347 pr_err("%s: Incorrect ext disp idx %d\n",
3348 __func__, idx);
3349 rc = idx;
3350 goto done;
3351 }
3352
3353 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3354 ext_disp_rx_cfg[idx].bit_format);
3355 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
3356 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
3357 break;
3358
3359 case MSM_BACKEND_DAI_AFE_PCM_RX:
3360 channels->min = channels->max = proxy_rx_cfg.channels;
3361 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3362 break;
3363
3364 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
3365 channels->min = channels->max =
3366 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3367 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3368 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3369 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3370 break;
3371
3372 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
3373 channels->min = channels->max =
3374 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3375 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3376 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3377 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3378 break;
3379
3380 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
3381 channels->min = channels->max =
3382 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3383 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3384 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3385 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3386 break;
3387
3388 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
3389 channels->min = channels->max =
3390 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
3391 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3392 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
3393 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
3394 break;
3395
3396 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
3397 channels->min = channels->max =
3398 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
3399 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3400 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
3401 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
3402 break;
3403
3404 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
3405 channels->min = channels->max =
3406 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
3407 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3408 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
3409 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
3410 break;
3411
3412 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
3413 channels->min = channels->max =
3414 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
3415 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3416 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
3417 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
3418 break;
3419
3420 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
3421 channels->min = channels->max =
3422 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
3423 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3424 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
3425 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
3426 break;
3427
3428 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
3429 channels->min = channels->max =
3430 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
3431 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3432 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
3433 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
3434 break;
3435
3436 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
3437 channels->min = channels->max =
3438 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
3439 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3440 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
3441 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
3442 break;
3443
3444
3445 case MSM_BACKEND_DAI_AUXPCM_RX:
3446 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3447 aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
3448 rate->min = rate->max =
3449 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
3450 channels->min = channels->max =
3451 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
3452 break;
3453
3454 case MSM_BACKEND_DAI_AUXPCM_TX:
3455 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3456 aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
3457 rate->min = rate->max =
3458 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
3459 channels->min = channels->max =
3460 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
3461 break;
3462
3463 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
3464 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3465 aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
3466 rate->min = rate->max =
3467 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
3468 channels->min = channels->max =
3469 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
3470 break;
3471
3472 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
3473 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3474 aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
3475 rate->min = rate->max =
3476 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
3477 channels->min = channels->max =
3478 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
3479 break;
3480
3481 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
3482 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3483 aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
3484 rate->min = rate->max =
3485 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
3486 channels->min = channels->max =
3487 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
3488 break;
3489
3490 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
3491 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3492 aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
3493 rate->min = rate->max =
3494 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
3495 channels->min = channels->max =
3496 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
3497 break;
3498
3499 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
3500 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3501 aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
3502 rate->min = rate->max =
3503 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
3504 channels->min = channels->max =
3505 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
3506 break;
3507
3508 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
3509 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3510 aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
3511 rate->min = rate->max =
3512 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
3513 channels->min = channels->max =
3514 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
3515 break;
3516
3517 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
3518 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3519 aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
3520 rate->min = rate->max =
3521 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
3522 channels->min = channels->max =
3523 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
3524 break;
3525
3526 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
3527 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3528 aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
3529 rate->min = rate->max =
3530 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
3531 channels->min = channels->max =
3532 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
3533 break;
3534
3535 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3536 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3537 mi2s_rx_cfg[PRIM_MI2S].bit_format);
3538 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
3539 channels->min = channels->max =
3540 mi2s_rx_cfg[PRIM_MI2S].channels;
3541 break;
3542
3543 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3544 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3545 mi2s_tx_cfg[PRIM_MI2S].bit_format);
3546 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
3547 channels->min = channels->max =
3548 mi2s_tx_cfg[PRIM_MI2S].channels;
3549 break;
3550
3551 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3552 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3553 mi2s_rx_cfg[SEC_MI2S].bit_format);
3554 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
3555 channels->min = channels->max =
3556 mi2s_rx_cfg[SEC_MI2S].channels;
3557 break;
3558
3559 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3560 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3561 mi2s_tx_cfg[SEC_MI2S].bit_format);
3562 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
3563 channels->min = channels->max =
3564 mi2s_tx_cfg[SEC_MI2S].channels;
3565 break;
3566
3567 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3568 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3569 mi2s_rx_cfg[TERT_MI2S].bit_format);
3570 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
3571 channels->min = channels->max =
3572 mi2s_rx_cfg[TERT_MI2S].channels;
3573 break;
3574
3575 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3576 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3577 mi2s_tx_cfg[TERT_MI2S].bit_format);
3578 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
3579 channels->min = channels->max =
3580 mi2s_tx_cfg[TERT_MI2S].channels;
3581 break;
3582
3583 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3584 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3585 mi2s_rx_cfg[QUAT_MI2S].bit_format);
3586 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
3587 channels->min = channels->max =
3588 mi2s_rx_cfg[QUAT_MI2S].channels;
3589 break;
3590
3591 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3592 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3593 mi2s_tx_cfg[QUAT_MI2S].bit_format);
3594 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
3595 channels->min = channels->max =
3596 mi2s_tx_cfg[QUAT_MI2S].channels;
3597 break;
3598
3599 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3600 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3601 mi2s_rx_cfg[QUIN_MI2S].bit_format);
3602 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
3603 channels->min = channels->max =
3604 mi2s_rx_cfg[QUIN_MI2S].channels;
3605 break;
3606
3607 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3608 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3609 mi2s_tx_cfg[QUIN_MI2S].bit_format);
3610 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
3611 channels->min = channels->max =
3612 mi2s_tx_cfg[QUIN_MI2S].channels;
3613 break;
3614
3615 default:
3616 rate->min = rate->max = SAMPLING_RATE_48KHZ;
3617 break;
3618 }
3619
3620done:
3621 return rc;
3622}
3623
3624static int msm_get_port_id(int be_id)
3625{
3626 int afe_port_id;
3627
3628 switch (be_id) {
3629 case MSM_BACKEND_DAI_PRI_MI2S_RX:
3630 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
3631 break;
3632 case MSM_BACKEND_DAI_PRI_MI2S_TX:
3633 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
3634 break;
3635 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
3636 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
3637 break;
3638 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
3639 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
3640 break;
3641 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
3642 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
3643 break;
3644 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
3645 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
3646 break;
3647 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
3648 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
3649 break;
3650 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
3651 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
3652 break;
3653 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
3654 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
3655 break;
3656 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
3657 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
3658 break;
3659 default:
3660 pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
3661 afe_port_id = -EINVAL;
3662 }
3663
3664 return afe_port_id;
3665}
3666
3667static u32 get_mi2s_bits_per_sample(u32 bit_format)
3668{
3669 u32 bit_per_sample;
3670
3671 switch (bit_format) {
3672 case SNDRV_PCM_FORMAT_S32_LE:
3673 case SNDRV_PCM_FORMAT_S24_3LE:
3674 case SNDRV_PCM_FORMAT_S24_LE:
3675 bit_per_sample = 32;
3676 break;
3677 case SNDRV_PCM_FORMAT_S16_LE:
3678 default:
3679 bit_per_sample = 16;
3680 break;
3681 }
3682
3683 return bit_per_sample;
3684}
3685
3686static void update_mi2s_clk_val(int dai_id, int stream)
3687{
3688 u32 bit_per_sample;
3689
3690 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
3691 bit_per_sample =
3692 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
3693 mi2s_clk[dai_id].clk_freq_in_hz =
3694 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3695 } else {
3696 bit_per_sample =
3697 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
3698 mi2s_clk[dai_id].clk_freq_in_hz =
3699 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
3700 }
3701}
3702
3703static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
3704{
3705 int ret = 0;
3706 struct snd_soc_pcm_runtime *rtd = substream->private_data;
3707 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3708 int port_id = 0;
3709 int index = cpu_dai->id;
3710
3711 port_id = msm_get_port_id(rtd->dai_link->id);
3712 if (port_id < 0) {
3713 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
3714 ret = port_id;
3715 goto err;
3716 }
3717
3718 if (enable) {
3719 update_mi2s_clk_val(index, substream->stream);
3720 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
3721 mi2s_clk[index].clk_freq_in_hz);
3722 }
3723
3724 mi2s_clk[index].enable = enable;
3725 ret = afe_set_lpass_clock_v2(port_id,
3726 &mi2s_clk[index]);
3727 if (ret < 0) {
3728 dev_err(rtd->card->dev,
3729 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
3730 __func__, port_id, ret);
3731 goto err;
3732 }
3733
3734err:
3735 return ret;
3736}
3737
3738#ifdef ENABLE_PINCTRL
3739static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3740 enum pinctrl_pin_state new_state)
3741{
3742 int ret = 0;
3743 int curr_state = 0;
3744
3745 if (pinctrl_info == NULL) {
3746 pr_err("%s: pinctrl_info is NULL\n", __func__);
3747 ret = -EINVAL;
3748 goto err;
3749 }
3750
3751 if (pinctrl_info->pinctrl == NULL) {
3752 pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
3753 ret = -EINVAL;
3754 goto err;
3755 }
3756
3757 curr_state = pinctrl_info->curr_state;
3758 pinctrl_info->curr_state = new_state;
3759 pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
3760 pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
3761
3762 if (curr_state == pinctrl_info->curr_state) {
3763 pr_debug("%s: Already in same state\n", __func__);
3764 goto err;
3765 }
3766
3767 if (curr_state != STATE_DISABLE &&
3768 pinctrl_info->curr_state != STATE_DISABLE) {
3769 pr_debug("%s: state already active cannot switch\n", __func__);
3770 ret = -EIO;
3771 goto err;
3772 }
3773
3774 switch (pinctrl_info->curr_state) {
3775 case STATE_MI2S_ACTIVE:
3776 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3777 pinctrl_info->mi2s_active);
3778 if (ret) {
3779 pr_err("%s: MI2S state select failed with %d\n",
3780 __func__, ret);
3781 ret = -EIO;
3782 goto err;
3783 }
3784 break;
3785 case STATE_TDM_ACTIVE:
3786 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3787 pinctrl_info->tdm_active);
3788 if (ret) {
3789 pr_err("%s: TDM state select failed with %d\n",
3790 __func__, ret);
3791 ret = -EIO;
3792 goto err;
3793 }
3794 break;
3795 case STATE_DISABLE:
3796 if (curr_state == STATE_MI2S_ACTIVE) {
3797 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3798 pinctrl_info->mi2s_disable);
3799 } else {
3800 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3801 pinctrl_info->tdm_disable);
3802 }
3803 if (ret) {
3804 pr_err("%s: state disable failed with %d\n",
3805 __func__, ret);
3806 ret = -EIO;
3807 goto err;
3808 }
3809 break;
3810 default:
3811 pr_err("%s: TLMM pin state is invalid\n", __func__);
3812 return -EINVAL;
3813 }
3814
3815err:
3816 return ret;
3817}
3818
3819static void msm_release_pinctrl(struct platform_device *pdev)
3820{
3821 struct snd_soc_card *card = platform_get_drvdata(pdev);
3822 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3823 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
3824
3825 if (pinctrl_info->pinctrl) {
3826 devm_pinctrl_put(pinctrl_info->pinctrl);
3827 pinctrl_info->pinctrl = NULL;
3828 }
3829}
3830
3831static int msm_get_pinctrl(struct platform_device *pdev)
3832{
3833 struct snd_soc_card *card = platform_get_drvdata(pdev);
3834 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
3835 struct msm_pinctrl_info *pinctrl_info = NULL;
3836 struct pinctrl *pinctrl;
3837 int ret = 0;
3838
3839 pinctrl_info = &pdata->pinctrl_info;
3840
3841 if (pinctrl_info == NULL) {
3842 pr_err("%s: pinctrl_info is NULL\n", __func__);
3843 return -EINVAL;
3844 }
3845
3846 pinctrl = devm_pinctrl_get(&pdev->dev);
3847 if (IS_ERR_OR_NULL(pinctrl)) {
3848 pr_err("%s: Unable to get pinctrl handle\n", __func__);
3849 return -EINVAL;
3850 }
3851 pinctrl_info->pinctrl = pinctrl;
3852
3853 /* get all the states handles from Device Tree */
3854 pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
3855 "quat_mi2s_disable");
3856 if (IS_ERR(pinctrl_info->mi2s_disable)) {
3857 pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
3858 goto err;
3859 }
3860 pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
3861 "quat_mi2s_enable");
3862 if (IS_ERR(pinctrl_info->mi2s_active)) {
3863 pr_err("%s: could not get mi2s_active pinstate\n", __func__);
3864 goto err;
3865 }
3866 pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
3867 "quat_tdm_disable");
3868 if (IS_ERR(pinctrl_info->tdm_disable)) {
3869 pr_err("%s: could not get tdm_disable pinstate\n", __func__);
3870 goto err;
3871 }
3872 pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
3873 "quat_tdm_enable");
3874 if (IS_ERR(pinctrl_info->tdm_active)) {
3875 pr_err("%s: could not get tdm_active pinstate\n",
3876 __func__);
3877 goto err;
3878 }
3879 /* Reset the TLMM pins to a default state */
3880 ret = pinctrl_select_state(pinctrl_info->pinctrl,
3881 pinctrl_info->mi2s_disable);
3882 if (ret != 0) {
3883 pr_err("%s: Disable TLMM pins failed with %d\n",
3884 __func__, ret);
3885 ret = -EIO;
3886 goto err;
3887 }
3888 pinctrl_info->curr_state = STATE_DISABLE;
3889
3890 return 0;
3891
3892err:
3893 devm_pinctrl_put(pinctrl);
3894 pinctrl_info->pinctrl = NULL;
3895 return -EINVAL;
3896}
3897#else
3898static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
3899 enum pinctrl_pin_state new_state)
3900{
3901 return 0;
3902}
3903
3904static void msm_release_pinctrl(struct platform_device *pdev)
3905{
3906 return;
3907}
3908
3909static int msm_get_pinctrl(struct platform_device *pdev)
3910{
3911 return 0;
3912}
3913#endif
3914
3915static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
3916 struct snd_pcm_hw_params *params)
3917{
3918 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
3919 struct snd_interval *rate = hw_param_interval(params,
3920 SNDRV_PCM_HW_PARAM_RATE);
3921 struct snd_interval *channels = hw_param_interval(params,
3922 SNDRV_PCM_HW_PARAM_CHANNELS);
3923
3924 switch (cpu_dai->id) {
3925 case AFE_PORT_ID_PRIMARY_TDM_RX:
3926 channels->min = channels->max =
3927 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
3928 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3929 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
3930 rate->min = rate->max =
3931 tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
3932 break;
3933 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
3934 channels->min = channels->max =
3935 tdm_rx_cfg[TDM_PRI][TDM_1].channels;
3936 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3937 tdm_rx_cfg[TDM_PRI][TDM_1].bit_format);
3938 rate->min = rate->max =
3939 tdm_rx_cfg[TDM_PRI][TDM_1].sample_rate;
3940 break;
3941 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
3942 channels->min = channels->max =
3943 tdm_rx_cfg[TDM_PRI][TDM_2].channels;
3944 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3945 tdm_rx_cfg[TDM_PRI][TDM_2].bit_format);
3946 rate->min = rate->max =
3947 tdm_rx_cfg[TDM_PRI][TDM_2].sample_rate;
3948 break;
3949 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
3950 channels->min = channels->max =
3951 tdm_rx_cfg[TDM_PRI][TDM_3].channels;
3952 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3953 tdm_rx_cfg[TDM_PRI][TDM_3].bit_format);
3954 rate->min = rate->max =
3955 tdm_rx_cfg[TDM_PRI][TDM_3].sample_rate;
3956 break;
3957 case AFE_PORT_ID_PRIMARY_TDM_TX:
3958 channels->min = channels->max =
3959 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
3960 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3961 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
3962 rate->min = rate->max =
3963 tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
3964 break;
3965 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
3966 channels->min = channels->max =
3967 tdm_tx_cfg[TDM_PRI][TDM_1].channels;
3968 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3969 tdm_tx_cfg[TDM_PRI][TDM_1].bit_format);
3970 rate->min = rate->max =
3971 tdm_tx_cfg[TDM_PRI][TDM_1].sample_rate;
3972 break;
3973 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
3974 channels->min = channels->max =
3975 tdm_tx_cfg[TDM_PRI][TDM_2].channels;
3976 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3977 tdm_tx_cfg[TDM_PRI][TDM_2].bit_format);
3978 rate->min = rate->max =
3979 tdm_tx_cfg[TDM_PRI][TDM_2].sample_rate;
3980 break;
3981 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
3982 channels->min = channels->max =
3983 tdm_tx_cfg[TDM_PRI][TDM_3].channels;
3984 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3985 tdm_tx_cfg[TDM_PRI][TDM_3].bit_format);
3986 rate->min = rate->max =
3987 tdm_tx_cfg[TDM_PRI][TDM_3].sample_rate;
3988 break;
3989 case AFE_PORT_ID_SECONDARY_TDM_RX:
3990 channels->min = channels->max =
3991 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
3992 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
3993 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
3994 rate->min = rate->max =
3995 tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
3996 break;
3997 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
3998 channels->min = channels->max =
3999 tdm_rx_cfg[TDM_SEC][TDM_1].channels;
4000 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4001 tdm_rx_cfg[TDM_SEC][TDM_1].bit_format);
4002 rate->min = rate->max =
4003 tdm_rx_cfg[TDM_SEC][TDM_1].sample_rate;
4004 break;
4005 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4006 channels->min = channels->max =
4007 tdm_rx_cfg[TDM_SEC][TDM_2].channels;
4008 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4009 tdm_rx_cfg[TDM_SEC][TDM_2].bit_format);
4010 rate->min = rate->max =
4011 tdm_rx_cfg[TDM_SEC][TDM_2].sample_rate;
4012 break;
4013 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4014 channels->min = channels->max =
4015 tdm_rx_cfg[TDM_SEC][TDM_3].channels;
4016 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4017 tdm_rx_cfg[TDM_SEC][TDM_3].bit_format);
4018 rate->min = rate->max =
4019 tdm_rx_cfg[TDM_SEC][TDM_3].sample_rate;
4020 break;
4021 case AFE_PORT_ID_SECONDARY_TDM_TX:
4022 channels->min = channels->max =
4023 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4024 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4025 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4026 rate->min = rate->max =
4027 tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4028 break;
4029 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4030 channels->min = channels->max =
4031 tdm_tx_cfg[TDM_SEC][TDM_1].channels;
4032 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4033 tdm_tx_cfg[TDM_SEC][TDM_1].bit_format);
4034 rate->min = rate->max =
4035 tdm_tx_cfg[TDM_SEC][TDM_1].sample_rate;
4036 break;
4037 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4038 channels->min = channels->max =
4039 tdm_tx_cfg[TDM_SEC][TDM_2].channels;
4040 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4041 tdm_tx_cfg[TDM_SEC][TDM_2].bit_format);
4042 rate->min = rate->max =
4043 tdm_tx_cfg[TDM_SEC][TDM_2].sample_rate;
4044 break;
4045 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4046 channels->min = channels->max =
4047 tdm_tx_cfg[TDM_SEC][TDM_3].channels;
4048 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4049 tdm_tx_cfg[TDM_SEC][TDM_3].bit_format);
4050 rate->min = rate->max =
4051 tdm_tx_cfg[TDM_SEC][TDM_3].sample_rate;
4052 break;
4053 case AFE_PORT_ID_TERTIARY_TDM_RX:
4054 channels->min = channels->max =
4055 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4056 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4057 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4058 rate->min = rate->max =
4059 tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4060 break;
4061 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4062 channels->min = channels->max =
4063 tdm_rx_cfg[TDM_TERT][TDM_1].channels;
4064 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4065 tdm_rx_cfg[TDM_TERT][TDM_1].bit_format);
4066 rate->min = rate->max =
4067 tdm_rx_cfg[TDM_TERT][TDM_1].sample_rate;
4068 break;
4069 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4070 channels->min = channels->max =
4071 tdm_rx_cfg[TDM_TERT][TDM_2].channels;
4072 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4073 tdm_rx_cfg[TDM_TERT][TDM_2].bit_format);
4074 rate->min = rate->max =
4075 tdm_rx_cfg[TDM_TERT][TDM_2].sample_rate;
4076 break;
4077 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4078 channels->min = channels->max =
4079 tdm_rx_cfg[TDM_TERT][TDM_3].channels;
4080 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4081 tdm_rx_cfg[TDM_TERT][TDM_3].bit_format);
4082 rate->min = rate->max =
4083 tdm_rx_cfg[TDM_TERT][TDM_3].sample_rate;
4084 break;
4085 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4086 channels->min = channels->max =
4087 tdm_rx_cfg[TDM_TERT][TDM_4].channels;
4088 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4089 tdm_rx_cfg[TDM_TERT][TDM_4].bit_format);
4090 rate->min = rate->max =
4091 tdm_rx_cfg[TDM_TERT][TDM_4].sample_rate;
4092 break;
4093 case AFE_PORT_ID_TERTIARY_TDM_TX:
4094 channels->min = channels->max =
4095 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4096 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4097 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4098 rate->min = rate->max =
4099 tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4100 break;
4101 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4102 channels->min = channels->max =
4103 tdm_tx_cfg[TDM_TERT][TDM_1].channels;
4104 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4105 tdm_tx_cfg[TDM_TERT][TDM_1].bit_format);
4106 rate->min = rate->max =
4107 tdm_tx_cfg[TDM_TERT][TDM_1].sample_rate;
4108 break;
4109 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4110 channels->min = channels->max =
4111 tdm_tx_cfg[TDM_TERT][TDM_2].channels;
4112 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4113 tdm_tx_cfg[TDM_TERT][TDM_2].bit_format);
4114 rate->min = rate->max =
4115 tdm_tx_cfg[TDM_TERT][TDM_2].sample_rate;
4116 break;
4117 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4118 channels->min = channels->max =
4119 tdm_tx_cfg[TDM_TERT][TDM_3].channels;
4120 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4121 tdm_tx_cfg[TDM_TERT][TDM_3].bit_format);
4122 rate->min = rate->max =
4123 tdm_tx_cfg[TDM_TERT][TDM_3].sample_rate;
4124 break;
4125 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4126 channels->min = channels->max =
4127 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4128 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4129 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4130 rate->min = rate->max =
4131 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4132 break;
4133 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4134 channels->min = channels->max =
4135 tdm_rx_cfg[TDM_QUAT][TDM_1].channels;
4136 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4137 tdm_rx_cfg[TDM_QUAT][TDM_1].bit_format);
4138 rate->min = rate->max =
4139 tdm_rx_cfg[TDM_QUAT][TDM_1].sample_rate;
4140 break;
4141 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4142 channels->min = channels->max =
4143 tdm_rx_cfg[TDM_QUAT][TDM_2].channels;
4144 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4145 tdm_rx_cfg[TDM_QUAT][TDM_2].bit_format);
4146 rate->min = rate->max =
4147 tdm_rx_cfg[TDM_QUAT][TDM_2].sample_rate;
4148 break;
4149 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4150 channels->min = channels->max =
4151 tdm_rx_cfg[TDM_QUAT][TDM_3].channels;
4152 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4153 tdm_rx_cfg[TDM_QUAT][TDM_3].bit_format);
4154 rate->min = rate->max =
4155 tdm_rx_cfg[TDM_QUAT][TDM_3].sample_rate;
4156 break;
4157 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4158 channels->min = channels->max =
4159 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4160 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4161 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4162 rate->min = rate->max =
4163 tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4164 break;
4165 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4166 channels->min = channels->max =
4167 tdm_tx_cfg[TDM_QUAT][TDM_1].channels;
4168 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4169 tdm_tx_cfg[TDM_QUAT][TDM_1].bit_format);
4170 rate->min = rate->max =
4171 tdm_tx_cfg[TDM_QUAT][TDM_1].sample_rate;
4172 break;
4173 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4174 channels->min = channels->max =
4175 tdm_tx_cfg[TDM_QUAT][TDM_2].channels;
4176 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4177 tdm_tx_cfg[TDM_QUAT][TDM_2].bit_format);
4178 rate->min = rate->max =
4179 tdm_tx_cfg[TDM_QUAT][TDM_2].sample_rate;
4180 break;
4181 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4182 channels->min = channels->max =
4183 tdm_tx_cfg[TDM_QUAT][TDM_3].channels;
4184 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4185 tdm_tx_cfg[TDM_QUAT][TDM_3].bit_format);
4186 rate->min = rate->max =
4187 tdm_tx_cfg[TDM_QUAT][TDM_3].sample_rate;
4188 break;
4189 case AFE_PORT_ID_QUINARY_TDM_RX:
4190 channels->min = channels->max =
4191 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4192 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4193 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4194 rate->min = rate->max =
4195 tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4196 break;
4197 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4198 channels->min = channels->max =
4199 tdm_rx_cfg[TDM_QUIN][TDM_1].channels;
4200 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4201 tdm_rx_cfg[TDM_QUIN][TDM_1].bit_format);
4202 rate->min = rate->max =
4203 tdm_rx_cfg[TDM_QUIN][TDM_1].sample_rate;
4204 break;
4205 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4206 channels->min = channels->max =
4207 tdm_rx_cfg[TDM_QUIN][TDM_2].channels;
4208 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4209 tdm_rx_cfg[TDM_QUIN][TDM_2].bit_format);
4210 rate->min = rate->max =
4211 tdm_rx_cfg[TDM_QUIN][TDM_2].sample_rate;
4212 break;
4213 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4214 channels->min = channels->max =
4215 tdm_rx_cfg[TDM_QUIN][TDM_3].channels;
4216 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4217 tdm_rx_cfg[TDM_QUIN][TDM_3].bit_format);
4218 rate->min = rate->max =
4219 tdm_rx_cfg[TDM_QUIN][TDM_3].sample_rate;
4220 break;
4221 case AFE_PORT_ID_QUINARY_TDM_TX:
4222 channels->min = channels->max =
4223 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4224 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4225 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4226 rate->min = rate->max =
4227 tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4228 break;
4229 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4230 channels->min = channels->max =
4231 tdm_tx_cfg[TDM_QUIN][TDM_1].channels;
4232 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4233 tdm_tx_cfg[TDM_QUIN][TDM_1].bit_format);
4234 rate->min = rate->max =
4235 tdm_tx_cfg[TDM_QUIN][TDM_1].sample_rate;
4236 break;
4237 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4238 channels->min = channels->max =
4239 tdm_tx_cfg[TDM_QUIN][TDM_2].channels;
4240 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4241 tdm_tx_cfg[TDM_QUIN][TDM_2].bit_format);
4242 rate->min = rate->max =
4243 tdm_tx_cfg[TDM_QUIN][TDM_2].sample_rate;
4244 break;
4245 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4246 channels->min = channels->max =
4247 tdm_tx_cfg[TDM_QUIN][TDM_3].channels;
4248 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4249 tdm_tx_cfg[TDM_QUIN][TDM_3].bit_format);
4250 rate->min = rate->max =
4251 tdm_tx_cfg[TDM_QUIN][TDM_3].sample_rate;
4252 break;
4253 default:
4254 pr_err("%s: dai id 0x%x not supported\n",
4255 __func__, cpu_dai->id);
4256 return -EINVAL;
4257 }
4258
4259 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
4260 __func__, cpu_dai->id, channels->max, rate->max,
4261 params_format(params));
4262
4263 return 0;
4264}
4265
4266static unsigned int tdm_param_set_slot_mask(int slots)
4267{
4268 unsigned int slot_mask = 0;
4269 int i = 0;
4270
4271 if ((slots <= 0) || (slots > 32)) {
4272 pr_err("%s: invalid slot number %d\n", __func__, slots);
4273 return -EINVAL;
4274 }
4275
4276 for (i = 0; i < slots ; i++)
4277 slot_mask |= 1 << i;
4278 return slot_mask;
4279}
4280
4281static int sa6155_tdm_snd_hw_params(struct snd_pcm_substream *substream,
4282 struct snd_pcm_hw_params *params)
4283{
4284 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4285 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4286 int ret = 0;
4287 int channels, slot_width, slots, rate, format;
4288 unsigned int slot_mask;
4289 unsigned int *slot_offset;
4290 int offset_channels = 0;
4291 int i;
4292 int clk_freq;
4293
4294 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
4295
4296 channels = params_channels(params);
4297 if (channels < 1 || channels > 32) {
4298 pr_err("%s: invalid param channels %d\n",
4299 __func__, channels);
4300 return -EINVAL;
4301 }
4302
4303 format = params_format(params);
4304 if (format != SNDRV_PCM_FORMAT_S32_LE &&
4305 format != SNDRV_PCM_FORMAT_S24_LE &&
4306 format != SNDRV_PCM_FORMAT_S16_LE) {
4307 /*
4308 * Up to 8 channel HW configuration should
4309 * use 32 bit slot width for max support of
4310 * stream bit width. (slot_width > bit_width)
4311 */
4312 pr_err("%s: invalid param format 0x%x\n",
4313 __func__, format);
4314 return -EINVAL;
4315 }
4316
4317 switch (cpu_dai->id) {
4318 case AFE_PORT_ID_PRIMARY_TDM_RX:
4319 slots = tdm_slot[TDM_PRI].num;
4320 slot_width = tdm_slot[TDM_PRI].width;
4321 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_0];
4322 break;
4323 case AFE_PORT_ID_PRIMARY_TDM_RX_1:
4324 slots = tdm_slot[TDM_PRI].num;
4325 slot_width = tdm_slot[TDM_PRI].width;
4326 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_1];
4327 break;
4328 case AFE_PORT_ID_PRIMARY_TDM_RX_2:
4329 slots = tdm_slot[TDM_PRI].num;
4330 slot_width = tdm_slot[TDM_PRI].width;
4331 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_2];
4332 break;
4333 case AFE_PORT_ID_PRIMARY_TDM_RX_3:
4334 slots = tdm_slot[TDM_PRI].num;
4335 slot_width = tdm_slot[TDM_PRI].width;
4336 slot_offset = tdm_rx_slot_offset[TDM_PRI][TDM_3];
4337 break;
4338 case AFE_PORT_ID_PRIMARY_TDM_TX:
4339 slots = tdm_slot[TDM_PRI].num;
4340 slot_width = tdm_slot[TDM_PRI].width;
4341 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_0];
4342 break;
4343 case AFE_PORT_ID_PRIMARY_TDM_TX_1:
4344 slots = tdm_slot[TDM_PRI].num;
4345 slot_width = tdm_slot[TDM_PRI].width;
4346 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_1];
4347 break;
4348 case AFE_PORT_ID_PRIMARY_TDM_TX_2:
4349 slots = tdm_slot[TDM_PRI].num;
4350 slot_width = tdm_slot[TDM_PRI].width;
4351 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_2];
4352 break;
4353 case AFE_PORT_ID_PRIMARY_TDM_TX_3:
4354 slots = tdm_slot[TDM_PRI].num;
4355 slot_width = tdm_slot[TDM_PRI].width;
4356 slot_offset = tdm_tx_slot_offset[TDM_PRI][TDM_3];
4357 break;
4358 case AFE_PORT_ID_SECONDARY_TDM_RX:
4359 slots = tdm_slot[TDM_SEC].num;
4360 slot_width = tdm_slot[TDM_SEC].width;
4361 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_0];
4362 break;
4363 case AFE_PORT_ID_SECONDARY_TDM_RX_1:
4364 slots = tdm_slot[TDM_SEC].num;
4365 slot_width = tdm_slot[TDM_SEC].width;
4366 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_1];
4367 break;
4368 case AFE_PORT_ID_SECONDARY_TDM_RX_2:
4369 slots = tdm_slot[TDM_SEC].num;
4370 slot_width = tdm_slot[TDM_SEC].width;
4371 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_2];
4372 break;
4373 case AFE_PORT_ID_SECONDARY_TDM_RX_3:
4374 slots = tdm_slot[TDM_SEC].num;
4375 slot_width = tdm_slot[TDM_SEC].width;
4376 slot_offset = tdm_rx_slot_offset[TDM_SEC][TDM_3];
4377 break;
4378 case AFE_PORT_ID_SECONDARY_TDM_TX:
4379 slots = tdm_slot[TDM_SEC].num;
4380 slot_width = tdm_slot[TDM_SEC].width;
4381 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_0];
4382 break;
4383 case AFE_PORT_ID_SECONDARY_TDM_TX_1:
4384 slots = tdm_slot[TDM_SEC].num;
4385 slot_width = tdm_slot[TDM_SEC].width;
4386 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_1];
4387 break;
4388 case AFE_PORT_ID_SECONDARY_TDM_TX_2:
4389 slots = tdm_slot[TDM_SEC].num;
4390 slot_width = tdm_slot[TDM_SEC].width;
4391 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_2];
4392 break;
4393 case AFE_PORT_ID_SECONDARY_TDM_TX_3:
4394 slots = tdm_slot[TDM_SEC].num;
4395 slot_width = tdm_slot[TDM_SEC].width;
4396 slot_offset = tdm_tx_slot_offset[TDM_SEC][TDM_3];
4397 break;
4398 case AFE_PORT_ID_TERTIARY_TDM_RX:
4399 slots = tdm_slot[TDM_TERT].num;
4400 slot_width = tdm_slot[TDM_TERT].width;
4401 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_0];
4402 break;
4403 case AFE_PORT_ID_TERTIARY_TDM_RX_1:
4404 slots = tdm_slot[TDM_TERT].num;
4405 slot_width = tdm_slot[TDM_TERT].width;
4406 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_1];
4407 break;
4408 case AFE_PORT_ID_TERTIARY_TDM_RX_2:
4409 slots = tdm_slot[TDM_TERT].num;
4410 slot_width = tdm_slot[TDM_TERT].width;
4411 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_2];
4412 break;
4413 case AFE_PORT_ID_TERTIARY_TDM_RX_3:
4414 slots = tdm_slot[TDM_TERT].num;
4415 slot_width = tdm_slot[TDM_TERT].width;
4416 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_3];
4417 break;
4418 case AFE_PORT_ID_TERTIARY_TDM_RX_4:
4419 slots = tdm_slot[TDM_TERT].num;
4420 slot_width = tdm_slot[TDM_TERT].width;
4421 slot_offset = tdm_rx_slot_offset[TDM_TERT][TDM_4];
4422 break;
4423 case AFE_PORT_ID_TERTIARY_TDM_TX:
4424 slots = tdm_slot[TDM_TERT].num;
4425 slot_width = tdm_slot[TDM_TERT].width;
4426 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_0];
4427 break;
4428 case AFE_PORT_ID_TERTIARY_TDM_TX_1:
4429 slots = tdm_slot[TDM_TERT].num;
4430 slot_width = tdm_slot[TDM_TERT].width;
4431 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_1];
4432 break;
4433 case AFE_PORT_ID_TERTIARY_TDM_TX_2:
4434 slots = tdm_slot[TDM_TERT].num;
4435 slot_width = tdm_slot[TDM_TERT].width;
4436 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_2];
4437 break;
4438 case AFE_PORT_ID_TERTIARY_TDM_TX_3:
4439 slots = tdm_slot[TDM_TERT].num;
4440 slot_width = tdm_slot[TDM_TERT].width;
4441 slot_offset = tdm_tx_slot_offset[TDM_TERT][TDM_3];
4442 break;
4443 case AFE_PORT_ID_QUATERNARY_TDM_RX:
4444 slots = tdm_slot[TDM_QUAT].num;
4445 slot_width = tdm_slot[TDM_QUAT].width;
4446 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_0];
4447 break;
4448 case AFE_PORT_ID_QUATERNARY_TDM_RX_1:
4449 slots = tdm_slot[TDM_QUAT].num;
4450 slot_width = tdm_slot[TDM_QUAT].width;
4451 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_1];
4452 break;
4453 case AFE_PORT_ID_QUATERNARY_TDM_RX_2:
4454 slots = tdm_slot[TDM_QUAT].num;
4455 slot_width = tdm_slot[TDM_QUAT].width;
4456 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_2];
4457 break;
4458 case AFE_PORT_ID_QUATERNARY_TDM_RX_3:
4459 slots = tdm_slot[TDM_QUAT].num;
4460 slot_width = tdm_slot[TDM_QUAT].width;
4461 slot_offset = tdm_rx_slot_offset[TDM_QUAT][TDM_3];
4462 break;
4463 case AFE_PORT_ID_QUATERNARY_TDM_TX:
4464 slots = tdm_slot[TDM_QUAT].num;
4465 slot_width = tdm_slot[TDM_QUAT].width;
4466 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_0];
4467 break;
4468 case AFE_PORT_ID_QUATERNARY_TDM_TX_1:
4469 slots = tdm_slot[TDM_QUAT].num;
4470 slot_width = tdm_slot[TDM_QUAT].width;
4471 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_1];
4472 break;
4473 case AFE_PORT_ID_QUATERNARY_TDM_TX_2:
4474 slots = tdm_slot[TDM_QUAT].num;
4475 slot_width = tdm_slot[TDM_QUAT].width;
4476 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_2];
4477 break;
4478 case AFE_PORT_ID_QUATERNARY_TDM_TX_3:
4479 slots = tdm_slot[TDM_QUAT].num;
4480 slot_width = tdm_slot[TDM_QUAT].width;
4481 slot_offset = tdm_tx_slot_offset[TDM_QUAT][TDM_3];
4482 break;
4483 case AFE_PORT_ID_QUINARY_TDM_RX:
4484 slots = tdm_slot[TDM_QUIN].num;
4485 slot_width = tdm_slot[TDM_QUIN].width;
4486 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_0];
4487 break;
4488 case AFE_PORT_ID_QUINARY_TDM_RX_1:
4489 slots = tdm_slot[TDM_QUIN].num;
4490 slot_width = tdm_slot[TDM_QUIN].width;
4491 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_1];
4492 break;
4493 case AFE_PORT_ID_QUINARY_TDM_RX_2:
4494 slots = tdm_slot[TDM_QUIN].num;
4495 slot_width = tdm_slot[TDM_QUIN].width;
4496 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_2];
4497 break;
4498 case AFE_PORT_ID_QUINARY_TDM_RX_3:
4499 slots = tdm_slot[TDM_QUIN].num;
4500 slot_width = tdm_slot[TDM_QUIN].width;
4501 slot_offset = tdm_rx_slot_offset[TDM_QUIN][TDM_3];
4502 break;
4503 case AFE_PORT_ID_QUINARY_TDM_TX:
4504 slots = tdm_slot[TDM_QUIN].num;
4505 slot_width = tdm_slot[TDM_QUIN].width;
4506 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_0];
4507 break;
4508 case AFE_PORT_ID_QUINARY_TDM_TX_1:
4509 slots = tdm_slot[TDM_QUIN].num;
4510 slot_width = tdm_slot[TDM_QUIN].width;
4511 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_1];
4512 break;
4513 case AFE_PORT_ID_QUINARY_TDM_TX_2:
4514 slots = tdm_slot[TDM_QUIN].num;
4515 slot_width = tdm_slot[TDM_QUIN].width;
4516 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_2];
4517 break;
4518 case AFE_PORT_ID_QUINARY_TDM_TX_3:
4519 slots = tdm_slot[TDM_QUIN].num;
4520 slot_width = tdm_slot[TDM_QUIN].width;
4521 slot_offset = tdm_tx_slot_offset[TDM_QUIN][TDM_3];
4522 break;
4523 default:
4524 pr_err("%s: dai id 0x%x not supported\n",
4525 __func__, cpu_dai->id);
4526 return -EINVAL;
4527 }
4528
4529 for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) {
4530 if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID)
4531 offset_channels++;
4532 else
4533 break;
4534 }
4535
4536 if (offset_channels == 0) {
4537 pr_err("%s: invalid offset_channels %d\n",
4538 __func__, offset_channels);
4539 return -EINVAL;
4540 }
4541
4542 if (channels > offset_channels) {
4543 pr_err("%s: channels %d exceed offset_channels %d\n",
4544 __func__, channels, offset_channels);
4545 return -EINVAL;
4546 }
4547
4548 slot_mask = tdm_param_set_slot_mask(slots);
4549 if (!slot_mask) {
4550 pr_err("%s: invalid slot_mask 0x%x\n",
4551 __func__, slot_mask);
4552 return -EINVAL;
4553 }
4554
4555 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4556 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
4557 slots, slot_width);
4558 if (ret < 0) {
4559 pr_err("%s: failed to set tdm slot, err:%d\n",
4560 __func__, ret);
4561 goto end;
4562 }
4563
4564 ret = snd_soc_dai_set_channel_map(cpu_dai,
4565 0, NULL, channels, slot_offset);
4566 if (ret < 0) {
4567 pr_err("%s: failed to set channel map, err:%d\n",
4568 __func__, ret);
4569 goto end;
4570 }
4571 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
4572 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
4573 slots, slot_width);
4574 if (ret < 0) {
4575 pr_err("%s: failed to set tdm slot, err:%d\n",
4576 __func__, ret);
4577 goto end;
4578 }
4579
4580 ret = snd_soc_dai_set_channel_map(cpu_dai,
4581 channels, slot_offset, 0, NULL);
4582 if (ret < 0) {
4583 pr_err("%s: failed to set channel map, err:%d\n",
4584 __func__, ret);
4585 goto end;
4586 }
4587 } else {
4588 ret = -EINVAL;
4589 pr_err("%s: invalid use case, err:%d\n",
4590 __func__, ret);
4591 goto end;
4592 }
4593
4594 rate = params_rate(params);
4595 clk_freq = rate * slot_width * slots;
4596 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
4597 if (ret < 0)
4598 pr_err("%s: failed to set tdm clk, err:%d\n",
4599 __func__, ret);
4600
4601end:
4602 return ret;
4603}
4604
4605static int sa6155_tdm_snd_startup(struct snd_pcm_substream *substream)
4606{
4607 int ret = 0;
4608 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4609 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4610 struct snd_soc_card *card = rtd->card;
4611 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4612 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4613
4614 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4615 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
4616 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
4617 ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
4618 if (ret)
4619 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4620 __func__, ret);
4621 }
4622
4623 return ret;
4624}
4625
4626static void sa6155_tdm_snd_shutdown(struct snd_pcm_substream *substream)
4627{
4628 int ret = 0;
4629 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4630 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4631 struct snd_soc_card *card = rtd->card;
4632 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4633 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4634
4635 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
4636 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
4637 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
4638 ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
4639 if (ret)
4640 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
4641 __func__, ret);
4642 }
4643}
4644
4645static struct snd_soc_ops sa6155_tdm_be_ops = {
4646 .hw_params = sa6155_tdm_snd_hw_params,
4647 .startup = sa6155_tdm_snd_startup,
4648 .shutdown = sa6155_tdm_snd_shutdown
4649};
4650
4651static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
4652{
4653 cpumask_t mask;
4654
4655 if (pm_qos_request_active(&substream->latency_pm_qos_req))
4656 pm_qos_remove_request(&substream->latency_pm_qos_req);
4657
4658 cpumask_clear(&mask);
4659 cpumask_set_cpu(1, &mask); /* affine to core 1 */
4660 cpumask_set_cpu(2, &mask); /* affine to core 2 */
4661 cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
4662
4663 substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
4664
4665 pm_qos_add_request(&substream->latency_pm_qos_req,
4666 PM_QOS_CPU_DMA_LATENCY,
4667 MSM_LL_QOS_VALUE);
4668 return 0;
4669}
4670
4671static struct snd_soc_ops msm_fe_qos_ops = {
4672 .prepare = msm_fe_qos_prepare,
4673};
4674
4675static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
4676{
4677 int ret = 0;
4678 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4679 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4680 int index = cpu_dai->id;
4681 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
4682 struct snd_soc_card *card = rtd->card;
4683 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4684 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4685 int ret_pinctrl = 0;
4686
4687 dev_dbg(rtd->card->dev,
4688 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
4689 __func__, substream->name, substream->stream,
4690 cpu_dai->name, cpu_dai->id);
4691
4692 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4693 ret = -EINVAL;
4694 dev_err(rtd->card->dev,
4695 "%s: CPU DAI id (%d) out of range\n",
4696 __func__, cpu_dai->id);
4697 goto err;
4698 }
4699 /*
4700 * Mutex protection in case the same MI2S
4701 * interface using for both TX and RX so
4702 * that the same clock won't be enable twice.
4703 */
4704 mutex_lock(&mi2s_intf_conf[index].lock);
4705 if (++mi2s_intf_conf[index].ref_cnt == 1) {
4706 /* Check if msm needs to provide the clock to the interface */
4707 if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
4708 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
4709 fmt = SND_SOC_DAIFMT_CBM_CFM;
4710 }
4711 ret = msm_mi2s_set_sclk(substream, true);
4712 if (ret < 0) {
4713 dev_err(rtd->card->dev,
4714 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
4715 __func__, ret);
4716 goto clean_up;
4717 }
4718
4719 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
4720 if (ret < 0) {
4721 pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
4722 __func__, index, ret);
4723 goto clk_off;
4724 }
4725 if (index == QUAT_MI2S) {
4726 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4727 STATE_MI2S_ACTIVE);
4728 if (ret_pinctrl)
4729 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4730 __func__, ret_pinctrl);
4731 }
4732 }
4733clk_off:
4734 if (ret < 0)
4735 msm_mi2s_set_sclk(substream, false);
4736clean_up:
4737 if (ret < 0)
4738 mi2s_intf_conf[index].ref_cnt--;
4739 mutex_unlock(&mi2s_intf_conf[index].lock);
4740err:
4741 return ret;
4742}
4743
4744static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
4745{
4746 int ret;
4747 struct snd_soc_pcm_runtime *rtd = substream->private_data;
4748 int index = rtd->cpu_dai->id;
4749 struct snd_soc_card *card = rtd->card;
4750 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
4751 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
4752 int ret_pinctrl = 0;
4753
4754 pr_debug("%s(): substream = %s stream = %d\n", __func__,
4755 substream->name, substream->stream);
4756 if (index < PRIM_MI2S || index >= MI2S_MAX) {
4757 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
4758 return;
4759 }
4760
4761 mutex_lock(&mi2s_intf_conf[index].lock);
4762 if (--mi2s_intf_conf[index].ref_cnt == 0) {
4763 ret = msm_mi2s_set_sclk(substream, false);
4764 if (ret < 0)
4765 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
4766 __func__, index, ret);
4767 if (index == QUAT_MI2S) {
4768 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
4769 STATE_DISABLE);
4770 if (ret_pinctrl)
4771 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
4772 __func__, ret_pinctrl);
4773 }
4774 }
4775 mutex_unlock(&mi2s_intf_conf[index].lock);
4776}
4777
4778static struct snd_soc_ops msm_mi2s_be_ops = {
4779 .startup = msm_mi2s_snd_startup,
4780 .shutdown = msm_mi2s_snd_shutdown,
4781};
4782
4783
4784/* Digital audio interface glue - connects codec <---> CPU */
4785static struct snd_soc_dai_link msm_common_dai_links[] = {
4786 /* FrontEnd DAI Links */
4787 {
4788 .name = MSM_DAILINK_NAME(Media1),
4789 .stream_name = "MultiMedia1",
4790 .cpu_dai_name = "MultiMedia1",
4791 .platform_name = "msm-pcm-dsp.0",
4792 .dynamic = 1,
4793 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4794 .dpcm_playback = 1,
4795 .dpcm_capture = 1,
4796 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4797 SND_SOC_DPCM_TRIGGER_POST},
4798 .codec_dai_name = "snd-soc-dummy-dai",
4799 .codec_name = "snd-soc-dummy",
4800 .ignore_suspend = 1,
4801 /* this dainlink has playback support */
4802 .ignore_pmdown_time = 1,
4803 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
4804 },
4805 {
4806 .name = MSM_DAILINK_NAME(Media2),
4807 .stream_name = "MultiMedia2",
4808 .cpu_dai_name = "MultiMedia2",
4809 .platform_name = "msm-pcm-dsp.0",
4810 .dynamic = 1,
4811 .dpcm_playback = 1,
4812 .dpcm_capture = 1,
4813 .codec_dai_name = "snd-soc-dummy-dai",
4814 .codec_name = "snd-soc-dummy",
4815 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4816 SND_SOC_DPCM_TRIGGER_POST},
4817 .ignore_suspend = 1,
4818 /* this dainlink has playback support */
4819 .ignore_pmdown_time = 1,
4820 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
4821 },
4822 {
4823 .name = "VoiceMMode1",
4824 .stream_name = "VoiceMMode1",
4825 .cpu_dai_name = "VoiceMMode1",
4826 .platform_name = "msm-pcm-voice",
4827 .dynamic = 1,
4828 .dpcm_playback = 1,
4829 .dpcm_capture = 1,
4830 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4831 SND_SOC_DPCM_TRIGGER_POST},
4832 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4833 .ignore_suspend = 1,
4834 .ignore_pmdown_time = 1,
4835 .codec_dai_name = "snd-soc-dummy-dai",
4836 .codec_name = "snd-soc-dummy",
4837 .id = MSM_FRONTEND_DAI_VOICEMMODE1,
4838 },
4839 {
4840 .name = "MSM VoIP",
4841 .stream_name = "VoIP",
4842 .cpu_dai_name = "VoIP",
4843 .platform_name = "msm-voip-dsp",
4844 .dynamic = 1,
4845 .dpcm_playback = 1,
4846 .dpcm_capture = 1,
4847 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4848 SND_SOC_DPCM_TRIGGER_POST},
4849 .codec_dai_name = "snd-soc-dummy-dai",
4850 .codec_name = "snd-soc-dummy",
4851 .ignore_suspend = 1,
4852 /* this dainlink has playback support */
4853 .ignore_pmdown_time = 1,
4854 .id = MSM_FRONTEND_DAI_VOIP,
4855 },
4856 {
4857 .name = MSM_DAILINK_NAME(ULL),
4858 .stream_name = "MultiMedia3",
4859 .cpu_dai_name = "MultiMedia3",
4860 .platform_name = "msm-pcm-dsp.2",
4861 .dynamic = 1,
4862 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4863 .dpcm_playback = 1,
4864 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4865 SND_SOC_DPCM_TRIGGER_POST},
4866 .codec_dai_name = "snd-soc-dummy-dai",
4867 .codec_name = "snd-soc-dummy",
4868 .ignore_suspend = 1,
4869 /* this dainlink has playback support */
4870 .ignore_pmdown_time = 1,
4871 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
4872 },
4873 /* - SLIMBUS_0 Hostless */
4874 {
4875 .name = "MSM AFE-PCM RX",
4876 .stream_name = "AFE-PROXY RX",
4877 .cpu_dai_name = "msm-dai-q6-dev.241",
4878 .codec_name = "msm-stub-codec.1",
4879 .codec_dai_name = "msm-stub-rx",
4880 .platform_name = "msm-pcm-afe",
4881 .dpcm_playback = 1,
4882 .ignore_suspend = 1,
4883 /* this dainlink has playback support */
4884 .ignore_pmdown_time = 1,
4885 },
4886 {
4887 .name = "MSM AFE-PCM TX",
4888 .stream_name = "AFE-PROXY TX",
4889 .cpu_dai_name = "msm-dai-q6-dev.240",
4890 .codec_name = "msm-stub-codec.1",
4891 .codec_dai_name = "msm-stub-tx",
4892 .platform_name = "msm-pcm-afe",
4893 .dpcm_capture = 1,
4894 .ignore_suspend = 1,
4895 },
4896 {
4897 .name = MSM_DAILINK_NAME(Compress1),
4898 .stream_name = "Compress1",
4899 .cpu_dai_name = "MultiMedia4",
4900 .platform_name = "msm-compress-dsp",
4901 .dynamic = 1,
4902 .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
4903 .dpcm_playback = 1,
4904 .dpcm_capture = 1,
4905 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4906 SND_SOC_DPCM_TRIGGER_POST},
4907 .codec_dai_name = "snd-soc-dummy-dai",
4908 .codec_name = "snd-soc-dummy",
4909 .ignore_suspend = 1,
4910 .ignore_pmdown_time = 1,
4911 /* this dainlink has playback support */
4912 .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
4913 },
4914 /* Hostless PCM purpose */
4915 {
4916 .name = "AUXPCM Hostless",
4917 .stream_name = "AUXPCM Hostless",
4918 .cpu_dai_name = "AUXPCM_HOSTLESS",
4919 .platform_name = "msm-pcm-hostless",
4920 .dynamic = 1,
4921 .dpcm_playback = 1,
4922 .dpcm_capture = 1,
4923 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4924 SND_SOC_DPCM_TRIGGER_POST},
4925 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4926 .ignore_suspend = 1,
4927 /* this dainlink has playback support */
4928 .ignore_pmdown_time = 1,
4929 .codec_dai_name = "snd-soc-dummy-dai",
4930 .codec_name = "snd-soc-dummy",
4931 },
4932 /* - SLIMBUS_1 Hostless */
4933 /* - SLIMBUS_3 Hostless */
4934 /* - SLIMBUS_4 Hostless */
4935 {
4936 .name = MSM_DAILINK_NAME(LowLatency),
4937 .stream_name = "MultiMedia5",
4938 .cpu_dai_name = "MultiMedia5",
4939 .platform_name = "msm-pcm-dsp.1",
4940 .dynamic = 1,
4941 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
4942 .dpcm_playback = 1,
4943 .dpcm_capture = 1,
4944 .codec_dai_name = "snd-soc-dummy-dai",
4945 .codec_name = "snd-soc-dummy",
4946 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4947 SND_SOC_DPCM_TRIGGER_POST},
4948 .ignore_suspend = 1,
4949 /* this dainlink has playback support */
4950 .ignore_pmdown_time = 1,
4951 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
4952 .ops = &msm_fe_qos_ops,
4953 },
4954 {
4955 .name = "Listen 1 Audio Service",
4956 .stream_name = "Listen 1 Audio Service",
4957 .cpu_dai_name = "LSM1",
4958 .platform_name = "msm-lsm-client",
4959 .dynamic = 1,
4960 .dpcm_capture = 1,
4961 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
4962 SND_SOC_DPCM_TRIGGER_POST },
4963 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
4964 .ignore_suspend = 1,
4965 .codec_dai_name = "snd-soc-dummy-dai",
4966 .codec_name = "snd-soc-dummy",
4967 .id = MSM_FRONTEND_DAI_LSM1,
4968 },
4969 /* Multiple Tunnel instances */
4970 {
4971 .name = MSM_DAILINK_NAME(Compress2),
4972 .stream_name = "Compress2",
4973 .cpu_dai_name = "MultiMedia7",
4974 .platform_name = "msm-compress-dsp",
4975 .dynamic = 1,
4976 .dpcm_playback = 1,
4977 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4978 SND_SOC_DPCM_TRIGGER_POST},
4979 .codec_dai_name = "snd-soc-dummy-dai",
4980 .codec_name = "snd-soc-dummy",
4981 .ignore_suspend = 1,
4982 .ignore_pmdown_time = 1,
4983 /* this dainlink has playback support */
4984 .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
4985 },
4986 {
4987 .name = MSM_DAILINK_NAME(MultiMedia10),
4988 .stream_name = "MultiMedia10",
4989 .cpu_dai_name = "MultiMedia10",
4990 .platform_name = "msm-pcm-dsp.1",
4991 .dynamic = 1,
4992 .dpcm_playback = 1,
4993 .dpcm_capture = 1,
4994 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
4995 SND_SOC_DPCM_TRIGGER_POST},
4996 .codec_dai_name = "snd-soc-dummy-dai",
4997 .codec_name = "snd-soc-dummy",
4998 .ignore_suspend = 1,
4999 .ignore_pmdown_time = 1,
5000 /* this dainlink has playback support */
5001 .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
5002 },
5003 {
5004 .name = MSM_DAILINK_NAME(ULL_NOIRQ),
5005 .stream_name = "MM_NOIRQ",
5006 .cpu_dai_name = "MultiMedia8",
5007 .platform_name = "msm-pcm-dsp-noirq",
5008 .dynamic = 1,
5009 .dpcm_playback = 1,
5010 .dpcm_capture = 1,
5011 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5012 SND_SOC_DPCM_TRIGGER_POST},
5013 .codec_dai_name = "snd-soc-dummy-dai",
5014 .codec_name = "snd-soc-dummy",
5015 .ignore_suspend = 1,
5016 .ignore_pmdown_time = 1,
5017 /* this dainlink has playback support */
5018 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5019 .ops = &msm_fe_qos_ops,
5020 },
5021 /* HDMI Hostless */
5022 {
5023 .name = "HDMI_RX_HOSTLESS",
5024 .stream_name = "HDMI_RX_HOSTLESS",
5025 .cpu_dai_name = "HDMI_HOSTLESS",
5026 .platform_name = "msm-pcm-hostless",
5027 .dynamic = 1,
5028 .dpcm_playback = 1,
5029 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5030 SND_SOC_DPCM_TRIGGER_POST},
5031 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5032 .ignore_suspend = 1,
5033 .ignore_pmdown_time = 1,
5034 .codec_dai_name = "snd-soc-dummy-dai",
5035 .codec_name = "snd-soc-dummy",
5036 },
5037 {
5038 .name = "VoiceMMode2",
5039 .stream_name = "VoiceMMode2",
5040 .cpu_dai_name = "VoiceMMode2",
5041 .platform_name = "msm-pcm-voice",
5042 .dynamic = 1,
5043 .dpcm_playback = 1,
5044 .dpcm_capture = 1,
5045 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5046 SND_SOC_DPCM_TRIGGER_POST},
5047 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5048 .ignore_suspend = 1,
5049 .ignore_pmdown_time = 1,
5050 .codec_dai_name = "snd-soc-dummy-dai",
5051 .codec_name = "snd-soc-dummy",
5052 .id = MSM_FRONTEND_DAI_VOICEMMODE2,
5053 },
5054 /* LSM FE */
5055 {
5056 .name = "Listen 2 Audio Service",
5057 .stream_name = "Listen 2 Audio Service",
5058 .cpu_dai_name = "LSM2",
5059 .platform_name = "msm-lsm-client",
5060 .dynamic = 1,
5061 .dpcm_capture = 1,
5062 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5063 SND_SOC_DPCM_TRIGGER_POST },
5064 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5065 .ignore_suspend = 1,
5066 .codec_dai_name = "snd-soc-dummy-dai",
5067 .codec_name = "snd-soc-dummy",
5068 .id = MSM_FRONTEND_DAI_LSM2,
5069 },
5070 {
5071 .name = "Listen 3 Audio Service",
5072 .stream_name = "Listen 3 Audio Service",
5073 .cpu_dai_name = "LSM3",
5074 .platform_name = "msm-lsm-client",
5075 .dynamic = 1,
5076 .dpcm_capture = 1,
5077 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5078 SND_SOC_DPCM_TRIGGER_POST },
5079 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5080 .ignore_suspend = 1,
5081 .codec_dai_name = "snd-soc-dummy-dai",
5082 .codec_name = "snd-soc-dummy",
5083 .id = MSM_FRONTEND_DAI_LSM3,
5084 },
5085 {
5086 .name = "Listen 4 Audio Service",
5087 .stream_name = "Listen 4 Audio Service",
5088 .cpu_dai_name = "LSM4",
5089 .platform_name = "msm-lsm-client",
5090 .dynamic = 1,
5091 .dpcm_capture = 1,
5092 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5093 SND_SOC_DPCM_TRIGGER_POST },
5094 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5095 .ignore_suspend = 1,
5096 .codec_dai_name = "snd-soc-dummy-dai",
5097 .codec_name = "snd-soc-dummy",
5098 .id = MSM_FRONTEND_DAI_LSM4,
5099 },
5100 {
5101 .name = "Listen 5 Audio Service",
5102 .stream_name = "Listen 5 Audio Service",
5103 .cpu_dai_name = "LSM5",
5104 .platform_name = "msm-lsm-client",
5105 .dynamic = 1,
5106 .dpcm_capture = 1,
5107 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5108 SND_SOC_DPCM_TRIGGER_POST },
5109 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5110 .ignore_suspend = 1,
5111 .codec_dai_name = "snd-soc-dummy-dai",
5112 .codec_name = "snd-soc-dummy",
5113 .id = MSM_FRONTEND_DAI_LSM5,
5114 },
5115 {
5116 .name = "Listen 6 Audio Service",
5117 .stream_name = "Listen 6 Audio Service",
5118 .cpu_dai_name = "LSM6",
5119 .platform_name = "msm-lsm-client",
5120 .dynamic = 1,
5121 .dpcm_capture = 1,
5122 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5123 SND_SOC_DPCM_TRIGGER_POST },
5124 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5125 .ignore_suspend = 1,
5126 .codec_dai_name = "snd-soc-dummy-dai",
5127 .codec_name = "snd-soc-dummy",
5128 .id = MSM_FRONTEND_DAI_LSM6,
5129 },
5130 {
5131 .name = "Listen 7 Audio Service",
5132 .stream_name = "Listen 7 Audio Service",
5133 .cpu_dai_name = "LSM7",
5134 .platform_name = "msm-lsm-client",
5135 .dynamic = 1,
5136 .dpcm_capture = 1,
5137 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5138 SND_SOC_DPCM_TRIGGER_POST },
5139 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5140 .ignore_suspend = 1,
5141 .codec_dai_name = "snd-soc-dummy-dai",
5142 .codec_name = "snd-soc-dummy",
5143 .id = MSM_FRONTEND_DAI_LSM7,
5144 },
5145 {
5146 .name = "Listen 8 Audio Service",
5147 .stream_name = "Listen 8 Audio Service",
5148 .cpu_dai_name = "LSM8",
5149 .platform_name = "msm-lsm-client",
5150 .dynamic = 1,
5151 .dpcm_capture = 1,
5152 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
5153 SND_SOC_DPCM_TRIGGER_POST },
5154 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5155 .ignore_suspend = 1,
5156 .codec_dai_name = "snd-soc-dummy-dai",
5157 .codec_name = "snd-soc-dummy",
5158 .id = MSM_FRONTEND_DAI_LSM8,
5159 },
5160 /* - Multimedia9 */
5161 {
5162 .name = MSM_DAILINK_NAME(Compress4),
5163 .stream_name = "Compress4",
5164 .cpu_dai_name = "MultiMedia11",
5165 .platform_name = "msm-compress-dsp",
5166 .dynamic = 1,
5167 .dpcm_playback = 1,
5168 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5169 SND_SOC_DPCM_TRIGGER_POST},
5170 .codec_dai_name = "snd-soc-dummy-dai",
5171 .codec_name = "snd-soc-dummy",
5172 .ignore_suspend = 1,
5173 .ignore_pmdown_time = 1,
5174 /* this dainlink has playback support */
5175 .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
5176 },
5177 {
5178 .name = MSM_DAILINK_NAME(Compress5),
5179 .stream_name = "Compress5",
5180 .cpu_dai_name = "MultiMedia12",
5181 .platform_name = "msm-compress-dsp",
5182 .dynamic = 1,
5183 .dpcm_playback = 1,
5184 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5185 SND_SOC_DPCM_TRIGGER_POST},
5186 .codec_dai_name = "snd-soc-dummy-dai",
5187 .codec_name = "snd-soc-dummy",
5188 .ignore_suspend = 1,
5189 .ignore_pmdown_time = 1,
5190 /* this dainlink has playback support */
5191 .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
5192 },
5193 {
5194 .name = MSM_DAILINK_NAME(Compress6),
5195 .stream_name = "Compress6",
5196 .cpu_dai_name = "MultiMedia13",
5197 .platform_name = "msm-compress-dsp",
5198 .dynamic = 1,
5199 .dpcm_playback = 1,
5200 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5201 SND_SOC_DPCM_TRIGGER_POST},
5202 .codec_dai_name = "snd-soc-dummy-dai",
5203 .codec_name = "snd-soc-dummy",
5204 .ignore_suspend = 1,
5205 .ignore_pmdown_time = 1,
5206 /* this dainlink has playback support */
5207 .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
5208 },
5209 {
5210 .name = MSM_DAILINK_NAME(Compress7),
5211 .stream_name = "Compress7",
5212 .cpu_dai_name = "MultiMedia14",
5213 .platform_name = "msm-compress-dsp",
5214 .dynamic = 1,
5215 .dpcm_playback = 1,
5216 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5217 SND_SOC_DPCM_TRIGGER_POST},
5218 .codec_dai_name = "snd-soc-dummy-dai",
5219 .codec_name = "snd-soc-dummy",
5220 .ignore_suspend = 1,
5221 .ignore_pmdown_time = 1,
5222 /* this dainlink has playback support */
5223 .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
5224 },
5225 {
5226 .name = MSM_DAILINK_NAME(Compress8),
5227 .stream_name = "Compress8",
5228 .cpu_dai_name = "MultiMedia15",
5229 .platform_name = "msm-compress-dsp",
5230 .dynamic = 1,
5231 .dpcm_playback = 1,
5232 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5233 SND_SOC_DPCM_TRIGGER_POST},
5234 .codec_dai_name = "snd-soc-dummy-dai",
5235 .codec_name = "snd-soc-dummy",
5236 .ignore_suspend = 1,
5237 .ignore_pmdown_time = 1,
5238 /* this dainlink has playback support */
5239 .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
5240 },
5241 {
5242 .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
5243 .stream_name = "MM_NOIRQ_2",
5244 .cpu_dai_name = "MultiMedia16",
5245 .platform_name = "msm-pcm-dsp-noirq",
5246 .dynamic = 1,
5247 .dpcm_playback = 1,
5248 .dpcm_capture = 1,
5249 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5250 SND_SOC_DPCM_TRIGGER_POST},
5251 .codec_dai_name = "snd-soc-dummy-dai",
5252 .codec_name = "snd-soc-dummy",
5253 .ignore_suspend = 1,
5254 .ignore_pmdown_time = 1,
5255 /* this dainlink has playback support */
5256 .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
5257 },
5258 /* - SLIMBUS_8 Hostless */
5259 /* - Slimbus4 Capture */
5260 /* - SLIMBUS_2 Hostless Playback */
5261 /* - SLIMBUS_2 Hostless Capture */
5262 /* HFP TX */
5263 {
5264 .name = MSM_DAILINK_NAME(ASM Loopback),
5265 .stream_name = "MultiMedia6",
5266 .cpu_dai_name = "MultiMedia6",
5267 .platform_name = "msm-pcm-loopback",
5268 .dynamic = 1,
5269 .dpcm_playback = 1,
5270 .dpcm_capture = 1,
5271 .codec_dai_name = "snd-soc-dummy-dai",
5272 .codec_name = "snd-soc-dummy",
5273 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5274 SND_SOC_DPCM_TRIGGER_POST},
5275 .ignore_suspend = 1,
5276 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5277 .ignore_pmdown_time = 1,
5278 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5279 },
5280 {
5281 .name = "USB Audio Hostless",
5282 .stream_name = "USB Audio Hostless",
5283 .cpu_dai_name = "USBAUDIO_HOSTLESS",
5284 .platform_name = "msm-pcm-hostless",
5285 .dynamic = 1,
5286 .dpcm_playback = 1,
5287 .dpcm_capture = 1,
5288 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5289 SND_SOC_DPCM_TRIGGER_POST},
5290 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5291 .ignore_suspend = 1,
5292 .ignore_pmdown_time = 1,
5293 .codec_dai_name = "snd-soc-dummy-dai",
5294 .codec_name = "snd-soc-dummy",
5295 },
5296 /* - SLIMBUS_7 Hostless */
5297 {
5298 .name = "Compress Capture",
5299 .stream_name = "Compress9",
5300 .cpu_dai_name = "MultiMedia17",
5301 .platform_name = "msm-compress-dsp",
5302 .dynamic = 1,
5303 .dpcm_capture = 1,
5304 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5305 SND_SOC_DPCM_TRIGGER_POST},
5306 .codec_dai_name = "snd-soc-dummy-dai",
5307 .codec_name = "snd-soc-dummy",
5308 .ignore_suspend = 1,
5309 .ignore_pmdown_time = 1,
5310 .id = MSM_FRONTEND_DAI_MULTIMEDIA17,
5311 },
5312};
5313
5314static struct snd_soc_dai_link msm_auto_fe_dai_links[] = {
5315 {
5316 .name = "INT_HFP_BT Hostless",
5317 .stream_name = "INT_HFP_BT Hostless",
5318 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5319 .platform_name = "msm-pcm-hostless",
5320 .dynamic = 1,
5321 .dpcm_playback = 1,
5322 .dpcm_capture = 1,
5323 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5324 SND_SOC_DPCM_TRIGGER_POST},
5325 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5326 .ignore_suspend = 1,
5327 /* this dainlink has playback support */
5328 .ignore_pmdown_time = 1,
5329 .codec_dai_name = "snd-soc-dummy-dai",
5330 .codec_name = "snd-soc-dummy",
5331 },
5332 /* Low latency ASM loopback for ICC */
5333 {
5334 .name = MSM_DAILINK_NAME(LowLatency Loopback),
5335 .stream_name = "MultiMedia9",
5336 .cpu_dai_name = "MultiMedia9",
5337 .platform_name = "msm-pcm-loopback.1",
5338 .dynamic = 1,
5339 .dpcm_playback = 1,
5340 .dpcm_capture = 1,
5341 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5342 SND_SOC_DPCM_TRIGGER_POST},
5343 .codec_dai_name = "snd-soc-dummy-dai",
5344 .codec_name = "snd-soc-dummy",
5345 .ignore_suspend = 1,
5346 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5347 /* this dainlink has playback support */
5348 .ignore_pmdown_time = 1,
5349 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5350 },
5351 {
5352 .name = "Tertiary MI2S TX_Hostless",
5353 .stream_name = "Tertiary MI2S_TX Hostless Capture",
5354 .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS",
5355 .platform_name = "msm-pcm-hostless",
5356 .dynamic = 1,
5357 .dpcm_capture = 1,
5358 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5359 SND_SOC_DPCM_TRIGGER_POST},
5360 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5361 .ignore_suspend = 1,
5362 .ignore_pmdown_time = 1,
5363 .codec_dai_name = "snd-soc-dummy-dai",
5364 .codec_name = "snd-soc-dummy",
5365 },
5366 {
5367 .name = MSM_DAILINK_NAME(Media20),
5368 .stream_name = "MultiMedia20",
5369 .cpu_dai_name = "MultiMedia20",
5370 .platform_name = "msm-pcm-loopback",
5371 .dynamic = 1,
5372 .dpcm_playback = 1,
5373 .dpcm_capture = 1,
5374 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5375 SND_SOC_DPCM_TRIGGER_POST},
5376 .codec_dai_name = "snd-soc-dummy-dai",
5377 .codec_name = "snd-soc-dummy",
5378 .ignore_suspend = 1,
5379 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5380 /* this dainlink has playback support */
5381 .ignore_pmdown_time = 1,
5382 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5383 },
5384 {
5385 .name = MSM_DAILINK_NAME(HFP RX),
5386 .stream_name = "MultiMedia21",
5387 .cpu_dai_name = "MultiMedia21",
5388 .platform_name = "msm-pcm-loopback",
5389 .dynamic = 1,
5390 .dpcm_playback = 1,
5391 .dpcm_capture = 1,
5392 .codec_dai_name = "snd-soc-dummy-dai",
5393 .codec_name = "snd-soc-dummy",
5394 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5395 SND_SOC_DPCM_TRIGGER_POST},
5396 .ignore_suspend = 1,
5397 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5398 .ignore_pmdown_time = 1,
5399 .id = MSM_FRONTEND_DAI_MULTIMEDIA21,
5400 },
5401 /* TDM Hostless */
5402 {
5403 .name = "Primary TDM RX 0 Hostless",
5404 .stream_name = "Primary TDM RX 0 Hostless",
5405 .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS",
5406 .platform_name = "msm-pcm-hostless",
5407 .dynamic = 1,
5408 .dpcm_playback = 1,
5409 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5410 SND_SOC_DPCM_TRIGGER_POST},
5411 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5412 .ignore_suspend = 1,
5413 .ignore_pmdown_time = 1,
5414 .codec_dai_name = "snd-soc-dummy-dai",
5415 .codec_name = "snd-soc-dummy",
5416 },
5417 {
5418 .name = "Primary TDM TX 0 Hostless",
5419 .stream_name = "Primary TDM TX 0 Hostless",
5420 .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS",
5421 .platform_name = "msm-pcm-hostless",
5422 .dynamic = 1,
5423 .dpcm_capture = 1,
5424 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5425 SND_SOC_DPCM_TRIGGER_POST},
5426 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5427 .ignore_suspend = 1,
5428 .ignore_pmdown_time = 1,
5429 .codec_dai_name = "snd-soc-dummy-dai",
5430 .codec_name = "snd-soc-dummy",
5431 },
5432 {
5433 .name = "Secondary TDM RX 0 Hostless",
5434 .stream_name = "Secondary TDM RX 0 Hostless",
5435 .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS",
5436 .platform_name = "msm-pcm-hostless",
5437 .dynamic = 1,
5438 .dpcm_playback = 1,
5439 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5440 SND_SOC_DPCM_TRIGGER_POST},
5441 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5442 .ignore_suspend = 1,
5443 .ignore_pmdown_time = 1,
5444 .codec_dai_name = "snd-soc-dummy-dai",
5445 .codec_name = "snd-soc-dummy",
5446 },
5447 {
5448 .name = "Secondary TDM TX 0 Hostless",
5449 .stream_name = "Secondary TDM TX 0 Hostless",
5450 .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS",
5451 .platform_name = "msm-pcm-hostless",
5452 .dynamic = 1,
5453 .dpcm_capture = 1,
5454 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5455 SND_SOC_DPCM_TRIGGER_POST},
5456 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5457 .ignore_suspend = 1,
5458 .ignore_pmdown_time = 1,
5459 .codec_dai_name = "snd-soc-dummy-dai",
5460 .codec_name = "snd-soc-dummy",
5461 },
5462 {
5463 .name = "Tertiary TDM RX 0 Hostless",
5464 .stream_name = "Tertiary TDM RX 0 Hostless",
5465 .cpu_dai_name = "TERT_TDM_RX_0_HOSTLESS",
5466 .platform_name = "msm-pcm-hostless",
5467 .dynamic = 1,
5468 .dpcm_playback = 1,
5469 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5470 SND_SOC_DPCM_TRIGGER_POST},
5471 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5472 .ignore_suspend = 1,
5473 .ignore_pmdown_time = 1,
5474 .codec_dai_name = "snd-soc-dummy-dai",
5475 .codec_name = "snd-soc-dummy",
5476 },
5477 {
5478 .name = "Tertiary TDM TX 0 Hostless",
5479 .stream_name = "Tertiary TDM TX 0 Hostless",
5480 .cpu_dai_name = "TERT_TDM_TX_0_HOSTLESS",
5481 .platform_name = "msm-pcm-hostless",
5482 .dynamic = 1,
5483 .dpcm_capture = 1,
5484 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5485 SND_SOC_DPCM_TRIGGER_POST},
5486 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5487 .ignore_suspend = 1,
5488 .ignore_pmdown_time = 1,
5489 .codec_dai_name = "snd-soc-dummy-dai",
5490 .codec_name = "snd-soc-dummy",
5491 },
5492 {
5493 .name = "Quaternary TDM RX 0 Hostless",
5494 .stream_name = "Quaternary TDM RX 0 Hostless",
5495 .cpu_dai_name = "QUAT_TDM_RX_0_HOSTLESS",
5496 .platform_name = "msm-pcm-hostless",
5497 .dynamic = 1,
5498 .dpcm_playback = 1,
5499 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5500 SND_SOC_DPCM_TRIGGER_POST},
5501 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5502 .ignore_suspend = 1,
5503 .ignore_pmdown_time = 1,
5504 .codec_dai_name = "snd-soc-dummy-dai",
5505 .codec_name = "snd-soc-dummy",
5506 },
5507 {
5508 .name = "Quaternary TDM TX 0 Hostless",
5509 .stream_name = "Quaternary TDM TX 0 Hostless",
5510 .cpu_dai_name = "QUAT_TDM_TX_0_HOSTLESS",
5511 .platform_name = "msm-pcm-hostless",
5512 .dynamic = 1,
5513 .dpcm_capture = 1,
5514 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5515 SND_SOC_DPCM_TRIGGER_POST},
5516 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5517 .ignore_suspend = 1,
5518 .ignore_pmdown_time = 1,
5519 .codec_dai_name = "snd-soc-dummy-dai",
5520 .codec_name = "snd-soc-dummy",
5521 },
5522 {
5523 .name = "Quaternary MI2S_RX Hostless Playback",
5524 .stream_name = "Quaternary MI2S_RX Hostless Playback",
5525 .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS",
5526 .platform_name = "msm-pcm-hostless",
5527 .dynamic = 1,
5528 .dpcm_playback = 1,
5529 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5530 SND_SOC_DPCM_TRIGGER_POST},
5531 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5532 .ignore_suspend = 1,
5533 .ignore_pmdown_time = 1,
5534 .codec_dai_name = "snd-soc-dummy-dai",
5535 .codec_name = "snd-soc-dummy",
5536 },
5537 {
5538 .name = "Secondary MI2S_TX Hostless Capture",
5539 .stream_name = "Secondary MI2S_TX Hostless Capture",
5540 .cpu_dai_name = "SEC_MI2S_TX_HOSTLESS",
5541 .platform_name = "msm-pcm-hostless",
5542 .dynamic = 1,
5543 .dpcm_capture = 1,
5544 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5545 SND_SOC_DPCM_TRIGGER_POST},
5546 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5547 .ignore_suspend = 1,
5548 .ignore_pmdown_time = 1,
5549 .codec_dai_name = "snd-soc-dummy-dai",
5550 .codec_name = "snd-soc-dummy",
5551 },
5552 {
5553 .name = "DTMF RX Hostless",
5554 .stream_name = "DTMF RX Hostless",
5555 .cpu_dai_name = "DTMF_RX_HOSTLESS",
5556 .platform_name = "msm-pcm-dtmf",
5557 .dynamic = 1,
5558 .dpcm_playback = 1,
5559 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5560 SND_SOC_DPCM_TRIGGER_POST},
5561 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5562 .ignore_suspend = 1,
5563 .ignore_pmdown_time = 1,
5564 .codec_dai_name = "snd-soc-dummy-dai",
5565 .codec_name = "snd-soc-dummy",
5566 .id = MSM_FRONTEND_DAI_DTMF_RX,
5567 }
5568};
5569
5570static struct snd_soc_dai_link msm_custom_fe_dai_links[] = {
5571 /* FrontEnd DAI Links */
5572 {
5573 .name = MSM_DAILINK_NAME(Media1),
5574 .stream_name = "MultiMedia1",
5575 .cpu_dai_name = "MultiMedia1",
5576 .platform_name = "msm-pcm-dsp.1",
5577 .dynamic = 1,
5578 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5579 .dpcm_playback = 1,
5580 .dpcm_capture = 1,
5581 .codec_dai_name = "snd-soc-dummy-dai",
5582 .codec_name = "snd-soc-dummy",
5583 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5584 SND_SOC_DPCM_TRIGGER_POST},
5585 .ignore_suspend = 1,
5586 /* this dainlink has playback support */
5587 .ignore_pmdown_time = 1,
5588 .id = MSM_FRONTEND_DAI_MULTIMEDIA1,
5589 .ops = &msm_fe_qos_ops,
5590 },
5591 {
5592 .name = MSM_DAILINK_NAME(Media2),
5593 .stream_name = "MultiMedia2",
5594 .cpu_dai_name = "MultiMedia2",
5595 .platform_name = "msm-pcm-dsp.1",
5596 .dynamic = 1,
5597 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5598 .dpcm_playback = 1,
5599 .dpcm_capture = 1,
5600 .codec_dai_name = "snd-soc-dummy-dai",
5601 .codec_name = "snd-soc-dummy",
5602 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5603 SND_SOC_DPCM_TRIGGER_POST},
5604 .ignore_suspend = 1,
5605 /* this dainlink has playback support */
5606 .ignore_pmdown_time = 1,
5607 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5608 .ops = &msm_fe_qos_ops,
5609 },
5610 {
5611 .name = MSM_DAILINK_NAME(Media3),
5612 .stream_name = "MultiMedia3",
5613 .cpu_dai_name = "MultiMedia3",
5614 .platform_name = "msm-pcm-dsp.1",
5615 .dynamic = 1,
5616 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5617 .dpcm_playback = 1,
5618 .dpcm_capture = 1,
5619 .codec_dai_name = "snd-soc-dummy-dai",
5620 .codec_name = "snd-soc-dummy",
5621 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5622 SND_SOC_DPCM_TRIGGER_POST},
5623 .ignore_suspend = 1,
5624 /* this dainlink has playback support */
5625 .ignore_pmdown_time = 1,
5626 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5627 .ops = &msm_fe_qos_ops,
5628 },
5629 {
5630 .name = MSM_DAILINK_NAME(Media5),
5631 .stream_name = "MultiMedia5",
5632 .cpu_dai_name = "MultiMedia5",
5633 .platform_name = "msm-pcm-dsp.1",
5634 .dynamic = 1,
5635 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5636 .dpcm_playback = 1,
5637 .dpcm_capture = 1,
5638 .codec_dai_name = "snd-soc-dummy-dai",
5639 .codec_name = "snd-soc-dummy",
5640 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5641 SND_SOC_DPCM_TRIGGER_POST},
5642 .ignore_suspend = 1,
5643 /* this dainlink has playback support */
5644 .ignore_pmdown_time = 1,
5645 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
5646 .ops = &msm_fe_qos_ops,
5647 },
5648 {
5649 .name = MSM_DAILINK_NAME(Media6),
5650 .stream_name = "MultiMedia6",
5651 .cpu_dai_name = "MultiMedia6",
5652 .platform_name = "msm-pcm-dsp.1",
5653 .dynamic = 1,
5654 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5655 .dpcm_playback = 1,
5656 .dpcm_capture = 1,
5657 .codec_dai_name = "snd-soc-dummy-dai",
5658 .codec_name = "snd-soc-dummy",
5659 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5660 SND_SOC_DPCM_TRIGGER_POST},
5661 .ignore_suspend = 1,
5662 /* this dainlink has playback support */
5663 .ignore_pmdown_time = 1,
5664 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
5665 .ops = &msm_fe_qos_ops,
5666 },
5667 {
5668 .name = MSM_DAILINK_NAME(Media8),
5669 .stream_name = "MultiMedia8",
5670 .cpu_dai_name = "MultiMedia8",
5671 .platform_name = "msm-pcm-dsp.1",
5672 .dynamic = 1,
5673 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5674 .dpcm_playback = 1,
5675 .dpcm_capture = 1,
5676 .codec_dai_name = "snd-soc-dummy-dai",
5677 .codec_name = "snd-soc-dummy",
5678 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5679 SND_SOC_DPCM_TRIGGER_POST},
5680 .ignore_suspend = 1,
5681 /* this dainlink has playback support */
5682 .ignore_pmdown_time = 1,
5683 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
5684 .ops = &msm_fe_qos_ops,
5685 },
5686 {
5687 .name = MSM_DAILINK_NAME(Media9),
5688 .stream_name = "MultiMedia9",
5689 .cpu_dai_name = "MultiMedia9",
5690 .platform_name = "msm-pcm-dsp.1",
5691 .dynamic = 1,
5692 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5693 .dpcm_playback = 1,
5694 .dpcm_capture = 1,
5695 .codec_dai_name = "snd-soc-dummy-dai",
5696 .codec_name = "snd-soc-dummy",
5697 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5698 SND_SOC_DPCM_TRIGGER_POST},
5699 .ignore_suspend = 1,
5700 /* this dainlink has playback support */
5701 .ignore_pmdown_time = 1,
5702 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
5703 .ops = &msm_fe_qos_ops,
5704 },
5705 {
5706 .name = "INT_HFP_BT Hostless",
5707 .stream_name = "INT_HFP_BT Hostless",
5708 .cpu_dai_name = "INT_HFP_BT_HOSTLESS",
5709 .platform_name = "msm-pcm-hostless",
5710 .dynamic = 1,
5711 .dpcm_playback = 1,
5712 .dpcm_capture = 1,
5713 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5714 SND_SOC_DPCM_TRIGGER_POST},
5715 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5716 .ignore_suspend = 1,
5717 /* this dainlink has playback support */
5718 .ignore_pmdown_time = 1,
5719 .codec_dai_name = "snd-soc-dummy-dai",
5720 .codec_name = "snd-soc-dummy",
5721 },
5722 {
5723 .name = "AUXPCM Hostless",
5724 .stream_name = "AUXPCM Hostless",
5725 .cpu_dai_name = "AUXPCM_HOSTLESS",
5726 .platform_name = "msm-pcm-hostless",
5727 .dynamic = 1,
5728 .dpcm_playback = 1,
5729 .dpcm_capture = 1,
5730 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5731 SND_SOC_DPCM_TRIGGER_POST},
5732 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5733 .ignore_suspend = 1,
5734 /* this dainlink has playback support */
5735 .ignore_pmdown_time = 1,
5736 .codec_dai_name = "snd-soc-dummy-dai",
5737 .codec_name = "snd-soc-dummy",
5738 },
5739 {
5740 .name = MSM_DAILINK_NAME(Media20),
5741 .stream_name = "MultiMedia20",
5742 .cpu_dai_name = "MultiMedia20",
5743 .platform_name = "msm-pcm-loopback",
5744 .dynamic = 1,
5745 .dpcm_playback = 1,
5746 .dpcm_capture = 1,
5747 .codec_dai_name = "snd-soc-dummy-dai",
5748 .codec_name = "snd-soc-dummy",
5749 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5750 SND_SOC_DPCM_TRIGGER_POST},
5751 .ignore_suspend = 1,
5752 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5753 /* this dainlink has playback support */
5754 .ignore_pmdown_time = 1,
5755 .id = MSM_FRONTEND_DAI_MULTIMEDIA20,
5756 },
5757};
5758
5759static struct snd_soc_dai_link msm_common_be_dai_links[] = {
5760 /* Backend AFE DAI Links */
5761 {
5762 .name = LPASS_BE_AFE_PCM_RX,
5763 .stream_name = "AFE Playback",
5764 .cpu_dai_name = "msm-dai-q6-dev.224",
5765 .platform_name = "msm-pcm-routing",
5766 .codec_name = "msm-stub-codec.1",
5767 .codec_dai_name = "msm-stub-rx",
5768 .no_pcm = 1,
5769 .dpcm_playback = 1,
5770 .id = MSM_BACKEND_DAI_AFE_PCM_RX,
5771 .be_hw_params_fixup = msm_be_hw_params_fixup,
5772 /* this dainlink has playback support */
5773 .ignore_pmdown_time = 1,
5774 .ignore_suspend = 1,
5775 },
5776 {
5777 .name = LPASS_BE_AFE_PCM_TX,
5778 .stream_name = "AFE Capture",
5779 .cpu_dai_name = "msm-dai-q6-dev.225",
5780 .platform_name = "msm-pcm-routing",
5781 .codec_name = "msm-stub-codec.1",
5782 .codec_dai_name = "msm-stub-tx",
5783 .no_pcm = 1,
5784 .dpcm_capture = 1,
5785 .id = MSM_BACKEND_DAI_AFE_PCM_TX,
5786 .be_hw_params_fixup = msm_be_hw_params_fixup,
5787 .ignore_suspend = 1,
5788 },
5789 /* Incall Record Uplink BACK END DAI Link */
5790 {
5791 .name = LPASS_BE_INCALL_RECORD_TX,
5792 .stream_name = "Voice Uplink Capture",
5793 .cpu_dai_name = "msm-dai-q6-dev.32772",
5794 .platform_name = "msm-pcm-routing",
5795 .codec_name = "msm-stub-codec.1",
5796 .codec_dai_name = "msm-stub-tx",
5797 .no_pcm = 1,
5798 .dpcm_capture = 1,
5799 .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
5800 .be_hw_params_fixup = msm_be_hw_params_fixup,
5801 .ignore_suspend = 1,
5802 },
5803 /* Incall Record Downlink BACK END DAI Link */
5804 {
5805 .name = LPASS_BE_INCALL_RECORD_RX,
5806 .stream_name = "Voice Downlink Capture",
5807 .cpu_dai_name = "msm-dai-q6-dev.32771",
5808 .platform_name = "msm-pcm-routing",
5809 .codec_name = "msm-stub-codec.1",
5810 .codec_dai_name = "msm-stub-tx",
5811 .no_pcm = 1,
5812 .dpcm_capture = 1,
5813 .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
5814 .be_hw_params_fixup = msm_be_hw_params_fixup,
5815 .ignore_suspend = 1,
5816 },
5817 /* Incall Music BACK END DAI Link */
5818 {
5819 .name = LPASS_BE_VOICE_PLAYBACK_TX,
5820 .stream_name = "Voice Farend Playback",
5821 .cpu_dai_name = "msm-dai-q6-dev.32773",
5822 .platform_name = "msm-pcm-routing",
5823 .codec_name = "msm-stub-codec.1",
5824 .codec_dai_name = "msm-stub-rx",
5825 .no_pcm = 1,
5826 .dpcm_playback = 1,
5827 .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
5828 .be_hw_params_fixup = msm_be_hw_params_fixup,
5829 .ignore_suspend = 1,
5830 .ignore_pmdown_time = 1,
5831 },
5832 /* Incall Music 2 BACK END DAI Link */
5833 {
5834 .name = LPASS_BE_VOICE2_PLAYBACK_TX,
5835 .stream_name = "Voice2 Farend Playback",
5836 .cpu_dai_name = "msm-dai-q6-dev.32770",
5837 .platform_name = "msm-pcm-routing",
5838 .codec_name = "msm-stub-codec.1",
5839 .codec_dai_name = "msm-stub-rx",
5840 .no_pcm = 1,
5841 .dpcm_playback = 1,
5842 .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
5843 .be_hw_params_fixup = msm_be_hw_params_fixup,
5844 .ignore_suspend = 1,
5845 .ignore_pmdown_time = 1,
5846 },
5847 {
5848 .name = LPASS_BE_USB_AUDIO_RX,
5849 .stream_name = "USB Audio Playback",
5850 .cpu_dai_name = "msm-dai-q6-dev.28672",
5851 .platform_name = "msm-pcm-routing",
5852 .codec_name = "msm-stub-codec.1",
5853 .codec_dai_name = "msm-stub-rx",
5854 .no_pcm = 1,
5855 .dpcm_playback = 1,
5856 .id = MSM_BACKEND_DAI_USB_RX,
5857 .be_hw_params_fixup = msm_be_hw_params_fixup,
5858 .ignore_pmdown_time = 1,
5859 .ignore_suspend = 1,
5860 },
5861 {
5862 .name = LPASS_BE_USB_AUDIO_TX,
5863 .stream_name = "USB Audio Capture",
5864 .cpu_dai_name = "msm-dai-q6-dev.28673",
5865 .platform_name = "msm-pcm-routing",
5866 .codec_name = "msm-stub-codec.1",
5867 .codec_dai_name = "msm-stub-tx",
5868 .no_pcm = 1,
5869 .dpcm_capture = 1,
5870 .id = MSM_BACKEND_DAI_USB_TX,
5871 .be_hw_params_fixup = msm_be_hw_params_fixup,
5872 .ignore_suspend = 1,
5873 },
5874 {
5875 .name = LPASS_BE_PRI_TDM_RX_0,
5876 .stream_name = "Primary TDM0 Playback",
5877 .cpu_dai_name = "msm-dai-q6-tdm.36864",
5878 .platform_name = "msm-pcm-routing",
5879 .codec_name = "msm-stub-codec.1",
5880 .codec_dai_name = "msm-stub-rx",
5881 .no_pcm = 1,
5882 .dpcm_playback = 1,
5883 .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
5884 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5885 .ops = &sa6155_tdm_be_ops,
5886 .ignore_suspend = 1,
5887 .ignore_pmdown_time = 1,
5888 },
5889 {
5890 .name = LPASS_BE_PRI_TDM_TX_0,
5891 .stream_name = "Primary TDM0 Capture",
5892 .cpu_dai_name = "msm-dai-q6-tdm.36865",
5893 .platform_name = "msm-pcm-routing",
5894 .codec_name = "msm-stub-codec.1",
5895 .codec_dai_name = "msm-stub-tx",
5896 .no_pcm = 1,
5897 .dpcm_capture = 1,
5898 .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
5899 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5900 .ops = &sa6155_tdm_be_ops,
5901 .ignore_suspend = 1,
5902 },
5903 {
5904 .name = LPASS_BE_SEC_TDM_RX_0,
5905 .stream_name = "Secondary TDM0 Playback",
5906 .cpu_dai_name = "msm-dai-q6-tdm.36880",
5907 .platform_name = "msm-pcm-routing",
5908 .codec_name = "msm-stub-codec.1",
5909 .codec_dai_name = "msm-stub-rx",
5910 .no_pcm = 1,
5911 .dpcm_playback = 1,
5912 .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
5913 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5914 .ops = &sa6155_tdm_be_ops,
5915 .ignore_suspend = 1,
5916 .ignore_pmdown_time = 1,
5917 },
5918 {
5919 .name = LPASS_BE_SEC_TDM_TX_0,
5920 .stream_name = "Secondary TDM0 Capture",
5921 .cpu_dai_name = "msm-dai-q6-tdm.36881",
5922 .platform_name = "msm-pcm-routing",
5923 .codec_name = "msm-stub-codec.1",
5924 .codec_dai_name = "msm-stub-tx",
5925 .no_pcm = 1,
5926 .dpcm_capture = 1,
5927 .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
5928 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5929 .ops = &sa6155_tdm_be_ops,
5930 .ignore_suspend = 1,
5931 },
5932 {
5933 .name = LPASS_BE_TERT_TDM_RX_0,
5934 .stream_name = "Tertiary TDM0 Playback",
5935 .cpu_dai_name = "msm-dai-q6-tdm.36896",
5936 .platform_name = "msm-pcm-routing",
5937 .codec_name = "msm-stub-codec.1",
5938 .codec_dai_name = "msm-stub-rx",
5939 .no_pcm = 1,
5940 .dpcm_playback = 1,
5941 .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
5942 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5943 .ops = &sa6155_tdm_be_ops,
5944 .ignore_suspend = 1,
5945 .ignore_pmdown_time = 1,
5946 },
5947 {
5948 .name = LPASS_BE_TERT_TDM_TX_0,
5949 .stream_name = "Tertiary TDM0 Capture",
5950 .cpu_dai_name = "msm-dai-q6-tdm.36897",
5951 .platform_name = "msm-pcm-routing",
5952 .codec_name = "msm-stub-codec.1",
5953 .codec_dai_name = "msm-stub-tx",
5954 .no_pcm = 1,
5955 .dpcm_capture = 1,
5956 .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
5957 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5958 .ops = &sa6155_tdm_be_ops,
5959 .ignore_suspend = 1,
5960 },
5961 {
5962 .name = LPASS_BE_QUAT_TDM_RX_0,
5963 .stream_name = "Quaternary TDM0 Playback",
5964 .cpu_dai_name = "msm-dai-q6-tdm.36912",
5965 .platform_name = "msm-pcm-routing",
5966 .codec_name = "msm-stub-codec.1",
5967 .codec_dai_name = "msm-stub-rx",
5968 .no_pcm = 1,
5969 .dpcm_playback = 1,
5970 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
5971 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5972 .ops = &sa6155_tdm_be_ops,
5973 .ignore_suspend = 1,
5974 .ignore_pmdown_time = 1,
5975 },
5976 {
5977 .name = LPASS_BE_QUAT_TDM_TX_0,
5978 .stream_name = "Quaternary TDM0 Capture",
5979 .cpu_dai_name = "msm-dai-q6-tdm.36913",
5980 .platform_name = "msm-pcm-routing",
5981 .codec_name = "msm-stub-codec.1",
5982 .codec_dai_name = "msm-stub-tx",
5983 .no_pcm = 1,
5984 .dpcm_capture = 1,
5985 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
5986 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
5987 .ops = &sa6155_tdm_be_ops,
5988 .ignore_suspend = 1,
5989 },
5990};
5991
5992static struct snd_soc_dai_link msm_auto_be_dai_links[] = {
5993 /* Backend DAI Links */
5994 {
5995 .name = LPASS_BE_PRI_TDM_RX_1,
5996 .stream_name = "Primary TDM1 Playback",
5997 .cpu_dai_name = "msm-dai-q6-tdm.36866",
5998 .platform_name = "msm-pcm-routing",
5999 .codec_name = "msm-stub-codec.1",
6000 .codec_dai_name = "msm-stub-rx",
6001 .no_pcm = 1,
6002 .dpcm_playback = 1,
6003 .id = MSM_BACKEND_DAI_PRI_TDM_RX_1,
6004 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6005 .ops = &sa6155_tdm_be_ops,
6006 .ignore_suspend = 1,
6007 },
6008 {
6009 .name = LPASS_BE_PRI_TDM_RX_2,
6010 .stream_name = "Primary TDM2 Playback",
6011 .cpu_dai_name = "msm-dai-q6-tdm.36868",
6012 .platform_name = "msm-pcm-routing",
6013 .codec_name = "msm-stub-codec.1",
6014 .codec_dai_name = "msm-stub-rx",
6015 .no_pcm = 1,
6016 .dpcm_playback = 1,
6017 .id = MSM_BACKEND_DAI_PRI_TDM_RX_2,
6018 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6019 .ops = &sa6155_tdm_be_ops,
6020 .ignore_suspend = 1,
6021 },
6022 {
6023 .name = LPASS_BE_PRI_TDM_RX_3,
6024 .stream_name = "Primary TDM3 Playback",
6025 .cpu_dai_name = "msm-dai-q6-tdm.36870",
6026 .platform_name = "msm-pcm-routing",
6027 .codec_name = "msm-stub-codec.1",
6028 .codec_dai_name = "msm-stub-rx",
6029 .no_pcm = 1,
6030 .dpcm_playback = 1,
6031 .id = MSM_BACKEND_DAI_PRI_TDM_RX_3,
6032 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6033 .ops = &sa6155_tdm_be_ops,
6034 .ignore_suspend = 1,
6035 },
6036 {
6037 .name = LPASS_BE_PRI_TDM_TX_1,
6038 .stream_name = "Primary TDM1 Capture",
6039 .cpu_dai_name = "msm-dai-q6-tdm.36867",
6040 .platform_name = "msm-pcm-routing",
6041 .codec_name = "msm-stub-codec.1",
6042 .codec_dai_name = "msm-stub-rx",
6043 .no_pcm = 1,
6044 .dpcm_capture = 1,
6045 .id = MSM_BACKEND_DAI_PRI_TDM_TX_1,
6046 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6047 .ops = &sa6155_tdm_be_ops,
6048 .ignore_suspend = 1,
6049 },
6050 {
6051 .name = LPASS_BE_PRI_TDM_TX_2,
6052 .stream_name = "Primary TDM2 Capture",
6053 .cpu_dai_name = "msm-dai-q6-tdm.36869",
6054 .platform_name = "msm-pcm-routing",
6055 .codec_name = "msm-stub-codec.1",
6056 .codec_dai_name = "msm-stub-rx",
6057 .no_pcm = 1,
6058 .dpcm_capture = 1,
6059 .id = MSM_BACKEND_DAI_PRI_TDM_TX_2,
6060 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6061 .ops = &sa6155_tdm_be_ops,
6062 .ignore_suspend = 1,
6063 },
6064 {
6065 .name = LPASS_BE_PRI_TDM_TX_3,
6066 .stream_name = "Primary TDM3 Capture",
6067 .cpu_dai_name = "msm-dai-q6-tdm.36871",
6068 .platform_name = "msm-pcm-routing",
6069 .codec_name = "msm-stub-codec.1",
6070 .codec_dai_name = "msm-stub-rx",
6071 .no_pcm = 1,
6072 .dpcm_capture = 1,
6073 .id = MSM_BACKEND_DAI_PRI_TDM_TX_3,
6074 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6075 .ops = &sa6155_tdm_be_ops,
6076 .ignore_suspend = 1,
6077 },
6078 {
6079 .name = LPASS_BE_SEC_TDM_RX_1,
6080 .stream_name = "Secondary TDM1 Playback",
6081 .cpu_dai_name = "msm-dai-q6-tdm.36882",
6082 .platform_name = "msm-pcm-routing",
6083 .codec_name = "msm-stub-codec.1",
6084 .codec_dai_name = "msm-stub-rx",
6085 .no_pcm = 1,
6086 .dpcm_playback = 1,
6087 .id = MSM_BACKEND_DAI_SEC_TDM_RX_1,
6088 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6089 .ops = &sa6155_tdm_be_ops,
6090 .ignore_suspend = 1,
6091 },
6092 {
6093 .name = LPASS_BE_SEC_TDM_RX_2,
6094 .stream_name = "Secondary TDM2 Playback",
6095 .cpu_dai_name = "msm-dai-q6-tdm.36884",
6096 .platform_name = "msm-pcm-routing",
6097 .codec_name = "msm-stub-codec.1",
6098 .codec_dai_name = "msm-stub-rx",
6099 .no_pcm = 1,
6100 .dpcm_playback = 1,
6101 .id = MSM_BACKEND_DAI_SEC_TDM_RX_2,
6102 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6103 .ops = &sa6155_tdm_be_ops,
6104 .ignore_suspend = 1,
6105 },
6106 {
6107 .name = LPASS_BE_SEC_TDM_RX_3,
6108 .stream_name = "Secondary TDM3 Playback",
6109 .cpu_dai_name = "msm-dai-q6-tdm.36886",
6110 .platform_name = "msm-pcm-routing",
6111 .codec_name = "msm-stub-codec.1",
6112 .codec_dai_name = "msm-stub-rx",
6113 .no_pcm = 1,
6114 .dpcm_playback = 1,
6115 .id = MSM_BACKEND_DAI_SEC_TDM_RX_3,
6116 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6117 .ops = &sa6155_tdm_be_ops,
6118 .ignore_suspend = 1,
6119 },
6120 {
6121 .name = LPASS_BE_SEC_TDM_TX_1,
6122 .stream_name = "Secondary TDM1 Capture",
6123 .cpu_dai_name = "msm-dai-q6-tdm.36883",
6124 .platform_name = "msm-pcm-routing",
6125 .codec_name = "msm-stub-codec.1",
6126 .codec_dai_name = "msm-stub-rx",
6127 .no_pcm = 1,
6128 .dpcm_capture = 1,
6129 .id = MSM_BACKEND_DAI_SEC_TDM_TX_1,
6130 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6131 .ops = &sa6155_tdm_be_ops,
6132 .ignore_suspend = 1,
6133 },
6134 {
6135 .name = LPASS_BE_SEC_TDM_TX_2,
6136 .stream_name = "Secondary TDM2 Capture",
6137 .cpu_dai_name = "msm-dai-q6-tdm.36885",
6138 .platform_name = "msm-pcm-routing",
6139 .codec_name = "msm-stub-codec.1",
6140 .codec_dai_name = "msm-stub-rx",
6141 .no_pcm = 1,
6142 .dpcm_capture = 1,
6143 .id = MSM_BACKEND_DAI_SEC_TDM_TX_2,
6144 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6145 .ops = &sa6155_tdm_be_ops,
6146 .ignore_suspend = 1,
6147 },
6148 {
6149 .name = LPASS_BE_SEC_TDM_TX_3,
6150 .stream_name = "Secondary TDM3 Capture",
6151 .cpu_dai_name = "msm-dai-q6-tdm.36887",
6152 .platform_name = "msm-pcm-routing",
6153 .codec_name = "msm-stub-codec.1",
6154 .codec_dai_name = "msm-stub-rx",
6155 .no_pcm = 1,
6156 .dpcm_capture = 1,
6157 .id = MSM_BACKEND_DAI_SEC_TDM_TX_3,
6158 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6159 .ops = &sa6155_tdm_be_ops,
6160 .ignore_suspend = 1,
6161 },
6162 {
6163 .name = LPASS_BE_TERT_TDM_RX_1,
6164 .stream_name = "Tertiary TDM1 Playback",
6165 .cpu_dai_name = "msm-dai-q6-tdm.36898",
6166 .platform_name = "msm-pcm-routing",
6167 .codec_name = "msm-stub-codec.1",
6168 .codec_dai_name = "msm-stub-rx",
6169 .no_pcm = 1,
6170 .dpcm_playback = 1,
6171 .id = MSM_BACKEND_DAI_TERT_TDM_RX_1,
6172 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6173 .ops = &sa6155_tdm_be_ops,
6174 .ignore_suspend = 1,
6175 },
6176 {
6177 .name = LPASS_BE_TERT_TDM_RX_2,
6178 .stream_name = "Tertiary TDM2 Playback",
6179 .cpu_dai_name = "msm-dai-q6-tdm.36900",
6180 .platform_name = "msm-pcm-routing",
6181 .codec_name = "msm-stub-codec.1",
6182 .codec_dai_name = "msm-stub-rx",
6183 .no_pcm = 1,
6184 .dpcm_playback = 1,
6185 .id = MSM_BACKEND_DAI_TERT_TDM_RX_2,
6186 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6187 .ops = &sa6155_tdm_be_ops,
6188 .ignore_suspend = 1,
6189 },
6190 {
6191 .name = LPASS_BE_TERT_TDM_RX_3,
6192 .stream_name = "Tertiary TDM3 Playback",
6193 .cpu_dai_name = "msm-dai-q6-tdm.36902",
6194 .platform_name = "msm-pcm-routing",
6195 .codec_name = "msm-stub-codec.1",
6196 .codec_dai_name = "msm-stub-rx",
6197 .no_pcm = 1,
6198 .dpcm_playback = 1,
6199 .id = MSM_BACKEND_DAI_TERT_TDM_RX_3,
6200 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6201 .ops = &sa6155_tdm_be_ops,
6202 .ignore_suspend = 1,
6203 },
6204 {
6205 .name = LPASS_BE_TERT_TDM_RX_4,
6206 .stream_name = "Tertiary TDM4 Playback",
6207 .cpu_dai_name = "msm-dai-q6-tdm.36904",
6208 .platform_name = "msm-pcm-routing",
6209 .codec_name = "msm-stub-codec.1",
6210 .codec_dai_name = "msm-stub-rx",
6211 .no_pcm = 1,
6212 .dpcm_playback = 1,
6213 .id = MSM_BACKEND_DAI_TERT_TDM_RX_4,
6214 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6215 .ops = &sa6155_tdm_be_ops,
6216 .ignore_suspend = 1,
6217 },
6218 {
6219 .name = LPASS_BE_TERT_TDM_TX_1,
6220 .stream_name = "Tertiary TDM1 Capture",
6221 .cpu_dai_name = "msm-dai-q6-tdm.36899",
6222 .platform_name = "msm-pcm-routing",
6223 .codec_name = "msm-stub-codec.1",
6224 .codec_dai_name = "msm-stub-rx",
6225 .no_pcm = 1,
6226 .dpcm_capture = 1,
6227 .id = MSM_BACKEND_DAI_TERT_TDM_TX_1,
6228 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6229 .ops = &sa6155_tdm_be_ops,
6230 .ignore_suspend = 1,
6231 },
6232 {
6233 .name = LPASS_BE_TERT_TDM_TX_2,
6234 .stream_name = "Tertiary TDM2 Capture",
6235 .cpu_dai_name = "msm-dai-q6-tdm.36901",
6236 .platform_name = "msm-pcm-routing",
6237 .codec_name = "msm-stub-codec.1",
6238 .codec_dai_name = "msm-stub-rx",
6239 .no_pcm = 1,
6240 .dpcm_capture = 1,
6241 .id = MSM_BACKEND_DAI_TERT_TDM_TX_2,
6242 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6243 .ops = &sa6155_tdm_be_ops,
6244 .ignore_suspend = 1,
6245 },
6246 {
6247 .name = LPASS_BE_TERT_TDM_TX_3,
6248 .stream_name = "Tertiary TDM3 Capture",
6249 .cpu_dai_name = "msm-dai-q6-tdm.36903",
6250 .platform_name = "msm-pcm-routing",
6251 .codec_name = "msm-stub-codec.1",
6252 .codec_dai_name = "msm-stub-rx",
6253 .no_pcm = 1,
6254 .dpcm_capture = 1,
6255 .id = MSM_BACKEND_DAI_TERT_TDM_TX_3,
6256 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6257 .ops = &sa6155_tdm_be_ops,
6258 .ignore_suspend = 1,
6259 },
6260 {
6261 .name = LPASS_BE_QUAT_TDM_RX_1,
6262 .stream_name = "Quaternary TDM1 Playback",
6263 .cpu_dai_name = "msm-dai-q6-tdm.36914",
6264 .platform_name = "msm-pcm-routing",
6265 .codec_name = "msm-stub-codec.1",
6266 .codec_dai_name = "msm-stub-rx",
6267 .no_pcm = 1,
6268 .dpcm_playback = 1,
6269 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_1,
6270 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6271 .ops = &sa6155_tdm_be_ops,
6272 .ignore_suspend = 1,
6273 },
6274 {
6275 .name = LPASS_BE_QUAT_TDM_RX_2,
6276 .stream_name = "Quaternary TDM2 Playback",
6277 .cpu_dai_name = "msm-dai-q6-tdm.36916",
6278 .platform_name = "msm-pcm-routing",
6279 .codec_name = "msm-stub-codec.1",
6280 .codec_dai_name = "msm-stub-rx",
6281 .no_pcm = 1,
6282 .dpcm_playback = 1,
6283 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_2,
6284 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6285 .ops = &sa6155_tdm_be_ops,
6286 .ignore_suspend = 1,
6287 },
6288 {
6289 .name = LPASS_BE_QUAT_TDM_RX_3,
6290 .stream_name = "Quaternary TDM3 Playback",
6291 .cpu_dai_name = "msm-dai-q6-tdm.36918",
6292 .platform_name = "msm-pcm-routing",
6293 .codec_name = "msm-stub-codec.1",
6294 .codec_dai_name = "msm-stub-rx",
6295 .no_pcm = 1,
6296 .dpcm_playback = 1,
6297 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_3,
6298 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6299 .ops = &sa6155_tdm_be_ops,
6300 .ignore_suspend = 1,
6301 },
6302 {
6303 .name = LPASS_BE_QUAT_TDM_TX_1,
6304 .stream_name = "Quaternary TDM1 Capture",
6305 .cpu_dai_name = "msm-dai-q6-tdm.36915",
6306 .platform_name = "msm-pcm-routing",
6307 .codec_name = "msm-stub-codec.1",
6308 .codec_dai_name = "msm-stub-rx",
6309 .no_pcm = 1,
6310 .dpcm_capture = 1,
6311 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_1,
6312 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6313 .ops = &sa6155_tdm_be_ops,
6314 .ignore_suspend = 1,
6315 },
6316 {
6317 .name = LPASS_BE_QUAT_TDM_TX_2,
6318 .stream_name = "Quaternary TDM2 Capture",
6319 .cpu_dai_name = "msm-dai-q6-tdm.36917",
6320 .platform_name = "msm-pcm-routing",
6321 .codec_name = "msm-stub-codec.1",
6322 .codec_dai_name = "msm-stub-rx",
6323 .no_pcm = 1,
6324 .dpcm_capture = 1,
6325 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_2,
6326 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6327 .ops = &sa6155_tdm_be_ops,
6328 .ignore_suspend = 1,
6329 },
6330 {
6331 .name = LPASS_BE_QUAT_TDM_TX_3,
6332 .stream_name = "Quaternary TDM3 Capture",
6333 .cpu_dai_name = "msm-dai-q6-tdm.36919",
6334 .platform_name = "msm-pcm-routing",
6335 .codec_name = "msm-stub-codec.1",
6336 .codec_dai_name = "msm-stub-rx",
6337 .no_pcm = 1,
6338 .dpcm_capture = 1,
6339 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_3,
6340 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6341 .ops = &sa6155_tdm_be_ops,
6342 .ignore_suspend = 1,
6343 },
6344};
6345
6346static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
6347 /* DISP PORT BACK END DAI Link */
6348 {
6349 .name = LPASS_BE_DISPLAY_PORT,
6350 .stream_name = "Display Port Playback",
6351 .cpu_dai_name = "msm-dai-q6-dp.24608",
6352 .platform_name = "msm-pcm-routing",
6353 .codec_name = "msm-ext-disp-audio-codec-rx",
6354 .codec_dai_name = "msm_dp_audio_codec_rx_dai",
6355 .no_pcm = 1,
6356 .dpcm_playback = 1,
6357 .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
6358 .be_hw_params_fixup = msm_be_hw_params_fixup,
6359 .ignore_pmdown_time = 1,
6360 .ignore_suspend = 1,
6361 },
6362};
6363
6364static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
6365 {
6366 .name = LPASS_BE_PRI_MI2S_RX,
6367 .stream_name = "Primary MI2S Playback",
6368 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6369 .platform_name = "msm-pcm-routing",
6370 .codec_name = "msm-stub-codec.1",
6371 .codec_dai_name = "msm-stub-rx",
6372 .no_pcm = 1,
6373 .dpcm_playback = 1,
6374 .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
6375 .be_hw_params_fixup = msm_be_hw_params_fixup,
6376 .ops = &msm_mi2s_be_ops,
6377 .ignore_suspend = 1,
6378 .ignore_pmdown_time = 1,
6379 },
6380 {
6381 .name = LPASS_BE_PRI_MI2S_TX,
6382 .stream_name = "Primary MI2S Capture",
6383 .cpu_dai_name = "msm-dai-q6-mi2s.0",
6384 .platform_name = "msm-pcm-routing",
6385 .codec_name = "msm-stub-codec.1",
6386 .codec_dai_name = "msm-stub-tx",
6387 .no_pcm = 1,
6388 .dpcm_capture = 1,
6389 .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
6390 .be_hw_params_fixup = msm_be_hw_params_fixup,
6391 .ops = &msm_mi2s_be_ops,
6392 .ignore_suspend = 1,
6393 },
6394 {
6395 .name = LPASS_BE_SEC_MI2S_RX,
6396 .stream_name = "Secondary MI2S Playback",
6397 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6398 .platform_name = "msm-pcm-routing",
6399 .codec_name = "msm-stub-codec.1",
6400 .codec_dai_name = "msm-stub-rx",
6401 .no_pcm = 1,
6402 .dpcm_playback = 1,
6403 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
6404 .be_hw_params_fixup = msm_be_hw_params_fixup,
6405 .ops = &msm_mi2s_be_ops,
6406 .ignore_suspend = 1,
6407 .ignore_pmdown_time = 1,
6408 },
6409 {
6410 .name = LPASS_BE_SEC_MI2S_TX,
6411 .stream_name = "Secondary MI2S Capture",
6412 .cpu_dai_name = "msm-dai-q6-mi2s.1",
6413 .platform_name = "msm-pcm-routing",
6414 .codec_name = "msm-stub-codec.1",
6415 .codec_dai_name = "msm-stub-tx",
6416 .no_pcm = 1,
6417 .dpcm_capture = 1,
6418 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
6419 .be_hw_params_fixup = msm_be_hw_params_fixup,
6420 .ops = &msm_mi2s_be_ops,
6421 .ignore_suspend = 1,
6422 },
6423 {
6424 .name = LPASS_BE_TERT_MI2S_RX,
6425 .stream_name = "Tertiary MI2S Playback",
6426 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6427 .platform_name = "msm-pcm-routing",
6428 .codec_name = "msm-stub-codec.1",
6429 .codec_dai_name = "msm-stub-rx",
6430 .no_pcm = 1,
6431 .dpcm_playback = 1,
6432 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
6433 .be_hw_params_fixup = msm_be_hw_params_fixup,
6434 .ops = &msm_mi2s_be_ops,
6435 .ignore_suspend = 1,
6436 .ignore_pmdown_time = 1,
6437 },
6438 {
6439 .name = LPASS_BE_TERT_MI2S_TX,
6440 .stream_name = "Tertiary MI2S Capture",
6441 .cpu_dai_name = "msm-dai-q6-mi2s.2",
6442 .platform_name = "msm-pcm-routing",
6443 .codec_name = "msm-stub-codec.1",
6444 .codec_dai_name = "msm-stub-tx",
6445 .no_pcm = 1,
6446 .dpcm_capture = 1,
6447 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
6448 .be_hw_params_fixup = msm_be_hw_params_fixup,
6449 .ops = &msm_mi2s_be_ops,
6450 .ignore_suspend = 1,
6451 },
6452 {
6453 .name = LPASS_BE_QUAT_MI2S_RX,
6454 .stream_name = "Quaternary MI2S Playback",
6455 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6456 .platform_name = "msm-pcm-routing",
6457 .codec_name = "msm-stub-codec.1",
6458 .codec_dai_name = "msm-stub-rx",
6459 .no_pcm = 1,
6460 .dpcm_playback = 1,
6461 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
6462 .be_hw_params_fixup = msm_be_hw_params_fixup,
6463 .ops = &msm_mi2s_be_ops,
6464 .ignore_suspend = 1,
6465 .ignore_pmdown_time = 1,
6466 },
6467 {
6468 .name = LPASS_BE_QUAT_MI2S_TX,
6469 .stream_name = "Quaternary MI2S Capture",
6470 .cpu_dai_name = "msm-dai-q6-mi2s.3",
6471 .platform_name = "msm-pcm-routing",
6472 .codec_name = "msm-stub-codec.1",
6473 .codec_dai_name = "msm-stub-tx",
6474 .no_pcm = 1,
6475 .dpcm_capture = 1,
6476 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
6477 .be_hw_params_fixup = msm_be_hw_params_fixup,
6478 .ops = &msm_mi2s_be_ops,
6479 .ignore_suspend = 1,
6480 },
6481 {
6482 .name = LPASS_BE_QUIN_MI2S_RX,
6483 .stream_name = "Quinary MI2S Playback",
6484 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6485 .platform_name = "msm-pcm-routing",
6486 .codec_name = "msm-stub-codec.1",
6487 .codec_dai_name = "msm-stub-rx",
6488 .no_pcm = 1,
6489 .dpcm_playback = 1,
6490 .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
6491 .be_hw_params_fixup = msm_be_hw_params_fixup,
6492 .ops = &msm_mi2s_be_ops,
6493 .ignore_suspend = 1,
6494 .ignore_pmdown_time = 1,
6495 },
6496 {
6497 .name = LPASS_BE_QUIN_MI2S_TX,
6498 .stream_name = "Quinary MI2S Capture",
6499 .cpu_dai_name = "msm-dai-q6-mi2s.4",
6500 .platform_name = "msm-pcm-routing",
6501 .codec_name = "msm-stub-codec.1",
6502 .codec_dai_name = "msm-stub-tx",
6503 .no_pcm = 1,
6504 .dpcm_capture = 1,
6505 .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
6506 .be_hw_params_fixup = msm_be_hw_params_fixup,
6507 .ops = &msm_mi2s_be_ops,
6508 .ignore_suspend = 1,
6509 },
6510};
6511
6512static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
6513 /* Primary AUX PCM Backend DAI Links */
6514 {
6515 .name = LPASS_BE_AUXPCM_RX,
6516 .stream_name = "AUX PCM Playback",
6517 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6518 .platform_name = "msm-pcm-routing",
6519 .codec_name = "msm-stub-codec.1",
6520 .codec_dai_name = "msm-stub-rx",
6521 .no_pcm = 1,
6522 .dpcm_playback = 1,
6523 .id = MSM_BACKEND_DAI_AUXPCM_RX,
6524 .be_hw_params_fixup = msm_be_hw_params_fixup,
6525 .ignore_pmdown_time = 1,
6526 .ignore_suspend = 1,
6527 },
6528 {
6529 .name = LPASS_BE_AUXPCM_TX,
6530 .stream_name = "AUX PCM Capture",
6531 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
6532 .platform_name = "msm-pcm-routing",
6533 .codec_name = "msm-stub-codec.1",
6534 .codec_dai_name = "msm-stub-tx",
6535 .no_pcm = 1,
6536 .dpcm_capture = 1,
6537 .id = MSM_BACKEND_DAI_AUXPCM_TX,
6538 .be_hw_params_fixup = msm_be_hw_params_fixup,
6539 .ignore_suspend = 1,
6540 },
6541 /* Secondary AUX PCM Backend DAI Links */
6542 {
6543 .name = LPASS_BE_SEC_AUXPCM_RX,
6544 .stream_name = "Sec AUX PCM Playback",
6545 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6546 .platform_name = "msm-pcm-routing",
6547 .codec_name = "msm-stub-codec.1",
6548 .codec_dai_name = "msm-stub-rx",
6549 .no_pcm = 1,
6550 .dpcm_playback = 1,
6551 .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
6552 .be_hw_params_fixup = msm_be_hw_params_fixup,
6553 .ignore_pmdown_time = 1,
6554 .ignore_suspend = 1,
6555 },
6556 {
6557 .name = LPASS_BE_SEC_AUXPCM_TX,
6558 .stream_name = "Sec AUX PCM Capture",
6559 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
6560 .platform_name = "msm-pcm-routing",
6561 .codec_name = "msm-stub-codec.1",
6562 .codec_dai_name = "msm-stub-tx",
6563 .no_pcm = 1,
6564 .dpcm_capture = 1,
6565 .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
6566 .be_hw_params_fixup = msm_be_hw_params_fixup,
6567 .ignore_suspend = 1,
6568 },
6569 /* Tertiary AUX PCM Backend DAI Links */
6570 {
6571 .name = LPASS_BE_TERT_AUXPCM_RX,
6572 .stream_name = "Tert AUX PCM Playback",
6573 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
6574 .platform_name = "msm-pcm-routing",
6575 .codec_name = "msm-stub-codec.1",
6576 .codec_dai_name = "msm-stub-rx",
6577 .no_pcm = 1,
6578 .dpcm_playback = 1,
6579 .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
6580 .be_hw_params_fixup = msm_be_hw_params_fixup,
6581 .ignore_suspend = 1,
6582 },
6583 {
6584 .name = LPASS_BE_TERT_AUXPCM_TX,
6585 .stream_name = "Tert AUX PCM Capture",
6586 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
6587 .platform_name = "msm-pcm-routing",
6588 .codec_name = "msm-stub-codec.1",
6589 .codec_dai_name = "msm-stub-tx",
6590 .no_pcm = 1,
6591 .dpcm_capture = 1,
6592 .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
6593 .be_hw_params_fixup = msm_be_hw_params_fixup,
6594 .ignore_suspend = 1,
6595 },
6596 /* Quaternary AUX PCM Backend DAI Links */
6597 {
6598 .name = LPASS_BE_QUAT_AUXPCM_RX,
6599 .stream_name = "Quat AUX PCM Playback",
6600 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
6601 .platform_name = "msm-pcm-routing",
6602 .codec_name = "msm-stub-codec.1",
6603 .codec_dai_name = "msm-stub-rx",
6604 .no_pcm = 1,
6605 .dpcm_playback = 1,
6606 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
6607 .be_hw_params_fixup = msm_be_hw_params_fixup,
6608 .ignore_pmdown_time = 1,
6609 .ignore_suspend = 1,
6610 },
6611 {
6612 .name = LPASS_BE_QUAT_AUXPCM_TX,
6613 .stream_name = "Quat AUX PCM Capture",
6614 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
6615 .platform_name = "msm-pcm-routing",
6616 .codec_name = "msm-stub-codec.1",
6617 .codec_dai_name = "msm-stub-tx",
6618 .no_pcm = 1,
6619 .dpcm_capture = 1,
6620 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
6621 .be_hw_params_fixup = msm_be_hw_params_fixup,
6622 .ignore_suspend = 1,
6623 },
6624 /* Quinary AUX PCM Backend DAI Links */
6625 {
6626 .name = LPASS_BE_QUIN_AUXPCM_RX,
6627 .stream_name = "Quin AUX PCM Playback",
6628 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
6629 .platform_name = "msm-pcm-routing",
6630 .codec_name = "msm-stub-codec.1",
6631 .codec_dai_name = "msm-stub-rx",
6632 .no_pcm = 1,
6633 .dpcm_playback = 1,
6634 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
6635 .be_hw_params_fixup = msm_be_hw_params_fixup,
6636 .ignore_pmdown_time = 1,
6637 .ignore_suspend = 1,
6638 },
6639 {
6640 .name = LPASS_BE_QUIN_AUXPCM_TX,
6641 .stream_name = "Quin AUX PCM Capture",
6642 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
6643 .platform_name = "msm-pcm-routing",
6644 .codec_name = "msm-stub-codec.1",
6645 .codec_dai_name = "msm-stub-tx",
6646 .no_pcm = 1,
6647 .dpcm_capture = 1,
6648 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
6649 .be_hw_params_fixup = msm_be_hw_params_fixup,
6650 .ignore_suspend = 1,
6651 },
6652};
6653
6654static struct snd_soc_dai_link msm_auto_dai_links[
6655 ARRAY_SIZE(msm_common_dai_links) +
6656 ARRAY_SIZE(msm_auto_fe_dai_links) +
6657 ARRAY_SIZE(msm_common_be_dai_links) +
6658 ARRAY_SIZE(msm_auto_be_dai_links) +
6659 ARRAY_SIZE(ext_disp_be_dai_link) +
6660 ARRAY_SIZE(msm_mi2s_be_dai_links) +
6661 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
6662
6663static struct snd_soc_dai_link msm_auto_custom_dai_links[
6664 ARRAY_SIZE(msm_custom_fe_dai_links) +
6665 ARRAY_SIZE(msm_auto_fe_dai_links) +
6666 ARRAY_SIZE(msm_common_be_dai_links) +
6667 ARRAY_SIZE(msm_auto_be_dai_links) +
6668 ARRAY_SIZE(ext_disp_be_dai_link) +
6669 ARRAY_SIZE(msm_mi2s_be_dai_links) +
6670 ARRAY_SIZE(msm_auxpcm_be_dai_links)];
6671
6672struct snd_soc_card snd_soc_card_auto_msm = {
6673 .name = "sa6155-adp-star-snd-card",
6674};
6675
6676struct snd_soc_card snd_soc_card_auto_custom_msm = {
6677 .name = "sa6155-custom-snd-card",
6678};
6679
6680static int msm_populate_dai_link_component_of_node(
6681 struct snd_soc_card *card)
6682{
6683 int i, index, ret = 0;
6684 struct device *cdev = card->dev;
6685 struct snd_soc_dai_link *dai_link = card->dai_link;
6686 struct device_node *np;
6687
6688 if (!cdev) {
6689 pr_err("%s: Sound card device memory NULL\n", __func__);
6690 return -ENODEV;
6691 }
6692
6693 for (i = 0; i < card->num_links; i++) {
6694 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
6695 continue;
6696
6697 /* populate platform_of_node for snd card dai links */
6698 if (dai_link[i].platform_name &&
6699 !dai_link[i].platform_of_node) {
6700 index = of_property_match_string(cdev->of_node,
6701 "asoc-platform-names",
6702 dai_link[i].platform_name);
6703 if (index < 0) {
6704 pr_err("%s: No match found for platform name: %s\n",
6705 __func__, dai_link[i].platform_name);
6706 ret = index;
6707 goto err;
6708 }
6709 np = of_parse_phandle(cdev->of_node, "asoc-platform",
6710 index);
6711 if (!np) {
6712 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
6713 __func__, dai_link[i].platform_name,
6714 index);
6715 ret = -ENODEV;
6716 goto err;
6717 }
6718 dai_link[i].platform_of_node = np;
6719 dai_link[i].platform_name = NULL;
6720 }
6721
6722 /* populate cpu_of_node for snd card dai links */
6723 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
6724 index = of_property_match_string(cdev->of_node,
6725 "asoc-cpu-names",
6726 dai_link[i].cpu_dai_name);
6727 if (index >= 0) {
6728 np = of_parse_phandle(cdev->of_node, "asoc-cpu",
6729 index);
6730 if (!np) {
6731 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
6732 __func__,
6733 dai_link[i].cpu_dai_name);
6734 ret = -ENODEV;
6735 goto err;
6736 }
6737 dai_link[i].cpu_of_node = np;
6738 dai_link[i].cpu_dai_name = NULL;
6739 }
6740 }
6741
6742 /* populate codec_of_node for snd card dai links */
6743 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
6744 index = of_property_match_string(cdev->of_node,
6745 "asoc-codec-names",
6746 dai_link[i].codec_name);
6747 if (index < 0)
6748 continue;
6749 np = of_parse_phandle(cdev->of_node, "asoc-codec",
6750 index);
6751 if (!np) {
6752 pr_err("%s: retrieving phandle for codec %s failed\n",
6753 __func__, dai_link[i].codec_name);
6754 ret = -ENODEV;
6755 goto err;
6756 }
6757 dai_link[i].codec_of_node = np;
6758 dai_link[i].codec_name = NULL;
6759 }
6760 }
6761
6762err:
6763 return ret;
6764}
6765
6766static const struct of_device_id sa6155_asoc_machine_of_match[] = {
6767 { .compatible = "qcom,sa6155-asoc-snd-adp-star",
6768 .data = "adp_star_codec"},
6769 { .compatible = "qcom,sa6155-asoc-snd-custom",
6770 .data = "custom_codec"},
6771 {},
6772};
6773
6774static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
6775{
6776 struct snd_soc_card *card = NULL;
6777 struct snd_soc_dai_link *dailink;
6778 int len_1, len_2, len_3;
6779 int total_links;
6780 const struct of_device_id *match;
6781
6782 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
6783 if (!match) {
6784 dev_err(dev, "%s: No DT match found for sound card\n",
6785 __func__);
6786 return NULL;
6787 }
6788
6789 if (!strcmp(match->data, "adp_star_codec")) {
6790 card = &snd_soc_card_auto_msm;
6791 len_1 = ARRAY_SIZE(msm_common_dai_links);
6792 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
6793 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
6794 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
6795 memcpy(msm_auto_dai_links,
6796 msm_common_dai_links,
6797 sizeof(msm_common_dai_links));
6798 memcpy(msm_auto_dai_links + len_1,
6799 msm_auto_fe_dai_links,
6800 sizeof(msm_auto_fe_dai_links));
6801 memcpy(msm_auto_dai_links + len_2,
6802 msm_common_be_dai_links,
6803 sizeof(msm_common_be_dai_links));
6804 memcpy(msm_auto_dai_links + len_3,
6805 msm_auto_be_dai_links,
6806 sizeof(msm_auto_be_dai_links));
6807
6808 if (of_property_read_bool(dev->of_node,
6809 "qcom,ext-disp-audio-rx")) {
6810 dev_dbg(dev, "%s(): ext disp audio support present\n",
6811 __func__);
6812 memcpy(msm_auto_dai_links + total_links,
6813 ext_disp_be_dai_link,
6814 sizeof(ext_disp_be_dai_link));
6815 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
6816 }
6817 if (of_property_read_bool(dev->of_node,
6818 "qcom,mi2s-audio-intf")) {
6819 memcpy(msm_auto_dai_links + total_links,
6820 msm_mi2s_be_dai_links,
6821 sizeof(msm_mi2s_be_dai_links));
6822 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
6823 }
6824 if (of_property_read_bool(dev->of_node,
6825 "qcom,auxpcm-audio-intf")) {
6826 memcpy(msm_auto_dai_links + total_links,
6827 msm_auxpcm_be_dai_links,
6828 sizeof(msm_auxpcm_be_dai_links));
6829 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
6830 }
6831
6832 dailink = msm_auto_dai_links;
6833 } else if (!strcmp(match->data, "custom_codec")) {
6834 card = &snd_soc_card_auto_custom_msm;
6835 len_1 = ARRAY_SIZE(msm_custom_fe_dai_links);
6836 len_2 = len_1 + ARRAY_SIZE(msm_auto_fe_dai_links);
6837 len_3 = len_2 + ARRAY_SIZE(msm_common_be_dai_links);
6838 total_links = len_3 + ARRAY_SIZE(msm_auto_be_dai_links);
6839 memcpy(msm_auto_custom_dai_links,
6840 msm_custom_fe_dai_links,
6841 sizeof(msm_custom_fe_dai_links));
6842 memcpy(msm_auto_custom_dai_links + len_1,
6843 msm_auto_fe_dai_links,
6844 sizeof(msm_auto_fe_dai_links));
6845 memcpy(msm_auto_custom_dai_links + len_2,
6846 msm_common_be_dai_links,
6847 sizeof(msm_common_be_dai_links));
6848 memcpy(msm_auto_custom_dai_links + len_3,
6849 msm_auto_be_dai_links,
6850 sizeof(msm_auto_be_dai_links));
6851
6852 if (of_property_read_bool(dev->of_node,
6853 "qcom,ext-disp-audio-rx")) {
6854 dev_dbg(dev, "%s(): ext disp audio support present\n",
6855 __func__);
6856 memcpy(msm_auto_custom_dai_links + total_links,
6857 ext_disp_be_dai_link,
6858 sizeof(ext_disp_be_dai_link));
6859 total_links += ARRAY_SIZE(ext_disp_be_dai_link);
6860 }
6861 if (of_property_read_bool(dev->of_node,
6862 "qcom,mi2s-audio-intf")) {
6863 memcpy(msm_auto_custom_dai_links + total_links,
6864 msm_mi2s_be_dai_links,
6865 sizeof(msm_mi2s_be_dai_links));
6866 total_links += ARRAY_SIZE(msm_mi2s_be_dai_links);
6867 }
6868 if (of_property_read_bool(dev->of_node,
6869 "qcom,auxpcm-audio-intf")) {
6870 memcpy(msm_auto_custom_dai_links + total_links,
6871 msm_auxpcm_be_dai_links,
6872 sizeof(msm_auxpcm_be_dai_links));
6873 total_links += ARRAY_SIZE(msm_auxpcm_be_dai_links);
6874 }
6875 dailink = msm_auto_custom_dai_links;
6876 } else {
6877 dev_err(dev, "%s: Codec not supported\n",
6878 __func__);
6879 return NULL;
6880 }
6881
6882 if (card) {
6883 card->dai_link = dailink;
6884 card->num_links = total_links;
6885 }
6886
6887 return card;
6888}
6889
6890/*****************************************************************************
6891* TO BE UPDATED: Codec/Platform specific tdm slot and offset table selection
6892*****************************************************************************/
6893static int msm_tdm_init(struct device *dev)
6894{
6895 const struct of_device_id *match;
6896
6897 match = of_match_node(sa6155_asoc_machine_of_match, dev->of_node);
6898 if (!match) {
6899 dev_err(dev, "%s: No DT match found for sound card\n",
6900 __func__);
6901 return -EINVAL;
6902 }
6903
6904 if (!strcmp(match->data, "custom_codec")) {
6905 dev_dbg(dev, "%s: custom tdm configuration\n", __func__);
6906
6907 memcpy(tdm_rx_slot_offset,
6908 tdm_rx_slot_offset_custom,
6909 sizeof(tdm_rx_slot_offset_custom));
6910 memcpy(tdm_tx_slot_offset,
6911 tdm_tx_slot_offset_custom,
6912 sizeof(tdm_tx_slot_offset_custom));
6913 memcpy(tdm_slot,
6914 tdm_slot_custom,
6915 sizeof(tdm_slot_custom));
6916 } else {
6917 dev_dbg(dev, "%s: default tdm configuration\n", __func__);
6918 }
6919
6920 return 0;
6921}
6922
6923static void msm_i2s_auxpcm_init(struct platform_device *pdev)
6924{
6925 int count;
6926 u32 mi2s_master_slave[MI2S_MAX];
6927 int ret;
6928
6929 for (count = 0; count < MI2S_MAX; count++) {
6930 mutex_init(&mi2s_intf_conf[count].lock);
6931 mi2s_intf_conf[count].ref_cnt = 0;
6932 }
6933
6934 ret = of_property_read_u32_array(pdev->dev.of_node,
6935 "qcom,msm-mi2s-master",
6936 mi2s_master_slave, MI2S_MAX);
6937 if (ret) {
6938 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
6939 __func__);
6940 } else {
6941 for (count = 0; count < MI2S_MAX; count++) {
6942 mi2s_intf_conf[count].msm_is_mi2s_master =
6943 mi2s_master_slave[count];
6944 }
6945 }
6946}
6947
6948static void msm_i2s_auxpcm_deinit(void)
6949{
6950 int count;
6951
6952 for (count = 0; count < MI2S_MAX; count++) {
6953 mutex_destroy(&mi2s_intf_conf[count].lock);
6954 mi2s_intf_conf[count].ref_cnt = 0;
6955 mi2s_intf_conf[count].msm_is_mi2s_master = 0;
6956 }
6957}
6958static int msm_asoc_machine_probe(struct platform_device *pdev)
6959{
6960 struct snd_soc_card *card;
6961 struct msm_asoc_mach_data *pdata;
6962 int ret;
6963 enum apr_subsys_state q6_state;
6964
6965 if (!pdev->dev.of_node) {
6966 dev_err(&pdev->dev, "No platform supplied from device tree\n");
6967 return -EINVAL;
6968 }
6969
6970 q6_state = apr_get_q6_state();
6971 if (q6_state == APR_SUBSYS_DOWN) {
6972 dev_dbg(&pdev->dev, "deferring %s, adsp_state %d\n",
6973 __func__, q6_state);
6974 return -EPROBE_DEFER;
6975 }
6976
6977 pdata = devm_kzalloc(&pdev->dev,
6978 sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
6979 if (!pdata)
6980 return -ENOMEM;
6981
6982 card = populate_snd_card_dailinks(&pdev->dev);
6983 if (!card) {
6984 dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
6985 ret = -EINVAL;
6986 goto err;
6987 }
6988 card->dev = &pdev->dev;
6989 platform_set_drvdata(pdev, card);
6990 snd_soc_card_set_drvdata(card, pdata);
6991
6992 ret = snd_soc_of_parse_card_name(card, "qcom,model");
6993 if (ret) {
6994 dev_err(&pdev->dev, "parse card name failed, err:%d\n",
6995 ret);
6996 goto err;
6997 }
6998
6999 ret = msm_populate_dai_link_component_of_node(card);
7000 if (ret) {
7001 ret = -EPROBE_DEFER;
7002 goto err;
7003 }
7004
7005 /* Populate controls of snd card */
7006 card->controls = msm_snd_controls;
7007 card->num_controls = ARRAY_SIZE(msm_snd_controls);
7008
7009 ret = msm_tdm_init(&pdev->dev);
7010 if (ret) {
7011 ret = -EPROBE_DEFER;
7012 goto err;
7013 }
7014
7015 ret = devm_snd_soc_register_card(&pdev->dev, card);
7016 if (ret == -EPROBE_DEFER) {
7017 goto err;
7018 } else if (ret) {
7019 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
7020 ret);
7021 goto err;
7022 }
7023 dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
7024
7025 /* Parse pinctrl info from devicetree */
7026 ret = msm_get_pinctrl(pdev);
7027 if (!ret) {
7028 pr_debug("%s: pinctrl parsing successful\n", __func__);
7029 } else {
7030 dev_dbg(&pdev->dev,
7031 "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
7032 __func__, ret);
7033 ret = 0;
7034 }
7035
7036 msm_i2s_auxpcm_init(pdev);
7037
7038 return 0;
7039err:
7040 msm_release_pinctrl(pdev);
7041 devm_kfree(&pdev->dev, pdata);
7042 return ret;
7043}
7044
7045static int msm_asoc_machine_remove(struct platform_device *pdev)
7046{
7047 msm_i2s_auxpcm_deinit();
7048
7049 msm_release_pinctrl(pdev);
7050 return 0;
7051}
7052
7053static struct platform_driver sa6155_asoc_machine_driver = {
7054 .driver = {
7055 .name = DRV_NAME,
7056 .owner = THIS_MODULE,
7057 .pm = &snd_soc_pm_ops,
7058 .of_match_table = sa6155_asoc_machine_of_match,
7059 },
7060 .probe = msm_asoc_machine_probe,
7061 .remove = msm_asoc_machine_remove,
7062};
7063
7064static int dummy_asoc_machine_probe(struct platform_device *pdev)
7065{
7066 return 0;
7067}
7068
7069static int dummy_asoc_machine_remove(struct platform_device *pdev)
7070{
7071 return 0;
7072}
7073
7074static struct platform_device sa6155_dummy_asoc_machine_device = {
7075 .name = "sa6155-asoc-snd-dummy",
7076};
7077
7078static struct platform_driver sa6155_dummy_asoc_machine_driver = {
7079 .driver = {
7080 .name = "sa6155-asoc-snd-dummy",
7081 .owner = THIS_MODULE,
7082 },
7083 .probe = dummy_asoc_machine_probe,
7084 .remove = dummy_asoc_machine_remove,
7085};
7086
7087static int sa6155_notifier_service_cb(struct notifier_block *this,
7088 unsigned long opcode, void *ptr)
7089{
7090 pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode);
7091
7092 switch (opcode) {
7093 case AUDIO_NOTIFIER_SERVICE_DOWN:
7094 break;
7095 case AUDIO_NOTIFIER_SERVICE_UP:
7096 if (is_initial_boot) {
7097 platform_driver_register(&sa6155_dummy_asoc_machine_driver);
7098 platform_device_register(&sa6155_dummy_asoc_machine_device);
7099 is_initial_boot = false;
7100 }
7101 break;
7102 default:
7103 break;
7104 }
7105
7106 return NOTIFY_OK;
7107}
7108
7109static struct notifier_block service_nb = {
7110 .notifier_call = sa6155_notifier_service_cb,
7111 .priority = -INT_MAX,
7112};
7113
7114int __init sa6155_init(void)
7115{
7116 pr_debug("%s\n", __func__);
7117 audio_notifier_register("sa6155", AUDIO_NOTIFIER_ADSP_DOMAIN,
7118 &service_nb);
7119 return platform_driver_register(&sa6155_asoc_machine_driver);
7120}
7121
7122void sa6155_exit(void)
7123{
7124 pr_debug("%s\n", __func__);
7125 platform_driver_unregister(&sa6155_asoc_machine_driver);
7126 audio_notifier_deregister("sa6155");
7127}
7128
7129MODULE_DESCRIPTION("ALSA SoC msm");
7130MODULE_LICENSE("GPL v2");
7131MODULE_ALIAS("platform:" DRV_NAME);
7132MODULE_DEVICE_TABLE(of, sa6155_asoc_machine_of_match);