Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/io.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/printk.h> |
| 17 | #include <linux/debugfs.h> |
| 18 | #include <linux/delay.h> |
| 19 | #include <linux/workqueue.h> |
| 20 | #include <linux/regmap.h> |
| 21 | #include <sound/pcm.h> |
| 22 | #include <sound/pcm_params.h> |
| 23 | #include <sound/soc.h> |
| 24 | #include <sound/soc-dapm.h> |
| 25 | #include <sound/tlv.h> |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 26 | #include <linux/regulator/consumer.h> |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 27 | #include <dsp/q6afe-v2.h> |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 28 | #include <dsp/q6core.h> |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 29 | #include <ipc/apr.h> |
| 30 | #include <soc/internal.h> |
| 31 | #include "sdm660-cdc-registers.h" |
| 32 | #include "msm-digital-cdc.h" |
| 33 | #include "msm-cdc-common.h" |
| 34 | #include "../../msm8952.h" |
| 35 | |
| 36 | #define DRV_NAME "msm_digital_codec" |
| 37 | #define MCLK_RATE_9P6MHZ 9600000 |
| 38 | #define MCLK_RATE_12P288MHZ 12288000 |
| 39 | #define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30 |
| 40 | #define CF_MIN_3DB_4HZ 0x0 |
| 41 | #define CF_MIN_3DB_75HZ 0x1 |
| 42 | #define CF_MIN_3DB_150HZ 0x2 |
| 43 | |
| 44 | #define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32 |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 45 | #define MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH 64 |
| 46 | #define CODEC_DT_MAX_PROP_SIZE 40 |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 47 | |
| 48 | static unsigned long rx_digital_gain_reg[] = { |
| 49 | MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, |
| 50 | MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, |
| 51 | MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, |
| 52 | }; |
| 53 | |
| 54 | static unsigned long tx_digital_gain_reg[] = { |
| 55 | MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, |
| 56 | MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, |
| 57 | MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, |
| 58 | MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, |
| 59 | }; |
| 60 | |
| 61 | #define SDM660_TX_UNMUTE_DELAY_MS 40 |
| 62 | static int tx_unmute_delay = SDM660_TX_UNMUTE_DELAY_MS; |
| 63 | module_param(tx_unmute_delay, int, 0664); |
| 64 | MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); |
| 65 | |
| 66 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 67 | |
| 68 | struct snd_soc_codec *registered_digcodec; |
| 69 | struct hpf_work tx_hpf_work[NUM_DECIMATORS]; |
| 70 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 71 | static int msm_dig_cdc_enable_on_demand_supply( |
| 72 | struct snd_soc_dapm_widget *w, |
| 73 | struct snd_kcontrol *kcontrol, int event); |
| 74 | static char on_demand_supply_name[][MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH] = { |
| 75 | "cdc-vdd-digital", |
| 76 | }; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 77 | /* Codec supports 2 IIR filters */ |
| 78 | enum { |
| 79 | IIR1 = 0, |
| 80 | IIR2, |
| 81 | IIR_MAX, |
| 82 | }; |
| 83 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 84 | /* |
| 85 | * msm_digcdc_mclk_enable - add mclk support in digital codec |
| 86 | * @codec: codec instance |
| 87 | * @mclk_enable: mclk enable/disable |
| 88 | * @dapm: check for dapm widget |
| 89 | */ |
| 90 | int msm_digcdc_mclk_enable(struct snd_soc_codec *codec, |
| 91 | int mclk_enable, bool dapm) |
| 92 | { |
| 93 | dev_dbg(codec->dev, "%s: mclk_enable = %u, dapm = %d\n", |
| 94 | __func__, mclk_enable, dapm); |
| 95 | if (mclk_enable) { |
| 96 | snd_soc_update_bits(codec, |
| 97 | MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); |
| 98 | snd_soc_update_bits(codec, |
| 99 | MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); |
| 100 | } else { |
| 101 | snd_soc_update_bits(codec, |
| 102 | MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x00); |
| 103 | snd_soc_update_bits(codec, |
| 104 | MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); |
| 105 | } |
| 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | EXPORT_SYMBOL(msm_digcdc_mclk_enable); |
| 110 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 111 | static int msm_digcdc_clock_control(bool flag) |
| 112 | { |
| 113 | int ret = -EINVAL; |
| 114 | struct msm_asoc_mach_data *pdata = NULL; |
| 115 | struct msm_dig_priv *msm_dig_cdc = |
| 116 | snd_soc_codec_get_drvdata(registered_digcodec); |
| 117 | |
| 118 | pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card); |
| 119 | |
| 120 | if (flag) { |
| 121 | mutex_lock(&pdata->cdc_int_mclk0_mutex); |
| 122 | if (atomic_read(&pdata->int_mclk0_enabled) == false) { |
Soumya Managoli | cab5e1c | 2018-04-30 15:32:01 +0530 | [diff] [blame] | 123 | if (msm_dig_cdc->regmap->cache_only == true) |
| 124 | return ret; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 125 | pdata->digital_cdc_core_clk.clk_freq_in_hz = |
| 126 | DEFAULT_MCLK_RATE; |
| 127 | pdata->digital_cdc_core_clk.enable = 1; |
| 128 | ret = afe_set_lpass_clock_v2( |
| 129 | AFE_PORT_ID_PRIMARY_MI2S_RX, |
| 130 | &pdata->digital_cdc_core_clk); |
| 131 | if (ret < 0) { |
| 132 | pr_err("%s:failed to enable the MCLK\n", |
| 133 | __func__); |
| 134 | /* |
| 135 | * Avoid access to lpass register |
| 136 | * as clock enable failed during SSR. |
| 137 | */ |
Soumya Managoli | cab5e1c | 2018-04-30 15:32:01 +0530 | [diff] [blame] | 138 | msm_dig_cdc->regmap->cache_only = true; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 139 | return ret; |
| 140 | } |
| 141 | pr_debug("enabled digital codec core clk\n"); |
| 142 | atomic_set(&pdata->int_mclk0_enabled, true); |
| 143 | schedule_delayed_work(&pdata->disable_int_mclk0_work, |
| 144 | 50); |
| 145 | } |
| 146 | } else { |
| 147 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
| 148 | dev_dbg(registered_digcodec->dev, |
| 149 | "disable MCLK, workq to disable set already\n"); |
| 150 | } |
| 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static void enable_digital_callback(void *flag) |
| 155 | { |
| 156 | msm_digcdc_clock_control(true); |
| 157 | } |
| 158 | |
| 159 | static void disable_digital_callback(void *flag) |
| 160 | { |
| 161 | msm_digcdc_clock_control(false); |
| 162 | pr_debug("disable mclk happens in workq\n"); |
| 163 | } |
| 164 | |
| 165 | static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol, |
| 166 | struct snd_ctl_elem_value *ucontrol) |
| 167 | { |
| 168 | struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); |
| 169 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 170 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 171 | unsigned int dec_mux, decimator; |
| 172 | char *dec_name = NULL; |
| 173 | char *widget_name = NULL; |
| 174 | char *temp; |
| 175 | u16 tx_mux_ctl_reg; |
| 176 | u8 adc_dmic_sel = 0x0; |
| 177 | int ret = 0; |
| 178 | char *dec_num; |
| 179 | |
| 180 | if (ucontrol->value.enumerated.item[0] > e->items) { |
| 181 | dev_err(codec->dev, "%s: Invalid enum value: %d\n", |
| 182 | __func__, ucontrol->value.enumerated.item[0]); |
| 183 | return -EINVAL; |
| 184 | } |
| 185 | dec_mux = ucontrol->value.enumerated.item[0]; |
| 186 | |
| 187 | widget_name = kstrndup(w->name, 15, GFP_KERNEL); |
| 188 | if (!widget_name) { |
| 189 | dev_err(codec->dev, "%s: failed to copy string\n", |
| 190 | __func__); |
| 191 | return -ENOMEM; |
| 192 | } |
| 193 | temp = widget_name; |
| 194 | |
| 195 | dec_name = strsep(&widget_name, " "); |
| 196 | widget_name = temp; |
| 197 | if (!dec_name) { |
| 198 | dev_err(codec->dev, "%s: Invalid decimator = %s\n", |
| 199 | __func__, w->name); |
| 200 | ret = -EINVAL; |
| 201 | goto out; |
| 202 | } |
| 203 | |
| 204 | dec_num = strpbrk(dec_name, "12"); |
| 205 | if (dec_num == NULL) { |
| 206 | dev_err(codec->dev, "%s: Invalid DEC selected\n", __func__); |
| 207 | ret = -EINVAL; |
| 208 | goto out; |
| 209 | } |
| 210 | |
| 211 | ret = kstrtouint(dec_num, 10, &decimator); |
| 212 | if (ret < 0) { |
| 213 | dev_err(codec->dev, "%s: Invalid decimator = %s\n", |
| 214 | __func__, dec_name); |
| 215 | ret = -EINVAL; |
| 216 | goto out; |
| 217 | } |
| 218 | |
| 219 | dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n" |
| 220 | , __func__, w->name, decimator, dec_mux); |
| 221 | |
| 222 | switch (decimator) { |
| 223 | case 1: |
| 224 | case 2: |
| 225 | if ((dec_mux == 4) || (dec_mux == 5)) |
| 226 | adc_dmic_sel = 0x1; |
| 227 | else |
| 228 | adc_dmic_sel = 0x0; |
| 229 | break; |
| 230 | default: |
| 231 | dev_err(codec->dev, "%s: Invalid Decimator = %u\n", |
| 232 | __func__, decimator); |
| 233 | ret = -EINVAL; |
| 234 | goto out; |
| 235 | } |
| 236 | |
| 237 | tx_mux_ctl_reg = |
| 238 | MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1); |
| 239 | |
| 240 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x1, adc_dmic_sel); |
| 241 | |
| 242 | ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 243 | |
| 244 | out: |
| 245 | kfree(widget_name); |
| 246 | return ret; |
| 247 | } |
| 248 | |
| 249 | |
| 250 | static int msm_dig_cdc_codec_config_compander(struct snd_soc_codec *codec, |
| 251 | int interp_n, int event) |
| 252 | { |
| 253 | struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 254 | int comp_ch_bits_set = 0x03; |
| 255 | int comp_ch_value; |
| 256 | |
| 257 | dev_dbg(codec->dev, "%s: event %d shift %d, enabled %d\n", |
| 258 | __func__, event, interp_n, |
| 259 | dig_cdc->comp_enabled[interp_n]); |
| 260 | |
| 261 | /* compander is invalid */ |
| 262 | if (dig_cdc->comp_enabled[interp_n] != COMPANDER_1 && |
| 263 | dig_cdc->comp_enabled[interp_n]) { |
| 264 | dev_dbg(codec->dev, "%s: Invalid compander %d\n", __func__, |
| 265 | dig_cdc->comp_enabled[interp_n]); |
| 266 | return 0; |
| 267 | } |
| 268 | |
| 269 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 270 | /* compander is not enabled */ |
| 271 | if (!dig_cdc->comp_enabled[interp_n]) { |
| 272 | dig_cdc->set_compander_mode(dig_cdc->handle, 0x00); |
| 273 | return 0; |
| 274 | }; |
| 275 | comp_ch_value = snd_soc_read(codec, |
| 276 | MSM89XX_CDC_CORE_COMP0_B1_CTL); |
| 277 | if (interp_n == 0) { |
| 278 | if (comp_ch_value & 0x02) { |
| 279 | dev_dbg(codec->dev, |
| 280 | "%s comp ch 1 already enabled\n", |
| 281 | __func__); |
| 282 | return 0; |
| 283 | } |
| 284 | } |
| 285 | if (interp_n == 1) { |
| 286 | if (comp_ch_value & 0x01) { |
| 287 | dev_dbg(codec->dev, |
| 288 | "%s comp ch 0 already enabled\n", |
| 289 | __func__); |
| 290 | return 0; |
| 291 | } |
| 292 | } |
| 293 | dig_cdc->set_compander_mode(dig_cdc->handle, 0x08); |
| 294 | /* Enable Compander Clock */ |
| 295 | snd_soc_update_bits(codec, |
| 296 | MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); |
| 297 | snd_soc_update_bits(codec, |
| 298 | MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); |
| 299 | if (dig_cdc->comp_enabled[MSM89XX_RX1]) { |
| 300 | snd_soc_update_bits(codec, |
| 301 | MSM89XX_CDC_CORE_COMP0_B1_CTL, |
| 302 | 0x02, 0x02); |
| 303 | } |
| 304 | if (dig_cdc->comp_enabled[MSM89XX_RX2]) { |
| 305 | snd_soc_update_bits(codec, |
| 306 | MSM89XX_CDC_CORE_COMP0_B1_CTL, |
| 307 | 0x01, 0x01); |
| 308 | } |
| 309 | snd_soc_update_bits(codec, |
| 310 | MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); |
| 311 | snd_soc_update_bits(codec, |
| 312 | MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0x50); |
| 313 | /* add sleep for compander to settle */ |
| 314 | usleep_range(1000, 1100); |
| 315 | snd_soc_update_bits(codec, |
| 316 | MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x28); |
| 317 | snd_soc_update_bits(codec, |
| 318 | MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0xB0); |
| 319 | |
| 320 | /* Enable Compander GPIO */ |
| 321 | if (dig_cdc->codec_hph_comp_gpio) |
| 322 | dig_cdc->codec_hph_comp_gpio(1, codec); |
| 323 | } else if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 324 | /* Disable Compander GPIO */ |
| 325 | if (dig_cdc->codec_hph_comp_gpio) |
| 326 | dig_cdc->codec_hph_comp_gpio(0, codec); |
| 327 | |
| 328 | snd_soc_update_bits(codec, |
| 329 | MSM89XX_CDC_CORE_COMP0_B1_CTL, |
| 330 | 1 << interp_n, 0); |
| 331 | comp_ch_bits_set = snd_soc_read(codec, |
| 332 | MSM89XX_CDC_CORE_COMP0_B1_CTL); |
| 333 | if ((comp_ch_bits_set & 0x03) == 0x00) { |
| 334 | snd_soc_update_bits(codec, |
| 335 | MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x05); |
| 336 | snd_soc_update_bits(codec, |
| 337 | MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x00); |
| 338 | } |
| 339 | } |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | /** |
| 344 | * msm_dig_cdc_hph_comp_cb - registers callback to codec by machine driver. |
| 345 | * |
| 346 | * @codec_hph_comp_gpio: function pointer to set comp gpio at machine driver |
| 347 | * @codec: codec pointer |
| 348 | * |
| 349 | */ |
| 350 | void msm_dig_cdc_hph_comp_cb( |
| 351 | int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec), |
| 352 | struct snd_soc_codec *codec) |
| 353 | { |
| 354 | struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 355 | |
| 356 | pr_debug("%s: Enter\n", __func__); |
| 357 | dig_cdc->codec_hph_comp_gpio = codec_hph_comp_gpio; |
| 358 | } |
| 359 | EXPORT_SYMBOL(msm_dig_cdc_hph_comp_cb); |
| 360 | |
| 361 | static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w, |
| 362 | struct snd_kcontrol *kcontrol, |
| 363 | int event) |
| 364 | { |
| 365 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 366 | struct msm_dig_priv *msm_dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 367 | |
| 368 | dev_dbg(codec->dev, "%s %d %s\n", __func__, event, w->name); |
| 369 | |
| 370 | if (w->shift >= MSM89XX_RX_MAX || w->shift < 0) { |
| 371 | dev_err(codec->dev, "%s: wrong RX index: %d\n", |
| 372 | __func__, w->shift); |
| 373 | return -EINVAL; |
| 374 | } |
| 375 | switch (event) { |
| 376 | case SND_SOC_DAPM_POST_PMU: |
| 377 | msm_dig_cdc_codec_config_compander(codec, w->shift, event); |
| 378 | /* apply the digital gain after the interpolator is enabled*/ |
| 379 | if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg)) |
| 380 | snd_soc_write(codec, |
| 381 | rx_digital_gain_reg[w->shift], |
| 382 | snd_soc_read(codec, |
| 383 | rx_digital_gain_reg[w->shift]) |
| 384 | ); |
| 385 | break; |
| 386 | case SND_SOC_DAPM_POST_PMD: |
| 387 | msm_dig_cdc_codec_config_compander(codec, w->shift, event); |
| 388 | snd_soc_update_bits(codec, |
| 389 | MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, |
| 390 | 1 << w->shift, 1 << w->shift); |
| 391 | snd_soc_update_bits(codec, |
| 392 | MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, |
| 393 | 1 << w->shift, 0x0); |
| 394 | /* |
| 395 | * disable the mute enabled during the PMD of this device |
| 396 | */ |
| 397 | if ((w->shift == 0) && |
| 398 | (msm_dig_cdc->mute_mask & HPHL_PA_DISABLE)) { |
| 399 | pr_debug("disabling HPHL mute\n"); |
| 400 | snd_soc_update_bits(codec, |
| 401 | MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); |
| 402 | msm_dig_cdc->mute_mask &= ~(HPHL_PA_DISABLE); |
| 403 | } else if ((w->shift == 1) && |
| 404 | (msm_dig_cdc->mute_mask & HPHR_PA_DISABLE)) { |
| 405 | pr_debug("disabling HPHR mute\n"); |
| 406 | snd_soc_update_bits(codec, |
| 407 | MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); |
| 408 | msm_dig_cdc->mute_mask &= ~(HPHR_PA_DISABLE); |
| 409 | } else if ((w->shift == 2) && |
| 410 | (msm_dig_cdc->mute_mask & SPKR_PA_DISABLE)) { |
| 411 | pr_debug("disabling SPKR mute\n"); |
| 412 | snd_soc_update_bits(codec, |
| 413 | MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); |
| 414 | msm_dig_cdc->mute_mask &= ~(SPKR_PA_DISABLE); |
| 415 | } |
| 416 | } |
| 417 | return 0; |
| 418 | } |
| 419 | |
| 420 | static int msm_dig_cdc_get_iir_enable_audio_mixer( |
| 421 | struct snd_kcontrol *kcontrol, |
| 422 | struct snd_ctl_elem_value *ucontrol) |
| 423 | { |
| 424 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 425 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 426 | kcontrol->private_value)->reg; |
| 427 | int band_idx = ((struct soc_multi_mixer_control *) |
| 428 | kcontrol->private_value)->shift; |
| 429 | |
| 430 | ucontrol->value.integer.value[0] = |
| 431 | (snd_soc_read(codec, |
| 432 | (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & |
| 433 | (1 << band_idx)) != 0; |
| 434 | |
| 435 | dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
| 436 | iir_idx, band_idx, |
| 437 | (uint32_t)ucontrol->value.integer.value[0]); |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static int msm_dig_cdc_put_iir_enable_audio_mixer( |
| 442 | struct snd_kcontrol *kcontrol, |
| 443 | struct snd_ctl_elem_value *ucontrol) |
| 444 | { |
| 445 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 446 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 447 | kcontrol->private_value)->reg; |
| 448 | int band_idx = ((struct soc_multi_mixer_control *) |
| 449 | kcontrol->private_value)->shift; |
| 450 | int value = ucontrol->value.integer.value[0]; |
| 451 | |
| 452 | /* Mask first 5 bits, 6-8 are reserved */ |
| 453 | snd_soc_update_bits(codec, |
| 454 | (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx), |
| 455 | (1 << band_idx), (value << band_idx)); |
| 456 | |
| 457 | dev_dbg(codec->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
| 458 | iir_idx, band_idx, |
| 459 | ((snd_soc_read(codec, |
| 460 | (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & |
| 461 | (1 << band_idx)) != 0)); |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | static uint32_t get_iir_band_coeff(struct snd_soc_codec *codec, |
| 467 | int iir_idx, int band_idx, |
| 468 | int coeff_idx) |
| 469 | { |
| 470 | uint32_t value = 0; |
| 471 | |
| 472 | /* Address does not automatically update if reading */ |
| 473 | snd_soc_write(codec, |
| 474 | (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), |
| 475 | ((band_idx * BAND_MAX + coeff_idx) |
| 476 | * sizeof(uint32_t)) & 0x7F); |
| 477 | |
| 478 | value |= snd_soc_read(codec, |
| 479 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)); |
| 480 | |
| 481 | snd_soc_write(codec, |
| 482 | (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), |
| 483 | ((band_idx * BAND_MAX + coeff_idx) |
| 484 | * sizeof(uint32_t) + 1) & 0x7F); |
| 485 | |
| 486 | value |= (snd_soc_read(codec, |
| 487 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8); |
| 488 | |
| 489 | snd_soc_write(codec, |
| 490 | (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), |
| 491 | ((band_idx * BAND_MAX + coeff_idx) |
| 492 | * sizeof(uint32_t) + 2) & 0x7F); |
| 493 | |
| 494 | value |= (snd_soc_read(codec, |
| 495 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16); |
| 496 | |
| 497 | snd_soc_write(codec, |
| 498 | (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), |
| 499 | ((band_idx * BAND_MAX + coeff_idx) |
| 500 | * sizeof(uint32_t) + 3) & 0x7F); |
| 501 | |
| 502 | /* Mask bits top 2 bits since they are reserved */ |
| 503 | value |= ((snd_soc_read(codec, (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL |
| 504 | + 64 * iir_idx)) & 0x3f) << 24); |
| 505 | |
| 506 | return value; |
| 507 | |
| 508 | } |
| 509 | |
| 510 | static void set_iir_band_coeff(struct snd_soc_codec *codec, |
| 511 | int iir_idx, int band_idx, |
| 512 | uint32_t value) |
| 513 | { |
| 514 | snd_soc_write(codec, |
| 515 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), |
| 516 | (value & 0xFF)); |
| 517 | |
| 518 | snd_soc_write(codec, |
| 519 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), |
| 520 | (value >> 8) & 0xFF); |
| 521 | |
| 522 | snd_soc_write(codec, |
| 523 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), |
| 524 | (value >> 16) & 0xFF); |
| 525 | |
| 526 | /* Mask top 2 bits, 7-8 are reserved */ |
| 527 | snd_soc_write(codec, |
| 528 | (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), |
| 529 | (value >> 24) & 0x3F); |
| 530 | |
| 531 | } |
| 532 | |
| 533 | static int msm_dig_cdc_get_iir_band_audio_mixer( |
| 534 | struct snd_kcontrol *kcontrol, |
| 535 | struct snd_ctl_elem_value *ucontrol) |
| 536 | { |
| 537 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 538 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 539 | kcontrol->private_value)->reg; |
| 540 | int band_idx = ((struct soc_multi_mixer_control *) |
| 541 | kcontrol->private_value)->shift; |
| 542 | |
| 543 | ucontrol->value.integer.value[0] = |
| 544 | get_iir_band_coeff(codec, iir_idx, band_idx, 0); |
| 545 | ucontrol->value.integer.value[1] = |
| 546 | get_iir_band_coeff(codec, iir_idx, band_idx, 1); |
| 547 | ucontrol->value.integer.value[2] = |
| 548 | get_iir_band_coeff(codec, iir_idx, band_idx, 2); |
| 549 | ucontrol->value.integer.value[3] = |
| 550 | get_iir_band_coeff(codec, iir_idx, band_idx, 3); |
| 551 | ucontrol->value.integer.value[4] = |
| 552 | get_iir_band_coeff(codec, iir_idx, band_idx, 4); |
| 553 | |
| 554 | dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" |
| 555 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 556 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 557 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 558 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 559 | __func__, iir_idx, band_idx, |
| 560 | (uint32_t)ucontrol->value.integer.value[0], |
| 561 | __func__, iir_idx, band_idx, |
| 562 | (uint32_t)ucontrol->value.integer.value[1], |
| 563 | __func__, iir_idx, band_idx, |
| 564 | (uint32_t)ucontrol->value.integer.value[2], |
| 565 | __func__, iir_idx, band_idx, |
| 566 | (uint32_t)ucontrol->value.integer.value[3], |
| 567 | __func__, iir_idx, band_idx, |
| 568 | (uint32_t)ucontrol->value.integer.value[4]); |
| 569 | return 0; |
| 570 | } |
| 571 | |
| 572 | static int msm_dig_cdc_put_iir_band_audio_mixer( |
| 573 | struct snd_kcontrol *kcontrol, |
| 574 | struct snd_ctl_elem_value *ucontrol) |
| 575 | { |
| 576 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 577 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 578 | kcontrol->private_value)->reg; |
| 579 | int band_idx = ((struct soc_multi_mixer_control *) |
| 580 | kcontrol->private_value)->shift; |
| 581 | |
| 582 | /* Mask top bit it is reserved */ |
| 583 | /* Updates addr automatically for each B2 write */ |
| 584 | snd_soc_write(codec, |
| 585 | (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), |
| 586 | (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); |
| 587 | |
| 588 | |
| 589 | set_iir_band_coeff(codec, iir_idx, band_idx, |
| 590 | ucontrol->value.integer.value[0]); |
| 591 | set_iir_band_coeff(codec, iir_idx, band_idx, |
| 592 | ucontrol->value.integer.value[1]); |
| 593 | set_iir_band_coeff(codec, iir_idx, band_idx, |
| 594 | ucontrol->value.integer.value[2]); |
| 595 | set_iir_band_coeff(codec, iir_idx, band_idx, |
| 596 | ucontrol->value.integer.value[3]); |
| 597 | set_iir_band_coeff(codec, iir_idx, band_idx, |
| 598 | ucontrol->value.integer.value[4]); |
| 599 | |
| 600 | dev_dbg(codec->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" |
| 601 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 602 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 603 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 604 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 605 | __func__, iir_idx, band_idx, |
| 606 | get_iir_band_coeff(codec, iir_idx, band_idx, 0), |
| 607 | __func__, iir_idx, band_idx, |
| 608 | get_iir_band_coeff(codec, iir_idx, band_idx, 1), |
| 609 | __func__, iir_idx, band_idx, |
| 610 | get_iir_band_coeff(codec, iir_idx, band_idx, 2), |
| 611 | __func__, iir_idx, band_idx, |
| 612 | get_iir_band_coeff(codec, iir_idx, band_idx, 3), |
| 613 | __func__, iir_idx, band_idx, |
| 614 | get_iir_band_coeff(codec, iir_idx, band_idx, 4)); |
| 615 | return 0; |
| 616 | } |
| 617 | |
| 618 | static void tx_hpf_corner_freq_callback(struct work_struct *work) |
| 619 | { |
| 620 | struct delayed_work *hpf_delayed_work; |
| 621 | struct hpf_work *hpf_work; |
| 622 | struct snd_soc_codec *codec; |
| 623 | struct msm_dig_priv *msm_dig_cdc; |
| 624 | u16 tx_mux_ctl_reg; |
| 625 | u8 hpf_cut_of_freq; |
| 626 | |
| 627 | hpf_delayed_work = to_delayed_work(work); |
| 628 | hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); |
| 629 | codec = hpf_work->dig_cdc->codec; |
| 630 | msm_dig_cdc = hpf_work->dig_cdc; |
| 631 | hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq; |
| 632 | |
| 633 | tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + |
| 634 | (hpf_work->decimator - 1) * 32; |
| 635 | |
| 636 | dev_dbg(codec->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n", |
| 637 | __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 638 | if (msm_dig_cdc->update_clkdiv) |
| 639 | msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 640 | |
| 641 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4); |
| 642 | } |
| 643 | |
| 644 | static int msm_dig_cdc_codec_set_iir_gain(struct snd_soc_dapm_widget *w, |
| 645 | struct snd_kcontrol *kcontrol, int event) |
| 646 | { |
| 647 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 648 | int value = 0, reg; |
| 649 | |
| 650 | switch (event) { |
| 651 | case SND_SOC_DAPM_POST_PMU: |
| 652 | if (w->shift == 0) |
| 653 | reg = MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL; |
| 654 | else if (w->shift == 1) |
| 655 | reg = MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL; |
| 656 | else |
| 657 | goto ret; |
| 658 | value = snd_soc_read(codec, reg); |
| 659 | snd_soc_write(codec, reg, value); |
| 660 | break; |
| 661 | default: |
| 662 | pr_err("%s: event = %d not expected\n", __func__, event); |
| 663 | } |
| 664 | ret: |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int msm_dig_cdc_compander_get(struct snd_kcontrol *kcontrol, |
| 669 | struct snd_ctl_elem_value *ucontrol) |
| 670 | { |
| 671 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 672 | struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 673 | int comp_idx = ((struct soc_multi_mixer_control *) |
| 674 | kcontrol->private_value)->reg; |
| 675 | int rx_idx = ((struct soc_multi_mixer_control *) |
| 676 | kcontrol->private_value)->shift; |
| 677 | |
| 678 | dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", |
| 679 | __func__, comp_idx, rx_idx, |
| 680 | dig_cdc->comp_enabled[rx_idx]); |
| 681 | |
| 682 | ucontrol->value.integer.value[0] = dig_cdc->comp_enabled[rx_idx]; |
| 683 | |
| 684 | dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
| 685 | __func__, ucontrol->value.integer.value[0]); |
| 686 | |
| 687 | return 0; |
| 688 | } |
| 689 | |
| 690 | static int msm_dig_cdc_compander_set(struct snd_kcontrol *kcontrol, |
| 691 | struct snd_ctl_elem_value *ucontrol) |
| 692 | { |
| 693 | struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); |
| 694 | struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 695 | int comp_idx = ((struct soc_multi_mixer_control *) |
| 696 | kcontrol->private_value)->reg; |
| 697 | int rx_idx = ((struct soc_multi_mixer_control *) |
| 698 | kcontrol->private_value)->shift; |
| 699 | int value = ucontrol->value.integer.value[0]; |
| 700 | |
| 701 | dev_dbg(codec->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
| 702 | __func__, ucontrol->value.integer.value[0]); |
| 703 | |
| 704 | if (dig_cdc->version >= DIANGU) { |
| 705 | if (!value) |
| 706 | dig_cdc->comp_enabled[rx_idx] = 0; |
| 707 | else |
| 708 | dig_cdc->comp_enabled[rx_idx] = comp_idx; |
| 709 | } |
| 710 | |
| 711 | dev_dbg(codec->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", |
| 712 | __func__, comp_idx, rx_idx, |
| 713 | dig_cdc->comp_enabled[rx_idx]); |
| 714 | |
| 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | static const struct snd_kcontrol_new compander_kcontrols[] = { |
| 719 | SOC_SINGLE_EXT("COMP0 RX1", COMPANDER_1, MSM89XX_RX1, 1, 0, |
| 720 | msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), |
| 721 | |
| 722 | SOC_SINGLE_EXT("COMP0 RX2", COMPANDER_1, MSM89XX_RX2, 1, 0, |
| 723 | msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), |
| 724 | |
| 725 | }; |
| 726 | |
| 727 | static int msm_dig_cdc_set_interpolator_rate(struct snd_soc_dai *dai, |
| 728 | u8 rx_fs_rate_reg_val, |
| 729 | u32 sample_rate) |
| 730 | { |
| 731 | snd_soc_update_bits(dai->codec, |
| 732 | MSM89XX_CDC_CORE_RX1_B5_CTL, 0xF0, rx_fs_rate_reg_val); |
| 733 | snd_soc_update_bits(dai->codec, |
| 734 | MSM89XX_CDC_CORE_RX2_B5_CTL, 0xF0, rx_fs_rate_reg_val); |
| 735 | return 0; |
| 736 | } |
| 737 | |
| 738 | static int msm_dig_cdc_hw_params(struct snd_pcm_substream *substream, |
| 739 | struct snd_pcm_hw_params *params, |
| 740 | struct snd_soc_dai *dai) |
| 741 | { |
| 742 | u8 tx_fs_rate, rx_fs_rate, rx_clk_fs_rate; |
| 743 | int ret; |
| 744 | |
| 745 | dev_dbg(dai->codec->dev, |
| 746 | "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n", |
| 747 | __func__, dai->name, dai->id, params_rate(params), |
| 748 | params_channels(params), params_format(params)); |
| 749 | |
| 750 | switch (params_rate(params)) { |
| 751 | case 8000: |
| 752 | tx_fs_rate = 0x00; |
| 753 | rx_fs_rate = 0x00; |
| 754 | rx_clk_fs_rate = 0x00; |
| 755 | break; |
| 756 | case 16000: |
| 757 | tx_fs_rate = 0x20; |
| 758 | rx_fs_rate = 0x20; |
| 759 | rx_clk_fs_rate = 0x01; |
| 760 | break; |
| 761 | case 32000: |
| 762 | tx_fs_rate = 0x40; |
| 763 | rx_fs_rate = 0x40; |
| 764 | rx_clk_fs_rate = 0x02; |
| 765 | break; |
| 766 | case 44100: |
| 767 | case 48000: |
| 768 | tx_fs_rate = 0x60; |
| 769 | rx_fs_rate = 0x60; |
| 770 | rx_clk_fs_rate = 0x03; |
| 771 | break; |
| 772 | case 96000: |
| 773 | tx_fs_rate = 0x80; |
| 774 | rx_fs_rate = 0x80; |
| 775 | rx_clk_fs_rate = 0x04; |
| 776 | break; |
| 777 | case 192000: |
| 778 | tx_fs_rate = 0xA0; |
| 779 | rx_fs_rate = 0xA0; |
| 780 | rx_clk_fs_rate = 0x05; |
| 781 | break; |
| 782 | default: |
| 783 | dev_err(dai->codec->dev, |
| 784 | "%s: Invalid sampling rate %d\n", __func__, |
| 785 | params_rate(params)); |
| 786 | return -EINVAL; |
| 787 | } |
| 788 | |
| 789 | snd_soc_update_bits(dai->codec, |
| 790 | MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x0F, rx_clk_fs_rate); |
| 791 | |
| 792 | switch (substream->stream) { |
| 793 | case SNDRV_PCM_STREAM_CAPTURE: |
| 794 | break; |
| 795 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 796 | ret = msm_dig_cdc_set_interpolator_rate(dai, rx_fs_rate, |
| 797 | params_rate(params)); |
| 798 | if (ret < 0) { |
| 799 | dev_err(dai->codec->dev, |
| 800 | "%s: set decimator rate failed %d\n", __func__, |
| 801 | ret); |
| 802 | return ret; |
| 803 | } |
| 804 | break; |
| 805 | default: |
| 806 | dev_err(dai->codec->dev, |
| 807 | "%s: Invalid stream type %d\n", __func__, |
| 808 | substream->stream); |
| 809 | return -EINVAL; |
| 810 | } |
| 811 | switch (params_format(params)) { |
| 812 | case SNDRV_PCM_FORMAT_S16_LE: |
| 813 | snd_soc_update_bits(dai->codec, |
| 814 | MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x20); |
| 815 | break; |
| 816 | case SNDRV_PCM_FORMAT_S24_LE: |
| 817 | case SNDRV_PCM_FORMAT_S24_3LE: |
| 818 | snd_soc_update_bits(dai->codec, |
| 819 | MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x00); |
| 820 | break; |
| 821 | default: |
| 822 | dev_err(dai->codec->dev, "%s: wrong format selected\n", |
| 823 | __func__); |
| 824 | return -EINVAL; |
| 825 | } |
| 826 | return 0; |
| 827 | } |
| 828 | |
| 829 | static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w, |
| 830 | struct snd_kcontrol *kcontrol, |
| 831 | int event) |
| 832 | { |
| 833 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 834 | struct msm_dig_priv *dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 835 | u8 dmic_clk_en; |
| 836 | u16 dmic_clk_reg; |
| 837 | s32 *dmic_clk_cnt; |
| 838 | unsigned int dmic; |
| 839 | int ret; |
| 840 | char *dmic_num = strpbrk(w->name, "12"); |
| 841 | |
| 842 | if (dmic_num == NULL) { |
| 843 | dev_err(codec->dev, "%s: Invalid DMIC\n", __func__); |
| 844 | return -EINVAL; |
| 845 | } |
| 846 | |
| 847 | ret = kstrtouint(dmic_num, 10, &dmic); |
| 848 | if (ret < 0) { |
| 849 | dev_err(codec->dev, |
| 850 | "%s: Invalid DMIC line on the codec\n", __func__); |
| 851 | return -EINVAL; |
| 852 | } |
| 853 | |
| 854 | switch (dmic) { |
| 855 | case 1: |
| 856 | case 2: |
| 857 | dmic_clk_en = 0x01; |
| 858 | dmic_clk_cnt = &(dig_cdc->dmic_1_2_clk_cnt); |
| 859 | dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL; |
| 860 | dev_dbg(codec->dev, |
| 861 | "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n", |
| 862 | __func__, event, dmic, *dmic_clk_cnt); |
| 863 | break; |
| 864 | default: |
| 865 | dev_err(codec->dev, "%s: Invalid DMIC Selection\n", __func__); |
| 866 | return -EINVAL; |
| 867 | } |
| 868 | |
| 869 | switch (event) { |
| 870 | case SND_SOC_DAPM_PRE_PMU: |
| 871 | (*dmic_clk_cnt)++; |
| 872 | if (*dmic_clk_cnt == 1) { |
| 873 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 874 | 0x0E, 0x04); |
| 875 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 876 | dmic_clk_en, dmic_clk_en); |
| 877 | } |
| 878 | snd_soc_update_bits(codec, |
| 879 | MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20, |
| 880 | 0x07, 0x02); |
| 881 | break; |
| 882 | case SND_SOC_DAPM_POST_PMD: |
| 883 | (*dmic_clk_cnt)--; |
| 884 | if (*dmic_clk_cnt == 0) |
| 885 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 886 | dmic_clk_en, 0); |
| 887 | break; |
| 888 | } |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w, |
| 893 | struct snd_kcontrol *kcontrol, |
| 894 | int event) |
| 895 | { |
| 896 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 897 | struct msm_asoc_mach_data *pdata = NULL; |
| 898 | unsigned int decimator; |
| 899 | struct msm_dig_priv *msm_dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 900 | char *dec_name = NULL; |
| 901 | char *widget_name = NULL; |
| 902 | char *temp; |
| 903 | int ret = 0, i; |
| 904 | u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; |
| 905 | u8 dec_hpf_cut_of_freq; |
| 906 | int offset; |
| 907 | char *dec_num; |
| 908 | |
| 909 | pdata = snd_soc_card_get_drvdata(codec->component.card); |
| 910 | dev_dbg(codec->dev, "%s %d\n", __func__, event); |
| 911 | |
| 912 | widget_name = kstrndup(w->name, 15, GFP_KERNEL); |
| 913 | if (!widget_name) |
| 914 | return -ENOMEM; |
| 915 | temp = widget_name; |
| 916 | |
| 917 | dec_name = strsep(&widget_name, " "); |
| 918 | widget_name = temp; |
| 919 | if (!dec_name) { |
| 920 | dev_err(codec->dev, |
| 921 | "%s: Invalid decimator = %s\n", __func__, w->name); |
| 922 | ret = -EINVAL; |
| 923 | goto out; |
| 924 | } |
| 925 | |
| 926 | dec_num = strpbrk(dec_name, "1234"); |
| 927 | if (dec_num == NULL) { |
| 928 | dev_err(codec->dev, "%s: Invalid Decimator\n", __func__); |
| 929 | ret = -EINVAL; |
| 930 | goto out; |
| 931 | } |
| 932 | |
| 933 | ret = kstrtouint(dec_num, 10, &decimator); |
| 934 | if (ret < 0) { |
| 935 | dev_err(codec->dev, |
| 936 | "%s: Invalid decimator = %s\n", __func__, dec_name); |
| 937 | ret = -EINVAL; |
| 938 | goto out; |
| 939 | } |
| 940 | |
| 941 | dev_dbg(codec->dev, |
| 942 | "%s(): widget = %s dec_name = %s decimator = %u\n", __func__, |
| 943 | w->name, dec_name, decimator); |
| 944 | |
| 945 | if (w->reg == MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL) { |
| 946 | dec_reset_reg = MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL; |
| 947 | offset = 0; |
| 948 | } else { |
| 949 | dev_err(codec->dev, "%s: Error, incorrect dec\n", __func__); |
| 950 | ret = -EINVAL; |
| 951 | goto out; |
| 952 | } |
| 953 | |
| 954 | tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + |
| 955 | 32 * (decimator - 1); |
| 956 | tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + |
| 957 | 32 * (decimator - 1); |
| 958 | |
| 959 | switch (event) { |
| 960 | case SND_SOC_DAPM_PRE_PMU: |
| 961 | if (decimator == 3 || decimator == 4) { |
| 962 | /* for WSA_VI */ |
| 963 | snd_soc_update_bits(codec, |
| 964 | MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, |
| 965 | 0xFF, 0x5); |
| 966 | snd_soc_update_bits(codec, |
| 967 | MSM89XX_CDC_CORE_TX1_DMIC_CTL + |
| 968 | (decimator - 1) * 0x20, 0x7, 0x2); |
| 969 | snd_soc_update_bits(codec, |
| 970 | MSM89XX_CDC_CORE_TX1_DMIC_CTL + |
| 971 | (decimator - 1) * 0x20, 0x7, 0x2); |
| 972 | } |
| 973 | /* Enableable TX digital mute */ |
| 974 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); |
| 975 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 976 | if (decimator == i + 1) |
| 977 | msm_dig_cdc->dec_active[i] = true; |
| 978 | } |
| 979 | |
| 980 | dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg); |
| 981 | |
| 982 | dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4; |
| 983 | |
| 984 | tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq = |
| 985 | dec_hpf_cut_of_freq; |
| 986 | |
| 987 | if (dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ) { |
| 988 | |
| 989 | /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */ |
| 990 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, |
| 991 | CF_MIN_3DB_150HZ << 4); |
| 992 | } |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 993 | if (msm_dig_cdc->update_clkdiv) |
| 994 | msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x42); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 995 | break; |
| 996 | case SND_SOC_DAPM_POST_PMU: |
| 997 | /* enable HPF */ |
| 998 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x00); |
| 999 | |
| 1000 | schedule_delayed_work( |
| 1001 | &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork, |
| 1002 | msecs_to_jiffies(tx_unmute_delay)); |
| 1003 | if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq != |
| 1004 | CF_MIN_3DB_150HZ) { |
| 1005 | |
| 1006 | schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork, |
| 1007 | msecs_to_jiffies(300)); |
| 1008 | } |
| 1009 | /* apply the digital gain after the decimator is enabled*/ |
| 1010 | if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg)) |
| 1011 | snd_soc_write(codec, |
| 1012 | tx_digital_gain_reg[w->shift + offset], |
| 1013 | snd_soc_read(codec, |
| 1014 | tx_digital_gain_reg[w->shift + offset]) |
| 1015 | ); |
| 1016 | break; |
| 1017 | case SND_SOC_DAPM_PRE_PMD: |
| 1018 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x01); |
| 1019 | msleep(20); |
| 1020 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); |
| 1021 | cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork); |
| 1022 | cancel_delayed_work_sync( |
| 1023 | &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork); |
| 1024 | break; |
| 1025 | case SND_SOC_DAPM_POST_PMD: |
| 1026 | snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, |
| 1027 | 1 << w->shift); |
| 1028 | snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0); |
| 1029 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x08, 0x08); |
| 1030 | snd_soc_update_bits(codec, tx_mux_ctl_reg, 0x30, |
| 1031 | (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4); |
| 1032 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x01, 0x00); |
| 1033 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1034 | if (decimator == i + 1) |
| 1035 | msm_dig_cdc->dec_active[i] = false; |
| 1036 | } |
| 1037 | if (decimator == 3 || decimator == 4) { |
| 1038 | /* for WSA_VI */ |
| 1039 | snd_soc_update_bits(codec, |
| 1040 | MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, |
| 1041 | 0xFF, 0x0); |
| 1042 | snd_soc_update_bits(codec, |
| 1043 | MSM89XX_CDC_CORE_TX1_DMIC_CTL + |
| 1044 | (decimator - 1) * 0x20, 0x7, 0x0); |
| 1045 | snd_soc_update_bits(codec, |
| 1046 | MSM89XX_CDC_CORE_TX1_DMIC_CTL + |
| 1047 | (decimator - 1) * 0x20, 0x7, 0x0); |
| 1048 | } |
| 1049 | break; |
| 1050 | } |
| 1051 | out: |
| 1052 | kfree(widget_name); |
| 1053 | return ret; |
| 1054 | } |
| 1055 | |
| 1056 | static int msm_dig_cdc_event_notify(struct notifier_block *block, |
| 1057 | unsigned long val, |
| 1058 | void *data) |
| 1059 | { |
| 1060 | enum dig_cdc_notify_event event = (enum dig_cdc_notify_event)val; |
| 1061 | struct snd_soc_codec *codec = registered_digcodec; |
| 1062 | struct msm_dig_priv *msm_dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 1063 | struct msm_asoc_mach_data *pdata = NULL; |
| 1064 | int ret = -EINVAL; |
Soumya Managoli | 5cde2af | 2018-03-09 19:05:45 +0530 | [diff] [blame] | 1065 | struct msm_cap_mode *capmode = NULL; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1066 | |
| 1067 | pdata = snd_soc_card_get_drvdata(codec->component.card); |
| 1068 | |
| 1069 | switch (event) { |
| 1070 | case DIG_CDC_EVENT_CLK_ON: |
| 1071 | snd_soc_update_bits(codec, |
| 1072 | MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x03); |
| 1073 | if (pdata->mclk_freq == MCLK_RATE_9P6MHZ) |
| 1074 | snd_soc_update_bits(codec, |
| 1075 | MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); |
| 1076 | snd_soc_update_bits(codec, |
| 1077 | MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); |
| 1078 | break; |
| 1079 | case DIG_CDC_EVENT_CLK_OFF: |
| 1080 | snd_soc_update_bits(codec, |
| 1081 | MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x00); |
| 1082 | snd_soc_update_bits(codec, |
| 1083 | MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); |
| 1084 | break; |
| 1085 | case DIG_CDC_EVENT_RX1_MUTE_ON: |
| 1086 | snd_soc_update_bits(codec, |
| 1087 | MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x01); |
| 1088 | msm_dig_cdc->mute_mask |= HPHL_PA_DISABLE; |
| 1089 | break; |
| 1090 | case DIG_CDC_EVENT_RX1_MUTE_OFF: |
| 1091 | snd_soc_update_bits(codec, |
| 1092 | MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); |
| 1093 | msm_dig_cdc->mute_mask &= (~HPHL_PA_DISABLE); |
| 1094 | break; |
| 1095 | case DIG_CDC_EVENT_RX2_MUTE_ON: |
| 1096 | snd_soc_update_bits(codec, |
| 1097 | MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x01); |
| 1098 | msm_dig_cdc->mute_mask |= HPHR_PA_DISABLE; |
| 1099 | break; |
| 1100 | case DIG_CDC_EVENT_RX2_MUTE_OFF: |
| 1101 | snd_soc_update_bits(codec, |
| 1102 | MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); |
| 1103 | msm_dig_cdc->mute_mask &= (~HPHR_PA_DISABLE); |
| 1104 | break; |
| 1105 | case DIG_CDC_EVENT_RX3_MUTE_ON: |
| 1106 | snd_soc_update_bits(codec, |
| 1107 | MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x01); |
| 1108 | msm_dig_cdc->mute_mask |= SPKR_PA_DISABLE; |
| 1109 | break; |
| 1110 | case DIG_CDC_EVENT_RX3_MUTE_OFF: |
| 1111 | snd_soc_update_bits(codec, |
| 1112 | MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); |
| 1113 | msm_dig_cdc->mute_mask &= (~SPKR_PA_DISABLE); |
| 1114 | break; |
| 1115 | case DIG_CDC_EVENT_PRE_RX1_INT_ON: |
| 1116 | snd_soc_update_bits(codec, |
| 1117 | MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x28); |
| 1118 | snd_soc_update_bits(codec, |
| 1119 | MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10); |
| 1120 | snd_soc_update_bits(codec, |
| 1121 | MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x80); |
| 1122 | break; |
| 1123 | case DIG_CDC_EVENT_PRE_RX2_INT_ON: |
| 1124 | snd_soc_update_bits(codec, |
| 1125 | MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x28); |
| 1126 | snd_soc_update_bits(codec, |
| 1127 | MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10); |
| 1128 | snd_soc_update_bits(codec, |
| 1129 | MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x80); |
| 1130 | break; |
| 1131 | case DIG_CDC_EVENT_POST_RX1_INT_OFF: |
| 1132 | snd_soc_update_bits(codec, |
| 1133 | MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x00); |
| 1134 | snd_soc_update_bits(codec, |
| 1135 | MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF); |
| 1136 | snd_soc_update_bits(codec, |
| 1137 | MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x00); |
| 1138 | break; |
| 1139 | case DIG_CDC_EVENT_POST_RX2_INT_OFF: |
| 1140 | snd_soc_update_bits(codec, |
| 1141 | MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x00); |
| 1142 | snd_soc_update_bits(codec, |
| 1143 | MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF); |
| 1144 | snd_soc_update_bits(codec, |
| 1145 | MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x00); |
| 1146 | break; |
| 1147 | case DIG_CDC_EVENT_SSR_DOWN: |
| 1148 | regcache_cache_only(msm_dig_cdc->regmap, true); |
Soumya Managoli | 5cde2af | 2018-03-09 19:05:45 +0530 | [diff] [blame] | 1149 | mutex_lock(&pdata->cdc_int_mclk0_mutex); |
| 1150 | atomic_set(&pdata->int_mclk0_enabled, false); |
| 1151 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1152 | break; |
| 1153 | case DIG_CDC_EVENT_SSR_UP: |
| 1154 | regcache_cache_only(msm_dig_cdc->regmap, false); |
| 1155 | regcache_mark_dirty(msm_dig_cdc->regmap); |
| 1156 | |
| 1157 | mutex_lock(&pdata->cdc_int_mclk0_mutex); |
| 1158 | pdata->digital_cdc_core_clk.enable = 1; |
| 1159 | ret = afe_set_lpass_clock_v2( |
| 1160 | AFE_PORT_ID_PRIMARY_MI2S_RX, |
| 1161 | &pdata->digital_cdc_core_clk); |
| 1162 | if (ret < 0) { |
| 1163 | pr_err("%s:failed to enable the MCLK\n", |
| 1164 | __func__); |
| 1165 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
| 1166 | break; |
| 1167 | } |
| 1168 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
| 1169 | |
| 1170 | regcache_sync(msm_dig_cdc->regmap); |
| 1171 | |
| 1172 | mutex_lock(&pdata->cdc_int_mclk0_mutex); |
| 1173 | pdata->digital_cdc_core_clk.enable = 0; |
| 1174 | afe_set_lpass_clock_v2( |
| 1175 | AFE_PORT_ID_PRIMARY_MI2S_RX, |
| 1176 | &pdata->digital_cdc_core_clk); |
| 1177 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
| 1178 | break; |
Soumya Managoli | 5cde2af | 2018-03-09 19:05:45 +0530 | [diff] [blame] | 1179 | case DIG_CDC_EVENT_CAP_CONFIGURE: |
| 1180 | capmode = (struct msm_cap_mode *)data; |
| 1181 | capmode->micbias1_cap_mode = pdata->micbias1_cap_mode; |
| 1182 | capmode->micbias2_cap_mode = pdata->micbias2_cap_mode; |
| 1183 | break; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1184 | case DIG_CDC_EVENT_INVALID: |
| 1185 | default: |
| 1186 | break; |
| 1187 | } |
| 1188 | return 0; |
| 1189 | } |
| 1190 | |
| 1191 | static ssize_t msm_dig_codec_version_read(struct snd_info_entry *entry, |
| 1192 | void *file_private_data, |
| 1193 | struct file *file, |
| 1194 | char __user *buf, size_t count, |
| 1195 | loff_t pos) |
| 1196 | { |
| 1197 | struct msm_dig_priv *msm_dig; |
| 1198 | char buffer[MSM_DIG_CDC_VERSION_ENTRY_SIZE]; |
| 1199 | int len = 0; |
| 1200 | |
| 1201 | msm_dig = (struct msm_dig_priv *) entry->private_data; |
| 1202 | if (!msm_dig) { |
| 1203 | pr_err("%s: msm_dig priv is null\n", __func__); |
| 1204 | return -EINVAL; |
| 1205 | } |
| 1206 | |
| 1207 | switch (msm_dig->version) { |
| 1208 | case DRAX_CDC: |
Shashi Kant Maurya | 2232e36 | 2019-07-26 09:48:25 +0530 | [diff] [blame^] | 1209 | case DIANGU: |
| 1210 | case CAJON_2_0: |
| 1211 | case CAJON: |
| 1212 | case CONGA: |
| 1213 | case TOMBAK_2_0: |
| 1214 | case TOMBAK_1_0: |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1215 | len = snprintf(buffer, sizeof(buffer), "SDM660-CDC_1_0\n"); |
| 1216 | break; |
| 1217 | default: |
| 1218 | len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); |
| 1219 | } |
| 1220 | |
| 1221 | return simple_read_from_buffer(buf, count, &pos, buffer, len); |
| 1222 | } |
| 1223 | |
| 1224 | static struct snd_info_entry_ops msm_dig_codec_info_ops = { |
| 1225 | .read = msm_dig_codec_version_read, |
| 1226 | }; |
| 1227 | |
| 1228 | /* |
| 1229 | * msm_dig_codec_info_create_codec_entry - creates msm_dig module |
| 1230 | * @codec_root: The parent directory |
| 1231 | * @codec: Codec instance |
| 1232 | * |
| 1233 | * Creates msm_dig module and version entry under the given |
| 1234 | * parent directory. |
| 1235 | * |
| 1236 | * Return: 0 on success or negative error code on failure. |
| 1237 | */ |
| 1238 | int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, |
| 1239 | struct snd_soc_codec *codec) |
| 1240 | { |
| 1241 | struct snd_info_entry *version_entry; |
| 1242 | struct msm_dig_priv *msm_dig; |
| 1243 | struct snd_soc_card *card; |
| 1244 | |
| 1245 | if (!codec_root || !codec) |
| 1246 | return -EINVAL; |
| 1247 | |
| 1248 | msm_dig = snd_soc_codec_get_drvdata(codec); |
| 1249 | card = codec->component.card; |
| 1250 | msm_dig->entry = snd_info_create_subdir(codec_root->module, |
| 1251 | "msm_digital_codec", |
| 1252 | codec_root); |
| 1253 | if (!msm_dig->entry) { |
| 1254 | dev_dbg(codec->dev, "%s: failed to create msm_digital entry\n", |
| 1255 | __func__); |
| 1256 | return -ENOMEM; |
| 1257 | } |
| 1258 | |
| 1259 | version_entry = snd_info_create_card_entry(card->snd_card, |
| 1260 | "version", |
| 1261 | msm_dig->entry); |
| 1262 | if (!version_entry) { |
| 1263 | dev_dbg(codec->dev, "%s: failed to create msm_digital version entry\n", |
| 1264 | __func__); |
| 1265 | return -ENOMEM; |
| 1266 | } |
| 1267 | |
| 1268 | version_entry->private_data = msm_dig; |
| 1269 | version_entry->size = MSM_DIG_CDC_VERSION_ENTRY_SIZE; |
| 1270 | version_entry->content = SNDRV_INFO_CONTENT_DATA; |
| 1271 | version_entry->c.ops = &msm_dig_codec_info_ops; |
| 1272 | |
| 1273 | if (snd_info_register(version_entry) < 0) { |
| 1274 | snd_info_free_entry(version_entry); |
| 1275 | return -ENOMEM; |
| 1276 | } |
| 1277 | msm_dig->version_entry = version_entry; |
| 1278 | if (msm_dig->get_cdc_version) |
| 1279 | msm_dig->version = msm_dig->get_cdc_version(msm_dig->handle); |
| 1280 | else |
| 1281 | msm_dig->version = DRAX_CDC; |
| 1282 | |
| 1283 | return 0; |
| 1284 | } |
| 1285 | EXPORT_SYMBOL(msm_dig_codec_info_create_codec_entry); |
| 1286 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 1287 | static void msm_dig_cdc_update_micbias_regulator( |
| 1288 | const struct msm_dig_priv *dig_cdc, |
| 1289 | const char *name, |
| 1290 | struct on_demand_dig_supply *micbias_supply) |
| 1291 | { |
| 1292 | int i; |
| 1293 | |
| 1294 | for (i = 0; i < dig_cdc->num_of_supplies; i++) { |
| 1295 | if (dig_cdc->supplies[i].supply && |
| 1296 | !strcmp(dig_cdc->supplies[i].supply, name)) { |
| 1297 | micbias_supply->supply = |
| 1298 | dig_cdc->supplies[i].consumer; |
| 1299 | micbias_supply->min_uv = dig_cdc->regulator[i].min_uv; |
| 1300 | micbias_supply->max_uv = dig_cdc->regulator[i].max_uv; |
| 1301 | micbias_supply->optimum_ua = |
| 1302 | dig_cdc->regulator[i].optimum_ua; |
| 1303 | return; |
| 1304 | } |
| 1305 | } |
| 1306 | |
| 1307 | dev_dbg(dig_cdc->dev, "Error: regulator not found:%s\n", name); |
| 1308 | } |
| 1309 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1310 | static void sdm660_tx_mute_update_callback(struct work_struct *work) |
| 1311 | { |
| 1312 | struct tx_mute_work *tx_mute_dwork; |
| 1313 | struct snd_soc_codec *codec = NULL; |
| 1314 | struct msm_dig_priv *dig_cdc; |
| 1315 | struct delayed_work *delayed_work; |
| 1316 | u16 tx_vol_ctl_reg = 0; |
| 1317 | u8 decimator = 0, i; |
| 1318 | |
| 1319 | delayed_work = to_delayed_work(work); |
| 1320 | tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); |
| 1321 | dig_cdc = tx_mute_dwork->dig_cdc; |
| 1322 | codec = dig_cdc->codec; |
| 1323 | |
| 1324 | for (i = 0; i < (NUM_DECIMATORS - 1); i++) { |
| 1325 | if (dig_cdc->dec_active[i]) |
| 1326 | decimator = i + 1; |
| 1327 | if (decimator && decimator < NUM_DECIMATORS) { |
| 1328 | /* unmute decimators corresponding to Tx DAI's*/ |
| 1329 | tx_vol_ctl_reg = |
| 1330 | MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + |
| 1331 | 32 * (decimator - 1); |
| 1332 | snd_soc_update_bits(codec, tx_vol_ctl_reg, |
| 1333 | 0x01, 0x00); |
| 1334 | } |
| 1335 | decimator = 0; |
| 1336 | } |
| 1337 | } |
| 1338 | static int msm_dig_cdc_soc_probe(struct snd_soc_codec *codec) |
| 1339 | { |
| 1340 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(codec->dev); |
| 1341 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
| 1342 | int i, ret; |
| 1343 | |
| 1344 | msm_dig_cdc->codec = codec; |
| 1345 | snd_soc_add_codec_controls(codec, compander_kcontrols, |
| 1346 | ARRAY_SIZE(compander_kcontrols)); |
| 1347 | |
| 1348 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1349 | tx_hpf_work[i].dig_cdc = msm_dig_cdc; |
| 1350 | tx_hpf_work[i].decimator = i + 1; |
| 1351 | INIT_DELAYED_WORK(&tx_hpf_work[i].dwork, |
| 1352 | tx_hpf_corner_freq_callback); |
| 1353 | msm_dig_cdc->tx_mute_dwork[i].dig_cdc = msm_dig_cdc; |
| 1354 | msm_dig_cdc->tx_mute_dwork[i].decimator = i + 1; |
| 1355 | INIT_DELAYED_WORK(&msm_dig_cdc->tx_mute_dwork[i].dwork, |
| 1356 | sdm660_tx_mute_update_callback); |
| 1357 | } |
| 1358 | |
| 1359 | for (i = 0; i < MSM89XX_RX_MAX; i++) |
| 1360 | msm_dig_cdc->comp_enabled[i] = COMPANDER_NONE; |
| 1361 | |
| 1362 | /* Register event notifier */ |
| 1363 | msm_dig_cdc->nblock.notifier_call = msm_dig_cdc_event_notify; |
| 1364 | if (msm_dig_cdc->register_notifier) { |
| 1365 | ret = msm_dig_cdc->register_notifier(msm_dig_cdc->handle, |
| 1366 | &msm_dig_cdc->nblock, |
| 1367 | true); |
| 1368 | if (ret) { |
| 1369 | pr_err("%s: Failed to register notifier %d\n", |
| 1370 | __func__, ret); |
| 1371 | return ret; |
| 1372 | } |
| 1373 | } |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 1374 | msm_dig_cdc_update_micbias_regulator( |
| 1375 | msm_dig_cdc, |
| 1376 | on_demand_supply_name[ON_DEMAND_DIGITAL], |
| 1377 | &msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL]); |
| 1378 | atomic_set(&msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL].ref, 0); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1379 | registered_digcodec = codec; |
| 1380 | |
| 1381 | snd_soc_dapm_ignore_suspend(dapm, "AIF1 Playback"); |
| 1382 | snd_soc_dapm_ignore_suspend(dapm, "AIF1 Capture"); |
| 1383 | snd_soc_dapm_ignore_suspend(dapm, "ADC1_IN"); |
| 1384 | snd_soc_dapm_ignore_suspend(dapm, "ADC2_IN"); |
| 1385 | snd_soc_dapm_ignore_suspend(dapm, "ADC3_IN"); |
| 1386 | snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX1"); |
| 1387 | snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX2"); |
| 1388 | snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX3"); |
| 1389 | |
| 1390 | snd_soc_dapm_sync(dapm); |
| 1391 | |
| 1392 | return 0; |
| 1393 | } |
| 1394 | |
| 1395 | static int msm_dig_cdc_soc_remove(struct snd_soc_codec *codec) |
| 1396 | { |
| 1397 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(codec->dev); |
| 1398 | |
| 1399 | if (msm_dig_cdc->register_notifier) |
| 1400 | msm_dig_cdc->register_notifier(msm_dig_cdc->handle, |
| 1401 | &msm_dig_cdc->nblock, |
| 1402 | false); |
| 1403 | iounmap(msm_dig_cdc->dig_base); |
| 1404 | return 0; |
| 1405 | } |
| 1406 | |
| 1407 | static const struct snd_soc_dapm_route audio_dig_map[] = { |
| 1408 | {"RX_I2S_CLK", NULL, "CDC_CONN"}, |
| 1409 | {"I2S RX1", NULL, "RX_I2S_CLK"}, |
| 1410 | {"I2S RX2", NULL, "RX_I2S_CLK"}, |
| 1411 | {"I2S RX3", NULL, "RX_I2S_CLK"}, |
| 1412 | |
| 1413 | {"I2S TX1", NULL, "TX_I2S_CLK"}, |
| 1414 | {"I2S TX2", NULL, "TX_I2S_CLK"}, |
| 1415 | {"AIF2 VI", NULL, "TX_I2S_CLK"}, |
| 1416 | |
| 1417 | {"I2S TX1", NULL, "DEC1 MUX"}, |
| 1418 | {"I2S TX2", NULL, "DEC2 MUX"}, |
| 1419 | {"AIF2 VI", NULL, "DEC3 MUX"}, |
| 1420 | {"AIF2 VI", NULL, "DEC4 MUX"}, |
| 1421 | |
| 1422 | {"PDM_OUT_RX1", NULL, "RX1 CHAIN"}, |
| 1423 | {"PDM_OUT_RX2", NULL, "RX2 CHAIN"}, |
| 1424 | {"PDM_OUT_RX3", NULL, "RX3 CHAIN"}, |
| 1425 | |
| 1426 | {"RX1 CHAIN", NULL, "RX1 MIX2"}, |
| 1427 | {"RX2 CHAIN", NULL, "RX2 MIX2"}, |
| 1428 | {"RX3 CHAIN", NULL, "RX3 MIX1"}, |
| 1429 | |
| 1430 | {"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, |
| 1431 | {"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, |
| 1432 | {"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, |
| 1433 | {"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, |
| 1434 | {"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, |
| 1435 | {"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, |
| 1436 | {"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, |
| 1437 | {"RX1 MIX2", NULL, "RX1 MIX1"}, |
| 1438 | {"RX1 MIX2", NULL, "RX1 MIX2 INP1"}, |
| 1439 | {"RX2 MIX2", NULL, "RX2 MIX1"}, |
| 1440 | {"RX2 MIX2", NULL, "RX2 MIX2 INP1"}, |
| 1441 | |
| 1442 | {"RX1 MIX1 INP1", "RX1", "I2S RX1"}, |
| 1443 | {"RX1 MIX1 INP1", "RX2", "I2S RX2"}, |
| 1444 | {"RX1 MIX1 INP1", "RX3", "I2S RX3"}, |
| 1445 | {"RX1 MIX1 INP1", "IIR1", "IIR1"}, |
| 1446 | {"RX1 MIX1 INP1", "IIR2", "IIR2"}, |
| 1447 | {"RX1 MIX1 INP2", "RX1", "I2S RX1"}, |
| 1448 | {"RX1 MIX1 INP2", "RX2", "I2S RX2"}, |
| 1449 | {"RX1 MIX1 INP2", "RX3", "I2S RX3"}, |
| 1450 | {"RX1 MIX1 INP2", "IIR1", "IIR1"}, |
| 1451 | {"RX1 MIX1 INP2", "IIR2", "IIR2"}, |
| 1452 | {"RX1 MIX1 INP3", "RX1", "I2S RX1"}, |
| 1453 | {"RX1 MIX1 INP3", "RX2", "I2S RX2"}, |
| 1454 | {"RX1 MIX1 INP3", "RX3", "I2S RX3"}, |
| 1455 | |
| 1456 | {"RX2 MIX1 INP1", "RX1", "I2S RX1"}, |
| 1457 | {"RX2 MIX1 INP1", "RX2", "I2S RX2"}, |
| 1458 | {"RX2 MIX1 INP1", "RX3", "I2S RX3"}, |
| 1459 | {"RX2 MIX1 INP1", "IIR1", "IIR1"}, |
| 1460 | {"RX2 MIX1 INP1", "IIR2", "IIR2"}, |
| 1461 | {"RX2 MIX1 INP2", "RX1", "I2S RX1"}, |
| 1462 | {"RX2 MIX1 INP2", "RX2", "I2S RX2"}, |
| 1463 | {"RX2 MIX1 INP2", "RX3", "I2S RX3"}, |
| 1464 | {"RX2 MIX1 INP2", "IIR1", "IIR1"}, |
| 1465 | {"RX2 MIX1 INP2", "IIR2", "IIR2"}, |
| 1466 | {"RX2 MIX1 INP3", "RX1", "I2S RX1"}, |
| 1467 | {"RX2 MIX1 INP3", "RX2", "I2S RX2"}, |
| 1468 | {"RX2 MIX1 INP3", "RX3", "I2S RX3"}, |
| 1469 | |
| 1470 | {"RX3 MIX1 INP1", "RX1", "I2S RX1"}, |
| 1471 | {"RX3 MIX1 INP1", "RX2", "I2S RX2"}, |
| 1472 | {"RX3 MIX1 INP1", "RX3", "I2S RX3"}, |
| 1473 | {"RX3 MIX1 INP1", "IIR1", "IIR1"}, |
| 1474 | {"RX3 MIX1 INP1", "IIR2", "IIR2"}, |
| 1475 | {"RX3 MIX1 INP2", "RX1", "I2S RX1"}, |
| 1476 | {"RX3 MIX1 INP2", "RX2", "I2S RX2"}, |
| 1477 | {"RX3 MIX1 INP2", "RX3", "I2S RX3"}, |
| 1478 | {"RX3 MIX1 INP2", "IIR1", "IIR1"}, |
| 1479 | {"RX3 MIX1 INP2", "IIR2", "IIR2"}, |
| 1480 | {"RX3 MIX1 INP3", "RX1", "I2S RX1"}, |
| 1481 | {"RX3 MIX1 INP3", "RX2", "I2S RX2"}, |
| 1482 | {"RX3 MIX1 INP3", "RX3", "I2S RX3"}, |
| 1483 | |
| 1484 | {"RX1 MIX2 INP1", "IIR1", "IIR1"}, |
| 1485 | {"RX2 MIX2 INP1", "IIR1", "IIR1"}, |
| 1486 | {"RX1 MIX2 INP1", "IIR2", "IIR2"}, |
| 1487 | {"RX2 MIX2 INP1", "IIR2", "IIR2"}, |
| 1488 | |
| 1489 | /* Decimator Inputs */ |
| 1490 | {"DEC1 MUX", "DMIC1", "DMIC1"}, |
| 1491 | {"DEC1 MUX", "DMIC2", "DMIC2"}, |
| 1492 | {"DEC1 MUX", "ADC1", "ADC1_IN"}, |
| 1493 | {"DEC1 MUX", "ADC2", "ADC2_IN"}, |
| 1494 | {"DEC1 MUX", "ADC3", "ADC3_IN"}, |
| 1495 | {"DEC1 MUX", NULL, "CDC_CONN"}, |
| 1496 | |
| 1497 | {"DEC2 MUX", "DMIC1", "DMIC1"}, |
| 1498 | {"DEC2 MUX", "DMIC2", "DMIC2"}, |
| 1499 | {"DEC2 MUX", "ADC1", "ADC1_IN"}, |
| 1500 | {"DEC2 MUX", "ADC2", "ADC2_IN"}, |
| 1501 | {"DEC2 MUX", "ADC3", "ADC3_IN"}, |
| 1502 | {"DEC2 MUX", NULL, "CDC_CONN"}, |
| 1503 | |
| 1504 | {"DEC3 MUX", "DMIC3", "DMIC3"}, |
| 1505 | {"DEC4 MUX", "DMIC4", "DMIC4"}, |
| 1506 | {"DEC3 MUX", NULL, "CDC_CONN"}, |
| 1507 | {"DEC4 MUX", NULL, "CDC_CONN"}, |
| 1508 | |
| 1509 | {"IIR1", NULL, "IIR1 INP1 MUX"}, |
| 1510 | {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"}, |
| 1511 | {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"}, |
| 1512 | {"IIR2", NULL, "IIR2 INP1 MUX"}, |
| 1513 | {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"}, |
| 1514 | {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"}, |
| 1515 | }; |
| 1516 | |
| 1517 | static const char * const rx_mix1_text[] = { |
| 1518 | "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" |
| 1519 | }; |
| 1520 | |
| 1521 | static const char * const rx_mix2_text[] = { |
| 1522 | "ZERO", "IIR1", "IIR2" |
| 1523 | }; |
| 1524 | |
| 1525 | static const char * const dec_mux_text[] = { |
| 1526 | "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2" |
| 1527 | }; |
| 1528 | |
| 1529 | static const char * const dec3_mux_text[] = { |
| 1530 | "ZERO", "DMIC3" |
| 1531 | }; |
| 1532 | |
| 1533 | static const char * const dec4_mux_text[] = { |
| 1534 | "ZERO", "DMIC4" |
| 1535 | }; |
| 1536 | |
| 1537 | static const char * const iir_inp1_text[] = { |
| 1538 | "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3" |
| 1539 | }; |
| 1540 | |
| 1541 | /* RX1 MIX1 */ |
| 1542 | static const struct soc_enum rx_mix1_inp1_chain_enum = |
| 1543 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, |
| 1544 | 0, 6, rx_mix1_text); |
| 1545 | |
| 1546 | static const struct soc_enum rx_mix1_inp2_chain_enum = |
| 1547 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, |
| 1548 | 3, 6, rx_mix1_text); |
| 1549 | |
| 1550 | static const struct soc_enum rx_mix1_inp3_chain_enum = |
| 1551 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, |
| 1552 | 0, 6, rx_mix1_text); |
| 1553 | |
| 1554 | /* RX1 MIX2 */ |
| 1555 | static const struct soc_enum rx_mix2_inp1_chain_enum = |
| 1556 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, |
| 1557 | 0, 3, rx_mix2_text); |
| 1558 | |
| 1559 | /* RX2 MIX1 */ |
| 1560 | static const struct soc_enum rx2_mix1_inp1_chain_enum = |
| 1561 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, |
| 1562 | 0, 6, rx_mix1_text); |
| 1563 | |
| 1564 | static const struct soc_enum rx2_mix1_inp2_chain_enum = |
| 1565 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, |
| 1566 | 3, 6, rx_mix1_text); |
| 1567 | |
| 1568 | static const struct soc_enum rx2_mix1_inp3_chain_enum = |
| 1569 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, |
| 1570 | 0, 6, rx_mix1_text); |
| 1571 | |
| 1572 | /* RX2 MIX2 */ |
| 1573 | static const struct soc_enum rx2_mix2_inp1_chain_enum = |
| 1574 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, |
| 1575 | 0, 3, rx_mix2_text); |
| 1576 | |
| 1577 | /* RX3 MIX1 */ |
| 1578 | static const struct soc_enum rx3_mix1_inp1_chain_enum = |
| 1579 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, |
| 1580 | 0, 6, rx_mix1_text); |
| 1581 | |
| 1582 | static const struct soc_enum rx3_mix1_inp2_chain_enum = |
| 1583 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, |
| 1584 | 3, 6, rx_mix1_text); |
| 1585 | |
| 1586 | static const struct soc_enum rx3_mix1_inp3_chain_enum = |
| 1587 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, |
| 1588 | 0, 6, rx_mix1_text); |
| 1589 | |
| 1590 | /* DEC */ |
| 1591 | static const struct soc_enum dec1_mux_enum = |
| 1592 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, |
| 1593 | 0, 6, dec_mux_text); |
| 1594 | |
| 1595 | static const struct soc_enum dec2_mux_enum = |
| 1596 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, |
| 1597 | 3, 6, dec_mux_text); |
| 1598 | |
| 1599 | static const struct soc_enum dec3_mux_enum = |
| 1600 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, |
| 1601 | 0, ARRAY_SIZE(dec3_mux_text), dec3_mux_text); |
| 1602 | |
| 1603 | static const struct soc_enum dec4_mux_enum = |
| 1604 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, |
| 1605 | 0, ARRAY_SIZE(dec4_mux_text), dec4_mux_text); |
| 1606 | |
| 1607 | static const struct soc_enum iir1_inp1_mux_enum = |
| 1608 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, |
| 1609 | 0, 6, iir_inp1_text); |
| 1610 | |
| 1611 | static const struct soc_enum iir2_inp1_mux_enum = |
| 1612 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, |
| 1613 | 0, 6, iir_inp1_text); |
| 1614 | |
| 1615 | /*cut of frequency for high pass filter*/ |
| 1616 | static const char * const cf_text[] = { |
| 1617 | "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" |
| 1618 | }; |
| 1619 | |
| 1620 | static const struct soc_enum cf_rxmix1_enum = |
| 1621 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX1_B4_CTL, 0, 3, cf_text); |
| 1622 | |
| 1623 | static const struct soc_enum cf_rxmix2_enum = |
| 1624 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX2_B4_CTL, 0, 3, cf_text); |
| 1625 | |
| 1626 | static const struct soc_enum cf_rxmix3_enum = |
| 1627 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX3_B4_CTL, 0, 3, cf_text); |
| 1628 | |
| 1629 | static const struct snd_kcontrol_new rx3_mix1_inp1_mux = |
| 1630 | SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum); |
| 1631 | |
| 1632 | #define MSM89XX_DEC_ENUM(xname, xenum) \ |
| 1633 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ |
| 1634 | .info = snd_soc_info_enum_double, \ |
| 1635 | .get = snd_soc_dapm_get_enum_double, \ |
| 1636 | .put = msm_dig_cdc_put_dec_enum, \ |
| 1637 | .private_value = (unsigned long)&xenum } |
| 1638 | |
| 1639 | static const struct snd_kcontrol_new dec1_mux = |
| 1640 | MSM89XX_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum); |
| 1641 | |
| 1642 | static const struct snd_kcontrol_new dec2_mux = |
| 1643 | MSM89XX_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum); |
| 1644 | |
| 1645 | static const struct snd_kcontrol_new dec3_mux = |
| 1646 | SOC_DAPM_ENUM("DEC3 MUX Mux", dec3_mux_enum); |
| 1647 | |
| 1648 | static const struct snd_kcontrol_new dec4_mux = |
| 1649 | SOC_DAPM_ENUM("DEC4 MUX Mux", dec4_mux_enum); |
| 1650 | |
| 1651 | static const struct snd_kcontrol_new iir1_inp1_mux = |
| 1652 | SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); |
| 1653 | |
| 1654 | static const struct snd_kcontrol_new iir2_inp1_mux = |
| 1655 | SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum); |
| 1656 | |
| 1657 | static const struct snd_kcontrol_new rx_mix1_inp1_mux = |
| 1658 | SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum); |
| 1659 | |
| 1660 | static const struct snd_kcontrol_new rx_mix1_inp2_mux = |
| 1661 | SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum); |
| 1662 | |
| 1663 | static const struct snd_kcontrol_new rx_mix1_inp3_mux = |
| 1664 | SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum); |
| 1665 | |
| 1666 | static const struct snd_kcontrol_new rx2_mix1_inp1_mux = |
| 1667 | SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum); |
| 1668 | |
| 1669 | static const struct snd_kcontrol_new rx2_mix1_inp2_mux = |
| 1670 | SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum); |
| 1671 | |
| 1672 | static const struct snd_kcontrol_new rx2_mix1_inp3_mux = |
| 1673 | SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum); |
| 1674 | |
| 1675 | static const struct snd_kcontrol_new rx3_mix1_inp2_mux = |
| 1676 | SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum); |
| 1677 | |
| 1678 | static const struct snd_kcontrol_new rx3_mix1_inp3_mux = |
| 1679 | SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum); |
| 1680 | |
| 1681 | static const struct snd_kcontrol_new rx1_mix2_inp1_mux = |
| 1682 | SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum); |
| 1683 | |
| 1684 | static const struct snd_kcontrol_new rx2_mix2_inp1_mux = |
| 1685 | SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum); |
| 1686 | |
| 1687 | static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = { |
| 1688 | SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 1689 | SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 1690 | SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), |
| 1691 | |
| 1692 | SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 1693 | SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 1694 | SND_SOC_DAPM_AIF_OUT("AIF2 VI", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), |
| 1695 | |
| 1696 | SND_SOC_DAPM_MIXER_E("RX1 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, |
| 1697 | MSM89XX_RX1, 0, NULL, 0, |
| 1698 | msm_dig_cdc_codec_enable_interpolator, |
| 1699 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1700 | SND_SOC_DAPM_MIXER_E("RX2 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, |
| 1701 | MSM89XX_RX2, 0, NULL, 0, |
| 1702 | msm_dig_cdc_codec_enable_interpolator, |
| 1703 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1704 | SND_SOC_DAPM_MIXER_E("RX3 MIX1", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, |
| 1705 | MSM89XX_RX3, 0, NULL, 0, |
| 1706 | msm_dig_cdc_codec_enable_interpolator, |
| 1707 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 1708 | |
| 1709 | SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1710 | SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1711 | |
| 1712 | SND_SOC_DAPM_MIXER("RX1 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1713 | SND_SOC_DAPM_MIXER("RX2 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1714 | SND_SOC_DAPM_MIXER("RX3 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 1715 | |
| 1716 | SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
| 1717 | &rx_mix1_inp1_mux), |
| 1718 | SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
| 1719 | &rx_mix1_inp2_mux), |
| 1720 | SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
| 1721 | &rx_mix1_inp3_mux), |
| 1722 | |
| 1723 | SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
| 1724 | &rx2_mix1_inp1_mux), |
| 1725 | SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
| 1726 | &rx2_mix1_inp2_mux), |
| 1727 | SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
| 1728 | &rx2_mix1_inp3_mux), |
| 1729 | |
| 1730 | SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
| 1731 | &rx3_mix1_inp1_mux), |
| 1732 | SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
| 1733 | &rx3_mix1_inp2_mux), |
| 1734 | SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
| 1735 | &rx3_mix1_inp3_mux), |
| 1736 | |
| 1737 | SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0, |
| 1738 | &rx1_mix2_inp1_mux), |
| 1739 | SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0, |
| 1740 | &rx2_mix2_inp1_mux), |
| 1741 | |
| 1742 | SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM89XX_CDC_CORE_CLK_OTHR_CTL, |
| 1743 | 2, 0, NULL, 0), |
| 1744 | |
| 1745 | SND_SOC_DAPM_MUX_E("DEC1 MUX", |
| 1746 | MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0, 0, |
| 1747 | &dec1_mux, msm_dig_cdc_codec_enable_dec, |
| 1748 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1749 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1750 | |
| 1751 | SND_SOC_DAPM_MUX_E("DEC2 MUX", |
| 1752 | MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 1, 0, |
| 1753 | &dec2_mux, msm_dig_cdc_codec_enable_dec, |
| 1754 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1755 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1756 | |
| 1757 | SND_SOC_DAPM_MUX_E("DEC3 MUX", |
| 1758 | MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 2, 0, |
| 1759 | &dec3_mux, msm_dig_cdc_codec_enable_dec, |
| 1760 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1761 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1762 | |
| 1763 | SND_SOC_DAPM_MUX_E("DEC4 MUX", |
| 1764 | MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 3, 0, |
| 1765 | &dec4_mux, msm_dig_cdc_codec_enable_dec, |
| 1766 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1767 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1768 | |
| 1769 | /* Sidetone */ |
| 1770 | SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), |
| 1771 | SND_SOC_DAPM_PGA_E("IIR1", MSM89XX_CDC_CORE_CLK_SD_CTL, 0, 0, NULL, 0, |
| 1772 | msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), |
| 1773 | |
| 1774 | SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux), |
| 1775 | SND_SOC_DAPM_PGA_E("IIR2", MSM89XX_CDC_CORE_CLK_SD_CTL, 1, 0, NULL, 0, |
| 1776 | msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), |
| 1777 | |
| 1778 | SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", |
| 1779 | MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 4, 0, NULL, 0), |
| 1780 | SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", |
| 1781 | MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 4, 0, NULL, 0), |
| 1782 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 1783 | SND_SOC_DAPM_SUPPLY("DIGITAL_REGULATOR", SND_SOC_NOPM, |
| 1784 | ON_DEMAND_DIGITAL, 0, |
| 1785 | msm_dig_cdc_enable_on_demand_supply, |
| 1786 | SND_SOC_DAPM_PRE_PMU | |
| 1787 | SND_SOC_DAPM_POST_PMD), |
| 1788 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 1789 | /* Digital Mic Inputs */ |
| 1790 | SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
| 1791 | msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1792 | SND_SOC_DAPM_POST_PMD), |
| 1793 | |
| 1794 | SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
| 1795 | msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1796 | SND_SOC_DAPM_POST_PMD), |
| 1797 | |
| 1798 | SND_SOC_DAPM_INPUT("DMIC3"), |
| 1799 | SND_SOC_DAPM_INPUT("DMIC4"), |
| 1800 | SND_SOC_DAPM_INPUT("ADC1_IN"), |
| 1801 | SND_SOC_DAPM_INPUT("ADC2_IN"), |
| 1802 | SND_SOC_DAPM_INPUT("ADC3_IN"), |
| 1803 | SND_SOC_DAPM_OUTPUT("PDM_OUT_RX1"), |
| 1804 | SND_SOC_DAPM_OUTPUT("PDM_OUT_RX2"), |
| 1805 | SND_SOC_DAPM_OUTPUT("PDM_OUT_RX3"), |
| 1806 | }; |
| 1807 | |
| 1808 | static const struct soc_enum cf_dec1_enum = |
| 1809 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX1_MUX_CTL, 4, 3, cf_text); |
| 1810 | |
| 1811 | static const struct soc_enum cf_dec2_enum = |
| 1812 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX2_MUX_CTL, 4, 3, cf_text); |
| 1813 | |
| 1814 | static const struct soc_enum cf_dec3_enum = |
| 1815 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, 4, 3, cf_text); |
| 1816 | |
| 1817 | static const struct soc_enum cf_dec4_enum = |
| 1818 | SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, 4, 3, cf_text); |
| 1819 | |
| 1820 | static const struct snd_kcontrol_new msm_dig_snd_controls[] = { |
| 1821 | SOC_SINGLE_SX_TLV("DEC1 Volume", |
| 1822 | MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, |
| 1823 | 0, -84, 40, digital_gain), |
| 1824 | SOC_SINGLE_SX_TLV("DEC2 Volume", |
| 1825 | MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, |
| 1826 | 0, -84, 40, digital_gain), |
| 1827 | SOC_SINGLE_SX_TLV("DEC3 Volume", |
| 1828 | MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, |
| 1829 | 0, -84, 40, digital_gain), |
| 1830 | SOC_SINGLE_SX_TLV("DEC4 Volume", |
| 1831 | MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, |
| 1832 | 0, -84, 40, digital_gain), |
| 1833 | |
| 1834 | SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", |
| 1835 | MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, |
| 1836 | 0, -84, 40, digital_gain), |
| 1837 | SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", |
| 1838 | MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, |
| 1839 | 0, -84, 40, digital_gain), |
| 1840 | SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", |
| 1841 | MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, |
| 1842 | 0, -84, 40, digital_gain), |
| 1843 | SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", |
| 1844 | MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, |
| 1845 | 0, -84, 40, digital_gain), |
| 1846 | SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", |
| 1847 | MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, |
| 1848 | 0, -84, 40, digital_gain), |
| 1849 | |
| 1850 | SOC_SINGLE_SX_TLV("RX1 Digital Volume", |
| 1851 | MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, |
| 1852 | 0, -84, 40, digital_gain), |
| 1853 | SOC_SINGLE_SX_TLV("RX2 Digital Volume", |
| 1854 | MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, |
| 1855 | 0, -84, 40, digital_gain), |
| 1856 | SOC_SINGLE_SX_TLV("RX3 Digital Volume", |
| 1857 | MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, |
| 1858 | 0, -84, 40, digital_gain), |
| 1859 | |
| 1860 | SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, |
| 1861 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1862 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1863 | SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, |
| 1864 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1865 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1866 | SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, |
| 1867 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1868 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1869 | SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, |
| 1870 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1871 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1872 | SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, |
| 1873 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1874 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1875 | |
| 1876 | SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0, |
| 1877 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1878 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1879 | SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0, |
| 1880 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1881 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1882 | SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0, |
| 1883 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1884 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1885 | SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0, |
| 1886 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1887 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1888 | SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0, |
| 1889 | msm_dig_cdc_get_iir_enable_audio_mixer, |
| 1890 | msm_dig_cdc_put_iir_enable_audio_mixer), |
| 1891 | |
| 1892 | SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, |
| 1893 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1894 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1895 | SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, |
| 1896 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1897 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1898 | SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, |
| 1899 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1900 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1901 | SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, |
| 1902 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1903 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1904 | SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, |
| 1905 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1906 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1907 | |
| 1908 | SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5, |
| 1909 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1910 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1911 | SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5, |
| 1912 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1913 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1914 | SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5, |
| 1915 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1916 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1917 | SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5, |
| 1918 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1919 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1920 | SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5, |
| 1921 | msm_dig_cdc_get_iir_band_audio_mixer, |
| 1922 | msm_dig_cdc_put_iir_band_audio_mixer), |
| 1923 | |
| 1924 | SOC_SINGLE("RX1 HPF Switch", |
| 1925 | MSM89XX_CDC_CORE_RX1_B5_CTL, 2, 1, 0), |
| 1926 | SOC_SINGLE("RX2 HPF Switch", |
| 1927 | MSM89XX_CDC_CORE_RX2_B5_CTL, 2, 1, 0), |
| 1928 | SOC_SINGLE("RX3 HPF Switch", |
| 1929 | MSM89XX_CDC_CORE_RX3_B5_CTL, 2, 1, 0), |
| 1930 | |
| 1931 | SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum), |
| 1932 | SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum), |
| 1933 | SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum), |
| 1934 | |
| 1935 | SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), |
| 1936 | SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), |
| 1937 | SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), |
| 1938 | SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), |
| 1939 | SOC_SINGLE("TX1 HPF Switch", |
| 1940 | MSM89XX_CDC_CORE_TX1_MUX_CTL, 3, 1, 0), |
| 1941 | SOC_SINGLE("TX2 HPF Switch", |
| 1942 | MSM89XX_CDC_CORE_TX2_MUX_CTL, 3, 1, 0), |
| 1943 | SOC_SINGLE("TX3 HPF Switch", |
| 1944 | MSM89XX_CDC_CORE_TX3_MUX_CTL, 3, 1, 0), |
| 1945 | SOC_SINGLE("TX4 HPF Switch", |
| 1946 | MSM89XX_CDC_CORE_TX4_MUX_CTL, 3, 1, 0), |
| 1947 | }; |
| 1948 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 1949 | static int msm_dig_cdc_enable_on_demand_supply( |
| 1950 | struct snd_soc_dapm_widget *w, |
| 1951 | struct snd_kcontrol *kcontrol, int event) |
| 1952 | { |
| 1953 | int ret = 0; |
| 1954 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 1955 | struct msm_dig_priv *msm_dig_cdc = snd_soc_codec_get_drvdata(codec); |
| 1956 | struct on_demand_dig_supply *supply; |
| 1957 | |
| 1958 | if (w->shift >= ON_DEMAND_DIG_SUPPLIES_MAX) { |
| 1959 | dev_err(codec->dev, "%s: error index >= MAX on demand supplies", |
| 1960 | __func__); |
| 1961 | ret = -EINVAL; |
| 1962 | goto out; |
| 1963 | } |
| 1964 | dev_dbg(codec->dev, "%s: supply: %s event: %d ref: %d\n", |
| 1965 | __func__, on_demand_supply_name[w->shift], event, |
| 1966 | atomic_read(&msm_dig_cdc->on_demand_list[w->shift].ref)); |
| 1967 | |
| 1968 | supply = &msm_dig_cdc->on_demand_list[w->shift]; |
| 1969 | if (!supply->supply) { |
| 1970 | dev_err(codec->dev, "%s: err supply not present ond for %d", |
| 1971 | __func__, w->shift); |
| 1972 | goto out; |
| 1973 | } |
| 1974 | switch (event) { |
| 1975 | case SND_SOC_DAPM_PRE_PMU: |
| 1976 | if (atomic_inc_return(&supply->ref) == 1) { |
| 1977 | ret = regulator_set_voltage(supply->supply, |
| 1978 | supply->min_uv, |
| 1979 | supply->max_uv); |
| 1980 | if (ret) { |
| 1981 | dev_err(codec->dev, |
| 1982 | "Setting regulator voltage(en) for micbias with err = %d\n", |
| 1983 | ret); |
| 1984 | goto out; |
| 1985 | } |
| 1986 | ret = regulator_set_load(supply->supply, |
| 1987 | supply->optimum_ua); |
| 1988 | if (ret < 0) { |
| 1989 | dev_err(codec->dev, |
| 1990 | "Setting regulator optimum mode(en) failed for micbias with err = %d\n", |
| 1991 | ret); |
| 1992 | goto out; |
| 1993 | } |
| 1994 | ret = regulator_enable(supply->supply); |
| 1995 | if (ret) |
| 1996 | dev_err(codec->dev, "%s: Failed to enable %s\n", |
| 1997 | __func__, |
| 1998 | on_demand_supply_name[w->shift]); |
| 1999 | } |
| 2000 | break; |
| 2001 | case SND_SOC_DAPM_POST_PMD: |
| 2002 | if (atomic_read(&supply->ref) == 0) { |
| 2003 | dev_dbg(codec->dev, "%s: %s supply has been disabled.\n", |
| 2004 | __func__, on_demand_supply_name[w->shift]); |
| 2005 | goto out; |
| 2006 | } |
| 2007 | if (atomic_dec_return(&supply->ref) == 0) { |
| 2008 | ret = regulator_disable(supply->supply); |
| 2009 | if (ret) |
| 2010 | dev_err(codec->dev, "%s: Failed to disable %s\n", |
| 2011 | __func__, |
| 2012 | on_demand_supply_name[w->shift]); |
| 2013 | ret = regulator_set_voltage(supply->supply, |
| 2014 | 0, |
| 2015 | supply->max_uv); |
| 2016 | if (ret) { |
| 2017 | dev_err(codec->dev, |
| 2018 | "Setting regulator voltage(dis) failed for micbias with err = %d\n", |
| 2019 | ret); |
| 2020 | goto out; |
| 2021 | } |
| 2022 | ret = regulator_set_load(supply->supply, 0); |
| 2023 | if (ret < 0) |
| 2024 | dev_err(codec->dev, |
| 2025 | "Setting regulator optimum mode(dis) failed for micbias with err = %d\n", |
| 2026 | ret); |
| 2027 | } |
| 2028 | break; |
| 2029 | default: |
| 2030 | break; |
| 2031 | } |
| 2032 | out: |
| 2033 | return ret; |
| 2034 | } |
| 2035 | |
| 2036 | static int msm_digital_cdc_init_supplies(struct msm_dig_priv *msm_cdc) |
| 2037 | { |
| 2038 | int ret; |
| 2039 | int i; |
| 2040 | |
| 2041 | msm_cdc->supplies = devm_kzalloc(msm_cdc->dev, |
| 2042 | sizeof(struct regulator_bulk_data) * |
| 2043 | ARRAY_SIZE(msm_cdc->regulator), |
| 2044 | GFP_KERNEL); |
| 2045 | if (!msm_cdc->supplies) { |
| 2046 | ret = -ENOMEM; |
| 2047 | goto err; |
| 2048 | } |
| 2049 | |
| 2050 | msm_cdc->num_of_supplies = 0; |
| 2051 | |
| 2052 | if (ARRAY_SIZE(msm_cdc->regulator) > MAX_REGULATOR) { |
| 2053 | dev_err(msm_cdc->dev, "%s: Array Size out of bound\n", |
| 2054 | __func__); |
| 2055 | ret = -EINVAL; |
| 2056 | goto err; |
| 2057 | } |
| 2058 | |
| 2059 | for (i = 0; i < ARRAY_SIZE(msm_cdc->regulator); i++) { |
| 2060 | if (msm_cdc->regulator[i].name) { |
| 2061 | msm_cdc->supplies[i].supply = |
| 2062 | msm_cdc->regulator[i].name; |
| 2063 | msm_cdc->num_of_supplies++; |
| 2064 | } |
| 2065 | } |
| 2066 | |
| 2067 | ret = devm_regulator_bulk_get(msm_cdc->dev, |
| 2068 | msm_cdc->num_of_supplies, |
| 2069 | msm_cdc->supplies); |
| 2070 | if (ret != 0) { |
| 2071 | dev_err(msm_cdc->dev, |
| 2072 | "Failed to get supplies: err = %d\n", |
| 2073 | ret); |
| 2074 | goto err_supplies; |
| 2075 | } |
| 2076 | |
| 2077 | for (i = 0; i < msm_cdc->num_of_supplies; i++) { |
| 2078 | if (regulator_count_voltages( |
| 2079 | msm_cdc->supplies[i].consumer) <= 0) |
| 2080 | continue; |
| 2081 | ret = regulator_set_voltage( |
| 2082 | msm_cdc->supplies[i].consumer, |
| 2083 | msm_cdc->regulator[i].min_uv, |
| 2084 | msm_cdc->regulator[i].max_uv); |
| 2085 | if (ret) { |
| 2086 | dev_err(msm_cdc->dev, |
| 2087 | "Setting regulator voltage failed for regulator %s err = %d\n", |
| 2088 | msm_cdc->supplies[i].supply, ret); |
| 2089 | goto err_supplies; |
| 2090 | } |
| 2091 | ret = regulator_set_load(msm_cdc->supplies[i].consumer, |
| 2092 | msm_cdc->regulator[i].optimum_ua); |
| 2093 | if (ret < 0) { |
| 2094 | dev_err(msm_cdc->dev, |
| 2095 | "Setting regulator optimum mode failed for regulator %s err = %d\n", |
| 2096 | msm_cdc->supplies[i].supply, ret); |
| 2097 | goto err_supplies; |
| 2098 | } else { |
| 2099 | ret = 0; |
| 2100 | } |
| 2101 | } |
| 2102 | |
| 2103 | return ret; |
| 2104 | |
| 2105 | err_supplies: |
| 2106 | err: |
| 2107 | return ret; |
| 2108 | } |
| 2109 | |
| 2110 | static int msm_digital_cdc_dt_parse_vreg_info(struct device *dev, |
| 2111 | struct dig_cdc_regulator *vreg, const char *vreg_name) |
| 2112 | { |
| 2113 | int len, ret = 0; |
| 2114 | const __be32 *prop; |
| 2115 | char prop_name[CODEC_DT_MAX_PROP_SIZE]; |
| 2116 | struct device_node *regnode = NULL; |
| 2117 | u32 prop_val; |
| 2118 | |
| 2119 | snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", |
| 2120 | vreg_name); |
| 2121 | regnode = of_parse_phandle(dev->of_node, prop_name, 0); |
| 2122 | |
| 2123 | if (!regnode) { |
| 2124 | dev_err(dev, "Looking up %s property in node %s failed\n", |
| 2125 | prop_name, dev->of_node->full_name); |
| 2126 | return -ENODEV; |
| 2127 | } |
| 2128 | |
| 2129 | dev_dbg(dev, "Looking up %s property in node %s\n", |
| 2130 | prop_name, dev->of_node->full_name); |
| 2131 | |
| 2132 | vreg->name = vreg_name; |
| 2133 | |
| 2134 | snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, |
| 2135 | "qcom,%s-voltage", vreg_name); |
| 2136 | prop = of_get_property(dev->of_node, prop_name, &len); |
| 2137 | |
| 2138 | if (!prop || (len != (2 * sizeof(__be32)))) { |
| 2139 | dev_err(dev, "%s %s property\n", |
| 2140 | prop ? "invalid format" : "no", prop_name); |
| 2141 | return -EINVAL; |
| 2142 | } |
| 2143 | vreg->min_uv = be32_to_cpup(&prop[0]); |
| 2144 | vreg->max_uv = be32_to_cpup(&prop[1]); |
| 2145 | |
| 2146 | snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, |
| 2147 | "qcom,%s-current", vreg_name); |
| 2148 | |
| 2149 | ret = of_property_read_u32(dev->of_node, prop_name, &prop_val); |
| 2150 | if (ret) { |
| 2151 | dev_err(dev, "Looking up %s property in node %s failed", |
| 2152 | prop_name, dev->of_node->full_name); |
| 2153 | return -EFAULT; |
| 2154 | } |
| 2155 | vreg->optimum_ua = prop_val; |
| 2156 | dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA\n", vreg->name, |
| 2157 | vreg->min_uv, vreg->max_uv, vreg->optimum_ua); |
| 2158 | return 0; |
| 2159 | } |
| 2160 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2161 | static struct snd_soc_dai_ops msm_dig_dai_ops = { |
| 2162 | .hw_params = msm_dig_cdc_hw_params, |
| 2163 | }; |
| 2164 | |
| 2165 | |
| 2166 | static struct snd_soc_dai_driver msm_codec_dais[] = { |
| 2167 | { |
| 2168 | .name = "msm_dig_cdc_dai_rx1", |
| 2169 | .id = AIF1_PB, |
| 2170 | .playback = { /* Support maximum range */ |
| 2171 | .stream_name = "AIF1 Playback", |
| 2172 | .channels_min = 1, |
| 2173 | .channels_max = 2, |
| 2174 | .rates = SNDRV_PCM_RATE_8000_192000, |
| 2175 | .rate_max = 192000, |
| 2176 | .rate_min = 8000, |
| 2177 | .formats = SNDRV_PCM_FMTBIT_S16_LE | |
| 2178 | SNDRV_PCM_FMTBIT_S24_LE | |
| 2179 | SNDRV_PCM_FMTBIT_S24_3LE, |
| 2180 | }, |
| 2181 | .ops = &msm_dig_dai_ops, |
| 2182 | }, |
| 2183 | { |
| 2184 | .name = "msm_dig_cdc_dai_tx1", |
| 2185 | .id = AIF1_CAP, |
| 2186 | .capture = { /* Support maximum range */ |
| 2187 | .stream_name = "AIF1 Capture", |
| 2188 | .channels_min = 1, |
| 2189 | .channels_max = 4, |
| 2190 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 2191 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
| 2192 | }, |
| 2193 | .ops = &msm_dig_dai_ops, |
| 2194 | }, |
| 2195 | { |
| 2196 | .name = "msm_dig_cdc_dai_vifeed", |
| 2197 | .id = AIF2_VIFEED, |
| 2198 | .capture = { /* Support maximum range */ |
| 2199 | .stream_name = "AIF2 Capture", |
| 2200 | .channels_min = 1, |
| 2201 | .channels_max = 2, |
| 2202 | .rates = SNDRV_PCM_RATE_8000_48000, |
| 2203 | .formats = SNDRV_PCM_FMTBIT_S16_LE, |
| 2204 | }, |
| 2205 | .ops = &msm_dig_dai_ops, |
| 2206 | }, |
| 2207 | }; |
| 2208 | |
| 2209 | static struct regmap *msm_digital_get_regmap(struct device *dev) |
| 2210 | { |
| 2211 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(dev); |
| 2212 | |
| 2213 | return msm_dig_cdc->regmap; |
| 2214 | } |
| 2215 | |
| 2216 | static int msm_dig_cdc_suspend(struct snd_soc_codec *codec) |
| 2217 | { |
| 2218 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(codec->dev); |
| 2219 | |
| 2220 | msm_dig_cdc->dapm_bias_off = 1; |
| 2221 | return 0; |
| 2222 | } |
| 2223 | |
| 2224 | static int msm_dig_cdc_resume(struct snd_soc_codec *codec) |
| 2225 | { |
| 2226 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(codec->dev); |
| 2227 | |
| 2228 | msm_dig_cdc->dapm_bias_off = 0; |
| 2229 | return 0; |
| 2230 | } |
| 2231 | |
| 2232 | static struct snd_soc_codec_driver soc_msm_dig_codec = { |
| 2233 | .probe = msm_dig_cdc_soc_probe, |
| 2234 | .remove = msm_dig_cdc_soc_remove, |
| 2235 | .suspend = msm_dig_cdc_suspend, |
| 2236 | .resume = msm_dig_cdc_resume, |
| 2237 | .get_regmap = msm_digital_get_regmap, |
| 2238 | .component_driver = { |
| 2239 | .controls = msm_dig_snd_controls, |
| 2240 | .num_controls = ARRAY_SIZE(msm_dig_snd_controls), |
| 2241 | .dapm_widgets = msm_dig_dapm_widgets, |
| 2242 | .num_dapm_widgets = ARRAY_SIZE(msm_dig_dapm_widgets), |
| 2243 | .dapm_routes = audio_dig_map, |
| 2244 | .num_dapm_routes = ARRAY_SIZE(audio_dig_map), |
| 2245 | }, |
| 2246 | }; |
| 2247 | |
| 2248 | const struct regmap_config msm_digital_regmap_config = { |
| 2249 | .reg_bits = 32, |
| 2250 | .reg_stride = 4, |
| 2251 | .val_bits = 8, |
| 2252 | .lock = enable_digital_callback, |
| 2253 | .unlock = disable_digital_callback, |
| 2254 | .cache_type = REGCACHE_FLAT, |
| 2255 | .reg_defaults = msm89xx_cdc_core_defaults, |
| 2256 | .num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER, |
| 2257 | .writeable_reg = msm89xx_cdc_core_writeable_reg, |
| 2258 | .readable_reg = msm89xx_cdc_core_readable_reg, |
| 2259 | .volatile_reg = msm89xx_cdc_core_volatile_reg, |
| 2260 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
| 2261 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
| 2262 | .max_register = MSM89XX_CDC_CORE_MAX_REGISTER, |
| 2263 | }; |
| 2264 | |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2265 | static bool msm_digital_cdc_populate_dt_pdata( |
| 2266 | struct device *dev, |
| 2267 | struct msm_dig_priv *dig_priv) |
| 2268 | { |
| 2269 | int ret, ond_cnt, i, idx = 0; |
| 2270 | const char *name = NULL; |
| 2271 | const char *ond_prop_name = "qcom,cdc-on-demand-supplies"; |
| 2272 | |
| 2273 | ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name); |
| 2274 | if (ond_cnt < 0) |
| 2275 | ond_cnt = 0; |
| 2276 | |
| 2277 | if (ond_cnt > ARRAY_SIZE(dig_priv->regulator)) { |
| 2278 | ret = -EINVAL; |
| 2279 | goto err; |
| 2280 | } |
| 2281 | |
| 2282 | for (i = 0; i < ond_cnt; i++, idx++) { |
| 2283 | ret = of_property_read_string_index(dev->of_node, ond_prop_name, |
| 2284 | i, &name); |
| 2285 | if (ret) { |
| 2286 | dev_err(dev, "%s: err parsing on_demand for %s idx %d\n", |
| 2287 | __func__, ond_prop_name, i); |
| 2288 | goto err; |
| 2289 | } |
| 2290 | |
| 2291 | dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__, |
| 2292 | name); |
| 2293 | ret = msm_digital_cdc_dt_parse_vreg_info(dev, |
| 2294 | &dig_priv->regulator[idx], |
| 2295 | name); |
| 2296 | if (ret) { |
| 2297 | dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n", |
| 2298 | __func__, name, idx); |
| 2299 | goto err; |
| 2300 | } |
| 2301 | } |
| 2302 | |
| 2303 | return true; |
| 2304 | err: |
| 2305 | dev_err(dev, "%s: Failed to populate DT data ret = %d\n", |
| 2306 | __func__, ret); |
| 2307 | return false; |
| 2308 | } |
| 2309 | |
| 2310 | static void msm_digital_cdc_disable_supplies(struct msm_dig_priv *msm_cdc) |
| 2311 | { |
| 2312 | int i; |
| 2313 | |
| 2314 | if (!msm_cdc->supplies) |
| 2315 | return; |
| 2316 | |
| 2317 | regulator_bulk_disable(msm_cdc->num_of_supplies, |
| 2318 | msm_cdc->supplies); |
| 2319 | for (i = 0; i < msm_cdc->num_of_supplies; i++) { |
| 2320 | if (regulator_count_voltages( |
| 2321 | msm_cdc->supplies[i].consumer) <= 0) |
| 2322 | continue; |
| 2323 | regulator_set_voltage(msm_cdc->supplies[i].consumer, 0, |
| 2324 | msm_cdc->regulator[i].max_uv); |
| 2325 | regulator_set_load(msm_cdc->supplies[i].consumer, 0); |
| 2326 | } |
| 2327 | regulator_bulk_free(msm_cdc->num_of_supplies, |
| 2328 | msm_cdc->supplies); |
| 2329 | devm_kfree(msm_cdc->dev, msm_cdc->supplies); |
| 2330 | } |
| 2331 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2332 | static int msm_dig_cdc_probe(struct platform_device *pdev) |
| 2333 | { |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2334 | int ret = -EINVAL; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2335 | u32 dig_cdc_addr; |
| 2336 | struct msm_dig_priv *msm_dig_cdc; |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2337 | struct dig_ctrl_platform_data *pdata = NULL; |
| 2338 | bool no_analog_codec = false; |
yang liu | 3745fe6 | 2018-08-10 12:30:01 +0800 | [diff] [blame] | 2339 | int adsp_state = 0; |
| 2340 | |
| 2341 | adsp_state = apr_get_subsys_state(); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2342 | if ((adsp_state != APR_SUBSYS_LOADED) || (!q6core_is_adsp_ready())) { |
yang liu | 3745fe6 | 2018-08-10 12:30:01 +0800 | [diff] [blame] | 2343 | dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", |
| 2344 | adsp_state); |
| 2345 | return -EPROBE_DEFER; |
| 2346 | } |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2347 | device_init_wakeup(&pdev->dev, true); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2348 | |
| 2349 | msm_dig_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msm_dig_priv), |
| 2350 | GFP_KERNEL); |
| 2351 | if (!msm_dig_cdc) |
| 2352 | return -ENOMEM; |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2353 | msm_dig_cdc->dev = &pdev->dev; |
| 2354 | if (pdev->dev.of_node == NULL) |
| 2355 | return -EINVAL; |
| 2356 | |
| 2357 | if (pdev->dev.of_node) |
| 2358 | no_analog_codec = of_property_read_bool(pdev->dev.of_node, |
| 2359 | "qcom,no-analog-codec"); |
| 2360 | if (no_analog_codec) { |
| 2361 | dev_dbg(&pdev->dev, "%s:Platform data from device tree\n", |
| 2362 | __func__); |
| 2363 | if (msm_digital_cdc_populate_dt_pdata(&pdev->dev, |
| 2364 | msm_dig_cdc)) { |
| 2365 | ret = msm_digital_cdc_init_supplies( |
| 2366 | msm_dig_cdc); |
| 2367 | if (ret) { |
| 2368 | dev_err(&pdev->dev, |
| 2369 | "%s: Fail to enable Codec supplies\n", |
| 2370 | __func__); |
| 2371 | goto rtn; |
| 2372 | } |
| 2373 | } |
| 2374 | } else { |
| 2375 | pdata = dev_get_platdata(&pdev->dev); |
| 2376 | if (!pdata) { |
| 2377 | dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", |
| 2378 | __func__); |
| 2379 | ret = -EINVAL; |
| 2380 | goto err_supplies; |
| 2381 | } |
| 2382 | msm_dig_cdc->update_clkdiv = pdata->update_clkdiv; |
| 2383 | msm_dig_cdc->set_compander_mode = pdata->set_compander_mode; |
| 2384 | msm_dig_cdc->get_cdc_version = pdata->get_cdc_version; |
| 2385 | msm_dig_cdc->handle = pdata->handle; |
| 2386 | msm_dig_cdc->register_notifier = pdata->register_notifier; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2387 | } |
| 2388 | |
| 2389 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 2390 | &dig_cdc_addr); |
| 2391 | if (ret) { |
| 2392 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 2393 | __func__, "reg"); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2394 | goto err_supplies; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2395 | } |
| 2396 | |
| 2397 | msm_dig_cdc->dig_base = ioremap(dig_cdc_addr, |
| 2398 | MSM89XX_CDC_CORE_MAX_REGISTER); |
| 2399 | if (msm_dig_cdc->dig_base == NULL) { |
| 2400 | dev_err(&pdev->dev, "%s ioremap failed\n", __func__); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2401 | ret = -ENOMEM; |
| 2402 | goto err_supplies; |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2403 | } |
| 2404 | msm_dig_cdc->regmap = |
| 2405 | devm_regmap_init_mmio_clk(&pdev->dev, NULL, |
| 2406 | msm_dig_cdc->dig_base, &msm_digital_regmap_config); |
| 2407 | |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2408 | |
| 2409 | dev_set_drvdata(&pdev->dev, msm_dig_cdc); |
| 2410 | snd_soc_register_codec(&pdev->dev, &soc_msm_dig_codec, |
| 2411 | msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); |
| 2412 | dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", |
| 2413 | __func__, dig_cdc_addr); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2414 | return ret; |
| 2415 | err_supplies: |
| 2416 | if (no_analog_codec) |
| 2417 | msm_digital_cdc_disable_supplies(msm_dig_cdc); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2418 | rtn: |
| 2419 | return ret; |
| 2420 | } |
| 2421 | |
| 2422 | static int msm_dig_cdc_remove(struct platform_device *pdev) |
| 2423 | { |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2424 | struct msm_dig_priv *msm_cdc = dev_get_drvdata(&pdev->dev); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2425 | snd_soc_unregister_codec(&pdev->dev); |
Manjunatha Madana | 80e8ffa | 2018-12-17 14:13:08 +0530 | [diff] [blame] | 2426 | msm_digital_cdc_disable_supplies(msm_cdc); |
Soumya Managoli | 88074fd | 2018-02-23 12:52:28 +0530 | [diff] [blame] | 2427 | return 0; |
| 2428 | } |
| 2429 | |
| 2430 | #ifdef CONFIG_PM |
| 2431 | static int msm_dig_suspend(struct device *dev) |
| 2432 | { |
| 2433 | struct msm_asoc_mach_data *pdata; |
| 2434 | struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(dev); |
| 2435 | |
| 2436 | if (!registered_digcodec || !msm_dig_cdc) { |
| 2437 | pr_debug("%s:digcodec not initialized, return\n", __func__); |
| 2438 | return 0; |
| 2439 | } |
| 2440 | pdata = snd_soc_card_get_drvdata(registered_digcodec->component.card); |
| 2441 | if (!pdata) { |
| 2442 | pr_debug("%s:card not initialized, return\n", __func__); |
| 2443 | return 0; |
| 2444 | } |
| 2445 | if (msm_dig_cdc->dapm_bias_off) { |
| 2446 | pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", |
| 2447 | __func__, atomic_read(&pdata->int_mclk0_rsc_ref), |
| 2448 | atomic_read(&pdata->int_mclk0_enabled)); |
| 2449 | |
| 2450 | if (atomic_read(&pdata->int_mclk0_enabled) == true) { |
| 2451 | cancel_delayed_work_sync( |
| 2452 | &pdata->disable_int_mclk0_work); |
| 2453 | mutex_lock(&pdata->cdc_int_mclk0_mutex); |
| 2454 | pdata->digital_cdc_core_clk.enable = 0; |
| 2455 | afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX, |
| 2456 | &pdata->digital_cdc_core_clk); |
| 2457 | atomic_set(&pdata->int_mclk0_enabled, false); |
| 2458 | mutex_unlock(&pdata->cdc_int_mclk0_mutex); |
| 2459 | } |
| 2460 | } |
| 2461 | |
| 2462 | return 0; |
| 2463 | } |
| 2464 | |
| 2465 | static int msm_dig_resume(struct device *dev) |
| 2466 | { |
| 2467 | return 0; |
| 2468 | } |
| 2469 | |
| 2470 | static const struct dev_pm_ops msm_dig_pm_ops = { |
| 2471 | .suspend_late = msm_dig_suspend, |
| 2472 | .resume_early = msm_dig_resume, |
| 2473 | }; |
| 2474 | #endif |
| 2475 | |
| 2476 | static const struct of_device_id msm_dig_cdc_of_match[] = { |
| 2477 | {.compatible = "qcom,msm-digital-codec"}, |
| 2478 | {}, |
| 2479 | }; |
| 2480 | |
| 2481 | static struct platform_driver msm_digcodec_driver = { |
| 2482 | .driver = { |
| 2483 | .owner = THIS_MODULE, |
| 2484 | .name = DRV_NAME, |
| 2485 | .of_match_table = msm_dig_cdc_of_match, |
| 2486 | #ifdef CONFIG_PM |
| 2487 | .pm = &msm_dig_pm_ops, |
| 2488 | #endif |
| 2489 | }, |
| 2490 | .probe = msm_dig_cdc_probe, |
| 2491 | .remove = msm_dig_cdc_remove, |
| 2492 | }; |
| 2493 | module_platform_driver(msm_digcodec_driver); |
| 2494 | |
| 2495 | MODULE_DESCRIPTION("MSM Audio Digital codec driver"); |
| 2496 | MODULE_LICENSE("GPL v2"); |