Blame - asoc/codecs/msm_sdw/msm_sdw_registers.h - platform/vendor/opensource/audio-kernel

Asish Bhattacharya

366f750

2017-07-25 15:15:56 +0530

[diff] [blame]

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*

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* This program is free software; you can redistribute it and/or modify

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* it under the terms of the GNU General Public License version 2 and

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* only version 2 as published by the Free Software Foundation.

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*

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* This program is distributed in the hope that it will be useful,

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* but WITHOUT ANY WARRANTY; without even the implied warranty of

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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

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* GNU General Public License for more details.

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*/

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#ifndef MSM_SDW_REGISTERS_H

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#define MSM_SDW_REGISTERS_H

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#define MSM_SDW_PAGE_REGISTER 0x0000

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/* Page-A Registers */

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#define MSM_SDW_TX9_SPKR_PROT_PATH_CTL 0x0308

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#define MSM_SDW_TX9_SPKR_PROT_PATH_CFG0 0x030c

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#define MSM_SDW_TX10_SPKR_PROT_PATH_CTL 0x0318

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#define MSM_SDW_TX10_SPKR_PROT_PATH_CFG0 0x031c

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#define MSM_SDW_TX11_SPKR_PROT_PATH_CTL 0x0328

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#define MSM_SDW_TX11_SPKR_PROT_PATH_CFG0 0x032c

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#define MSM_SDW_TX12_SPKR_PROT_PATH_CTL 0x0338

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#define MSM_SDW_TX12_SPKR_PROT_PATH_CFG0 0x033c

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/* Page-B Registers */

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#define MSM_SDW_COMPANDER7_CTL0 0x0024

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#define MSM_SDW_COMPANDER7_CTL1 0x0028

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#define MSM_SDW_COMPANDER7_CTL2 0x002c

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#define MSM_SDW_COMPANDER7_CTL3 0x0030

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#define MSM_SDW_COMPANDER7_CTL4 0x0034

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#define MSM_SDW_COMPANDER7_CTL5 0x0038

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#define MSM_SDW_COMPANDER7_CTL6 0x003c

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#define MSM_SDW_COMPANDER7_CTL7 0x0040

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#define MSM_SDW_COMPANDER8_CTL0 0x0044

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#define MSM_SDW_COMPANDER8_CTL1 0x0048

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#define MSM_SDW_COMPANDER8_CTL2 0x004c

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#define MSM_SDW_COMPANDER8_CTL3 0x0050

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#define MSM_SDW_COMPANDER8_CTL4 0x0054

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#define MSM_SDW_COMPANDER8_CTL5 0x0058

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#define MSM_SDW_COMPANDER8_CTL6 0x005c

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#define MSM_SDW_COMPANDER8_CTL7 0x0060

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#define MSM_SDW_RX7_RX_PATH_CTL 0x01a4

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#define MSM_SDW_RX7_RX_PATH_CFG0 0x01a8

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#define MSM_SDW_RX7_RX_PATH_CFG1 0x01ac

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#define MSM_SDW_RX7_RX_PATH_CFG2 0x01b0

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#define MSM_SDW_RX7_RX_VOL_CTL 0x01b4

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#define MSM_SDW_RX7_RX_PATH_MIX_CTL 0x01b8

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#define MSM_SDW_RX7_RX_PATH_MIX_CFG 0x01bc

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#define MSM_SDW_RX7_RX_VOL_MIX_CTL 0x01c0

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#define MSM_SDW_RX7_RX_PATH_SEC0 0x01c4

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#define MSM_SDW_RX7_RX_PATH_SEC1 0x01c8

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#define MSM_SDW_RX7_RX_PATH_SEC2 0x01cc

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#define MSM_SDW_RX7_RX_PATH_SEC3 0x01d0

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#define MSM_SDW_RX7_RX_PATH_SEC5 0x01d8

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#define MSM_SDW_RX7_RX_PATH_SEC6 0x01dc

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#define MSM_SDW_RX7_RX_PATH_SEC7 0x01e0

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#define MSM_SDW_RX7_RX_PATH_MIX_SEC0 0x01e4

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#define MSM_SDW_RX7_RX_PATH_MIX_SEC1 0x01e8

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#define MSM_SDW_RX8_RX_PATH_CTL 0x0384

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#define MSM_SDW_RX8_RX_PATH_CFG0 0x0388

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#define MSM_SDW_RX8_RX_PATH_CFG1 0x038c

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#define MSM_SDW_RX8_RX_PATH_CFG2 0x0390

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#define MSM_SDW_RX8_RX_VOL_CTL 0x0394

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#define MSM_SDW_RX8_RX_PATH_MIX_CTL 0x0398

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#define MSM_SDW_RX8_RX_PATH_MIX_CFG 0x039c

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#define MSM_SDW_RX8_RX_VOL_MIX_CTL 0x03a0

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#define MSM_SDW_RX8_RX_PATH_SEC0 0x03a4

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#define MSM_SDW_RX8_RX_PATH_SEC1 0x03a8

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#define MSM_SDW_RX8_RX_PATH_SEC2 0x03ac

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#define MSM_SDW_RX8_RX_PATH_SEC3 0x03b0

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#define MSM_SDW_RX8_RX_PATH_SEC5 0x03b8

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#define MSM_SDW_RX8_RX_PATH_SEC6 0x03bc

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#define MSM_SDW_RX8_RX_PATH_SEC7 0x03c0

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#define MSM_SDW_RX8_RX_PATH_MIX_SEC0 0x03c4

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#define MSM_SDW_RX8_RX_PATH_MIX_SEC1 0x03c8

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/* Page-C Registers */

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#define MSM_SDW_BOOST0_BOOST_PATH_CTL 0x0064

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#define MSM_SDW_BOOST0_BOOST_CTL 0x0068

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#define MSM_SDW_BOOST0_BOOST_CFG1 0x006c

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#define MSM_SDW_BOOST0_BOOST_CFG2 0x0070

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#define MSM_SDW_BOOST1_BOOST_PATH_CTL 0x0084

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#define MSM_SDW_BOOST1_BOOST_CTL 0x0088

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#define MSM_SDW_BOOST1_BOOST_CFG1 0x008c

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#define MSM_SDW_BOOST1_BOOST_CFG2 0x0090

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#define MSM_SDW_AHB_BRIDGE_WR_DATA_0 0x00a4

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#define MSM_SDW_AHB_BRIDGE_WR_DATA_1 0x00a8

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#define MSM_SDW_AHB_BRIDGE_WR_DATA_2 0x00ac

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#define MSM_SDW_AHB_BRIDGE_WR_DATA_3 0x00b0

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#define MSM_SDW_AHB_BRIDGE_WR_ADDR_0 0x00b4

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#define MSM_SDW_AHB_BRIDGE_WR_ADDR_1 0x00b8

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#define MSM_SDW_AHB_BRIDGE_WR_ADDR_2 0x00bc

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#define MSM_SDW_AHB_BRIDGE_WR_ADDR_3 0x00c0

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#define MSM_SDW_AHB_BRIDGE_RD_ADDR_0 0x00c4

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#define MSM_SDW_AHB_BRIDGE_RD_ADDR_1 0x00c8

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#define MSM_SDW_AHB_BRIDGE_RD_ADDR_2 0x00cc

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#define MSM_SDW_AHB_BRIDGE_RD_ADDR_3 0x00d0

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#define MSM_SDW_AHB_BRIDGE_RD_DATA_0 0x00d4

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#define MSM_SDW_AHB_BRIDGE_RD_DATA_1 0x00d8

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#define MSM_SDW_AHB_BRIDGE_RD_DATA_2 0x00dc

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#define MSM_SDW_AHB_BRIDGE_RD_DATA_3 0x00e0

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#define MSM_SDW_AHB_BRIDGE_ACCESS_CFG 0x00e4

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#define MSM_SDW_AHB_BRIDGE_ACCESS_STATUS 0x00e8

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/* Page-D Registers */

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#define MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL 0x0104

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#define MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL 0x0108

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#define MSM_SDW_CLK_RST_CTRL_SWR_CONTROL 0x010c

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#define MSM_SDW_TOP_TOP_CFG0 0x0204

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#define MSM_SDW_TOP_TOP_CFG1 0x0208

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#define MSM_SDW_TOP_RX_I2S_CTL 0x020c

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#define MSM_SDW_TOP_TX_I2S_CTL 0x0210

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#define MSM_SDW_TOP_I2S_CLK 0x0214

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#define MSM_SDW_TOP_RX7_PATH_INPUT0_MUX 0x0218

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#define MSM_SDW_TOP_RX7_PATH_INPUT1_MUX 0x021c

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#define MSM_SDW_TOP_RX8_PATH_INPUT0_MUX 0x0220

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#define MSM_SDW_TOP_RX8_PATH_INPUT1_MUX 0x0224

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#define MSM_SDW_TOP_FREQ_MCLK 0x0228

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#define MSM_SDW_TOP_DEBUG_BUS_SEL 0x022c

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#define MSM_SDW_TOP_DEBUG_EN 0x0230

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#define MSM_SDW_TOP_I2S_RESET 0x0234

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#define MSM_SDW_TOP_BLOCKS_RESET 0x0238

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#endif