Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <linux/regmap.h> |
| 7 | #include <linux/device.h> |
| 8 | #include "wsa881x-registers.h" |
| 9 | #include "wsa881x.h" |
| 10 | |
| 11 | /* |
| 12 | * Default register reset values that are common across different versions |
| 13 | * are defined here. If a register reset value is changed based on version |
| 14 | * then remove it from this structure and add it in version specific |
| 15 | * structures. |
| 16 | */ |
| 17 | static struct reg_default wsa881x_defaults[] = { |
| 18 | {WSA881X_CHIP_ID0, 0x00}, |
| 19 | {WSA881X_CHIP_ID1, 0x00}, |
| 20 | {WSA881X_CHIP_ID2, 0x00}, |
| 21 | {WSA881X_CHIP_ID3, 0x02}, |
| 22 | {WSA881X_BUS_ID, 0x00}, |
| 23 | {WSA881X_CDC_RST_CTL, 0x00}, |
| 24 | {WSA881X_CDC_TOP_CLK_CTL, 0x03}, |
| 25 | {WSA881X_CDC_ANA_CLK_CTL, 0x00}, |
| 26 | {WSA881X_CDC_DIG_CLK_CTL, 0x00}, |
| 27 | {WSA881X_CLOCK_CONFIG, 0x00}, |
| 28 | {WSA881X_ANA_CTL, 0x08}, |
| 29 | {WSA881X_SWR_RESET_EN, 0x00}, |
| 30 | {WSA881X_TEMP_DETECT_CTL, 0x01}, |
| 31 | {WSA881X_TEMP_MSB, 0x00}, |
| 32 | {WSA881X_TEMP_LSB, 0x00}, |
| 33 | {WSA881X_TEMP_CONFIG0, 0x00}, |
| 34 | {WSA881X_TEMP_CONFIG1, 0x00}, |
| 35 | {WSA881X_CDC_CLIP_CTL, 0x03}, |
| 36 | {WSA881X_SDM_PDM9_LSB, 0x00}, |
| 37 | {WSA881X_SDM_PDM9_MSB, 0x00}, |
| 38 | {WSA881X_CDC_RX_CTL, 0x7E}, |
| 39 | {WSA881X_DEM_BYPASS_DATA0, 0x00}, |
| 40 | {WSA881X_DEM_BYPASS_DATA1, 0x00}, |
| 41 | {WSA881X_DEM_BYPASS_DATA2, 0x00}, |
| 42 | {WSA881X_DEM_BYPASS_DATA3, 0x00}, |
| 43 | {WSA881X_OTP_CTRL0, 0x00}, |
| 44 | {WSA881X_OTP_CTRL1, 0x00}, |
| 45 | {WSA881X_HDRIVE_CTL_GROUP1, 0x00}, |
| 46 | {WSA881X_INTR_MODE, 0x00}, |
| 47 | {WSA881X_INTR_STATUS, 0x00}, |
| 48 | {WSA881X_INTR_CLEAR, 0x00}, |
| 49 | {WSA881X_INTR_LEVEL, 0x00}, |
| 50 | {WSA881X_INTR_SET, 0x00}, |
| 51 | {WSA881X_INTR_TEST, 0x00}, |
| 52 | {WSA881X_PDM_TEST_MODE, 0x00}, |
| 53 | {WSA881X_ATE_TEST_MODE, 0x00}, |
| 54 | {WSA881X_PIN_CTL_MODE, 0x00}, |
| 55 | {WSA881X_PIN_CTL_OE, 0x00}, |
| 56 | {WSA881X_PIN_WDATA_IOPAD, 0x00}, |
| 57 | {WSA881X_PIN_STATUS, 0x00}, |
| 58 | {WSA881X_DIG_DEBUG_MODE, 0x00}, |
| 59 | {WSA881X_DIG_DEBUG_SEL, 0x00}, |
| 60 | {WSA881X_DIG_DEBUG_EN, 0x00}, |
| 61 | {WSA881X_SWR_HM_TEST1, 0x08}, |
| 62 | {WSA881X_SWR_HM_TEST2, 0x00}, |
| 63 | {WSA881X_TEMP_DETECT_DBG_CTL, 0x00}, |
| 64 | {WSA881X_TEMP_DEBUG_MSB, 0x00}, |
| 65 | {WSA881X_TEMP_DEBUG_LSB, 0x00}, |
| 66 | {WSA881X_SAMPLE_EDGE_SEL, 0x0C}, |
| 67 | {WSA881X_SPARE_0, 0x00}, |
| 68 | {WSA881X_SPARE_1, 0x00}, |
| 69 | {WSA881X_SPARE_2, 0x00}, |
| 70 | {WSA881X_OTP_REG_0, 0x01}, |
| 71 | {WSA881X_OTP_REG_1, 0xFF}, |
| 72 | {WSA881X_OTP_REG_2, 0xC0}, |
| 73 | {WSA881X_OTP_REG_3, 0xFF}, |
| 74 | {WSA881X_OTP_REG_4, 0xC0}, |
| 75 | {WSA881X_OTP_REG_5, 0xFF}, |
| 76 | {WSA881X_OTP_REG_6, 0xFF}, |
| 77 | {WSA881X_OTP_REG_7, 0xFF}, |
| 78 | {WSA881X_OTP_REG_8, 0xFF}, |
| 79 | {WSA881X_OTP_REG_9, 0xFF}, |
| 80 | {WSA881X_OTP_REG_10, 0xFF}, |
| 81 | {WSA881X_OTP_REG_11, 0xFF}, |
| 82 | {WSA881X_OTP_REG_12, 0xFF}, |
| 83 | {WSA881X_OTP_REG_13, 0xFF}, |
| 84 | {WSA881X_OTP_REG_14, 0xFF}, |
| 85 | {WSA881X_OTP_REG_15, 0xFF}, |
| 86 | {WSA881X_OTP_REG_16, 0xFF}, |
| 87 | {WSA881X_OTP_REG_17, 0xFF}, |
| 88 | {WSA881X_OTP_REG_18, 0xFF}, |
| 89 | {WSA881X_OTP_REG_19, 0xFF}, |
| 90 | {WSA881X_OTP_REG_20, 0xFF}, |
| 91 | {WSA881X_OTP_REG_21, 0xFF}, |
| 92 | {WSA881X_OTP_REG_22, 0xFF}, |
| 93 | {WSA881X_OTP_REG_23, 0xFF}, |
| 94 | {WSA881X_OTP_REG_24, 0x03}, |
| 95 | {WSA881X_OTP_REG_25, 0x01}, |
| 96 | {WSA881X_OTP_REG_26, 0x03}, |
| 97 | {WSA881X_OTP_REG_27, 0x11}, |
| 98 | {WSA881X_OTP_REG_63, 0x40}, |
| 99 | /* WSA881x Analog registers */ |
| 100 | {WSA881X_BIAS_REF_CTRL, 0x6C}, |
| 101 | {WSA881X_BIAS_TEST, 0x16}, |
| 102 | {WSA881X_BIAS_BIAS, 0xF0}, |
| 103 | {WSA881X_TEMP_OP, 0x00}, |
| 104 | {WSA881X_TEMP_IREF_CTRL, 0x56}, |
| 105 | {WSA881X_TEMP_ISENS_CTRL, 0x47}, |
| 106 | {WSA881X_TEMP_CLK_CTRL, 0x87}, |
| 107 | {WSA881X_TEMP_TEST, 0x00}, |
| 108 | {WSA881X_TEMP_BIAS, 0x51}, |
| 109 | {WSA881X_TEMP_DOUT_MSB, 0x00}, |
| 110 | {WSA881X_TEMP_DOUT_LSB, 0x00}, |
| 111 | {WSA881X_ADC_EN_MODU_V, 0x00}, |
| 112 | {WSA881X_ADC_EN_MODU_I, 0x00}, |
| 113 | {WSA881X_ADC_EN_DET_TEST_V, 0x00}, |
| 114 | {WSA881X_ADC_EN_DET_TEST_I, 0x00}, |
| 115 | {WSA881X_ADC_EN_SEL_IBAIS, 0x10}, |
| 116 | {WSA881X_SPKR_DRV_EN, 0x74}, |
| 117 | {WSA881X_SPKR_DRV_DBG, 0x15}, |
| 118 | {WSA881X_SPKR_PWRSTG_DBG, 0x00}, |
| 119 | {WSA881X_SPKR_OCP_CTL, 0xD4}, |
| 120 | {WSA881X_SPKR_CLIP_CTL, 0x90}, |
| 121 | {WSA881X_SPKR_PA_INT, 0x54}, |
| 122 | {WSA881X_SPKR_BIAS_CAL, 0xAC}, |
| 123 | {WSA881X_SPKR_STATUS1, 0x00}, |
| 124 | {WSA881X_SPKR_STATUS2, 0x00}, |
| 125 | {WSA881X_BOOST_EN_CTL, 0x18}, |
| 126 | {WSA881X_BOOST_CURRENT_LIMIT, 0x7A}, |
| 127 | {WSA881X_BOOST_PRESET_OUT2, 0x70}, |
| 128 | {WSA881X_BOOST_FORCE_OUT, 0x0E}, |
| 129 | {WSA881X_BOOST_LDO_PROG, 0x16}, |
| 130 | {WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71}, |
| 131 | {WSA881X_BOOST_RON_CTL, 0x0F}, |
| 132 | {WSA881X_BOOST_ZX_CTL, 0x34}, |
| 133 | {WSA881X_BOOST_START_CTL, 0x23}, |
| 134 | {WSA881X_BOOST_MISC1_CTL, 0x80}, |
| 135 | {WSA881X_BOOST_MISC2_CTL, 0x00}, |
| 136 | {WSA881X_BOOST_MISC3_CTL, 0x00}, |
| 137 | {WSA881X_BOOST_ATEST_CTL, 0x00}, |
| 138 | {WSA881X_SPKR_PROT_FE_GAIN, 0x46}, |
| 139 | {WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B}, |
| 140 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D}, |
| 141 | {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D}, |
| 142 | {WSA881X_SPKR_PROT_ATEST1, 0x01}, |
| 143 | {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D}, |
| 144 | {WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D}, |
| 145 | {WSA881X_SPKR_PROT_SAR, 0x00}, |
| 146 | {WSA881X_SPKR_STATUS3, 0x00}, |
| 147 | }; |
| 148 | |
| 149 | /* Default register reset values for WSA881x rev 2.0 */ |
| 150 | static struct reg_sequence wsa881x_rev_2_0[] = { |
| 151 | {WSA881X_RESET_CTL, 0x00, 0x00}, |
| 152 | {WSA881X_TADC_VALUE_CTL, 0x01, 0x00}, |
| 153 | {WSA881X_INTR_MASK, 0x1B, 0x00}, |
| 154 | {WSA881X_IOPAD_CTL, 0x00, 0x00}, |
| 155 | {WSA881X_OTP_REG_28, 0x3F, 0x00}, |
| 156 | {WSA881X_OTP_REG_29, 0x3F, 0x00}, |
| 157 | {WSA881X_OTP_REG_30, 0x01, 0x00}, |
| 158 | {WSA881X_OTP_REG_31, 0x01, 0x00}, |
| 159 | {WSA881X_TEMP_ADC_CTRL, 0x03, 0x00}, |
| 160 | {WSA881X_ADC_SEL_IBIAS, 0x45, 0x00}, |
| 161 | {WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00}, |
| 162 | {WSA881X_SPKR_DAC_CTL, 0x42, 0x00}, |
| 163 | {WSA881X_SPKR_BBM_CTL, 0x02, 0x00}, |
| 164 | {WSA881X_SPKR_MISC_CTL1, 0x40, 0x00}, |
| 165 | {WSA881X_SPKR_MISC_CTL2, 0x07, 0x00}, |
| 166 | {WSA881X_SPKR_BIAS_INT, 0x5F, 0x00}, |
| 167 | {WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00}, |
| 168 | {WSA881X_BOOST_PS_CTL, 0xA0, 0x00}, |
| 169 | {WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00}, |
| 170 | {WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00}, |
| 171 | {WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00}, |
| 172 | {WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00}, |
| 173 | {WSA881X_BONGO_RESRV_REG2, 0x07, 0x00}, |
| 174 | }; |
| 175 | |
| 176 | /* |
| 177 | * wsa881x_regmap_defaults - update regmap default register values |
| 178 | * @regmap: pointer to regmap structure |
| 179 | * @version: wsa881x version id |
| 180 | * |
| 181 | * Update regmap default register values based on version id |
| 182 | * |
| 183 | */ |
| 184 | void wsa881x_regmap_defaults(struct regmap *regmap, u8 version) |
| 185 | { |
| 186 | u16 ret = 0; |
| 187 | |
| 188 | if (!regmap) { |
| 189 | pr_debug("%s: regmap structure is NULL\n", __func__); |
| 190 | return; |
| 191 | } |
| 192 | |
| 193 | regcache_cache_only(regmap, true); |
| 194 | ret = regmap_multi_reg_write(regmap, wsa881x_rev_2_0, |
| 195 | ARRAY_SIZE(wsa881x_rev_2_0)); |
| 196 | regcache_cache_only(regmap, false); |
| 197 | |
| 198 | if (ret) |
| 199 | pr_debug("%s: Failed to update regmap defaults ret= %d\n", |
| 200 | __func__, ret); |
| 201 | } |
| 202 | EXPORT_SYMBOL(wsa881x_regmap_defaults); |
| 203 | |
| 204 | static bool wsa881x_readable_register(struct device *dev, unsigned int reg) |
| 205 | { |
| 206 | return wsa881x_reg_readable[reg]; |
| 207 | } |
| 208 | |
| 209 | static bool wsa881x_volatile_register(struct device *dev, unsigned int reg) |
| 210 | { |
| 211 | switch (reg) { |
| 212 | case WSA881X_CHIP_ID0: |
| 213 | case WSA881X_CHIP_ID1: |
| 214 | case WSA881X_CHIP_ID2: |
| 215 | case WSA881X_CHIP_ID3: |
| 216 | case WSA881X_BUS_ID: |
| 217 | case WSA881X_TEMP_MSB: |
| 218 | case WSA881X_TEMP_LSB: |
| 219 | case WSA881X_SDM_PDM9_LSB: |
| 220 | case WSA881X_SDM_PDM9_MSB: |
| 221 | case WSA881X_OTP_CTRL1: |
| 222 | case WSA881X_INTR_STATUS: |
| 223 | case WSA881X_ATE_TEST_MODE: |
| 224 | case WSA881X_PIN_STATUS: |
| 225 | case WSA881X_SWR_HM_TEST2: |
| 226 | case WSA881X_SPKR_STATUS1: |
| 227 | case WSA881X_SPKR_STATUS2: |
| 228 | case WSA881X_SPKR_STATUS3: |
| 229 | case WSA881X_OTP_REG_0: |
| 230 | case WSA881X_OTP_REG_1: |
| 231 | case WSA881X_OTP_REG_2: |
| 232 | case WSA881X_OTP_REG_3: |
| 233 | case WSA881X_OTP_REG_4: |
| 234 | case WSA881X_OTP_REG_5: |
| 235 | case WSA881X_OTP_REG_31: |
| 236 | case WSA881X_TEMP_DOUT_MSB: |
| 237 | case WSA881X_TEMP_DOUT_LSB: |
| 238 | case WSA881X_TEMP_OP: |
| 239 | case WSA881X_SPKR_PROT_SAR: |
| 240 | return true; |
| 241 | default: |
| 242 | return false; |
| 243 | } |
| 244 | } |
| 245 | |
| 246 | struct regmap_config wsa881x_regmap_config = { |
| 247 | .reg_bits = 16, |
| 248 | .val_bits = 8, |
| 249 | .cache_type = REGCACHE_RBTREE, |
| 250 | .reg_defaults = wsa881x_defaults, |
| 251 | .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults), |
| 252 | .max_register = WSA881X_MAX_REGISTER, |
| 253 | .volatile_reg = wsa881x_volatile_register, |
| 254 | .readable_reg = wsa881x_readable_register, |
| 255 | .reg_format_endian = REGMAP_ENDIAN_NATIVE, |
| 256 | .val_format_endian = REGMAP_ENDIAN_NATIVE, |
| 257 | .can_multi_write = true, |
| 258 | }; |