| Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #ifndef _BOLERO_CDC_REGISTERS_H |
| 6 | #define _BOLERO_CDC_REGISTERS_H |
| 7 | |
| 8 | #define TX_START_OFFSET 0x0000 |
| 9 | |
| 10 | #define BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (TX_START_OFFSET + 0x0000) |
| 11 | #define BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (TX_START_OFFSET + 0x0004) |
| 12 | #define BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL (TX_START_OFFSET + 0x0008) |
| 13 | #define BOLERO_CDC_TX_TOP_CSR_TOP_CFG0 (TX_START_OFFSET + 0x0080) |
| 14 | #define BOLERO_CDC_TX_TOP_CSR_ANC_CFG (TX_START_OFFSET + 0x0084) |
| 15 | #define BOLERO_CDC_TX_TOP_CSR_SWR_CTRL (TX_START_OFFSET + 0x0088) |
| 16 | #define BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK (TX_START_OFFSET + 0x0090) |
| 17 | #define BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS (TX_START_OFFSET + 0x0094) |
| 18 | #define BOLERO_CDC_TX_TOP_CSR_DEBUG_EN (TX_START_OFFSET + 0x0098) |
| 19 | #define BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL (TX_START_OFFSET + 0x00A4) |
| 20 | #define BOLERO_CDC_TX_TOP_CSR_I2S_CLK (TX_START_OFFSET + 0x00A8) |
| 21 | #define BOLERO_CDC_TX_TOP_CSR_I2S_RESET (TX_START_OFFSET + 0x00AC) |
| 22 | #define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL (TX_START_OFFSET + 0x00C0) |
| 23 | #define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL (TX_START_OFFSET + 0x00C4) |
| 24 | #define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL (TX_START_OFFSET + 0x00C8) |
| 25 | #define BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL (TX_START_OFFSET + 0x00CC) |
| 26 | #define BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL (TX_START_OFFSET + 0x00D0) |
| 27 | #define BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL (TX_START_OFFSET + 0x00D4) |
| 28 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0 (TX_START_OFFSET + 0x0100) |
| 29 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1 (TX_START_OFFSET + 0x0104) |
| 30 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0 (TX_START_OFFSET + 0x0108) |
| 31 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1 (TX_START_OFFSET + 0x010C) |
| 32 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0 (TX_START_OFFSET + 0x0110) |
| 33 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1 (TX_START_OFFSET + 0x0114) |
| 34 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0 (TX_START_OFFSET + 0x0118) |
| 35 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1 (TX_START_OFFSET + 0x011C) |
| 36 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0 (TX_START_OFFSET + 0x0120) |
| 37 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1 (TX_START_OFFSET + 0x0124) |
| 38 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0 (TX_START_OFFSET + 0x0128) |
| 39 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1 (TX_START_OFFSET + 0x012C) |
| 40 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0 (TX_START_OFFSET + 0x0130) |
| 41 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1 (TX_START_OFFSET + 0x0134) |
| 42 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0 (TX_START_OFFSET + 0x0138) |
| 43 | #define BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1 (TX_START_OFFSET + 0x013C) |
| 44 | #define BOLERO_CDC_TX_ANC0_CLK_RESET_CTL (TX_START_OFFSET + 0x0200) |
| 45 | #define BOLERO_CDC_TX_ANC0_MODE_1_CTL (TX_START_OFFSET + 0x0204) |
| 46 | #define BOLERO_CDC_TX_ANC0_MODE_2_CTL (TX_START_OFFSET + 0x0208) |
| 47 | #define BOLERO_CDC_TX_ANC0_FF_SHIFT (TX_START_OFFSET + 0x020C) |
| 48 | #define BOLERO_CDC_TX_ANC0_FB_SHIFT (TX_START_OFFSET + 0x0210) |
| 49 | #define BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL (TX_START_OFFSET + 0x0214) |
| 50 | #define BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL (TX_START_OFFSET + 0x0218) |
| 51 | #define BOLERO_CDC_TX_ANC0_LPF_FB_CTL (TX_START_OFFSET + 0x021C) |
| 52 | #define BOLERO_CDC_TX_ANC0_SMLPF_CTL (TX_START_OFFSET + 0x0220) |
| 53 | #define BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL (TX_START_OFFSET + 0x0224) |
| 54 | #define BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL (TX_START_OFFSET + 0x0228) |
| 55 | #define BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL (TX_START_OFFSET + 0x022C) |
| 56 | #define BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL (TX_START_OFFSET + 0x0230) |
| 57 | #define BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL (TX_START_OFFSET + 0x0234) |
| 58 | #define BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL (TX_START_OFFSET + 0x0238) |
| 59 | #define BOLERO_CDC_TX_ANC0_FB_GAIN_CTL (TX_START_OFFSET + 0x023C) |
| 60 | #define BOLERO_CDC_TX0_TX_PATH_CTL (TX_START_OFFSET + 0x0400) |
| 61 | #define BOLERO_CDC_TX0_TX_PATH_CFG0 (TX_START_OFFSET + 0x0404) |
| 62 | #define BOLERO_CDC_TX0_TX_PATH_CFG1 (TX_START_OFFSET + 0x0408) |
| 63 | #define BOLERO_CDC_TX0_TX_VOL_CTL (TX_START_OFFSET + 0x040C) |
| 64 | #define BOLERO_CDC_TX0_TX_PATH_SEC0 (TX_START_OFFSET + 0x0410) |
| 65 | #define BOLERO_CDC_TX0_TX_PATH_SEC1 (TX_START_OFFSET + 0x0414) |
| 66 | #define BOLERO_CDC_TX0_TX_PATH_SEC2 (TX_START_OFFSET + 0x0418) |
| 67 | #define BOLERO_CDC_TX0_TX_PATH_SEC3 (TX_START_OFFSET + 0x041C) |
| 68 | #define BOLERO_CDC_TX0_TX_PATH_SEC4 (TX_START_OFFSET + 0x0420) |
| 69 | #define BOLERO_CDC_TX0_TX_PATH_SEC5 (TX_START_OFFSET + 0x0424) |
| 70 | #define BOLERO_CDC_TX0_TX_PATH_SEC6 (TX_START_OFFSET + 0x0428) |
| 71 | #define BOLERO_CDC_TX0_TX_PATH_SEC7 (TX_START_OFFSET + 0x042C) |
| 72 | #define BOLERO_CDC_TX1_TX_PATH_CTL (TX_START_OFFSET + 0x0480) |
| 73 | #define BOLERO_CDC_TX1_TX_PATH_CFG0 (TX_START_OFFSET + 0x0484) |
| 74 | #define BOLERO_CDC_TX1_TX_PATH_CFG1 (TX_START_OFFSET + 0x0488) |
| 75 | #define BOLERO_CDC_TX1_TX_VOL_CTL (TX_START_OFFSET + 0x048C) |
| 76 | #define BOLERO_CDC_TX1_TX_PATH_SEC0 (TX_START_OFFSET + 0x0490) |
| 77 | #define BOLERO_CDC_TX1_TX_PATH_SEC1 (TX_START_OFFSET + 0x0494) |
| 78 | #define BOLERO_CDC_TX1_TX_PATH_SEC2 (TX_START_OFFSET + 0x0498) |
| 79 | #define BOLERO_CDC_TX1_TX_PATH_SEC3 (TX_START_OFFSET + 0x049C) |
| 80 | #define BOLERO_CDC_TX1_TX_PATH_SEC4 (TX_START_OFFSET + 0x04A0) |
| 81 | #define BOLERO_CDC_TX1_TX_PATH_SEC5 (TX_START_OFFSET + 0x04A4) |
| 82 | #define BOLERO_CDC_TX1_TX_PATH_SEC6 (TX_START_OFFSET + 0x04A8) |
| 83 | #define BOLERO_CDC_TX2_TX_PATH_CTL (TX_START_OFFSET + 0x0500) |
| 84 | #define BOLERO_CDC_TX2_TX_PATH_CFG0 (TX_START_OFFSET + 0x0504) |
| 85 | #define BOLERO_CDC_TX2_TX_PATH_CFG1 (TX_START_OFFSET + 0x0508) |
| 86 | #define BOLERO_CDC_TX2_TX_VOL_CTL (TX_START_OFFSET + 0x050C) |
| 87 | #define BOLERO_CDC_TX2_TX_PATH_SEC0 (TX_START_OFFSET + 0x0510) |
| 88 | #define BOLERO_CDC_TX2_TX_PATH_SEC1 (TX_START_OFFSET + 0x0514) |
| 89 | #define BOLERO_CDC_TX2_TX_PATH_SEC2 (TX_START_OFFSET + 0x0518) |
| 90 | #define BOLERO_CDC_TX2_TX_PATH_SEC3 (TX_START_OFFSET + 0x051C) |
| 91 | #define BOLERO_CDC_TX2_TX_PATH_SEC4 (TX_START_OFFSET + 0x0520) |
| 92 | #define BOLERO_CDC_TX2_TX_PATH_SEC5 (TX_START_OFFSET + 0x0524) |
| 93 | #define BOLERO_CDC_TX2_TX_PATH_SEC6 (TX_START_OFFSET + 0x0528) |
| 94 | #define BOLERO_CDC_TX3_TX_PATH_CTL (TX_START_OFFSET + 0x0580) |
| 95 | #define BOLERO_CDC_TX3_TX_PATH_CFG0 (TX_START_OFFSET + 0x0584) |
| 96 | #define BOLERO_CDC_TX3_TX_PATH_CFG1 (TX_START_OFFSET + 0x0588) |
| 97 | #define BOLERO_CDC_TX3_TX_VOL_CTL (TX_START_OFFSET + 0x058C) |
| 98 | #define BOLERO_CDC_TX3_TX_PATH_SEC0 (TX_START_OFFSET + 0x0590) |
| 99 | #define BOLERO_CDC_TX3_TX_PATH_SEC1 (TX_START_OFFSET + 0x0594) |
| 100 | #define BOLERO_CDC_TX3_TX_PATH_SEC2 (TX_START_OFFSET + 0x0598) |
| 101 | #define BOLERO_CDC_TX3_TX_PATH_SEC3 (TX_START_OFFSET + 0x059C) |
| 102 | #define BOLERO_CDC_TX3_TX_PATH_SEC4 (TX_START_OFFSET + 0x05A0) |
| 103 | #define BOLERO_CDC_TX3_TX_PATH_SEC5 (TX_START_OFFSET + 0x05A4) |
| 104 | #define BOLERO_CDC_TX3_TX_PATH_SEC6 (TX_START_OFFSET + 0x05A8) |
| 105 | #define BOLERO_CDC_TX4_TX_PATH_CTL (TX_START_OFFSET + 0x0600) |
| 106 | #define BOLERO_CDC_TX4_TX_PATH_CFG0 (TX_START_OFFSET + 0x0604) |
| 107 | #define BOLERO_CDC_TX4_TX_PATH_CFG1 (TX_START_OFFSET + 0x0608) |
| 108 | #define BOLERO_CDC_TX4_TX_VOL_CTL (TX_START_OFFSET + 0x060C) |
| 109 | #define BOLERO_CDC_TX4_TX_PATH_SEC0 (TX_START_OFFSET + 0x0610) |
| 110 | #define BOLERO_CDC_TX4_TX_PATH_SEC1 (TX_START_OFFSET + 0x0614) |
| 111 | #define BOLERO_CDC_TX4_TX_PATH_SEC2 (TX_START_OFFSET + 0x0618) |
| 112 | #define BOLERO_CDC_TX4_TX_PATH_SEC3 (TX_START_OFFSET + 0x061C) |
| 113 | #define BOLERO_CDC_TX4_TX_PATH_SEC4 (TX_START_OFFSET + 0x0620) |
| 114 | #define BOLERO_CDC_TX4_TX_PATH_SEC5 (TX_START_OFFSET + 0x0624) |
| 115 | #define BOLERO_CDC_TX4_TX_PATH_SEC6 (TX_START_OFFSET + 0x0628) |
| 116 | #define BOLERO_CDC_TX5_TX_PATH_CTL (TX_START_OFFSET + 0x0680) |
| 117 | #define BOLERO_CDC_TX5_TX_PATH_CFG0 (TX_START_OFFSET + 0x0684) |
| 118 | #define BOLERO_CDC_TX5_TX_PATH_CFG1 (TX_START_OFFSET + 0x0688) |
| 119 | #define BOLERO_CDC_TX5_TX_VOL_CTL (TX_START_OFFSET + 0x068C) |
| 120 | #define BOLERO_CDC_TX5_TX_PATH_SEC0 (TX_START_OFFSET + 0x0690) |
| 121 | #define BOLERO_CDC_TX5_TX_PATH_SEC1 (TX_START_OFFSET + 0x0694) |
| 122 | #define BOLERO_CDC_TX5_TX_PATH_SEC2 (TX_START_OFFSET + 0x0698) |
| 123 | #define BOLERO_CDC_TX5_TX_PATH_SEC3 (TX_START_OFFSET + 0x069C) |
| 124 | #define BOLERO_CDC_TX5_TX_PATH_SEC4 (TX_START_OFFSET + 0x06A0) |
| 125 | #define BOLERO_CDC_TX5_TX_PATH_SEC5 (TX_START_OFFSET + 0x06A4) |
| 126 | #define BOLERO_CDC_TX5_TX_PATH_SEC6 (TX_START_OFFSET + 0x06A8) |
| 127 | #define BOLERO_CDC_TX6_TX_PATH_CTL (TX_START_OFFSET + 0x0700) |
| 128 | #define BOLERO_CDC_TX6_TX_PATH_CFG0 (TX_START_OFFSET + 0x0704) |
| 129 | #define BOLERO_CDC_TX6_TX_PATH_CFG1 (TX_START_OFFSET + 0x0708) |
| 130 | #define BOLERO_CDC_TX6_TX_VOL_CTL (TX_START_OFFSET + 0x070C) |
| 131 | #define BOLERO_CDC_TX6_TX_PATH_SEC0 (TX_START_OFFSET + 0x0710) |
| 132 | #define BOLERO_CDC_TX6_TX_PATH_SEC1 (TX_START_OFFSET + 0x0714) |
| 133 | #define BOLERO_CDC_TX6_TX_PATH_SEC2 (TX_START_OFFSET + 0x0718) |
| 134 | #define BOLERO_CDC_TX6_TX_PATH_SEC3 (TX_START_OFFSET + 0x071C) |
| 135 | #define BOLERO_CDC_TX6_TX_PATH_SEC4 (TX_START_OFFSET + 0x0720) |
| 136 | #define BOLERO_CDC_TX6_TX_PATH_SEC5 (TX_START_OFFSET + 0x0724) |
| 137 | #define BOLERO_CDC_TX6_TX_PATH_SEC6 (TX_START_OFFSET + 0x0728) |
| 138 | #define BOLERO_CDC_TX7_TX_PATH_CTL (TX_START_OFFSET + 0x0780) |
| 139 | #define BOLERO_CDC_TX7_TX_PATH_CFG0 (TX_START_OFFSET + 0x0784) |
| 140 | #define BOLERO_CDC_TX7_TX_PATH_CFG1 (TX_START_OFFSET + 0x0788) |
| 141 | #define BOLERO_CDC_TX7_TX_VOL_CTL (TX_START_OFFSET + 0x078C) |
| 142 | #define BOLERO_CDC_TX7_TX_PATH_SEC0 (TX_START_OFFSET + 0x0790) |
| 143 | #define BOLERO_CDC_TX7_TX_PATH_SEC1 (TX_START_OFFSET + 0x0794) |
| 144 | #define BOLERO_CDC_TX7_TX_PATH_SEC2 (TX_START_OFFSET + 0x0798) |
| 145 | #define BOLERO_CDC_TX7_TX_PATH_SEC3 (TX_START_OFFSET + 0x079C) |
| 146 | #define BOLERO_CDC_TX7_TX_PATH_SEC4 (TX_START_OFFSET + 0x07A0) |
| 147 | #define BOLERO_CDC_TX7_TX_PATH_SEC5 (TX_START_OFFSET + 0x07A4) |
| 148 | #define BOLERO_CDC_TX7_TX_PATH_SEC6 (TX_START_OFFSET + 0x07A8) |
| 149 | #define TX_MAX_OFFSET (TX_START_OFFSET + 0x07A8) |
| 150 | |
| 151 | #define BOLERO_CDC_TX_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 */ |
| 152 | |
| 153 | #define RX_START_OFFSET 0x1000 |
| 154 | #define BOLERO_CDC_RX_TOP_TOP_CFG0 (RX_START_OFFSET + 0x0000) |
| 155 | #define BOLERO_CDC_RX_TOP_SWR_CTRL (RX_START_OFFSET + 0x0008) |
| 156 | #define BOLERO_CDC_RX_TOP_DEBUG (RX_START_OFFSET + 0x000C) |
| 157 | #define BOLERO_CDC_RX_TOP_DEBUG_BUS (RX_START_OFFSET + 0x0010) |
| 158 | #define BOLERO_CDC_RX_TOP_DEBUG_EN0 (RX_START_OFFSET + 0x0014) |
| 159 | #define BOLERO_CDC_RX_TOP_DEBUG_EN1 (RX_START_OFFSET + 0x0018) |
| 160 | #define BOLERO_CDC_RX_TOP_DEBUG_EN2 (RX_START_OFFSET + 0x001C) |
| 161 | #define BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB (RX_START_OFFSET + 0x0020) |
| 162 | #define BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB (RX_START_OFFSET + 0x0024) |
| 163 | #define BOLERO_CDC_RX_TOP_HPHL_COMP_LUT (RX_START_OFFSET + 0x0028) |
| 164 | #define BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB (RX_START_OFFSET + 0x002C) |
| 165 | #define BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB (RX_START_OFFSET + 0x0030) |
| 166 | #define BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB (RX_START_OFFSET + 0x0034) |
| 167 | #define BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB (RX_START_OFFSET + 0x0038) |
| 168 | #define BOLERO_CDC_RX_TOP_HPHR_COMP_LUT (RX_START_OFFSET + 0x003C) |
| 169 | #define BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB (RX_START_OFFSET + 0x0040) |
| 170 | #define BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB (RX_START_OFFSET + 0x0044) |
| 171 | #define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG0 (RX_START_OFFSET + 0x0070) |
| 172 | #define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG1 (RX_START_OFFSET + 0x0074) |
| 173 | #define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2 (RX_START_OFFSET + 0x0078) |
| 174 | #define BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG3 (RX_START_OFFSET + 0x007C) |
| 175 | #define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG0 (RX_START_OFFSET + 0x0080) |
| 176 | #define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG1 (RX_START_OFFSET + 0x0084) |
| 177 | #define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2 (RX_START_OFFSET + 0x0088) |
| 178 | #define BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG3 (RX_START_OFFSET + 0x008C) |
| 179 | #define BOLERO_CDC_RX_TOP_RX_I2S_CTL (RX_START_OFFSET + 0x0090) |
| 180 | #define BOLERO_CDC_RX_TOP_TX_I2S2_CTL (RX_START_OFFSET + 0x0094) |
| 181 | #define BOLERO_CDC_RX_TOP_I2S_CLK (RX_START_OFFSET + 0x0098) |
| 182 | #define BOLERO_CDC_RX_TOP_I2S_RESET (RX_START_OFFSET + 0x009C) |
| 183 | #define BOLERO_CDC_RX_TOP_I2S_MUX (RX_START_OFFSET + 0x00A0) |
| 184 | #define BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (RX_START_OFFSET + 0x0100) |
| 185 | #define BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL \ |
| 186 | (RX_START_OFFSET + 0x0104) |
| 187 | #define BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL (RX_START_OFFSET + 0x0108) |
| 188 | #define BOLERO_CDC_RX_CLK_RST_CTRL_DSD_CONTROL (RX_START_OFFSET + 0x010C) |
| 189 | #define BOLERO_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL \ |
| 190 | (RX_START_OFFSET + 0x0110) |
| 191 | #define BOLERO_CDC_RX_SOFTCLIP_CRC (RX_START_OFFSET + 0x0140) |
| 192 | #define BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (RX_START_OFFSET + 0x0144) |
| 193 | #define BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0 (RX_START_OFFSET + 0x0180) |
| 194 | #define BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1 (RX_START_OFFSET + 0x0184) |
| 195 | #define BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0 (RX_START_OFFSET + 0x0188) |
| 196 | #define BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1 (RX_START_OFFSET + 0x018C) |
| 197 | #define BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0 (RX_START_OFFSET + 0x0190) |
| 198 | #define BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1 (RX_START_OFFSET + 0x0194) |
| 199 | #define BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4 (RX_START_OFFSET + 0x0198) |
| 200 | #define BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5 (RX_START_OFFSET + 0x019C) |
| 201 | #define BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (RX_START_OFFSET + 0x01A0) |
| 202 | #define BOLERO_CDC_RX_CLSH_CRC (RX_START_OFFSET + 0x0200) |
| 203 | #define BOLERO_CDC_RX_CLSH_DLY_CTRL (RX_START_OFFSET + 0x0204) |
| 204 | #define BOLERO_CDC_RX_CLSH_DECAY_CTRL (RX_START_OFFSET + 0x0208) |
| 205 | #define BOLERO_CDC_RX_CLSH_HPH_V_PA (RX_START_OFFSET + 0x020C) |
| 206 | #define BOLERO_CDC_RX_CLSH_EAR_V_PA (RX_START_OFFSET + 0x0210) |
| 207 | #define BOLERO_CDC_RX_CLSH_HPH_V_HD (RX_START_OFFSET + 0x0214) |
| 208 | #define BOLERO_CDC_RX_CLSH_EAR_V_HD (RX_START_OFFSET + 0x0218) |
| 209 | #define BOLERO_CDC_RX_CLSH_K1_MSB (RX_START_OFFSET + 0x021C) |
| 210 | #define BOLERO_CDC_RX_CLSH_K1_LSB (RX_START_OFFSET + 0x0220) |
| 211 | #define BOLERO_CDC_RX_CLSH_K2_MSB (RX_START_OFFSET + 0x0224) |
| 212 | #define BOLERO_CDC_RX_CLSH_K2_LSB (RX_START_OFFSET + 0x0228) |
| 213 | #define BOLERO_CDC_RX_CLSH_IDLE_CTRL (RX_START_OFFSET + 0x022C) |
| 214 | #define BOLERO_CDC_RX_CLSH_IDLE_HPH (RX_START_OFFSET + 0x0230) |
| 215 | #define BOLERO_CDC_RX_CLSH_IDLE_EAR (RX_START_OFFSET + 0x0234) |
| 216 | #define BOLERO_CDC_RX_CLSH_TEST0 (RX_START_OFFSET + 0x0238) |
| 217 | #define BOLERO_CDC_RX_CLSH_TEST1 (RX_START_OFFSET + 0x023C) |
| 218 | #define BOLERO_CDC_RX_CLSH_OVR_VREF (RX_START_OFFSET + 0x0240) |
| 219 | #define BOLERO_CDC_RX_CLSH_CLSG_CTL (RX_START_OFFSET + 0x0244) |
| 220 | #define BOLERO_CDC_RX_CLSH_CLSG_CFG1 (RX_START_OFFSET + 0x0248) |
| 221 | #define BOLERO_CDC_RX_CLSH_CLSG_CFG2 (RX_START_OFFSET + 0x024C) |
| 222 | #define BOLERO_CDC_RX_BCL_VBAT_PATH_CTL (RX_START_OFFSET + 0x0280) |
| 223 | #define BOLERO_CDC_RX_BCL_VBAT_CFG (RX_START_OFFSET + 0x0284) |
| 224 | #define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL1 (RX_START_OFFSET + 0x0288) |
| 225 | #define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL2 (RX_START_OFFSET + 0x028C) |
| 226 | #define BOLERO_CDC_RX_BCL_VBAT_ADC_CAL3 (RX_START_OFFSET + 0x0290) |
| 227 | #define BOLERO_CDC_RX_BCL_VBAT_PK_EST1 (RX_START_OFFSET + 0x0294) |
| 228 | #define BOLERO_CDC_RX_BCL_VBAT_PK_EST2 (RX_START_OFFSET + 0x0298) |
| 229 | #define BOLERO_CDC_RX_BCL_VBAT_PK_EST3 (RX_START_OFFSET + 0x029C) |
| 230 | #define BOLERO_CDC_RX_BCL_VBAT_RF_PROC1 (RX_START_OFFSET + 0x02A0) |
| 231 | #define BOLERO_CDC_RX_BCL_VBAT_RF_PROC2 (RX_START_OFFSET + 0x02A4) |
| 232 | #define BOLERO_CDC_RX_BCL_VBAT_TAC1 (RX_START_OFFSET + 0x02A8) |
| 233 | #define BOLERO_CDC_RX_BCL_VBAT_TAC2 (RX_START_OFFSET + 0x02AC) |
| 234 | #define BOLERO_CDC_RX_BCL_VBAT_TAC3 (RX_START_OFFSET + 0x02B0) |
| 235 | #define BOLERO_CDC_RX_BCL_VBAT_TAC4 (RX_START_OFFSET + 0x02B4) |
| 236 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD1 (RX_START_OFFSET + 0x02B8) |
| 237 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD2 (RX_START_OFFSET + 0x02BC) |
| 238 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD3 (RX_START_OFFSET + 0x02C0) |
| 239 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD4 (RX_START_OFFSET + 0x02C4) |
| 240 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD5 (RX_START_OFFSET + 0x02C8) |
| 241 | #define BOLERO_CDC_RX_BCL_VBAT_DEBUG1 (RX_START_OFFSET + 0x02CC) |
| 242 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD_MON (RX_START_OFFSET + 0x02D0) |
| 243 | #define BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL (RX_START_OFFSET + 0x02D4) |
| 244 | #define BOLERO_CDC_RX_BCL_VBAT_BAN (RX_START_OFFSET + 0x02D8) |
| 245 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (RX_START_OFFSET + 0x02DC) |
| 246 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (RX_START_OFFSET + 0x02E0) |
| 247 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (RX_START_OFFSET + 0x02E4) |
| 248 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (RX_START_OFFSET + 0x02E8) |
| 249 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (RX_START_OFFSET + 0x02EC) |
| 250 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (RX_START_OFFSET + 0x02F0) |
| 251 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (RX_START_OFFSET + 0x02F4) |
| 252 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (RX_START_OFFSET + 0x02F8) |
| 253 | #define BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (RX_START_OFFSET + 0x02FC) |
| 254 | #define BOLERO_CDC_RX_BCL_VBAT_ATTN1 (RX_START_OFFSET + 0x0300) |
| 255 | #define BOLERO_CDC_RX_BCL_VBAT_ATTN2 (RX_START_OFFSET + 0x0304) |
| 256 | #define BOLERO_CDC_RX_BCL_VBAT_ATTN3 (RX_START_OFFSET + 0x0308) |
| 257 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1 (RX_START_OFFSET + 0x030C) |
| 258 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL2 (RX_START_OFFSET + 0x0310) |
| 259 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1 (RX_START_OFFSET + 0x0314) |
| 260 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2 (RX_START_OFFSET + 0x0318) |
| 261 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3 (RX_START_OFFSET + 0x031C) |
| 262 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG4 (RX_START_OFFSET + 0x0320) |
| 263 | #define BOLERO_CDC_RX_BCL_VBAT_DECODE_ST (RX_START_OFFSET + 0x0324) |
| 264 | #define BOLERO_CDC_RX_INTR_CTRL_CFG (RX_START_OFFSET + 0x0340) |
| 265 | #define BOLERO_CDC_RX_INTR_CTRL_CLR_COMMIT (RX_START_OFFSET + 0x0344) |
| 266 | #define BOLERO_CDC_RX_INTR_CTRL_PIN1_MASK0 (RX_START_OFFSET + 0x0360) |
| 267 | #define BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0 (RX_START_OFFSET + 0x0368) |
| 268 | #define BOLERO_CDC_RX_INTR_CTRL_PIN1_CLEAR0 (RX_START_OFFSET + 0x0370) |
| 269 | #define BOLERO_CDC_RX_INTR_CTRL_PIN2_MASK0 (RX_START_OFFSET + 0x0380) |
| 270 | #define BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0 (RX_START_OFFSET + 0x0388) |
| 271 | #define BOLERO_CDC_RX_INTR_CTRL_PIN2_CLEAR0 (RX_START_OFFSET + 0x0390) |
| 272 | #define BOLERO_CDC_RX_INTR_CTRL_LEVEL0 (RX_START_OFFSET + 0x03C0) |
| 273 | #define BOLERO_CDC_RX_INTR_CTRL_BYPASS0 (RX_START_OFFSET + 0x03C8) |
| 274 | #define BOLERO_CDC_RX_INTR_CTRL_SET0 (RX_START_OFFSET + 0x03D0) |
| 275 | #define BOLERO_CDC_RX_RX0_RX_PATH_CTL (RX_START_OFFSET + 0x0400) |
| 276 | #define BOLERO_CDC_RX_RX0_RX_PATH_CFG0 (RX_START_OFFSET + 0x0404) |
| 277 | #define BOLERO_CDC_RX_RX0_RX_PATH_CFG1 (RX_START_OFFSET + 0x0408) |
| 278 | #define BOLERO_CDC_RX_RX0_RX_PATH_CFG2 (RX_START_OFFSET + 0x040C) |
| 279 | #define BOLERO_CDC_RX_RX0_RX_PATH_CFG3 (RX_START_OFFSET + 0x0410) |
| 280 | #define BOLERO_CDC_RX_RX0_RX_VOL_CTL (RX_START_OFFSET + 0x0414) |
| 281 | #define BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0418) |
| 282 | #define BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x041C) |
| 283 | #define BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0420) |
| 284 | #define BOLERO_CDC_RX_RX0_RX_PATH_SEC1 (RX_START_OFFSET + 0x0424) |
| 285 | #define BOLERO_CDC_RX_RX0_RX_PATH_SEC2 (RX_START_OFFSET + 0x0428) |
| 286 | #define BOLERO_CDC_RX_RX0_RX_PATH_SEC3 (RX_START_OFFSET + 0x042C) |
| 287 | #define BOLERO_CDC_RX_RX0_RX_PATH_SEC4 (RX_START_OFFSET + 0x0430) |
| 288 | #define BOLERO_CDC_RX_RX0_RX_PATH_SEC7 (RX_START_OFFSET + 0x0434) |
| 289 | #define BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0438) |
| 290 | #define BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x043C) |
| 291 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x0440) |
| 292 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x0444) |
| 293 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x0448) |
| 294 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x044C) |
| 295 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x0450) |
| 296 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x0454) |
| 297 | #define BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x0458) |
| 298 | #define BOLERO_CDC_RX_RX1_RX_PATH_CTL (RX_START_OFFSET + 0x0480) |
| 299 | #define BOLERO_CDC_RX_RX1_RX_PATH_CFG0 (RX_START_OFFSET + 0x0484) |
| 300 | #define BOLERO_CDC_RX_RX1_RX_PATH_CFG1 (RX_START_OFFSET + 0x0488) |
| 301 | #define BOLERO_CDC_RX_RX1_RX_PATH_CFG2 (RX_START_OFFSET + 0x048C) |
| 302 | #define BOLERO_CDC_RX_RX1_RX_PATH_CFG3 (RX_START_OFFSET + 0x0490) |
| 303 | #define BOLERO_CDC_RX_RX1_RX_VOL_CTL (RX_START_OFFSET + 0x0494) |
| 304 | #define BOLERO_CDC_RX_RX1_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0498) |
| 305 | #define BOLERO_CDC_RX_RX1_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x049C) |
| 306 | #define BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x04A0) |
| 307 | #define BOLERO_CDC_RX_RX1_RX_PATH_SEC1 (RX_START_OFFSET + 0x04A4) |
| 308 | #define BOLERO_CDC_RX_RX1_RX_PATH_SEC2 (RX_START_OFFSET + 0x04A8) |
| 309 | #define BOLERO_CDC_RX_RX1_RX_PATH_SEC3 (RX_START_OFFSET + 0x04AC) |
| 310 | #define BOLERO_CDC_RX_RX1_RX_PATH_SEC4 (RX_START_OFFSET + 0x04B0) |
| 311 | #define BOLERO_CDC_RX_RX1_RX_PATH_SEC7 (RX_START_OFFSET + 0x04B4) |
| 312 | #define BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x04B8) |
| 313 | #define BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x04BC) |
| 314 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x04C0) |
| 315 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA1 (RX_START_OFFSET + 0x04C4) |
| 316 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA2 (RX_START_OFFSET + 0x04C8) |
| 317 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA3 (RX_START_OFFSET + 0x04CC) |
| 318 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA4 (RX_START_OFFSET + 0x04D0) |
| 319 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA5 (RX_START_OFFSET + 0x04D4) |
| 320 | #define BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA6 (RX_START_OFFSET + 0x04D8) |
| 321 | #define BOLERO_CDC_RX_RX2_RX_PATH_CTL (RX_START_OFFSET + 0x0500) |
| 322 | #define BOLERO_CDC_RX_RX2_RX_PATH_CFG0 (RX_START_OFFSET + 0x0504) |
| 323 | #define BOLERO_CDC_RX_RX2_RX_PATH_CFG1 (RX_START_OFFSET + 0x0508) |
| 324 | #define BOLERO_CDC_RX_RX2_RX_PATH_CFG2 (RX_START_OFFSET + 0x050C) |
| 325 | #define BOLERO_CDC_RX_RX2_RX_PATH_CFG3 (RX_START_OFFSET + 0x0510) |
| 326 | #define BOLERO_CDC_RX_RX2_RX_VOL_CTL (RX_START_OFFSET + 0x0514) |
| 327 | #define BOLERO_CDC_RX_RX2_RX_PATH_MIX_CTL (RX_START_OFFSET + 0x0518) |
| 328 | #define BOLERO_CDC_RX_RX2_RX_PATH_MIX_CFG (RX_START_OFFSET + 0x051C) |
| 329 | #define BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL (RX_START_OFFSET + 0x0520) |
| 330 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC0 (RX_START_OFFSET + 0x0524) |
| 331 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC1 (RX_START_OFFSET + 0x0528) |
| 332 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC2 (RX_START_OFFSET + 0x052C) |
| 333 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC3 (RX_START_OFFSET + 0x0530) |
| 334 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC4 (RX_START_OFFSET + 0x0534) |
| 335 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC5 (RX_START_OFFSET + 0x0538) |
| 336 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC6 (RX_START_OFFSET + 0x053C) |
| 337 | #define BOLERO_CDC_RX_RX2_RX_PATH_SEC7 (RX_START_OFFSET + 0x0540) |
| 338 | #define BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC0 (RX_START_OFFSET + 0x0544) |
| 339 | #define BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC1 (RX_START_OFFSET + 0x0548) |
| 340 | #define BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL (RX_START_OFFSET + 0x054C) |
| 341 | #define BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL (RX_START_OFFSET + 0x0780) |
| 342 | #define BOLERO_CDC_RX_IDLE_DETECT_CFG0 (RX_START_OFFSET + 0x0784) |
| 343 | #define BOLERO_CDC_RX_IDLE_DETECT_CFG1 (RX_START_OFFSET + 0x0788) |
| 344 | #define BOLERO_CDC_RX_IDLE_DETECT_CFG2 (RX_START_OFFSET + 0x078C) |
| 345 | #define BOLERO_CDC_RX_IDLE_DETECT_CFG3 (RX_START_OFFSET + 0x0790) |
| 346 | #define BOLERO_CDC_RX_COMPANDER0_CTL0 (RX_START_OFFSET + 0x0800) |
| 347 | #define BOLERO_CDC_RX_COMPANDER0_CTL1 (RX_START_OFFSET + 0x0804) |
| 348 | #define BOLERO_CDC_RX_COMPANDER0_CTL2 (RX_START_OFFSET + 0x0808) |
| 349 | #define BOLERO_CDC_RX_COMPANDER0_CTL3 (RX_START_OFFSET + 0x080C) |
| 350 | #define BOLERO_CDC_RX_COMPANDER0_CTL4 (RX_START_OFFSET + 0x0810) |
| 351 | #define BOLERO_CDC_RX_COMPANDER0_CTL5 (RX_START_OFFSET + 0x0814) |
| 352 | #define BOLERO_CDC_RX_COMPANDER0_CTL6 (RX_START_OFFSET + 0x0818) |
| 353 | #define BOLERO_CDC_RX_COMPANDER0_CTL7 (RX_START_OFFSET + 0x081C) |
| 354 | #define BOLERO_CDC_RX_COMPANDER1_CTL0 (RX_START_OFFSET + 0x0840) |
| 355 | #define BOLERO_CDC_RX_COMPANDER1_CTL1 (RX_START_OFFSET + 0x0844) |
| 356 | #define BOLERO_CDC_RX_COMPANDER1_CTL2 (RX_START_OFFSET + 0x0848) |
| 357 | #define BOLERO_CDC_RX_COMPANDER1_CTL3 (RX_START_OFFSET + 0x084C) |
| 358 | #define BOLERO_CDC_RX_COMPANDER1_CTL4 (RX_START_OFFSET + 0x0850) |
| 359 | #define BOLERO_CDC_RX_COMPANDER1_CTL5 (RX_START_OFFSET + 0x0854) |
| 360 | #define BOLERO_CDC_RX_COMPANDER1_CTL6 (RX_START_OFFSET + 0x0858) |
| 361 | #define BOLERO_CDC_RX_COMPANDER1_CTL7 (RX_START_OFFSET + 0x085C) |
| 362 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL \ |
| 363 | (RX_START_OFFSET + 0x0A00) |
| 364 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL \ |
| 365 | (RX_START_OFFSET + 0x0A04) |
| 366 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL \ |
| 367 | (RX_START_OFFSET + 0x0A08) |
| 368 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL \ |
| 369 | (RX_START_OFFSET + 0x0A0C) |
| 370 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL \ |
| 371 | (RX_START_OFFSET + 0x0A10) |
| 372 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL \ |
| 373 | (RX_START_OFFSET + 0x0A14) |
| 374 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL \ |
| 375 | (RX_START_OFFSET + 0x0A18) |
| 376 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL \ |
| 377 | (RX_START_OFFSET + 0x0A1C) |
| 378 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL \ |
| 379 | (RX_START_OFFSET + 0x0A20) |
| 380 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL (RX_START_OFFSET + 0x0A24) |
| 381 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL \ |
| 382 | (RX_START_OFFSET + 0x0A28) |
| 383 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL \ |
| 384 | (RX_START_OFFSET + 0x0A2C) |
| 385 | #define BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL \ |
| 386 | (RX_START_OFFSET + 0x0A30) |
| 387 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL \ |
| 388 | (RX_START_OFFSET + 0x0A80) |
| 389 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL \ |
| 390 | (RX_START_OFFSET + 0x0A84) |
| 391 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL \ |
| 392 | (RX_START_OFFSET + 0x0A88) |
| 393 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL \ |
| 394 | (RX_START_OFFSET + 0x0A8C) |
| 395 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL \ |
| 396 | (RX_START_OFFSET + 0x0A90) |
| 397 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL \ |
| 398 | (RX_START_OFFSET + 0x0A94) |
| 399 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL \ |
| 400 | (RX_START_OFFSET + 0x0A98) |
| 401 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL \ |
| 402 | (RX_START_OFFSET + 0x0A9C) |
| 403 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL \ |
| 404 | (RX_START_OFFSET + 0x0AA0) |
| 405 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_CTL (RX_START_OFFSET + 0x0AA4) |
| 406 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL \ |
| 407 | (RX_START_OFFSET + 0x0AA8) |
| 408 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL \ |
| 409 | (RX_START_OFFSET + 0x0AAC) |
| 410 | #define BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL \ |
| 411 | (RX_START_OFFSET + 0x0AB0) |
| 412 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (RX_START_OFFSET + 0x0B00) |
| 413 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (RX_START_OFFSET + 0x0B04) |
| 414 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (RX_START_OFFSET + 0x0B08) |
| 415 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (RX_START_OFFSET + 0x0B0C) |
| 416 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (RX_START_OFFSET + 0x0B10) |
| 417 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (RX_START_OFFSET + 0x0B14) |
| 418 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (RX_START_OFFSET + 0x0B18) |
| 419 | #define BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (RX_START_OFFSET + 0x0B1C) |
| 420 | #define BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL \ |
| 421 | (RX_START_OFFSET + 0x0B40) |
| 422 | #define BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 \ |
| 423 | (RX_START_OFFSET + 0x0B44) |
| 424 | #define BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL \ |
| 425 | (RX_START_OFFSET + 0x0B50) |
| 426 | #define BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 \ |
| 427 | (RX_START_OFFSET + 0x0B54) |
| 428 | #define BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL \ |
| 429 | (RX_START_OFFSET + 0x0C00) |
| 430 | #define BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C04) |
| 431 | #define BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL \ |
| 432 | (RX_START_OFFSET + 0x0C40) |
| 433 | #define BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C44) |
| 434 | #define BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL \ |
| 435 | (RX_START_OFFSET + 0x0C80) |
| 436 | #define BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (RX_START_OFFSET + 0x0C84) |
| 437 | #define BOLERO_CDC_RX_EC_ASRC0_CLK_RST_CTL (RX_START_OFFSET + 0x0D00) |
| 438 | #define BOLERO_CDC_RX_EC_ASRC0_CTL0 (RX_START_OFFSET + 0x0D04) |
| 439 | #define BOLERO_CDC_RX_EC_ASRC0_CTL1 (RX_START_OFFSET + 0x0D08) |
| 440 | #define BOLERO_CDC_RX_EC_ASRC0_FIFO_CTL (RX_START_OFFSET + 0x0D0C) |
| 441 | #define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB \ |
| 442 | (RX_START_OFFSET + 0x0D10) |
| 443 | #define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB \ |
| 444 | (RX_START_OFFSET + 0x0D14) |
| 445 | #define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB \ |
| 446 | (RX_START_OFFSET + 0x0D18) |
| 447 | #define BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB \ |
| 448 | (RX_START_OFFSET + 0x0D1C) |
| 449 | #define BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO (RX_START_OFFSET + 0x0D20) |
| 450 | #define BOLERO_CDC_RX_EC_ASRC1_CLK_RST_CTL (RX_START_OFFSET + 0x0D40) |
| 451 | #define BOLERO_CDC_RX_EC_ASRC1_CTL0 (RX_START_OFFSET + 0x0D44) |
| 452 | #define BOLERO_CDC_RX_EC_ASRC1_CTL1 (RX_START_OFFSET + 0x0D48) |
| 453 | #define BOLERO_CDC_RX_EC_ASRC1_FIFO_CTL (RX_START_OFFSET + 0x0D4C) |
| 454 | #define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB \ |
| 455 | (RX_START_OFFSET + 0x0D50) |
| 456 | #define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB \ |
| 457 | (RX_START_OFFSET + 0x0D54) |
| 458 | #define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB \ |
| 459 | (RX_START_OFFSET + 0x0D58) |
| 460 | #define BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB \ |
| 461 | (RX_START_OFFSET + 0x0D5C) |
| 462 | #define BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO (RX_START_OFFSET + 0x0D60) |
| 463 | #define BOLERO_CDC_RX_EC_ASRC2_CLK_RST_CTL (RX_START_OFFSET + 0x0D80) |
| 464 | #define BOLERO_CDC_RX_EC_ASRC2_CTL0 (RX_START_OFFSET + 0x0D84) |
| 465 | #define BOLERO_CDC_RX_EC_ASRC2_CTL1 (RX_START_OFFSET + 0x0D88) |
| 466 | #define BOLERO_CDC_RX_EC_ASRC2_FIFO_CTL (RX_START_OFFSET + 0x0D8C) |
| 467 | #define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB \ |
| 468 | (RX_START_OFFSET + 0x0D90) |
| 469 | #define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB \ |
| 470 | (RX_START_OFFSET + 0x0D94) |
| 471 | #define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB \ |
| 472 | (RX_START_OFFSET + 0x0D98) |
| 473 | #define BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB \ |
| 474 | (RX_START_OFFSET + 0x0D9C) |
| 475 | #define BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO (RX_START_OFFSET + 0x0DA0) |
| 476 | #define BOLERO_CDC_RX_DSD0_PATH_CTL (RX_START_OFFSET + 0x0F00) |
| 477 | #define BOLERO_CDC_RX_DSD0_CFG0 (RX_START_OFFSET + 0x0F04) |
| 478 | #define BOLERO_CDC_RX_DSD0_CFG1 (RX_START_OFFSET + 0x0F08) |
| 479 | #define BOLERO_CDC_RX_DSD0_CFG2 (RX_START_OFFSET + 0x0F0C) |
| 480 | #define BOLERO_CDC_RX_DSD1_PATH_CTL (RX_START_OFFSET + 0x0F80) |
| 481 | #define BOLERO_CDC_RX_DSD1_CFG0 (RX_START_OFFSET + 0x0F84) |
| 482 | #define BOLERO_CDC_RX_DSD1_CFG1 (RX_START_OFFSET + 0x0F88) |
| 483 | #define BOLERO_CDC_RX_DSD1_CFG2 (RX_START_OFFSET + 0x0F8C) |
| 484 | #define RX_MAX_OFFSET (RX_START_OFFSET + 0x0F8C) |
| 485 | |
| 486 | #define BOLERO_CDC_RX_MACRO_MAX 0x3E4 /* F8C/4 = 3E3 + 1 */ |
| 487 | |
| 488 | /* WSA - macro#2 */ |
| 489 | #define WSA_START_OFFSET 0x2000 |
| 490 | #define BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL \ |
| 491 | (WSA_START_OFFSET + 0x0000) |
| 492 | #define BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL \ |
| 493 | (WSA_START_OFFSET + 0x0004) |
| 494 | #define BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (WSA_START_OFFSET + 0x0008) |
| 495 | #define BOLERO_CDC_WSA_TOP_TOP_CFG0 (WSA_START_OFFSET + 0x0080) |
| 496 | #define BOLERO_CDC_WSA_TOP_TOP_CFG1 (WSA_START_OFFSET + 0x0084) |
| 497 | #define BOLERO_CDC_WSA_TOP_FREQ_MCLK (WSA_START_OFFSET + 0x0088) |
| 498 | #define BOLERO_CDC_WSA_TOP_DEBUG_BUS_SEL (WSA_START_OFFSET + 0x008C) |
| 499 | #define BOLERO_CDC_WSA_TOP_DEBUG_EN0 (WSA_START_OFFSET + 0x0090) |
| 500 | #define BOLERO_CDC_WSA_TOP_DEBUG_EN1 (WSA_START_OFFSET + 0x0094) |
| 501 | #define BOLERO_CDC_WSA_TOP_DEBUG_DSM_LB (WSA_START_OFFSET + 0x0098) |
| 502 | #define BOLERO_CDC_WSA_TOP_RX_I2S_CTL (WSA_START_OFFSET + 0x009C) |
| 503 | #define BOLERO_CDC_WSA_TOP_TX_I2S_CTL (WSA_START_OFFSET + 0x00A0) |
| 504 | #define BOLERO_CDC_WSA_TOP_I2S_CLK (WSA_START_OFFSET + 0x00A4) |
| 505 | #define BOLERO_CDC_WSA_TOP_I2S_RESET (WSA_START_OFFSET + 0x00A8) |
| 506 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (WSA_START_OFFSET + 0x0100) |
| 507 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (WSA_START_OFFSET + 0x0104) |
| 508 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (WSA_START_OFFSET + 0x0108) |
| 509 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (WSA_START_OFFSET + 0x010C) |
| 510 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (WSA_START_OFFSET + 0x0110) |
| 511 | #define BOLERO_CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (WSA_START_OFFSET + 0x0114) |
| 512 | #define BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (WSA_START_OFFSET + 0x0118) |
| 513 | /* VBAT registers */ |
| 514 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL (WSA_START_OFFSET + 0x0180) |
| 515 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG (WSA_START_OFFSET + 0x0184) |
| 516 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1 (WSA_START_OFFSET + 0x0188) |
| 517 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2 (WSA_START_OFFSET + 0x018C) |
| 518 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3 (WSA_START_OFFSET + 0x0190) |
| 519 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST1 (WSA_START_OFFSET + 0x0194) |
| 520 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST2 (WSA_START_OFFSET + 0x0198) |
| 521 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST3 (WSA_START_OFFSET + 0x019C) |
| 522 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1 (WSA_START_OFFSET + 0x01A0) |
| 523 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2 (WSA_START_OFFSET + 0x01A4) |
| 524 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC1 (WSA_START_OFFSET + 0x01A8) |
| 525 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC2 (WSA_START_OFFSET + 0x01AC) |
| 526 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC3 (WSA_START_OFFSET + 0x01B0) |
| 527 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC4 (WSA_START_OFFSET + 0x01B4) |
| 528 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1 (WSA_START_OFFSET + 0x01B8) |
| 529 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2 (WSA_START_OFFSET + 0x01BC) |
| 530 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3 (WSA_START_OFFSET + 0x01C0) |
| 531 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4 (WSA_START_OFFSET + 0x01C4) |
| 532 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5 (WSA_START_OFFSET + 0x01C8) |
| 533 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DEBUG1 (WSA_START_OFFSET + 0x01CC) |
| 534 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON \ |
| 535 | (WSA_START_OFFSET + 0x01D0) |
| 536 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL \ |
| 537 | (WSA_START_OFFSET + 0x01D4) |
| 538 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BAN (WSA_START_OFFSET + 0x01D8) |
| 539 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1 \ |
| 540 | (WSA_START_OFFSET + 0x01DC) |
| 541 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2 \ |
| 542 | (WSA_START_OFFSET + 0x01E0) |
| 543 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3 \ |
| 544 | (WSA_START_OFFSET + 0x01E4) |
| 545 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4 \ |
| 546 | (WSA_START_OFFSET + 0x01E8) |
| 547 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5 \ |
| 548 | (WSA_START_OFFSET + 0x01EC) |
| 549 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6 \ |
| 550 | (WSA_START_OFFSET + 0x01F0) |
| 551 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7 \ |
| 552 | (WSA_START_OFFSET + 0x01F4) |
| 553 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8 \ |
| 554 | (WSA_START_OFFSET + 0x01F8) |
| 555 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9 \ |
| 556 | (WSA_START_OFFSET + 0x01FC) |
| 557 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1 (WSA_START_OFFSET + 0x0200) |
| 558 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2 (WSA_START_OFFSET + 0x0204) |
| 559 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3 (WSA_START_OFFSET + 0x0208) |
| 560 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1 \ |
| 561 | (WSA_START_OFFSET + 0x020C) |
| 562 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2 \ |
| 563 | (WSA_START_OFFSET + 0x0210) |
| 564 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1 \ |
| 565 | (WSA_START_OFFSET + 0x0214) |
| 566 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2 \ |
| 567 | (WSA_START_OFFSET + 0x0218) |
| 568 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3 \ |
| 569 | (WSA_START_OFFSET + 0x021C) |
| 570 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4 \ |
| 571 | (WSA_START_OFFSET + 0x0220) |
| 572 | #define BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST (WSA_START_OFFSET + 0x0224) |
| 573 | #define BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0244) |
| 574 | #define BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0248) |
| 575 | #define BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0264) |
| 576 | #define BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0268) |
| 577 | #define BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x0284) |
| 578 | #define BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x0288) |
| 579 | #define BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL (WSA_START_OFFSET + 0x02A4) |
| 580 | #define BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (WSA_START_OFFSET + 0x02A8) |
| 581 | #define BOLERO_CDC_WSA_INTR_CTRL_CFG (WSA_START_OFFSET + 0x0340) |
| 582 | #define BOLERO_CDC_WSA_INTR_CTRL_CLR_COMMIT (WSA_START_OFFSET + 0x0344) |
| 583 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN1_MASK0 (WSA_START_OFFSET + 0x0360) |
| 584 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0 (WSA_START_OFFSET + 0x0368) |
| 585 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (WSA_START_OFFSET + 0x0370) |
| 586 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN2_MASK0 (WSA_START_OFFSET + 0x0380) |
| 587 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0 (WSA_START_OFFSET + 0x0388) |
| 588 | #define BOLERO_CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (WSA_START_OFFSET + 0x0390) |
| 589 | #define BOLERO_CDC_WSA_INTR_CTRL_LEVEL0 (WSA_START_OFFSET + 0x03C0) |
| 590 | #define BOLERO_CDC_WSA_INTR_CTRL_BYPASS0 (WSA_START_OFFSET + 0x03C8) |
| 591 | #define BOLERO_CDC_WSA_INTR_CTRL_SET0 (WSA_START_OFFSET + 0x03D0) |
| 592 | #define BOLERO_CDC_WSA_RX0_RX_PATH_CTL (WSA_START_OFFSET + 0x0400) |
| 593 | #define BOLERO_CDC_WSA_RX0_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0404) |
| 594 | #define BOLERO_CDC_WSA_RX0_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0408) |
| 595 | #define BOLERO_CDC_WSA_RX0_RX_PATH_CFG2 (WSA_START_OFFSET + 0x040C) |
| 596 | #define BOLERO_CDC_WSA_RX0_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0410) |
| 597 | #define BOLERO_CDC_WSA_RX0_RX_VOL_CTL (WSA_START_OFFSET + 0x0414) |
| 598 | #define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0418) |
| 599 | #define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x041C) |
| 600 | #define BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x0420) |
| 601 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC0 (WSA_START_OFFSET + 0x0424) |
| 602 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC1 (WSA_START_OFFSET + 0x0428) |
| 603 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC2 (WSA_START_OFFSET + 0x042C) |
| 604 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC3 (WSA_START_OFFSET + 0x0430) |
| 605 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC5 (WSA_START_OFFSET + 0x0438) |
| 606 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC6 (WSA_START_OFFSET + 0x043C) |
| 607 | #define BOLERO_CDC_WSA_RX0_RX_PATH_SEC7 (WSA_START_OFFSET + 0x0440) |
| 608 | #define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x0444) |
| 609 | #define BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x0448) |
| 610 | #define BOLERO_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x044C) |
| 611 | #define BOLERO_CDC_WSA_RX1_RX_PATH_CTL (WSA_START_OFFSET + 0x0480) |
| 612 | #define BOLERO_CDC_WSA_RX1_RX_PATH_CFG0 (WSA_START_OFFSET + 0x0484) |
| 613 | #define BOLERO_CDC_WSA_RX1_RX_PATH_CFG1 (WSA_START_OFFSET + 0x0488) |
| 614 | #define BOLERO_CDC_WSA_RX1_RX_PATH_CFG2 (WSA_START_OFFSET + 0x048C) |
| 615 | #define BOLERO_CDC_WSA_RX1_RX_PATH_CFG3 (WSA_START_OFFSET + 0x0490) |
| 616 | #define BOLERO_CDC_WSA_RX1_RX_VOL_CTL (WSA_START_OFFSET + 0x0494) |
| 617 | #define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL (WSA_START_OFFSET + 0x0498) |
| 618 | #define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG (WSA_START_OFFSET + 0x049C) |
| 619 | #define BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL (WSA_START_OFFSET + 0x04A0) |
| 620 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC0 (WSA_START_OFFSET + 0x04A4) |
| 621 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC1 (WSA_START_OFFSET + 0x04A8) |
| 622 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC2 (WSA_START_OFFSET + 0x04AC) |
| 623 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC3 (WSA_START_OFFSET + 0x04B0) |
| 624 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC5 (WSA_START_OFFSET + 0x04B8) |
| 625 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC6 (WSA_START_OFFSET + 0x04BC) |
| 626 | #define BOLERO_CDC_WSA_RX1_RX_PATH_SEC7 (WSA_START_OFFSET + 0x04C0) |
| 627 | #define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0 (WSA_START_OFFSET + 0x04C4) |
| 628 | #define BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC1 (WSA_START_OFFSET + 0x04C8) |
| 629 | #define BOLERO_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (WSA_START_OFFSET + 0x04CC) |
| 630 | #define BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0500) |
| 631 | #define BOLERO_CDC_WSA_BOOST0_BOOST_CTL (WSA_START_OFFSET + 0x0504) |
| 632 | #define BOLERO_CDC_WSA_BOOST0_BOOST_CFG1 (WSA_START_OFFSET + 0x0508) |
| 633 | #define BOLERO_CDC_WSA_BOOST0_BOOST_CFG2 (WSA_START_OFFSET + 0x050C) |
| 634 | #define BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL (WSA_START_OFFSET + 0x0540) |
| 635 | #define BOLERO_CDC_WSA_BOOST1_BOOST_CTL (WSA_START_OFFSET + 0x0544) |
| 636 | #define BOLERO_CDC_WSA_BOOST1_BOOST_CFG1 (WSA_START_OFFSET + 0x0548) |
| 637 | #define BOLERO_CDC_WSA_BOOST1_BOOST_CFG2 (WSA_START_OFFSET + 0x054C) |
| 638 | #define BOLERO_CDC_WSA_COMPANDER0_CTL0 (WSA_START_OFFSET + 0x0580) |
| 639 | #define BOLERO_CDC_WSA_COMPANDER0_CTL1 (WSA_START_OFFSET + 0x0584) |
| 640 | #define BOLERO_CDC_WSA_COMPANDER0_CTL2 (WSA_START_OFFSET + 0x0588) |
| 641 | #define BOLERO_CDC_WSA_COMPANDER0_CTL3 (WSA_START_OFFSET + 0x058C) |
| 642 | #define BOLERO_CDC_WSA_COMPANDER0_CTL4 (WSA_START_OFFSET + 0x0590) |
| 643 | #define BOLERO_CDC_WSA_COMPANDER0_CTL5 (WSA_START_OFFSET + 0x0594) |
| 644 | #define BOLERO_CDC_WSA_COMPANDER0_CTL6 (WSA_START_OFFSET + 0x0598) |
| 645 | #define BOLERO_CDC_WSA_COMPANDER0_CTL7 (WSA_START_OFFSET + 0x059C) |
| 646 | #define BOLERO_CDC_WSA_COMPANDER1_CTL0 (WSA_START_OFFSET + 0x05C0) |
| 647 | #define BOLERO_CDC_WSA_COMPANDER1_CTL1 (WSA_START_OFFSET + 0x05C4) |
| 648 | #define BOLERO_CDC_WSA_COMPANDER1_CTL2 (WSA_START_OFFSET + 0x05C8) |
| 649 | #define BOLERO_CDC_WSA_COMPANDER1_CTL3 (WSA_START_OFFSET + 0x05CC) |
| 650 | #define BOLERO_CDC_WSA_COMPANDER1_CTL4 (WSA_START_OFFSET + 0x05D0) |
| 651 | #define BOLERO_CDC_WSA_COMPANDER1_CTL5 (WSA_START_OFFSET + 0x05D4) |
| 652 | #define BOLERO_CDC_WSA_COMPANDER1_CTL6 (WSA_START_OFFSET + 0x05D8) |
| 653 | #define BOLERO_CDC_WSA_COMPANDER1_CTL7 (WSA_START_OFFSET + 0x05DC) |
| 654 | #define BOLERO_CDC_WSA_SOFTCLIP0_CRC (WSA_START_OFFSET + 0x0600) |
| 655 | #define BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0604) |
| 656 | #define BOLERO_CDC_WSA_SOFTCLIP1_CRC (WSA_START_OFFSET + 0x0640) |
| 657 | #define BOLERO_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (WSA_START_OFFSET + 0x0644) |
| 658 | #define BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL \ |
| 659 | (WSA_START_OFFSET + 0x0680) |
| 660 | #define BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x0684) |
| 661 | #define BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL \ |
| 662 | (WSA_START_OFFSET + 0x06C0) |
| 663 | #define BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (WSA_START_OFFSET + 0x06C4) |
| 664 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (WSA_START_OFFSET + 0x0700) |
| 665 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_CTL0 (WSA_START_OFFSET + 0x0704) |
| 666 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_CTL1 (WSA_START_OFFSET + 0x0708) |
| 667 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_FIFO_CTL (WSA_START_OFFSET + 0x070C) |
| 668 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB \ |
| 669 | (WSA_START_OFFSET + 0x0710) |
| 670 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB \ |
| 671 | (WSA_START_OFFSET + 0x0714) |
| 672 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB \ |
| 673 | (WSA_START_OFFSET + 0x0718) |
| 674 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB \ |
| 675 | (WSA_START_OFFSET + 0x071C) |
| 676 | #define BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (WSA_START_OFFSET + 0x0720) |
| 677 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (WSA_START_OFFSET + 0x0740) |
| 678 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_CTL0 (WSA_START_OFFSET + 0x0744) |
| 679 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_CTL1 (WSA_START_OFFSET + 0x0748) |
| 680 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_FIFO_CTL (WSA_START_OFFSET + 0x074C) |
| 681 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB \ |
| 682 | (WSA_START_OFFSET + 0x0750) |
| 683 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB \ |
| 684 | (WSA_START_OFFSET + 0x0754) |
| 685 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB \ |
| 686 | (WSA_START_OFFSET + 0x0758) |
| 687 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB \ |
| 688 | (WSA_START_OFFSET + 0x075C) |
| 689 | #define BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (WSA_START_OFFSET + 0x0760) |
| 690 | #define WSA_MAX_OFFSET (WSA_START_OFFSET + 0x0760) |
| 691 | |
| 692 | #define BOLERO_CDC_WSA_MACRO_MAX 0x1D9 /* 0x760/4 = 0x1D8 + 1 registers */ |
| 693 | |
| 694 | /* VA macro registers */ |
| 695 | #define VA_START_OFFSET 0x3000 |
| 696 | #define BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (VA_START_OFFSET + 0x0000) |
| 697 | #define BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL \ |
| 698 | (VA_START_OFFSET + 0x0004) |
| Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 699 | #define BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL (VA_START_OFFSET + 0x0008) |
| Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 700 | #define BOLERO_CDC_VA_TOP_CSR_TOP_CFG0 (VA_START_OFFSET + 0x0080) |
| 701 | #define BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL (VA_START_OFFSET + 0x0084) |
| 702 | #define BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL (VA_START_OFFSET + 0x0088) |
| 703 | #define BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL (VA_START_OFFSET + 0x008C) |
| 704 | #define BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL (VA_START_OFFSET + 0x0090) |
| 705 | #define BOLERO_CDC_VA_TOP_CSR_DMIC_CFG (VA_START_OFFSET + 0x0094) |
| 706 | #define BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS (VA_START_OFFSET + 0x009C) |
| 707 | #define BOLERO_CDC_VA_TOP_CSR_DEBUG_EN (VA_START_OFFSET + 0x00A0) |
| 708 | #define BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL (VA_START_OFFSET + 0x00A4) |
| 709 | #define BOLERO_CDC_VA_TOP_CSR_I2S_CLK (VA_START_OFFSET + 0x00A8) |
| 710 | #define BOLERO_CDC_VA_TOP_CSR_I2S_RESET (VA_START_OFFSET + 0x00AC) |
| 711 | #define BOLERO_CDC_VA_TOP_CSR_CORE_ID_0 (VA_START_OFFSET + 0x00C0) |
| 712 | #define BOLERO_CDC_VA_TOP_CSR_CORE_ID_1 (VA_START_OFFSET + 0x00C4) |
| 713 | #define BOLERO_CDC_VA_TOP_CSR_CORE_ID_2 (VA_START_OFFSET + 0x00C8) |
| 714 | #define BOLERO_CDC_VA_TOP_CSR_CORE_ID_3 (VA_START_OFFSET + 0x00CC) |
| 715 | #define VA_TOP_MAX_OFFSET (VA_START_OFFSET + 0x00CC) |
| 716 | |
| 717 | #define BOLERO_CDC_VA_MACRO_TOP_MAX 0x34 /* 0x0CC/4 = 0x33 + 1 = 0x34 */ |
| 718 | |
| Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame] | 719 | #define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0 (VA_START_OFFSET + 0x00D0) |
| 720 | #define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1 (VA_START_OFFSET + 0x00D4) |
| 721 | #define BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2 (VA_START_OFFSET + 0x00D8) |
| 722 | #define BOLERO_CDC_VA_TOP_CSR_SWR_CTRL (VA_START_OFFSET + 0x00DC) |
| 723 | |
| Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 724 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0 (VA_START_OFFSET + 0x0100) |
| 725 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1 (VA_START_OFFSET + 0x0104) |
| 726 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0 (VA_START_OFFSET + 0x0108) |
| 727 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1 (VA_START_OFFSET + 0x010C) |
| 728 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0 (VA_START_OFFSET + 0x0110) |
| 729 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1 (VA_START_OFFSET + 0x0114) |
| 730 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0 (VA_START_OFFSET + 0x0118) |
| 731 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1 (VA_START_OFFSET + 0x011C) |
| 732 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG0 (VA_START_OFFSET + 0x0120) |
| 733 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG1 (VA_START_OFFSET + 0x0124) |
| 734 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG0 (VA_START_OFFSET + 0x0128) |
| 735 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG1 (VA_START_OFFSET + 0x012C) |
| 736 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG0 (VA_START_OFFSET + 0x0130) |
| 737 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG1 (VA_START_OFFSET + 0x0134) |
| 738 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG0 (VA_START_OFFSET + 0x0138) |
| 739 | #define BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG1 (VA_START_OFFSET + 0x013C) |
| 740 | |
| 741 | #define BOLERO_CDC_VA_TX0_TX_PATH_CTL (VA_START_OFFSET + 0x0400) |
| 742 | #define BOLERO_CDC_VA_TX0_TX_PATH_CFG0 (VA_START_OFFSET + 0x0404) |
| 743 | #define BOLERO_CDC_VA_TX0_TX_PATH_CFG1 (VA_START_OFFSET + 0x0408) |
| 744 | #define BOLERO_CDC_VA_TX0_TX_VOL_CTL (VA_START_OFFSET + 0x040C) |
| 745 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC0 (VA_START_OFFSET + 0x0410) |
| 746 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC1 (VA_START_OFFSET + 0x0414) |
| 747 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC2 (VA_START_OFFSET + 0x0418) |
| 748 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC3 (VA_START_OFFSET + 0x041C) |
| 749 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC4 (VA_START_OFFSET + 0x0420) |
| 750 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC5 (VA_START_OFFSET + 0x0424) |
| 751 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC6 (VA_START_OFFSET + 0x0428) |
| 752 | #define BOLERO_CDC_VA_TX0_TX_PATH_SEC7 (VA_START_OFFSET + 0x042C) |
| 753 | #define BOLERO_CDC_VA_TX1_TX_PATH_CTL (VA_START_OFFSET + 0x0480) |
| 754 | #define BOLERO_CDC_VA_TX1_TX_PATH_CFG0 (VA_START_OFFSET + 0x0484) |
| 755 | #define BOLERO_CDC_VA_TX1_TX_PATH_CFG1 (VA_START_OFFSET + 0x0488) |
| 756 | #define BOLERO_CDC_VA_TX1_TX_VOL_CTL (VA_START_OFFSET + 0x048C) |
| 757 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC0 (VA_START_OFFSET + 0x0490) |
| 758 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC1 (VA_START_OFFSET + 0x0494) |
| 759 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC2 (VA_START_OFFSET + 0x0498) |
| 760 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC3 (VA_START_OFFSET + 0x049C) |
| 761 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC4 (VA_START_OFFSET + 0x04A0) |
| 762 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC5 (VA_START_OFFSET + 0x04A4) |
| 763 | #define BOLERO_CDC_VA_TX1_TX_PATH_SEC6 (VA_START_OFFSET + 0x04A8) |
| 764 | #define BOLERO_CDC_VA_TX2_TX_PATH_CTL (VA_START_OFFSET + 0x0500) |
| 765 | #define BOLERO_CDC_VA_TX2_TX_PATH_CFG0 (VA_START_OFFSET + 0x0504) |
| 766 | #define BOLERO_CDC_VA_TX2_TX_PATH_CFG1 (VA_START_OFFSET + 0x0508) |
| 767 | #define BOLERO_CDC_VA_TX2_TX_VOL_CTL (VA_START_OFFSET + 0x050C) |
| 768 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC0 (VA_START_OFFSET + 0x0510) |
| 769 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC1 (VA_START_OFFSET + 0x0514) |
| 770 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC2 (VA_START_OFFSET + 0x0518) |
| 771 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC3 (VA_START_OFFSET + 0x051C) |
| 772 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC4 (VA_START_OFFSET + 0x0520) |
| 773 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC5 (VA_START_OFFSET + 0x0524) |
| 774 | #define BOLERO_CDC_VA_TX2_TX_PATH_SEC6 (VA_START_OFFSET + 0x0528) |
| 775 | #define BOLERO_CDC_VA_TX3_TX_PATH_CTL (VA_START_OFFSET + 0x0580) |
| 776 | #define BOLERO_CDC_VA_TX3_TX_PATH_CFG0 (VA_START_OFFSET + 0x0584) |
| 777 | #define BOLERO_CDC_VA_TX3_TX_PATH_CFG1 (VA_START_OFFSET + 0x0588) |
| 778 | #define BOLERO_CDC_VA_TX3_TX_VOL_CTL (VA_START_OFFSET + 0x058C) |
| 779 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC0 (VA_START_OFFSET + 0x0590) |
| 780 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC1 (VA_START_OFFSET + 0x0594) |
| 781 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC2 (VA_START_OFFSET + 0x0598) |
| 782 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC3 (VA_START_OFFSET + 0x059C) |
| 783 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC4 (VA_START_OFFSET + 0x05A0) |
| 784 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC5 (VA_START_OFFSET + 0x05A4) |
| 785 | #define BOLERO_CDC_VA_TX3_TX_PATH_SEC6 (VA_START_OFFSET + 0x05A8) |
| 786 | #define BOLERO_CDC_VA_TX4_TX_PATH_CTL (VA_START_OFFSET + 0x0600) |
| 787 | #define BOLERO_CDC_VA_TX4_TX_PATH_CFG0 (VA_START_OFFSET + 0x0604) |
| 788 | #define BOLERO_CDC_VA_TX4_TX_PATH_CFG1 (VA_START_OFFSET + 0x0608) |
| 789 | #define BOLERO_CDC_VA_TX4_TX_VOL_CTL (VA_START_OFFSET + 0x060C) |
| 790 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC0 (VA_START_OFFSET + 0x0610) |
| 791 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC1 (VA_START_OFFSET + 0x0614) |
| 792 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC2 (VA_START_OFFSET + 0x0618) |
| 793 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC3 (VA_START_OFFSET + 0x061C) |
| 794 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC4 (VA_START_OFFSET + 0x0620) |
| 795 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC5 (VA_START_OFFSET + 0x0624) |
| 796 | #define BOLERO_CDC_VA_TX4_TX_PATH_SEC6 (VA_START_OFFSET + 0x0628) |
| 797 | #define BOLERO_CDC_VA_TX5_TX_PATH_CTL (VA_START_OFFSET + 0x0680) |
| 798 | #define BOLERO_CDC_VA_TX5_TX_PATH_CFG0 (VA_START_OFFSET + 0x0684) |
| 799 | #define BOLERO_CDC_VA_TX5_TX_PATH_CFG1 (VA_START_OFFSET + 0x0688) |
| 800 | #define BOLERO_CDC_VA_TX5_TX_VOL_CTL (VA_START_OFFSET + 0x068C) |
| 801 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC0 (VA_START_OFFSET + 0x0690) |
| 802 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC1 (VA_START_OFFSET + 0x0694) |
| 803 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC2 (VA_START_OFFSET + 0x0698) |
| 804 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC3 (VA_START_OFFSET + 0x069C) |
| 805 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC4 (VA_START_OFFSET + 0x06A0) |
| 806 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC5 (VA_START_OFFSET + 0x06A4) |
| 807 | #define BOLERO_CDC_VA_TX5_TX_PATH_SEC6 (VA_START_OFFSET + 0x06A8) |
| 808 | #define BOLERO_CDC_VA_TX6_TX_PATH_CTL (VA_START_OFFSET + 0x0700) |
| 809 | #define BOLERO_CDC_VA_TX6_TX_PATH_CFG0 (VA_START_OFFSET + 0x0704) |
| 810 | #define BOLERO_CDC_VA_TX6_TX_PATH_CFG1 (VA_START_OFFSET + 0x0708) |
| 811 | #define BOLERO_CDC_VA_TX6_TX_VOL_CTL (VA_START_OFFSET + 0x070C) |
| 812 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC0 (VA_START_OFFSET + 0x0710) |
| 813 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC1 (VA_START_OFFSET + 0x0714) |
| 814 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC2 (VA_START_OFFSET + 0x0718) |
| 815 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC3 (VA_START_OFFSET + 0x071C) |
| 816 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC4 (VA_START_OFFSET + 0x0720) |
| 817 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC5 (VA_START_OFFSET + 0x0724) |
| 818 | #define BOLERO_CDC_VA_TX6_TX_PATH_SEC6 (VA_START_OFFSET + 0x0728) |
| 819 | #define BOLERO_CDC_VA_TX7_TX_PATH_CTL (VA_START_OFFSET + 0x0780) |
| 820 | #define BOLERO_CDC_VA_TX7_TX_PATH_CFG0 (VA_START_OFFSET + 0x0784) |
| 821 | #define BOLERO_CDC_VA_TX7_TX_PATH_CFG1 (VA_START_OFFSET + 0x0788) |
| 822 | #define BOLERO_CDC_VA_TX7_TX_VOL_CTL (VA_START_OFFSET + 0x078C) |
| 823 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC0 (VA_START_OFFSET + 0x0790) |
| 824 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC1 (VA_START_OFFSET + 0x0794) |
| 825 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC2 (VA_START_OFFSET + 0x0798) |
| 826 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC3 (VA_START_OFFSET + 0x079C) |
| 827 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC4 (VA_START_OFFSET + 0x07A0) |
| 828 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC5 (VA_START_OFFSET + 0x07A4) |
| 829 | #define BOLERO_CDC_VA_TX7_TX_PATH_SEC6 (VA_START_OFFSET + 0x07A8) |
| 830 | #define VA_MAX_OFFSET (VA_START_OFFSET + 0x07A8) |
| 831 | |
| 832 | #define BOLERO_CDC_VA_MACRO_MAX 0x1EB /* 7A8/4 = 1EA + 1 = 1EB */ |
| 833 | |
| 834 | #define BOLERO_CDC_MAX_REGISTER VA_MAX_OFFSET |
| 835 | |
| 836 | #define BOLERO_REG(reg) (((reg) & 0x0FFF)/4) |
| 837 | |
| 838 | #endif |