| Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Mangesh Kunchamwar | 82f6168 | 2018-05-17 18:47:47 +0530 | [diff] [blame] | 2 | /* |
| Sanjana B | 22cd4cb | 2020-04-05 18:24:24 +0530 | [diff] [blame] | 3 | * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
| Mangesh Kunchamwar | 82f6168 | 2018-05-17 18:47:47 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CSRA66X0_H |
| 7 | #define _CSRA66X0_H |
| 8 | |
| 9 | /* CSRA66X0 register addresses */ |
| 10 | #define CSRA66X0_BASE 0x7000 |
| 11 | |
| 12 | #define CSRA66X0_AUDIO_IF_RX_CONFIG1 (CSRA66X0_BASE+0x0000) |
| 13 | #define CSRA66X0_AUDIO_IF_RX_CONFIG2 (CSRA66X0_BASE+0x0001) |
| 14 | #define CSRA66X0_AUDIO_IF_RX_CONFIG3 (CSRA66X0_BASE+0x0002) |
| 15 | #define CSRA66X0_AUDIO_IF_TX_EN (CSRA66X0_BASE+0x0003) |
| 16 | #define CSRA66X0_AUDIO_IF_TX_CONFIG1 (CSRA66X0_BASE+0x0004) |
| 17 | #define CSRA66X0_AUDIO_IF_TX_CONFIG2 (CSRA66X0_BASE+0x0005) |
| 18 | #define CSRA66X0_I2C_DEVICE_ADDRESS (CSRA66X0_BASE+0x0006) |
| 19 | #define CSRA66X0_CHIP_ID_FA (CSRA66X0_BASE+0x0007) |
| 20 | #define CSRA66X0_ROM_VER_FA (CSRA66X0_BASE+0x0008) |
| 21 | #define CSRA66X0_CHIP_REV_0_FA (CSRA66X0_BASE+0x0009) |
| 22 | #define CSRA66X0_CHIP_REV_1_FA (CSRA66X0_BASE+0x000A) |
| 23 | #define CSRA66X0_CH1_MIX_SEL (CSRA66X0_BASE+0x000B) |
| 24 | #define CSRA66X0_CH2_MIX_SEL (CSRA66X0_BASE+0x000C) |
| 25 | #define CSRA66X0_CH1_SAMPLE1_SCALE_0 (CSRA66X0_BASE+0x000D) |
| 26 | #define CSRA66X0_CH1_SAMPLE1_SCALE_1 (CSRA66X0_BASE+0x000E) |
| 27 | #define CSRA66X0_CH1_SAMPLE3_SCALE_0 (CSRA66X0_BASE+0x000F) |
| 28 | #define CSRA66X0_CH1_SAMPLE3_SCALE_1 (CSRA66X0_BASE+0x0010) |
| 29 | #define CSRA66X0_CH1_SAMPLE5_SCALE_0 (CSRA66X0_BASE+0x0011) |
| 30 | #define CSRA66X0_CH1_SAMPLE5_SCALE_1 (CSRA66X0_BASE+0x0012) |
| 31 | #define CSRA66X0_CH1_SAMPLE7_SCALE_0 (CSRA66X0_BASE+0x0013) |
| 32 | #define CSRA66X0_CH1_SAMPLE7_SCALE_1 (CSRA66X0_BASE+0x0014) |
| 33 | #define CSRA66X0_CH1_SAMPLE2_SCALE_0 (CSRA66X0_BASE+0x0015) |
| 34 | #define CSRA66X0_CH1_SAMPLE2_SCALE_1 (CSRA66X0_BASE+0x0016) |
| 35 | #define CSRA66X0_CH1_SAMPLE4_SCALE_0 (CSRA66X0_BASE+0x0017) |
| 36 | #define CSRA66X0_CH1_SAMPLE4_SCALE_1 (CSRA66X0_BASE+0x0018) |
| 37 | #define CSRA66X0_CH1_SAMPLE6_SCALE_0 (CSRA66X0_BASE+0x0019) |
| 38 | #define CSRA66X0_CH1_SAMPLE6_SCALE_1 (CSRA66X0_BASE+0x001A) |
| 39 | #define CSRA66X0_CH1_SAMPLE8_SCALE_0 (CSRA66X0_BASE+0x001B) |
| 40 | #define CSRA66X0_CH1_SAMPLE8_SCALE_1 (CSRA66X0_BASE+0x001C) |
| 41 | #define CSRA66X0_CH2_SAMPLE1_SCALE_0 (CSRA66X0_BASE+0x001D) |
| 42 | #define CSRA66X0_CH2_SAMPLE1_SCALE_1 (CSRA66X0_BASE+0x001E) |
| 43 | #define CSRA66X0_CH2_SAMPLE3_SCALE_0 (CSRA66X0_BASE+0x001F) |
| 44 | #define CSRA66X0_CH2_SAMPLE3_SCALE_1 (CSRA66X0_BASE+0x0020) |
| 45 | #define CSRA66X0_CH2_SAMPLE5_SCALE_0 (CSRA66X0_BASE+0x0021) |
| 46 | #define CSRA66X0_CH2_SAMPLE5_SCALE_1 (CSRA66X0_BASE+0x0022) |
| 47 | #define CSRA66X0_CH2_SAMPLE7_SCALE_0 (CSRA66X0_BASE+0x0023) |
| 48 | #define CSRA66X0_CH2_SAMPLE7_SCALE_1 (CSRA66X0_BASE+0x0024) |
| 49 | #define CSRA66X0_CH2_SAMPLE2_SCALE_0 (CSRA66X0_BASE+0x0025) |
| 50 | #define CSRA66X0_CH2_SAMPLE2_SCALE_1 (CSRA66X0_BASE+0x0026) |
| 51 | #define CSRA66X0_CH2_SAMPLE4_SCALE_0 (CSRA66X0_BASE+0x0027) |
| 52 | #define CSRA66X0_CH2_SAMPLE4_SCALE_1 (CSRA66X0_BASE+0x0028) |
| 53 | #define CSRA66X0_CH2_SAMPLE6_SCALE_0 (CSRA66X0_BASE+0x0029) |
| 54 | #define CSRA66X0_CH2_SAMPLE6_SCALE_1 (CSRA66X0_BASE+0x002A) |
| 55 | #define CSRA66X0_CH2_SAMPLE8_SCALE_0 (CSRA66X0_BASE+0x002B) |
| 56 | #define CSRA66X0_CH2_SAMPLE8_SCALE_1 (CSRA66X0_BASE+0x002C) |
| 57 | #define CSRA66X0_VOLUME_CONFIG_FA (CSRA66X0_BASE+0x002D) |
| 58 | #define CSRA66X0_STARTUP_DELAY_FA (CSRA66X0_BASE+0x002E) |
| 59 | #define CSRA66X0_CH1_VOLUME_0_FA (CSRA66X0_BASE+0x002F) |
| 60 | #define CSRA66X0_CH1_VOLUME_1_FA (CSRA66X0_BASE+0x0030) |
| 61 | #define CSRA66X0_CH2_VOLUME_0_FA (CSRA66X0_BASE+0x0031) |
| 62 | #define CSRA66X0_CH2_VOLUME_1_FA (CSRA66X0_BASE+0x0032) |
| 63 | #define CSRA66X0_QUAD_ENC_COUNT_0_FA (CSRA66X0_BASE+0x0033) |
| 64 | #define CSRA66X0_QUAD_ENC_COUNT_1_FA (CSRA66X0_BASE+0x0034) |
| 65 | #define CSRA66X0_SOFT_CLIP_CONFIG (CSRA66X0_BASE+0x0035) |
| 66 | #define CSRA66X0_CH1_HARD_CLIP_THRESH (CSRA66X0_BASE+0x0036) |
| 67 | #define CSRA66X0_CH2_HARD_CLIP_THRESH (CSRA66X0_BASE+0x0037) |
| 68 | #define CSRA66X0_SOFT_CLIP_THRESH (CSRA66X0_BASE+0x0038) |
| 69 | #define CSRA66X0_DS_ENABLE_THRESH_0 (CSRA66X0_BASE+0x0039) |
| 70 | #define CSRA66X0_DS_ENABLE_THRESH_1 (CSRA66X0_BASE+0x003A) |
| 71 | #define CSRA66X0_DS_TARGET_COUNT_0 (CSRA66X0_BASE+0x003B) |
| 72 | #define CSRA66X0_DS_TARGET_COUNT_1 (CSRA66X0_BASE+0x003C) |
| 73 | #define CSRA66X0_DS_TARGET_COUNT_2 (CSRA66X0_BASE+0x003D) |
| 74 | #define CSRA66X0_DS_DISABLE_THRESH_0 (CSRA66X0_BASE+0x003E) |
| 75 | #define CSRA66X0_DS_DISABLE_THRESH_1 (CSRA66X0_BASE+0x003F) |
| 76 | #define CSRA66X0_DCA_CTRL (CSRA66X0_BASE+0x0040) |
| 77 | #define CSRA66X0_CH1_DCA_THRESH (CSRA66X0_BASE+0x0041) |
| 78 | #define CSRA66X0_CH2_DCA_THRESH (CSRA66X0_BASE+0x0042) |
| 79 | #define CSRA66X0_DCA_ATTACK_RATE (CSRA66X0_BASE+0x0043) |
| 80 | #define CSRA66X0_DCA_RELEASE_RATE (CSRA66X0_BASE+0x0044) |
| 81 | #define CSRA66X0_CH1_OUTPUT_INVERT_EN (CSRA66X0_BASE+0x0045) |
| 82 | #define CSRA66X0_CH2_OUTPUT_INVERT_EN (CSRA66X0_BASE+0x0046) |
| 83 | #define CSRA66X0_CH1_176P4K_DELAY (CSRA66X0_BASE+0x0047) |
| 84 | #define CSRA66X0_CH2_176P4K_DELAY (CSRA66X0_BASE+0x0048) |
| 85 | #define CSRA66X0_CH1_192K_DELAY (CSRA66X0_BASE+0x0049) |
| 86 | #define CSRA66X0_CH2_192K_DELAY (CSRA66X0_BASE+0x004A) |
| 87 | #define CSRA66X0_DEEMP_CONFIG_FA (CSRA66X0_BASE+0x004B) |
| 88 | #define CSRA66X0_CH1_TREBLE_GAIN_CTRL_FA (CSRA66X0_BASE+0x004C) |
| 89 | #define CSRA66X0_CH2_TREBLE_GAIN_CTRL_FA (CSRA66X0_BASE+0x004D) |
| 90 | #define CSRA66X0_CH1_TREBLE_FC_CTRL_FA (CSRA66X0_BASE+0x004E) |
| 91 | #define CSRA66X0_CH2_TREBLE_FC_CTRL_FA (CSRA66X0_BASE+0x004F) |
| 92 | #define CSRA66X0_CH1_BASS_GAIN_CTRL_FA (CSRA66X0_BASE+0x0050) |
| 93 | #define CSRA66X0_CH2_BASS_GAIN_CTRL_FA (CSRA66X0_BASE+0x0051) |
| 94 | #define CSRA66X0_CH1_BASS_FC_CTRL_FA (CSRA66X0_BASE+0x0052) |
| 95 | #define CSRA66X0_CH2_BASS_FC_CTRL_FA (CSRA66X0_BASE+0x0053) |
| 96 | #define CSRA66X0_FILTER_SEL_8K (CSRA66X0_BASE+0x0054) |
| 97 | #define CSRA66X0_FILTER_SEL_11P025K (CSRA66X0_BASE+0x0055) |
| 98 | #define CSRA66X0_FILTER_SEL_16K (CSRA66X0_BASE+0x0056) |
| 99 | #define CSRA66X0_FILTER_SEL_22P05K (CSRA66X0_BASE+0x0057) |
| 100 | #define CSRA66X0_FILTER_SEL_32K (CSRA66X0_BASE+0x0058) |
| 101 | #define CSRA66X0_FILTER_SEL_44P1K_48K (CSRA66X0_BASE+0x0059) |
| 102 | #define CSRA66X0_FILTER_SEL_88P2K_96K (CSRA66X0_BASE+0x005A) |
| 103 | #define CSRA66X0_FILTER_SEL_176P4K_192K (CSRA66X0_BASE+0x005B) |
| 104 | /* RESERVED (CSRA66X0_BASE+0x005C) */ |
| 105 | #define CSRA66X0_USER_DSP_CTRL (CSRA66X0_BASE+0x005D) |
| 106 | #define CSRA66X0_TEST_TONE_CTRL (CSRA66X0_BASE+0x005E) |
| 107 | #define CSRA66X0_TEST_TONE_FREQ_0 (CSRA66X0_BASE+0x005F) |
| 108 | #define CSRA66X0_TEST_TONE_FREQ_1 (CSRA66X0_BASE+0x0060) |
| 109 | #define CSRA66X0_TEST_TONE_FREQ_2 (CSRA66X0_BASE+0x0061) |
| 110 | #define CSRA66X0_AUDIO_RATE_CTRL_FA (CSRA66X0_BASE+0x0062) |
| 111 | #define CSRA66X0_MODULATION_INDEX_CTRL (CSRA66X0_BASE+0x0063) |
| 112 | #define CSRA66X0_MODULATION_INDEX_COUNT (CSRA66X0_BASE+0x0064) |
| 113 | #define CSRA66X0_MIN_MODULATION_PULSE_WIDTH (CSRA66X0_BASE+0x0065) |
| 114 | #define CSRA66X0_DEAD_TIME_CTRL (CSRA66X0_BASE+0x0066) |
| 115 | #define CSRA66X0_DEAD_TIME_THRESHOLD_0 (CSRA66X0_BASE+0x0067) |
| 116 | #define CSRA66X0_DEAD_TIME_THRESHOLD_1 (CSRA66X0_BASE+0x0068) |
| 117 | #define CSRA66X0_DEAD_TIME_THRESHOLD_2 (CSRA66X0_BASE+0x0069) |
| 118 | #define CSRA66X0_CH1_LOW_SIDE_DLY (CSRA66X0_BASE+0x006A) |
| 119 | #define CSRA66X0_CH2_LOW_SIDE_DLY (CSRA66X0_BASE+0x006B) |
| 120 | #define CSRA66X0_SPECTRUM_CTRL (CSRA66X0_BASE+0x006C) |
| 121 | /* RESERVED (CSRA66X0_BASE+0x006D) */ |
| 122 | #define CSRA66X0_SPECTRUM_SPREAD_CTRL (CSRA66X0_BASE+0x006E) |
| 123 | /* RESERVED (CSRA66X0_BASE+0x006F) */ |
| 124 | /* ... */ |
| 125 | /* RESERVED (CSRA66X0_BASE+0x007C) */ |
| 126 | #define CSRA66X0_EXT_PA_PROTECT_POLARITY (CSRA66X0_BASE+0x007D) |
| 127 | #define CSRA66X0_TEMP0_BACKOFF_COMP_VALUE (CSRA66X0_BASE+0x007E) |
| 128 | #define CSRA66X0_TEMP0_SHUTDOWN_COMP_VALUE (CSRA66X0_BASE+0x007F) |
| 129 | #define CSRA66X0_TEMP1_BACKOFF_COMP_VALUE (CSRA66X0_BASE+0x0080) |
| 130 | #define CSRA66X0_TEMP1_SHUTDOWN_COMP_VALUE (CSRA66X0_BASE+0x0081) |
| 131 | #define CSRA66X0_TEMP_PROT_BACKOFF (CSRA66X0_BASE+0x0082) |
| 132 | #define CSRA66X0_TEMP_READ0_FA (CSRA66X0_BASE+0x0083) |
| 133 | #define CSRA66X0_TEMP_READ1_FA (CSRA66X0_BASE+0x0084) |
| 134 | #define CSRA66X0_CHIP_STATE_CTRL_FA (CSRA66X0_BASE+0x0085) |
| 135 | /* RESERVED (CSRA66X0_BASE+0x0086) */ |
| 136 | #define CSRA66X0_PWM_OUTPUT_CONFIG (CSRA66X0_BASE+0x0087) |
| 137 | #define CSRA66X0_MISC_CONTROL_STATUS_0 (CSRA66X0_BASE+0x0088) |
| 138 | #define CSRA66X0_MISC_CONTROL_STATUS_1_FA (CSRA66X0_BASE+0x0089) |
| 139 | #define CSRA66X0_PIO0_SELECT (CSRA66X0_BASE+0x008A) |
| 140 | #define CSRA66X0_PIO1_SELECT (CSRA66X0_BASE+0x008B) |
| 141 | #define CSRA66X0_PIO2_SELECT (CSRA66X0_BASE+0x008C) |
| 142 | #define CSRA66X0_PIO3_SELECT (CSRA66X0_BASE+0x008D) |
| 143 | #define CSRA66X0_PIO4_SELECT (CSRA66X0_BASE+0x008E) |
| 144 | #define CSRA66X0_PIO5_SELECT (CSRA66X0_BASE+0x008F) |
| 145 | #define CSRA66X0_PIO6_SELECT (CSRA66X0_BASE+0x0090) |
| 146 | #define CSRA66X0_PIO7_SELECT (CSRA66X0_BASE+0x0091) |
| 147 | #define CSRA66X0_PIO8_SELECT (CSRA66X0_BASE+0x0092) |
| 148 | #define CSRA66X0_PIO_DIRN0 (CSRA66X0_BASE+0x0093) |
| 149 | #define CSRA66X0_PIO_DIRN1 (CSRA66X0_BASE+0x0094) |
| 150 | #define CSRA66X0_PIO_PULL_EN0 (CSRA66X0_BASE+0x0095) |
| 151 | #define CSRA66X0_PIO_PULL_EN1 (CSRA66X0_BASE+0x0096) |
| 152 | #define CSRA66X0_PIO_PULL_DIR0 (CSRA66X0_BASE+0x0097) |
| 153 | #define CSRA66X0_PIO_PULL_DIR1 (CSRA66X0_BASE+0x0098) |
| 154 | #define CSRA66X0_PIO_DRIVE_OUT0_FA (CSRA66X0_BASE+0x0099) |
| 155 | #define CSRA66X0_PIO_DRIVE_OUT1_FA (CSRA66X0_BASE+0x009A) |
| 156 | #define CSRA66X0_PIO_STATUS_IN0_FA (CSRA66X0_BASE+0x009B) |
| 157 | #define CSRA66X0_PIO_STATUS_IN1_FA (CSRA66X0_BASE+0x009C) |
| 158 | /* RESERVED (CSRA66X0_BASE+0x009D) */ |
| 159 | #define CSRA66X0_IRQ_OUTPUT_ENABLE (CSRA66X0_BASE+0x009E) |
| 160 | #define CSRA66X0_IRQ_OUTPUT_POLARITY (CSRA66X0_BASE+0x009F) |
| 161 | #define CSRA66X0_IRQ_OUTPUT_STATUS_FA (CSRA66X0_BASE+0x00A0) |
| 162 | #define CSRA66X0_CLIP_DCA_STATUS_FA (CSRA66X0_BASE+0x00A1) |
| 163 | #define CSRA66X0_CHIP_STATE_STATUS_FA (CSRA66X0_BASE+0x00A2) |
| 164 | #define CSRA66X0_FAULT_STATUS_FA (CSRA66X0_BASE+0x00A3) |
| 165 | #define CSRA66X0_OTP_STATUS_FA (CSRA66X0_BASE+0x00A4) |
| 166 | #define CSRA66X0_AUDIO_IF_STATUS_FA (CSRA66X0_BASE+0x00A5) |
| 167 | /* RESERVED (CSRA66X0_BASE+0x00A6) */ |
| 168 | #define CSRA66X0_DSP_SATURATION_STATUS_FA (CSRA66X0_BASE+0x00A7) |
| 169 | #define CSRA66X0_AUDIO_RATE_STATUS_FA (CSRA66X0_BASE+0x00A8) |
| 170 | /* RESERVED (CSRA66X0_BASE+0x00A9) */ |
| 171 | /* ... */ |
| 172 | /* RESERVED (CSRA66X0_BASE+0x00AB) */ |
| 173 | #define CSRA66X0_DISABLE_PWM_OUTPUT (CSRA66X0_BASE+0x00AC) |
| 174 | /* RESERVED (CSRA66X0_BASE+0x00AD) */ |
| 175 | /* ... */ |
| 176 | /* RESERVED (CSRA66X0_BASE+0x00B0) */ |
| 177 | #define CSRA66X0_OTP_VER_FA (CSRA66X0_BASE+0x00B1) |
| 178 | #define CSRA66X0_RAM_VER_FA (CSRA66X0_BASE+0x00B2) |
| 179 | /* RESERVED (CSRA66X0_BASE+0x00B3) */ |
| 180 | #define CSRA66X0_AUDIO_SATURATION_FLAGS_FA (CSRA66X0_BASE+0x00B4) |
| 181 | #define CSRA66X0_DCOFFSET_CHAN_1_01_FA (CSRA66X0_BASE+0x00B5) |
| 182 | #define CSRA66X0_DCOFFSET_CHAN_1_02_FA (CSRA66X0_BASE+0x00B6) |
| 183 | #define CSRA66X0_DCOFFSET_CHAN_1_03_FA (CSRA66X0_BASE+0x00B7) |
| 184 | #define CSRA66X0_DCOFFSET_CHAN_2_01_FA (CSRA66X0_BASE+0x00B8) |
| 185 | #define CSRA66X0_DCOFFSET_CHAN_2_02_FA (CSRA66X0_BASE+0x00B9) |
| 186 | #define CSRA66X0_DCOFFSET_CHAN_2_03_FA (CSRA66X0_BASE+0x00BA) |
| 187 | #define CSRA66X0_FORCED_PA_SWITCHING_CTRL (CSRA66X0_BASE+0x00BB) |
| 188 | #define CSRA66X0_PA_FORCE_PULSE_WIDTH (CSRA66X0_BASE+0x00BC) |
| 189 | #define CSRA66X0_PA_HIGH_MODULATION_CTRL_CH1 (CSRA66X0_BASE+0x00BD) |
| 190 | /* RESERVED (CSRA66X0_BASE+0x00BE) */ |
| 191 | /* RESERVED (CSRA66X0_BASE+0x00BF) */ |
| 192 | #define CSRA66X0_HIGH_MODULATION_THRESHOLD_LOW (CSRA66X0_BASE+0x00C0) |
| 193 | #define CSRA66X0_HIGH_MODULATION_THRESHOLD_HIGH (CSRA66X0_BASE+0x00C1) |
| 194 | /* RESERVED (CSRA66X0_BASE+0x00C2) */ |
| 195 | /* RESERVED (CSRA66X0_BASE+0x00C3) */ |
| 196 | #define CSRA66X0_PA_FREEZE_CTRL (CSRA66X0_BASE+0x00C4) |
| 197 | #define CSRA66X0_DCA_FREEZE_CTRL (CSRA66X0_BASE+0x00C5) |
| 198 | /* RESERVED (CSRA66X0_BASE+0x00C6) */ |
| 199 | /* ... */ |
| 200 | /* RESERVED (CSRA66X0_BASE+0x00FF) */ |
| Romed Schur | 8883e44 | 2018-11-06 14:06:58 +0100 | [diff] [blame] | 201 | #define CSRA66X0_MAX_REGISTER_ADDR CSRA66X0_DCA_FREEZE_CTRL |
| 202 | |
| 203 | #define CSRA66X0_COEFF_BASE 0xD000 |
| 204 | #define CSRA66X0_MAX_COEFF_ADDR 0xD6DF |
| Mangesh Kunchamwar | 82f6168 | 2018-05-17 18:47:47 +0530 | [diff] [blame] | 205 | |
| 206 | #define EXPECTED_CSRA66X0_CHIP_ID 0x39 |
| 207 | |
| 208 | #define SPK_VOLUME_M20DB 0x119 |
| 209 | #define SPK_VOLUME_M20DB_LSB (SPK_VOLUME_M20DB & 0x0FF) |
| 210 | #define SPK_VOLUME_M20DB_MSB ((SPK_VOLUME_M20DB & 0x100)>>8) |
| 211 | #define SPK_VOLUME_LSB_MSK 0x00FF |
| 212 | #define SPK_VOLUME_MSB_MSK 0x0100 |
| 213 | |
| Romed Schur | 8883e44 | 2018-11-06 14:06:58 +0100 | [diff] [blame] | 214 | #define SET_CONFIG_STATE 0x0 |
| 215 | #define SET_RUN_STATE 0x1 |
| 216 | #define SET_STDBY_STATE 0x2 |
| 217 | |
| 218 | #define CONFIG_STATE_ID 0x3 |
| 219 | #define WAIT_FOR_CONFIG_STATE_TIMEOUT_MS 2000 |
| 220 | #define SYSFS_RESET 1 |
| Mangesh Kunchamwar | 82f6168 | 2018-05-17 18:47:47 +0530 | [diff] [blame] | 221 | |
| 222 | #define FAULT_STATUS_INTERNAL 0x01 |
| 223 | #define FAULT_STATUS_OTP_INTEGRITY 0x02 |
| 224 | #define FAULT_STATUS_PADS2 0x04 |
| 225 | #define FAULT_STATUS_SMPS 0x08 |
| 226 | #define FAULT_STATUS_TEMP 0x10 |
| 227 | #define FAULT_STATUS_PROTECT 0x20 |
| 228 | |
| Sanjana B | 22cd4cb | 2020-04-05 18:24:24 +0530 | [diff] [blame] | 229 | |
| 230 | void csra66x0_hw_free_mute(struct snd_soc_component *component); |
| Mangesh Kunchamwar | 82f6168 | 2018-05-17 18:47:47 +0530 | [diff] [blame] | 231 | #endif /* _CSRA66X0_H */ |