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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / 4d6a6dc9e3aeaa351ba6e8f88863e058fc61c5a6 / . / asoc / codecs / msm_sdw / msm_sdw.h
blob: 82cff87d6417a820c8b42024a7da9b872d0aabdb [file] [log] [blame]
Soumya Managolid11d6f02020-05-27 17:25:12 +0530[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved.
4 */
5#ifndef MSM_SDW_H
6#define MSM_SDW_H
7
8#include <sound/soc.h>
9#include <dsp/q6afe-v2.h>
10#include "msm_sdw_registers.h"
11
12#define MSM_SDW_MAX_REGISTER 0x400
13#define MSM_SDW_CHILD_DEVICES_MAX 1
14
15extern const struct regmap_config msm_sdw_regmap_config;
16extern const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER];
17extern const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER];
18extern const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER];
19
20enum {
21 MSM_SDW_RX4 = 0,
22 MSM_SDW_RX5,
23 MSM_SDW_RX_MAX,
24};
25
26enum {
27 MSM_SDW_TX0 = 0,
28 MSM_SDW_TX1,
29 MSM_SDW_TX_MAX,
30};
31
32enum {
33 COMP1, /* SPK_L */
34 COMP2, /* SPK_R */
35 COMP_MAX
36};
37
38/*
39 * Structure used to update codec
40 * register defaults after reset
41 */
42struct msm_sdw_reg_mask_val {
43 u16 reg;
44 u8 mask;
45 u8 val;
46};
47
48/*
49 * Selects compander and smart boost settings
50 * for a given speaker mode
51 */
52enum {
53 SPKR_MODE_DEFAULT,
54 SPKR_MODE_1, /* COMP Gain = 12dB, Smartboost Max = 5.5V */
55};
56
57/* Rx path gain offsets */
58enum {
59 RX_GAIN_OFFSET_M1P5_DB,
60 RX_GAIN_OFFSET_0_DB,
61};
62
63struct msm_sdw_reg_val {
64 unsigned short reg; /* register address */
65 u8 *buf; /* buffer to be written to reg. addr */
66 int bytes; /* number of bytes to be written */
67};
68
69/* Hold instance to soundwire platform device */
70struct msm_sdw_ctrl_data {
71 struct platform_device *sdw_pdev;
72};
73
74struct wcd_sdw_ctrl_platform_data {
75 void *handle; /* holds codec private data */
76 int (*read)(void *handle, int reg);
77 int (*write)(void *handle, int reg, int val);
78 int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
79 int (*clk)(void *handle, bool enable);
80 int (*handle_irq)(void *handle,
81 irqreturn_t (*swrm_irq_handler)(int irq,
82 void *data),
83 void *swrm_handle,
84 int action);
85};
86
87struct msm_sdw_priv {
88 struct device *dev;
89 struct mutex io_lock;
90
91 int (*read_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
92 int bytes, void *dest);
93 int (*write_dev)(struct msm_sdw_priv *msm_sdw, unsigned short reg,
94 int bytes, void *src);
95 int (*multi_reg_write)(struct msm_sdw_priv *msm_sdw, const void *data,
96 size_t count);
97 struct snd_soc_component *component;
98 struct device_node *sdw_gpio_p; /* used by pinctrl API */
99 /* SoundWire data structure */
100 struct msm_sdw_ctrl_data *sdw_ctrl_data;
101 int nr;
102
103 /* compander */
104 int comp_enabled[COMP_MAX];
105 int ear_spkr_gain;
106
107 /* to track the status */
108 unsigned long status_mask;
109
110 struct work_struct msm_sdw_add_child_devices_work;
111 struct wcd_sdw_ctrl_platform_data sdw_plat_data;
112
113 unsigned int vi_feed_value;
114
115 struct mutex sdw_read_lock;
116 struct mutex sdw_write_lock;
117 struct mutex sdw_clk_lock;
118 int sdw_clk_users;
119 int sdw_mclk_users;
120
121 int sdw_irq;
122 int int_mclk1_rsc_ref;
123 bool int_mclk1_enabled;
124 bool sdw_npl_clk_enabled;
125 struct mutex cdc_int_mclk1_mutex;
126 struct mutex sdw_npl_clk_mutex;
127 struct delayed_work disable_int_mclk1_work;
128 struct afe_clk_set sdw_cdc_core_clk;
129 struct afe_clk_set sdw_npl_clk;
130 struct notifier_block service_nb;
131 int (*sdw_cdc_gpio_fn)(bool enable,
132 struct snd_soc_component *component);
133 bool dev_up;
134
135 int spkr_gain_offset;
136 int spkr_mode;
137 struct mutex codec_mutex;
138 int rx_4_count;
139 int rx_5_count;
140 u32 mclk_rate;
141 struct regmap *regmap;
142
143 bool prev_pg_valid;
144 u8 prev_pg;
145 u32 sdw_base_addr;
146 char __iomem *sdw_base;
147 u32 version;
148
149 /* Entry for version info */
150 struct snd_info_entry *entry;
151 struct snd_info_entry *version_entry;
152 struct platform_device *pdev_child_devices
153 [MSM_SDW_CHILD_DEVICES_MAX];
154 int child_count;
155};
156
157#if IS_ENABLED(CONFIG_SND_SOC_MSM_SDW)
158extern int msm_sdw_set_spkr_mode(struct snd_soc_component *component, int mode);
159extern int msm_sdw_set_spkr_gain_offset(struct snd_soc_component *component,
160 int offset);
161extern void msm_sdw_gpio_cb(
162 int (*sdw_cdc_gpio_fn)(bool enable,
163 struct snd_soc_component *component),
164 struct snd_soc_component *component);
165extern struct regmap *msm_sdw_regmap_init(struct device *dev,
166 const struct regmap_config *config);
167extern int msm_sdw_codec_info_create_codec_entry(
168 struct snd_info_entry *component_root,
169 struct snd_soc_component *component);
170#else /* CONFIG_SND_SOC_MSM_SDW */
171static inline int msm_sdw_set_spkr_mode(struct snd_soc_component *component,
172 int mode)
173{
174 return 0;
175}
176static inline int msm_sdw_set_spkr_gain_offset(
177 struct snd_soc_component *component,
178 int offset);
179{
180 return 0;
181}
182static inline void msm_sdw_gpio_cb(
183 int (*sdw_cdc_gpio_fn)(bool enable,
184 struct snd_soc_component *component),
185 struct snd_soc_component *component);
186{
187
188}
189static inline struct regmap *msm_sdw_regmap_init(struct device *dev,
190 const struct regmap_config *config);
191{
192 return NULL;
193}
194static inline int msm_sdw_codec_info_create_codec_entry(
195 struct snd_info_entry *component_root,
196 struct snd_soc_component *component)
197{
198 return 0;
199}
200#endif /* CONFIG_SND_SOC_MSM_SDW */
201#endif