| Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Tanya Dixit | 9b37ac9 | 2018-07-27 16:52:47 +0530 | [diff] [blame] | 2 | /* |
| Tanya Dixit | 46ec0f2 | 2018-10-16 14:48:37 +0530 | [diff] [blame] | 3 | * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| Tanya Dixit | 9b37ac9 | 2018-07-27 16:52:47 +0530 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _WCD937X_REGISTERS_H |
| 7 | #define _WCD937X_REGISTERS_H |
| 8 | |
| 9 | #define WCD937X_BASE_ADDRESS 0x3000 |
| 10 | |
| 11 | #define WCD937X_REG(reg) (reg - WCD937X_BASE_ADDRESS) |
| 12 | |
| 13 | enum { |
| 14 | REG_NO_ACCESS, |
| 15 | RD_REG, |
| 16 | WR_REG, |
| 17 | RD_WR_REG |
| 18 | }; |
| 19 | |
| 20 | #define WCD937X_ANA_BIAS (WCD937X_BASE_ADDRESS+0x001) |
| 21 | #define WCD937X_ANA_RX_SUPPLIES (WCD937X_BASE_ADDRESS+0x008) |
| 22 | #define WCD937X_ANA_HPH (WCD937X_BASE_ADDRESS+0x009) |
| 23 | #define WCD937X_ANA_EAR (WCD937X_BASE_ADDRESS+0x00A) |
| 24 | #define WCD937X_ANA_EAR_COMPANDER_CTL (WCD937X_BASE_ADDRESS+0x00B) |
| 25 | #define WCD937X_ANA_TX_CH1 (WCD937X_BASE_ADDRESS+0x00E) |
| 26 | #define WCD937X_ANA_TX_CH2 (WCD937X_BASE_ADDRESS+0x00F) |
| 27 | #define WCD937X_ANA_TX_CH3 (WCD937X_BASE_ADDRESS+0x010) |
| 28 | #define WCD937X_ANA_TX_CH3_HPF (WCD937X_BASE_ADDRESS+0x011) |
| 29 | #define WCD937X_ANA_MICB1_MICB2_DSP_EN_LOGIC (WCD937X_BASE_ADDRESS+0x012) |
| 30 | #define WCD937X_ANA_MICB3_DSP_EN_LOGIC (WCD937X_BASE_ADDRESS+0x013) |
| 31 | #define WCD937X_ANA_MBHC_MECH (WCD937X_BASE_ADDRESS+0x014) |
| 32 | #define WCD937X_ANA_MBHC_ELECT (WCD937X_BASE_ADDRESS+0x015) |
| 33 | #define WCD937X_ANA_MBHC_ZDET (WCD937X_BASE_ADDRESS+0x016) |
| 34 | #define WCD937X_ANA_MBHC_RESULT_1 (WCD937X_BASE_ADDRESS+0x017) |
| 35 | #define WCD937X_ANA_MBHC_RESULT_2 (WCD937X_BASE_ADDRESS+0x018) |
| 36 | #define WCD937X_ANA_MBHC_RESULT_3 (WCD937X_BASE_ADDRESS+0x019) |
| 37 | #define WCD937X_ANA_MBHC_BTN0 (WCD937X_BASE_ADDRESS+0x01A) |
| 38 | #define WCD937X_ANA_MBHC_BTN1 (WCD937X_BASE_ADDRESS+0x01B) |
| 39 | #define WCD937X_ANA_MBHC_BTN2 (WCD937X_BASE_ADDRESS+0x01C) |
| 40 | #define WCD937X_ANA_MBHC_BTN3 (WCD937X_BASE_ADDRESS+0x01D) |
| 41 | #define WCD937X_ANA_MBHC_BTN4 (WCD937X_BASE_ADDRESS+0x01E) |
| 42 | #define WCD937X_ANA_MBHC_BTN5 (WCD937X_BASE_ADDRESS+0x01F) |
| 43 | #define WCD937X_ANA_MBHC_BTN6 (WCD937X_BASE_ADDRESS+0x020) |
| 44 | #define WCD937X_ANA_MBHC_BTN7 (WCD937X_BASE_ADDRESS+0x021) |
| 45 | #define WCD937X_ANA_MICB1 (WCD937X_BASE_ADDRESS+0x022) |
| 46 | #define WCD937X_ANA_MICB2 (WCD937X_BASE_ADDRESS+0x023) |
| 47 | #define WCD937X_ANA_MICB2_RAMP (WCD937X_BASE_ADDRESS+0x024) |
| 48 | #define WCD937X_ANA_MICB3 (WCD937X_BASE_ADDRESS+0x025) |
| 49 | #define WCD937X_BIAS_CTL (WCD937X_BASE_ADDRESS+0x028) |
| 50 | #define WCD937X_BIAS_VBG_FINE_ADJ (WCD937X_BASE_ADDRESS+0x029) |
| 51 | #define WCD937X_LDOL_VDDCX_ADJUST (WCD937X_BASE_ADDRESS+0x040) |
| 52 | #define WCD937X_LDOL_DISABLE_LDOL (WCD937X_BASE_ADDRESS+0x041) |
| 53 | #define WCD937X_MBHC_CTL_CLK (WCD937X_BASE_ADDRESS+0x056) |
| 54 | #define WCD937X_MBHC_CTL_ANA (WCD937X_BASE_ADDRESS+0x057) |
| 55 | #define WCD937X_MBHC_CTL_SPARE_1 (WCD937X_BASE_ADDRESS+0x058) |
| 56 | #define WCD937X_MBHC_CTL_SPARE_2 (WCD937X_BASE_ADDRESS+0x059) |
| 57 | #define WCD937X_MBHC_CTL_BCS (WCD937X_BASE_ADDRESS+0x05A) |
| 58 | #define WCD937X_MBHC_MOISTURE_DET_FSM_STATUS (WCD937X_BASE_ADDRESS+0x05B) |
| 59 | #define WCD937X_MBHC_TEST_CTL (WCD937X_BASE_ADDRESS+0x05C) |
| 60 | #define WCD937X_LDOH_MODE (WCD937X_BASE_ADDRESS+0x067) |
| 61 | #define WCD937X_LDOH_BIAS (WCD937X_BASE_ADDRESS+0x068) |
| 62 | #define WCD937X_LDOH_STB_LOADS (WCD937X_BASE_ADDRESS+0x069) |
| 63 | #define WCD937X_LDOH_SLOWRAMP (WCD937X_BASE_ADDRESS+0x06A) |
| 64 | #define WCD937X_MICB1_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x06B) |
| 65 | #define WCD937X_MICB1_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x06C) |
| 66 | #define WCD937X_MICB1_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x06D) |
| 67 | #define WCD937X_MICB2_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x06E) |
| 68 | #define WCD937X_MICB2_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x06F) |
| 69 | #define WCD937X_MICB2_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x070) |
| 70 | #define WCD937X_MICB3_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x071) |
| 71 | #define WCD937X_MICB3_TEST_CTL_2 (WCD937X_BASE_ADDRESS+0x072) |
| 72 | #define WCD937X_MICB3_TEST_CTL_3 (WCD937X_BASE_ADDRESS+0x073) |
| 73 | #define WCD937X_TX_COM_ADC_VCM (WCD937X_BASE_ADDRESS+0x077) |
| 74 | #define WCD937X_TX_COM_BIAS_ATEST (WCD937X_BASE_ADDRESS+0x078) |
| 75 | #define WCD937X_TX_COM_ADC_INT1_IB (WCD937X_BASE_ADDRESS+0x079) |
| 76 | #define WCD937X_TX_COM_ADC_INT2_IB (WCD937X_BASE_ADDRESS+0x07A) |
| 77 | #define WCD937X_TX_COM_TXFE_DIV_CTL (WCD937X_BASE_ADDRESS+0x07B) |
| 78 | #define WCD937X_TX_COM_TXFE_DIV_START (WCD937X_BASE_ADDRESS+0x07C) |
| 79 | #define WCD937X_TX_COM_TXFE_DIV_STOP_9P6M (WCD937X_BASE_ADDRESS+0x07D) |
| 80 | #define WCD937X_TX_COM_TXFE_DIV_STOP_12P288M (WCD937X_BASE_ADDRESS+0x07E) |
| 81 | #define WCD937X_TX_1_2_TEST_EN (WCD937X_BASE_ADDRESS+0x07F) |
| 82 | #define WCD937X_TX_1_2_ADC_IB (WCD937X_BASE_ADDRESS+0x080) |
| 83 | #define WCD937X_TX_1_2_ATEST_REFCTL (WCD937X_BASE_ADDRESS+0x081) |
| 84 | #define WCD937X_TX_1_2_TEST_CTL (WCD937X_BASE_ADDRESS+0x082) |
| 85 | #define WCD937X_TX_1_2_TEST_BLK_EN (WCD937X_BASE_ADDRESS+0x083) |
| 86 | #define WCD937X_TX_1_2_TXFE_CLKDIV (WCD937X_BASE_ADDRESS+0x084) |
| 87 | #define WCD937X_TX_1_2_SAR2_ERR (WCD937X_BASE_ADDRESS+0x085) |
| 88 | #define WCD937X_TX_1_2_SAR1_ERR (WCD937X_BASE_ADDRESS+0x086) |
| 89 | #define WCD937X_TX_3_TEST_EN (WCD937X_BASE_ADDRESS+0x087) |
| 90 | #define WCD937X_TX_3_ADC_IB (WCD937X_BASE_ADDRESS+0x088) |
| 91 | #define WCD937X_TX_3_ATEST_REFCTL (WCD937X_BASE_ADDRESS+0x089) |
| 92 | #define WCD937X_TX_3_TEST_CTL (WCD937X_BASE_ADDRESS+0x08A) |
| 93 | #define WCD937X_TX_3_TEST_BLK_EN (WCD937X_BASE_ADDRESS+0x08B) |
| 94 | #define WCD937X_TX_3_TXFE_CLKDIV (WCD937X_BASE_ADDRESS+0x08C) |
| 95 | #define WCD937X_TX_3_SPARE_MONO (WCD937X_BASE_ADDRESS+0x08D) |
| 96 | #define WCD937X_TX_3_SAR1_ERR (WCD937X_BASE_ADDRESS+0x08E) |
| 97 | #define WCD937X_CLASSH_MODE_1 (WCD937X_BASE_ADDRESS+0x097) |
| 98 | #define WCD937X_CLASSH_MODE_2 (WCD937X_BASE_ADDRESS+0x098) |
| 99 | #define WCD937X_CLASSH_MODE_3 (WCD937X_BASE_ADDRESS+0x099) |
| 100 | #define WCD937X_CLASSH_CTRL_VCL_1 (WCD937X_BASE_ADDRESS+0x09A) |
| 101 | #define WCD937X_CLASSH_CTRL_VCL_2 (WCD937X_BASE_ADDRESS+0x09B) |
| 102 | #define WCD937X_CLASSH_CTRL_CCL_1 (WCD937X_BASE_ADDRESS+0x09C) |
| 103 | #define WCD937X_CLASSH_CTRL_CCL_2 (WCD937X_BASE_ADDRESS+0x09D) |
| 104 | #define WCD937X_CLASSH_CTRL_CCL_3 (WCD937X_BASE_ADDRESS+0x09E) |
| 105 | #define WCD937X_CLASSH_CTRL_CCL_4 (WCD937X_BASE_ADDRESS+0x09F) |
| 106 | #define WCD937X_CLASSH_CTRL_CCL_5 (WCD937X_BASE_ADDRESS+0x0A0) |
| 107 | #define WCD937X_CLASSH_BUCK_TMUX_A_D (WCD937X_BASE_ADDRESS+0x0A1) |
| 108 | #define WCD937X_CLASSH_BUCK_SW_DRV_CNTL (WCD937X_BASE_ADDRESS+0x0A2) |
| 109 | #define WCD937X_CLASSH_SPARE (WCD937X_BASE_ADDRESS+0x0A3) |
| 110 | #define WCD937X_FLYBACK_EN (WCD937X_BASE_ADDRESS+0x0A4) |
| 111 | #define WCD937X_FLYBACK_VNEG_CTRL_1 (WCD937X_BASE_ADDRESS+0x0A5) |
| 112 | #define WCD937X_FLYBACK_VNEG_CTRL_2 (WCD937X_BASE_ADDRESS+0x0A6) |
| 113 | #define WCD937X_FLYBACK_VNEG_CTRL_3 (WCD937X_BASE_ADDRESS+0x0A7) |
| 114 | #define WCD937X_FLYBACK_VNEG_CTRL_4 (WCD937X_BASE_ADDRESS+0x0A8) |
| 115 | #define WCD937X_FLYBACK_VNEG_CTRL_5 (WCD937X_BASE_ADDRESS+0x0A9) |
| 116 | #define WCD937X_FLYBACK_VNEG_CTRL_6 (WCD937X_BASE_ADDRESS+0x0AA) |
| 117 | #define WCD937X_FLYBACK_VNEG_CTRL_7 (WCD937X_BASE_ADDRESS+0x0AB) |
| 118 | #define WCD937X_FLYBACK_VNEG_CTRL_8 (WCD937X_BASE_ADDRESS+0x0AC) |
| 119 | #define WCD937X_FLYBACK_VNEG_CTRL_9 (WCD937X_BASE_ADDRESS+0x0AD) |
| 120 | #define WCD937X_FLYBACK_VNEGDAC_CTRL_1 (WCD937X_BASE_ADDRESS+0x0AE) |
| 121 | #define WCD937X_FLYBACK_VNEGDAC_CTRL_2 (WCD937X_BASE_ADDRESS+0x0AF) |
| 122 | #define WCD937X_FLYBACK_VNEGDAC_CTRL_3 (WCD937X_BASE_ADDRESS+0x0B0) |
| 123 | #define WCD937X_FLYBACK_CTRL_1 (WCD937X_BASE_ADDRESS+0x0B1) |
| 124 | #define WCD937X_FLYBACK_TEST_CTL (WCD937X_BASE_ADDRESS+0x0B2) |
| 125 | #define WCD937X_RX_AUX_SW_CTL (WCD937X_BASE_ADDRESS+0x0B3) |
| 126 | #define WCD937X_RX_PA_AUX_IN_CONN (WCD937X_BASE_ADDRESS+0x0B4) |
| 127 | #define WCD937X_RX_TIMER_DIV (WCD937X_BASE_ADDRESS+0x0B5) |
| 128 | #define WCD937X_RX_OCP_CTL (WCD937X_BASE_ADDRESS+0x0B6) |
| 129 | #define WCD937X_RX_OCP_COUNT (WCD937X_BASE_ADDRESS+0x0B7) |
| 130 | #define WCD937X_RX_BIAS_EAR_DAC (WCD937X_BASE_ADDRESS+0x0B8) |
| 131 | #define WCD937X_RX_BIAS_EAR_AMP (WCD937X_BASE_ADDRESS+0x0B9) |
| 132 | #define WCD937X_RX_BIAS_HPH_LDO (WCD937X_BASE_ADDRESS+0x0BA) |
| 133 | #define WCD937X_RX_BIAS_HPH_PA (WCD937X_BASE_ADDRESS+0x0BB) |
| 134 | #define WCD937X_RX_BIAS_HPH_RDACBUFF_CNP2 (WCD937X_BASE_ADDRESS+0x0BC) |
| 135 | #define WCD937X_RX_BIAS_HPH_RDAC_LDO (WCD937X_BASE_ADDRESS+0x0BD) |
| 136 | #define WCD937X_RX_BIAS_HPH_CNP1 (WCD937X_BASE_ADDRESS+0x0BE) |
| 137 | #define WCD937X_RX_BIAS_HPH_LOWPOWER (WCD937X_BASE_ADDRESS+0x0BF) |
| 138 | #define WCD937X_RX_BIAS_AUX_DAC (WCD937X_BASE_ADDRESS+0x0C0) |
| 139 | #define WCD937X_RX_BIAS_AUX_AMP (WCD937X_BASE_ADDRESS+0x0C1) |
| 140 | #define WCD937X_RX_BIAS_VNEGDAC_BLEEDER (WCD937X_BASE_ADDRESS+0x0C2) |
| 141 | #define WCD937X_RX_BIAS_MISC (WCD937X_BASE_ADDRESS+0x0C3) |
| 142 | #define WCD937X_RX_BIAS_BUCK_RST (WCD937X_BASE_ADDRESS+0x0C4) |
| 143 | #define WCD937X_RX_BIAS_BUCK_VREF_ERRAMP (WCD937X_BASE_ADDRESS+0x0C5) |
| 144 | #define WCD937X_RX_BIAS_FLYB_ERRAMP (WCD937X_BASE_ADDRESS+0x0C6) |
| 145 | #define WCD937X_RX_BIAS_FLYB_BUFF (WCD937X_BASE_ADDRESS+0x0C7) |
| 146 | #define WCD937X_RX_BIAS_FLYB_MID_RST (WCD937X_BASE_ADDRESS+0x0C8) |
| 147 | #define WCD937X_HPH_L_STATUS (WCD937X_BASE_ADDRESS+0x0C9) |
| 148 | #define WCD937X_HPH_R_STATUS (WCD937X_BASE_ADDRESS+0x0CA) |
| 149 | #define WCD937X_HPH_CNP_EN (WCD937X_BASE_ADDRESS+0x0CB) |
| 150 | #define WCD937X_HPH_CNP_WG_CTL (WCD937X_BASE_ADDRESS+0x0CC) |
| 151 | #define WCD937X_HPH_CNP_WG_TIME (WCD937X_BASE_ADDRESS+0x0CD) |
| 152 | #define WCD937X_HPH_OCP_CTL (WCD937X_BASE_ADDRESS+0x0CE) |
| 153 | #define WCD937X_HPH_AUTO_CHOP (WCD937X_BASE_ADDRESS+0x0CF) |
| 154 | #define WCD937X_HPH_CHOP_CTL (WCD937X_BASE_ADDRESS+0x0D0) |
| 155 | #define WCD937X_HPH_PA_CTL1 (WCD937X_BASE_ADDRESS+0x0D1) |
| 156 | #define WCD937X_HPH_PA_CTL2 (WCD937X_BASE_ADDRESS+0x0D2) |
| 157 | #define WCD937X_HPH_L_EN (WCD937X_BASE_ADDRESS+0x0D3) |
| 158 | #define WCD937X_HPH_L_TEST (WCD937X_BASE_ADDRESS+0x0D4) |
| 159 | #define WCD937X_HPH_L_ATEST (WCD937X_BASE_ADDRESS+0x0D5) |
| 160 | #define WCD937X_HPH_R_EN (WCD937X_BASE_ADDRESS+0x0D6) |
| 161 | #define WCD937X_HPH_R_TEST (WCD937X_BASE_ADDRESS+0x0D7) |
| 162 | #define WCD937X_HPH_R_ATEST (WCD937X_BASE_ADDRESS+0x0D8) |
| 163 | #define WCD937X_HPH_RDAC_CLK_CTL1 (WCD937X_BASE_ADDRESS+0x0D9) |
| 164 | #define WCD937X_HPH_RDAC_CLK_CTL2 (WCD937X_BASE_ADDRESS+0x0DA) |
| 165 | #define WCD937X_HPH_RDAC_LDO_CTL (WCD937X_BASE_ADDRESS+0x0DB) |
| 166 | #define WCD937X_HPH_RDAC_CHOP_CLK_LP_CTL (WCD937X_BASE_ADDRESS+0x0DC) |
| 167 | #define WCD937X_HPH_REFBUFF_UHQA_CTL (WCD937X_BASE_ADDRESS+0x0DD) |
| 168 | #define WCD937X_HPH_REFBUFF_LP_CTL (WCD937X_BASE_ADDRESS+0x0DE) |
| 169 | #define WCD937X_HPH_L_DAC_CTL (WCD937X_BASE_ADDRESS+0x0DF) |
| 170 | #define WCD937X_HPH_R_DAC_CTL (WCD937X_BASE_ADDRESS+0x0E0) |
| 171 | #define WCD937X_HPH_SURGE_HPHLR_SURGE_COMP_SEL (WCD937X_BASE_ADDRESS+0x0E1) |
| 172 | #define WCD937X_HPH_SURGE_HPHLR_SURGE_EN (WCD937X_BASE_ADDRESS+0x0E2) |
| 173 | #define WCD937X_HPH_SURGE_HPHLR_SURGE_MISC1 (WCD937X_BASE_ADDRESS+0x0E3) |
| 174 | #define WCD937X_HPH_SURGE_HPHLR_SURGE_STATUS (WCD937X_BASE_ADDRESS+0x0E4) |
| 175 | #define WCD937X_EAR_EAR_EN_REG (WCD937X_BASE_ADDRESS+0x0E9) |
| 176 | #define WCD937X_EAR_EAR_PA_CON (WCD937X_BASE_ADDRESS+0x0EA) |
| 177 | #define WCD937X_EAR_EAR_SP_CON (WCD937X_BASE_ADDRESS+0x0EB) |
| 178 | #define WCD937X_EAR_EAR_DAC_CON (WCD937X_BASE_ADDRESS+0x0EC) |
| 179 | #define WCD937X_EAR_EAR_CNP_FSM_CON (WCD937X_BASE_ADDRESS+0x0ED) |
| 180 | #define WCD937X_EAR_TEST_CTL (WCD937X_BASE_ADDRESS+0x0EE) |
| 181 | #define WCD937X_EAR_STATUS_REG_1 (WCD937X_BASE_ADDRESS+0x0EF) |
| 182 | #define WCD937X_EAR_STATUS_REG_2 (WCD937X_BASE_ADDRESS+0x0F0) |
| 183 | #define WCD937X_ANA_NEW_PAGE_REGISTER (WCD937X_BASE_ADDRESS+0x100) |
| 184 | #define WCD937X_HPH_NEW_ANA_HPH2 (WCD937X_BASE_ADDRESS+0x101) |
| 185 | #define WCD937X_HPH_NEW_ANA_HPH3 (WCD937X_BASE_ADDRESS+0x102) |
| 186 | #define WCD937X_SLEEP_CTL (WCD937X_BASE_ADDRESS+0x103) |
| 187 | #define WCD937X_SLEEP_WATCHDOG_CTL (WCD937X_BASE_ADDRESS+0x104) |
| 188 | #define WCD937X_MBHC_NEW_ELECT_REM_CLAMP_CTL (WCD937X_BASE_ADDRESS+0x11F) |
| 189 | #define WCD937X_MBHC_NEW_CTL_1 (WCD937X_BASE_ADDRESS+0x120) |
| 190 | #define WCD937X_MBHC_NEW_CTL_2 (WCD937X_BASE_ADDRESS+0x121) |
| 191 | #define WCD937X_MBHC_NEW_PLUG_DETECT_CTL (WCD937X_BASE_ADDRESS+0x122) |
| 192 | #define WCD937X_MBHC_NEW_ZDET_ANA_CTL (WCD937X_BASE_ADDRESS+0x123) |
| 193 | #define WCD937X_MBHC_NEW_ZDET_RAMP_CTL (WCD937X_BASE_ADDRESS+0x124) |
| 194 | #define WCD937X_MBHC_NEW_FSM_STATUS (WCD937X_BASE_ADDRESS+0x125) |
| 195 | #define WCD937X_MBHC_NEW_ADC_RESULT (WCD937X_BASE_ADDRESS+0x126) |
| 196 | #define WCD937X_TX_NEW_TX_CH2_SEL (WCD937X_BASE_ADDRESS+0x127) |
| 197 | #define WCD937X_AUX_AUXPA (WCD937X_BASE_ADDRESS+0x128) |
| 198 | #define WCD937X_LDORXTX_MODE (WCD937X_BASE_ADDRESS+0x129) |
| 199 | #define WCD937X_LDORXTX_CONFIG (WCD937X_BASE_ADDRESS+0x12A) |
| 200 | #define WCD937X_DIE_CRACK_DIE_CRK_DET_EN (WCD937X_BASE_ADDRESS+0x12C) |
| 201 | #define WCD937X_DIE_CRACK_DIE_CRK_DET_OUT (WCD937X_BASE_ADDRESS+0x12D) |
| 202 | #define WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL (WCD937X_BASE_ADDRESS+0x132) |
| 203 | #define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L (WCD937X_BASE_ADDRESS+0x133) |
| 204 | #define WCD937X_HPH_NEW_INT_RDAC_VREF_CTL (WCD937X_BASE_ADDRESS+0x134) |
| 205 | #define WCD937X_HPH_NEW_INT_RDAC_OVERRIDE_CTL (WCD937X_BASE_ADDRESS+0x135) |
| 206 | #define WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R (WCD937X_BASE_ADDRESS+0x136) |
| 207 | #define WCD937X_HPH_NEW_INT_PA_MISC1 (WCD937X_BASE_ADDRESS+0x137) |
| 208 | #define WCD937X_HPH_NEW_INT_PA_MISC2 (WCD937X_BASE_ADDRESS+0x138) |
| 209 | #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC (WCD937X_BASE_ADDRESS+0x139) |
| 210 | #define WCD937X_HPH_NEW_INT_HPH_TIMER1 (WCD937X_BASE_ADDRESS+0x13A) |
| 211 | #define WCD937X_HPH_NEW_INT_HPH_TIMER2 (WCD937X_BASE_ADDRESS+0x13B) |
| 212 | #define WCD937X_HPH_NEW_INT_HPH_TIMER3 (WCD937X_BASE_ADDRESS+0x13C) |
| 213 | #define WCD937X_HPH_NEW_INT_HPH_TIMER4 (WCD937X_BASE_ADDRESS+0x13D) |
| 214 | #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC2 (WCD937X_BASE_ADDRESS+0x13E) |
| 215 | #define WCD937X_HPH_NEW_INT_PA_RDAC_MISC3 (WCD937X_BASE_ADDRESS+0x13F) |
| 216 | #define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI (WCD937X_BASE_ADDRESS+0x145) |
| 217 | #define WCD937X_RX_NEW_INT_HPH_RDAC_BIAS_ULP (WCD937X_BASE_ADDRESS+0x146) |
| 218 | #define WCD937X_RX_NEW_INT_HPH_RDAC_LDO_LP (WCD937X_BASE_ADDRESS+0x147) |
| 219 | #define WCD937X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL (WCD937X_BASE_ADDRESS+0x1AF) |
| 220 | #define WCD937X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL \ |
| 221 | (WCD937X_BASE_ADDRESS+0x1B0) |
| 222 | #define WCD937X_MBHC_NEW_INT_MECH_DET_CURRENT (WCD937X_BASE_ADDRESS+0x1B1) |
| 223 | #define WCD937X_MBHC_NEW_INT_SPARE_2 (WCD937X_BASE_ADDRESS+0x1B2) |
| 224 | #define WCD937X_EAR_INT_NEW_EAR_CHOPPER_CON (WCD937X_BASE_ADDRESS+0x1B7) |
| 225 | #define WCD937X_EAR_INT_NEW_CNP_VCM_CON1 (WCD937X_BASE_ADDRESS+0x1B8) |
| 226 | #define WCD937X_EAR_INT_NEW_CNP_VCM_CON2 (WCD937X_BASE_ADDRESS+0x1B9) |
| 227 | #define WCD937X_EAR_INT_NEW_EAR_DYNAMIC_BIAS (WCD937X_BASE_ADDRESS+0x1BA) |
| 228 | #define WCD937X_AUX_INT_EN_REG (WCD937X_BASE_ADDRESS+0x1BD) |
| 229 | #define WCD937X_AUX_INT_PA_CTRL (WCD937X_BASE_ADDRESS+0x1BE) |
| 230 | #define WCD937X_AUX_INT_SP_CTRL (WCD937X_BASE_ADDRESS+0x1BF) |
| 231 | #define WCD937X_AUX_INT_DAC_CTRL (WCD937X_BASE_ADDRESS+0x1C0) |
| 232 | #define WCD937X_AUX_INT_CLK_CTRL (WCD937X_BASE_ADDRESS+0x1C1) |
| 233 | #define WCD937X_AUX_INT_TEST_CTRL (WCD937X_BASE_ADDRESS+0x1C2) |
| 234 | #define WCD937X_AUX_INT_STATUS_REG (WCD937X_BASE_ADDRESS+0x1C3) |
| 235 | #define WCD937X_AUX_INT_MISC (WCD937X_BASE_ADDRESS+0x1C4) |
| 236 | #define WCD937X_LDORXTX_INT_BIAS (WCD937X_BASE_ADDRESS+0x1C5) |
| 237 | #define WCD937X_LDORXTX_INT_STB_LOADS_DTEST (WCD937X_BASE_ADDRESS+0x1C6) |
| 238 | #define WCD937X_LDORXTX_INT_TEST0 (WCD937X_BASE_ADDRESS+0x1C7) |
| 239 | #define WCD937X_LDORXTX_INT_STARTUP_TIMER (WCD937X_BASE_ADDRESS+0x1C8) |
| 240 | #define WCD937X_LDORXTX_INT_TEST1 (WCD937X_BASE_ADDRESS+0x1C9) |
| 241 | #define WCD937X_LDORXTX_INT_STATUS (WCD937X_BASE_ADDRESS+0x1CA) |
| 242 | #define WCD937X_SLEEP_INT_WATCHDOG_CTL_1 (WCD937X_BASE_ADDRESS+0x1D0) |
| 243 | #define WCD937X_SLEEP_INT_WATCHDOG_CTL_2 (WCD937X_BASE_ADDRESS+0x1D1) |
| 244 | #define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT1 (WCD937X_BASE_ADDRESS+0x1D3) |
| 245 | #define WCD937X_DIE_CRACK_INT_DIE_CRK_DET_INT2 (WCD937X_BASE_ADDRESS+0x1D4) |
| 246 | #define WCD937X_DIGITAL_PAGE_REGISTER (WCD937X_BASE_ADDRESS+0x400) |
| 247 | #define WCD937X_DIGITAL_CHIP_ID0 (WCD937X_BASE_ADDRESS+0x401) |
| 248 | #define WCD937X_DIGITAL_CHIP_ID1 (WCD937X_BASE_ADDRESS+0x402) |
| 249 | #define WCD937X_DIGITAL_CHIP_ID2 (WCD937X_BASE_ADDRESS+0x403) |
| 250 | #define WCD937X_DIGITAL_CHIP_ID3 (WCD937X_BASE_ADDRESS+0x404) |
| 251 | #define WCD937X_DIGITAL_CDC_RST_CTL (WCD937X_BASE_ADDRESS+0x406) |
| 252 | #define WCD937X_DIGITAL_TOP_CLK_CFG (WCD937X_BASE_ADDRESS+0x407) |
| 253 | #define WCD937X_DIGITAL_CDC_ANA_CLK_CTL (WCD937X_BASE_ADDRESS+0x408) |
| 254 | #define WCD937X_DIGITAL_CDC_DIG_CLK_CTL (WCD937X_BASE_ADDRESS+0x409) |
| 255 | #define WCD937X_DIGITAL_SWR_RST_EN (WCD937X_BASE_ADDRESS+0x40A) |
| 256 | #define WCD937X_DIGITAL_CDC_PATH_MODE (WCD937X_BASE_ADDRESS+0x40B) |
| 257 | #define WCD937X_DIGITAL_CDC_RX_RST (WCD937X_BASE_ADDRESS+0x40C) |
| 258 | #define WCD937X_DIGITAL_CDC_RX0_CTL (WCD937X_BASE_ADDRESS+0x40D) |
| 259 | #define WCD937X_DIGITAL_CDC_RX1_CTL (WCD937X_BASE_ADDRESS+0x40E) |
| 260 | #define WCD937X_DIGITAL_CDC_RX2_CTL (WCD937X_BASE_ADDRESS+0x40F) |
| 261 | #define WCD937X_DIGITAL_DEM_BYPASS_DATA0 (WCD937X_BASE_ADDRESS+0x410) |
| 262 | #define WCD937X_DIGITAL_DEM_BYPASS_DATA1 (WCD937X_BASE_ADDRESS+0x411) |
| 263 | #define WCD937X_DIGITAL_DEM_BYPASS_DATA2 (WCD937X_BASE_ADDRESS+0x412) |
| 264 | #define WCD937X_DIGITAL_DEM_BYPASS_DATA3 (WCD937X_BASE_ADDRESS+0x413) |
| 265 | #define WCD937X_DIGITAL_CDC_COMP_CTL_0 (WCD937X_BASE_ADDRESS+0x414) |
| 266 | #define WCD937X_DIGITAL_CDC_RX_DELAY_CTL (WCD937X_BASE_ADDRESS+0x417) |
| 267 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A1_0 (WCD937X_BASE_ADDRESS+0x418) |
| 268 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A1_1 (WCD937X_BASE_ADDRESS+0x419) |
| 269 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A2_0 (WCD937X_BASE_ADDRESS+0x41A) |
| 270 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A2_1 (WCD937X_BASE_ADDRESS+0x41B) |
| 271 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A3_0 (WCD937X_BASE_ADDRESS+0x41C) |
| 272 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A3_1 (WCD937X_BASE_ADDRESS+0x41D) |
| 273 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A4_0 (WCD937X_BASE_ADDRESS+0x41E) |
| 274 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A4_1 (WCD937X_BASE_ADDRESS+0x41F) |
| 275 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A5_0 (WCD937X_BASE_ADDRESS+0x420) |
| 276 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A5_1 (WCD937X_BASE_ADDRESS+0x421) |
| 277 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A6_0 (WCD937X_BASE_ADDRESS+0x422) |
| 278 | #define WCD937X_DIGITAL_CDC_HPH_DSM_A7_0 (WCD937X_BASE_ADDRESS+0x423) |
| 279 | #define WCD937X_DIGITAL_CDC_HPH_DSM_C_0 (WCD937X_BASE_ADDRESS+0x424) |
| 280 | #define WCD937X_DIGITAL_CDC_HPH_DSM_C_1 (WCD937X_BASE_ADDRESS+0x425) |
| 281 | #define WCD937X_DIGITAL_CDC_HPH_DSM_C_2 (WCD937X_BASE_ADDRESS+0x426) |
| 282 | #define WCD937X_DIGITAL_CDC_HPH_DSM_C_3 (WCD937X_BASE_ADDRESS+0x427) |
| 283 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R1 (WCD937X_BASE_ADDRESS+0x428) |
| 284 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R2 (WCD937X_BASE_ADDRESS+0x429) |
| 285 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R3 (WCD937X_BASE_ADDRESS+0x42A) |
| 286 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R4 (WCD937X_BASE_ADDRESS+0x42B) |
| 287 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R5 (WCD937X_BASE_ADDRESS+0x42C) |
| 288 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R6 (WCD937X_BASE_ADDRESS+0x42D) |
| 289 | #define WCD937X_DIGITAL_CDC_HPH_DSM_R7 (WCD937X_BASE_ADDRESS+0x42E) |
| 290 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A1_0 (WCD937X_BASE_ADDRESS+0x42F) |
| 291 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A1_1 (WCD937X_BASE_ADDRESS+0x430) |
| 292 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A2_0 (WCD937X_BASE_ADDRESS+0x431) |
| 293 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A2_1 (WCD937X_BASE_ADDRESS+0x432) |
| 294 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A3_0 (WCD937X_BASE_ADDRESS+0x433) |
| 295 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A3_1 (WCD937X_BASE_ADDRESS+0x434) |
| 296 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A4_0 (WCD937X_BASE_ADDRESS+0x435) |
| 297 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A4_1 (WCD937X_BASE_ADDRESS+0x436) |
| 298 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A5_0 (WCD937X_BASE_ADDRESS+0x437) |
| 299 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A5_1 (WCD937X_BASE_ADDRESS+0x438) |
| 300 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A6_0 (WCD937X_BASE_ADDRESS+0x439) |
| 301 | #define WCD937X_DIGITAL_CDC_AUX_DSM_A7_0 (WCD937X_BASE_ADDRESS+0x43A) |
| 302 | #define WCD937X_DIGITAL_CDC_AUX_DSM_C_0 (WCD937X_BASE_ADDRESS+0x43B) |
| 303 | #define WCD937X_DIGITAL_CDC_AUX_DSM_C_1 (WCD937X_BASE_ADDRESS+0x43C) |
| 304 | #define WCD937X_DIGITAL_CDC_AUX_DSM_C_2 (WCD937X_BASE_ADDRESS+0x43D) |
| 305 | #define WCD937X_DIGITAL_CDC_AUX_DSM_C_3 (WCD937X_BASE_ADDRESS+0x43E) |
| 306 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R1 (WCD937X_BASE_ADDRESS+0x43F) |
| 307 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R2 (WCD937X_BASE_ADDRESS+0x440) |
| 308 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R3 (WCD937X_BASE_ADDRESS+0x441) |
| 309 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R4 (WCD937X_BASE_ADDRESS+0x442) |
| 310 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R5 (WCD937X_BASE_ADDRESS+0x443) |
| 311 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R6 (WCD937X_BASE_ADDRESS+0x444) |
| 312 | #define WCD937X_DIGITAL_CDC_AUX_DSM_R7 (WCD937X_BASE_ADDRESS+0x445) |
| 313 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_0 (WCD937X_BASE_ADDRESS+0x446) |
| 314 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_RX_1 (WCD937X_BASE_ADDRESS+0x447) |
| 315 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_0 (WCD937X_BASE_ADDRESS+0x448) |
| 316 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_1 (WCD937X_BASE_ADDRESS+0x449) |
| 317 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_DSD_2 (WCD937X_BASE_ADDRESS+0x44A) |
| 318 | #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_0 (WCD937X_BASE_ADDRESS+0x44B) |
| 319 | #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_1 (WCD937X_BASE_ADDRESS+0x44C) |
| 320 | #define WCD937X_DIGITAL_CDC_AUX_GAIN_DSD_2 (WCD937X_BASE_ADDRESS+0x44D) |
| 321 | #define WCD937X_DIGITAL_CDC_HPH_GAIN_CTL (WCD937X_BASE_ADDRESS+0x44E) |
| 322 | #define WCD937X_DIGITAL_CDC_AUX_GAIN_CTL (WCD937X_BASE_ADDRESS+0x44F) |
| 323 | #define WCD937X_DIGITAL_CDC_EAR_PATH_CTL (WCD937X_BASE_ADDRESS+0x450) |
| 324 | #define WCD937X_DIGITAL_CDC_SWR_CLH (WCD937X_BASE_ADDRESS+0x451) |
| 325 | #define WCD937X_DIGITAL_SWR_CLH_BYP (WCD937X_BASE_ADDRESS+0x452) |
| 326 | #define WCD937X_DIGITAL_CDC_TX0_CTL (WCD937X_BASE_ADDRESS+0x453) |
| 327 | #define WCD937X_DIGITAL_CDC_TX1_CTL (WCD937X_BASE_ADDRESS+0x454) |
| 328 | #define WCD937X_DIGITAL_CDC_TX2_CTL (WCD937X_BASE_ADDRESS+0x455) |
| 329 | #define WCD937X_DIGITAL_CDC_TX_RST (WCD937X_BASE_ADDRESS+0x456) |
| 330 | #define WCD937X_DIGITAL_CDC_REQ_CTL (WCD937X_BASE_ADDRESS+0x457) |
| 331 | #define WCD937X_DIGITAL_CDC_AMIC_CTL (WCD937X_BASE_ADDRESS+0x45A) |
| 332 | #define WCD937X_DIGITAL_CDC_DMIC_CTL (WCD937X_BASE_ADDRESS+0x45B) |
| Tanya Dixit | 46ec0f2 | 2018-10-16 14:48:37 +0530 | [diff] [blame] | 333 | #define WCD937X_DIGITAL_CDC_DMIC1_CTL (WCD937X_BASE_ADDRESS+0x45C) |
| 334 | #define WCD937X_DIGITAL_CDC_DMIC2_CTL (WCD937X_BASE_ADDRESS+0x45D) |
| 335 | #define WCD937X_DIGITAL_CDC_DMIC3_CTL (WCD937X_BASE_ADDRESS+0x45E) |
| Tanya Dixit | 9b37ac9 | 2018-07-27 16:52:47 +0530 | [diff] [blame] | 336 | #define WCD937X_DIGITAL_EFUSE_CTL (WCD937X_BASE_ADDRESS+0x45F) |
| 337 | #define WCD937X_DIGITAL_EFUSE_PRG_CTL (WCD937X_BASE_ADDRESS+0x460) |
| 338 | #define WCD937X_DIGITAL_EFUSE_TEST_CTL_0 (WCD937X_BASE_ADDRESS+0x461) |
| 339 | #define WCD937X_DIGITAL_EFUSE_TEST_CTL_1 (WCD937X_BASE_ADDRESS+0x462) |
| 340 | #define WCD937X_DIGITAL_EFUSE_T_DATA_0 (WCD937X_BASE_ADDRESS+0x463) |
| 341 | #define WCD937X_DIGITAL_EFUSE_T_DATA_1 (WCD937X_BASE_ADDRESS+0x464) |
| 342 | #define WCD937X_DIGITAL_PDM_WD_CTL0 (WCD937X_BASE_ADDRESS+0x465) |
| 343 | #define WCD937X_DIGITAL_PDM_WD_CTL1 (WCD937X_BASE_ADDRESS+0x466) |
| 344 | #define WCD937X_DIGITAL_PDM_WD_CTL2 (WCD937X_BASE_ADDRESS+0x467) |
| 345 | #define WCD937X_DIGITAL_INTR_MODE (WCD937X_BASE_ADDRESS+0x46A) |
| 346 | #define WCD937X_DIGITAL_INTR_MASK_0 (WCD937X_BASE_ADDRESS+0x46B) |
| 347 | #define WCD937X_DIGITAL_INTR_MASK_1 (WCD937X_BASE_ADDRESS+0x46C) |
| 348 | #define WCD937X_DIGITAL_INTR_MASK_2 (WCD937X_BASE_ADDRESS+0x46D) |
| 349 | #define WCD937X_DIGITAL_INTR_STATUS_0 (WCD937X_BASE_ADDRESS+0x46E) |
| 350 | #define WCD937X_DIGITAL_INTR_STATUS_1 (WCD937X_BASE_ADDRESS+0x46F) |
| 351 | #define WCD937X_DIGITAL_INTR_STATUS_2 (WCD937X_BASE_ADDRESS+0x470) |
| 352 | #define WCD937X_DIGITAL_INTR_CLEAR_0 (WCD937X_BASE_ADDRESS+0x471) |
| 353 | #define WCD937X_DIGITAL_INTR_CLEAR_1 (WCD937X_BASE_ADDRESS+0x472) |
| 354 | #define WCD937X_DIGITAL_INTR_CLEAR_2 (WCD937X_BASE_ADDRESS+0x473) |
| 355 | #define WCD937X_DIGITAL_INTR_LEVEL_0 (WCD937X_BASE_ADDRESS+0x474) |
| 356 | #define WCD937X_DIGITAL_INTR_LEVEL_1 (WCD937X_BASE_ADDRESS+0x475) |
| 357 | #define WCD937X_DIGITAL_INTR_LEVEL_2 (WCD937X_BASE_ADDRESS+0x476) |
| 358 | #define WCD937X_DIGITAL_INTR_SET_0 (WCD937X_BASE_ADDRESS+0x477) |
| 359 | #define WCD937X_DIGITAL_INTR_SET_1 (WCD937X_BASE_ADDRESS+0x478) |
| 360 | #define WCD937X_DIGITAL_INTR_SET_2 (WCD937X_BASE_ADDRESS+0x479) |
| 361 | #define WCD937X_DIGITAL_INTR_TEST_0 (WCD937X_BASE_ADDRESS+0x47A) |
| 362 | #define WCD937X_DIGITAL_INTR_TEST_1 (WCD937X_BASE_ADDRESS+0x47B) |
| 363 | #define WCD937X_DIGITAL_INTR_TEST_2 (WCD937X_BASE_ADDRESS+0x47C) |
| 364 | #define WCD937X_DIGITAL_CDC_CONN_RX0_CTL (WCD937X_BASE_ADDRESS+0x47F) |
| 365 | #define WCD937X_DIGITAL_CDC_CONN_RX1_CTL (WCD937X_BASE_ADDRESS+0x480) |
| 366 | #define WCD937X_DIGITAL_CDC_CONN_RX2_CTL (WCD937X_BASE_ADDRESS+0x481) |
| 367 | #define WCD937X_DIGITAL_CDC_CONN_TX_CTL (WCD937X_BASE_ADDRESS+0x482) |
| 368 | #define WCD937X_DIGITAL_LOOP_BACK_MODE (WCD937X_BASE_ADDRESS+0x483) |
| 369 | #define WCD937X_DIGITAL_SWR_DAC_TEST (WCD937X_BASE_ADDRESS+0x484) |
| 370 | #define WCD937X_DIGITAL_SWR_HM_TEST_RX_0 (WCD937X_BASE_ADDRESS+0x485) |
| 371 | #define WCD937X_DIGITAL_SWR_HM_TEST_TX_0 (WCD937X_BASE_ADDRESS+0x491) |
| 372 | #define WCD937X_DIGITAL_SWR_HM_TEST_RX_1 (WCD937X_BASE_ADDRESS+0x492) |
| 373 | #define WCD937X_DIGITAL_SWR_HM_TEST_TX_1 (WCD937X_BASE_ADDRESS+0x493) |
| 374 | #define WCD937X_DIGITAL_SWR_HM_TEST (WCD937X_BASE_ADDRESS+0x494) |
| 375 | #define WCD937X_DIGITAL_PAD_CTL_PDM_RX0 (WCD937X_BASE_ADDRESS+0x495) |
| 376 | #define WCD937X_DIGITAL_PAD_CTL_PDM_RX1 (WCD937X_BASE_ADDRESS+0x496) |
| Tanya Dixit | 46ec0f2 | 2018-10-16 14:48:37 +0530 | [diff] [blame] | 377 | #define WCD937X_DIGITAL_PAD_CTL_PDM_TX0 (WCD937X_BASE_ADDRESS+0x497) |
| 378 | #define WCD937X_DIGITAL_PAD_CTL_PDM_TX1 (WCD937X_BASE_ADDRESS+0x498) |
| Tanya Dixit | 9b37ac9 | 2018-07-27 16:52:47 +0530 | [diff] [blame] | 379 | #define WCD937X_DIGITAL_PAD_INP_DIS_0 (WCD937X_BASE_ADDRESS+0x499) |
| 380 | #define WCD937X_DIGITAL_PAD_INP_DIS_1 (WCD937X_BASE_ADDRESS+0x49A) |
| 381 | #define WCD937X_DIGITAL_DRIVE_STRENGTH_0 (WCD937X_BASE_ADDRESS+0x49B) |
| 382 | #define WCD937X_DIGITAL_DRIVE_STRENGTH_1 (WCD937X_BASE_ADDRESS+0x49C) |
| 383 | #define WCD937X_DIGITAL_DRIVE_STRENGTH_2 (WCD937X_BASE_ADDRESS+0x49D) |
| 384 | #define WCD937X_DIGITAL_RX_DATA_EDGE_CTL (WCD937X_BASE_ADDRESS+0x49E) |
| 385 | #define WCD937X_DIGITAL_TX_DATA_EDGE_CTL (WCD937X_BASE_ADDRESS+0x49F) |
| 386 | #define WCD937X_DIGITAL_GPIO_MODE (WCD937X_BASE_ADDRESS+0x4A0) |
| 387 | #define WCD937X_DIGITAL_PIN_CTL_OE (WCD937X_BASE_ADDRESS+0x4A1) |
| 388 | #define WCD937X_DIGITAL_PIN_CTL_DATA_0 (WCD937X_BASE_ADDRESS+0x4A2) |
| 389 | #define WCD937X_DIGITAL_PIN_CTL_DATA_1 (WCD937X_BASE_ADDRESS+0x4A3) |
| 390 | #define WCD937X_DIGITAL_PIN_STATUS_0 (WCD937X_BASE_ADDRESS+0x4A4) |
| 391 | #define WCD937X_DIGITAL_PIN_STATUS_1 (WCD937X_BASE_ADDRESS+0x4A5) |
| 392 | #define WCD937X_DIGITAL_DIG_DEBUG_CTL (WCD937X_BASE_ADDRESS+0x4A6) |
| 393 | #define WCD937X_DIGITAL_DIG_DEBUG_EN (WCD937X_BASE_ADDRESS+0x4A7) |
| 394 | #define WCD937X_DIGITAL_ANA_CSR_DBG_ADD (WCD937X_BASE_ADDRESS+0x4A8) |
| 395 | #define WCD937X_DIGITAL_ANA_CSR_DBG_CTL (WCD937X_BASE_ADDRESS+0x4A9) |
| 396 | #define WCD937X_DIGITAL_SSP_DBG (WCD937X_BASE_ADDRESS+0x4AA) |
| 397 | #define WCD937X_DIGITAL_MODE_STATUS_0 (WCD937X_BASE_ADDRESS+0x4AB) |
| 398 | #define WCD937X_DIGITAL_MODE_STATUS_1 (WCD937X_BASE_ADDRESS+0x4AC) |
| 399 | #define WCD937X_DIGITAL_SPARE_0 (WCD937X_BASE_ADDRESS+0x4AD) |
| 400 | #define WCD937X_DIGITAL_SPARE_1 (WCD937X_BASE_ADDRESS+0x4AE) |
| 401 | #define WCD937X_DIGITAL_SPARE_2 (WCD937X_BASE_ADDRESS+0x4AF) |
| 402 | #define WCD937X_DIGITAL_EFUSE_REG_0 (WCD937X_BASE_ADDRESS+0x4B0) |
| 403 | #define WCD937X_DIGITAL_EFUSE_REG_1 (WCD937X_BASE_ADDRESS+0x4B1) |
| 404 | #define WCD937X_DIGITAL_EFUSE_REG_2 (WCD937X_BASE_ADDRESS+0x4B2) |
| 405 | #define WCD937X_DIGITAL_EFUSE_REG_3 (WCD937X_BASE_ADDRESS+0x4B3) |
| 406 | #define WCD937X_DIGITAL_EFUSE_REG_4 (WCD937X_BASE_ADDRESS+0x4B4) |
| 407 | #define WCD937X_DIGITAL_EFUSE_REG_5 (WCD937X_BASE_ADDRESS+0x4B5) |
| 408 | #define WCD937X_DIGITAL_EFUSE_REG_6 (WCD937X_BASE_ADDRESS+0x4B6) |
| 409 | #define WCD937X_DIGITAL_EFUSE_REG_7 (WCD937X_BASE_ADDRESS+0x4B7) |
| 410 | #define WCD937X_DIGITAL_EFUSE_REG_8 (WCD937X_BASE_ADDRESS+0x4B8) |
| 411 | #define WCD937X_DIGITAL_EFUSE_REG_9 (WCD937X_BASE_ADDRESS+0x4B9) |
| 412 | #define WCD937X_DIGITAL_EFUSE_REG_10 (WCD937X_BASE_ADDRESS+0x4BA) |
| 413 | #define WCD937X_DIGITAL_EFUSE_REG_11 (WCD937X_BASE_ADDRESS+0x4BB) |
| 414 | #define WCD937X_DIGITAL_EFUSE_REG_12 (WCD937X_BASE_ADDRESS+0x4BC) |
| 415 | #define WCD937X_DIGITAL_EFUSE_REG_13 (WCD937X_BASE_ADDRESS+0x4BD) |
| 416 | #define WCD937X_DIGITAL_EFUSE_REG_14 (WCD937X_BASE_ADDRESS+0x4BE) |
| 417 | #define WCD937X_DIGITAL_EFUSE_REG_15 (WCD937X_BASE_ADDRESS+0x4BF) |
| 418 | #define WCD937X_DIGITAL_EFUSE_REG_16 (WCD937X_BASE_ADDRESS+0x4C0) |
| 419 | #define WCD937X_DIGITAL_EFUSE_REG_17 (WCD937X_BASE_ADDRESS+0x4C1) |
| 420 | #define WCD937X_DIGITAL_EFUSE_REG_18 (WCD937X_BASE_ADDRESS+0x4C2) |
| 421 | #define WCD937X_DIGITAL_EFUSE_REG_19 (WCD937X_BASE_ADDRESS+0x4C3) |
| 422 | #define WCD937X_DIGITAL_EFUSE_REG_20 (WCD937X_BASE_ADDRESS+0x4C4) |
| 423 | #define WCD937X_DIGITAL_EFUSE_REG_21 (WCD937X_BASE_ADDRESS+0x4C5) |
| 424 | #define WCD937X_DIGITAL_EFUSE_REG_22 (WCD937X_BASE_ADDRESS+0x4C6) |
| 425 | #define WCD937X_DIGITAL_EFUSE_REG_23 (WCD937X_BASE_ADDRESS+0x4C7) |
| 426 | #define WCD937X_DIGITAL_EFUSE_REG_24 (WCD937X_BASE_ADDRESS+0x4C8) |
| 427 | #define WCD937X_DIGITAL_EFUSE_REG_25 (WCD937X_BASE_ADDRESS+0x4C9) |
| 428 | #define WCD937X_DIGITAL_EFUSE_REG_26 (WCD937X_BASE_ADDRESS+0x4CA) |
| 429 | #define WCD937X_DIGITAL_EFUSE_REG_27 (WCD937X_BASE_ADDRESS+0x4CB) |
| 430 | #define WCD937X_DIGITAL_EFUSE_REG_28 (WCD937X_BASE_ADDRESS+0x4CC) |
| 431 | #define WCD937X_DIGITAL_EFUSE_REG_29 (WCD937X_BASE_ADDRESS+0x4CD) |
| 432 | #define WCD937X_DIGITAL_EFUSE_REG_30 (WCD937X_BASE_ADDRESS+0x4CE) |
| 433 | #define WCD937X_DIGITAL_EFUSE_REG_31 (WCD937X_BASE_ADDRESS+0x4CF) |
| 434 | |
| 435 | #define WCD937X_REGISTERS_MAX_SIZE (WCD937X_BASE_ADDRESS+0x4D0) |
| 436 | #define WCD937X_MAX_REGISTER (WCD937X_REGISTERS_MAX_SIZE - 1) |
| 437 | |
| 438 | #endif |