Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/io.h> |
| 8 | #include <linux/platform_device.h> |
| 9 | #include <linux/clk.h> |
| 10 | #include <sound/soc.h> |
| 11 | #include <sound/pcm.h> |
| 12 | #include <sound/pcm_params.h> |
| 13 | #include <sound/soc-dapm.h> |
| 14 | #include <sound/tlv.h> |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 15 | #include <soc/swr-common.h> |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 16 | #include <soc/swr-wcd.h> |
| 17 | |
Meng Wang | 11a25cf | 2018-10-31 14:11:26 +0800 | [diff] [blame] | 18 | #include <asoc/msm-cdc-pinctrl.h> |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 19 | #include "bolero-cdc.h" |
| 20 | #include "bolero-cdc-registers.h" |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 21 | #include "bolero-clk-rsc.h" |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 22 | |
| 23 | #define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 24 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 25 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ |
| 26 | SNDRV_PCM_RATE_384000) |
| 27 | /* Fractional Rates */ |
| 28 | #define RX_MACRO_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\ |
| 29 | SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800) |
| 30 | |
| 31 | #define RX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 32 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 33 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 34 | |
| 35 | #define RX_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 36 | SNDRV_PCM_RATE_48000) |
| 37 | #define RX_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 38 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 39 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 40 | |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 41 | #define SAMPLING_RATE_44P1KHZ 44100 |
| 42 | #define SAMPLING_RATE_88P2KHZ 88200 |
| 43 | #define SAMPLING_RATE_176P4KHZ 176400 |
| 44 | #define SAMPLING_RATE_352P8KHZ 352800 |
| 45 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 46 | #define RX_MACRO_MAX_OFFSET 0x1000 |
| 47 | |
| 48 | #define RX_MACRO_MAX_DMA_CH_PER_PORT 2 |
| 49 | #define RX_SWR_STRING_LEN 80 |
| 50 | #define RX_MACRO_CHILD_DEVICES_MAX 3 |
| 51 | |
| 52 | #define RX_MACRO_INTERP_MUX_NUM_INPUTS 3 |
| 53 | #define RX_MACRO_SIDETONE_IIR_COEFF_MAX 5 |
| 54 | |
| 55 | #define STRING(name) #name |
| 56 | #define RX_MACRO_DAPM_ENUM(name, reg, offset, text) \ |
| 57 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 58 | static const struct snd_kcontrol_new name##_mux = \ |
| 59 | SOC_DAPM_ENUM(STRING(name), name##_enum) |
| 60 | |
| 61 | #define RX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \ |
| 62 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 63 | static const struct snd_kcontrol_new name##_mux = \ |
| 64 | SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname) |
| 65 | |
| 66 | #define RX_MACRO_DAPM_MUX(name, shift, kctl) \ |
| 67 | SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux) |
| 68 | |
| 69 | #define RX_MACRO_RX_PATH_OFFSET 0x80 |
| 70 | #define RX_MACRO_COMP_OFFSET 0x40 |
| 71 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 72 | #define MAX_IMPED_PARAMS 6 |
| 73 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 74 | #define RX_MACRO_EC_MIX_TX0_MASK 0xf0 |
| 75 | #define RX_MACRO_EC_MIX_TX1_MASK 0x0f |
| 76 | #define RX_MACRO_EC_MIX_TX2_MASK 0x0f |
| 77 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 78 | struct wcd_imped_val { |
| 79 | u32 imped_val; |
| 80 | u8 index; |
| 81 | }; |
| 82 | |
| 83 | static const struct wcd_imped_val imped_index[] = { |
| 84 | {4, 0}, |
| 85 | {5, 1}, |
| 86 | {6, 2}, |
| 87 | {7, 3}, |
| 88 | {8, 4}, |
| 89 | {9, 5}, |
| 90 | {10, 6}, |
| 91 | {11, 7}, |
| 92 | {12, 8}, |
| 93 | {13, 9}, |
| 94 | }; |
| 95 | |
| 96 | struct rx_macro_reg_mask_val { |
| 97 | u16 reg; |
| 98 | u8 mask; |
| 99 | u8 val; |
| 100 | }; |
| 101 | |
| 102 | static const struct rx_macro_reg_mask_val imped_table[][MAX_IMPED_PARAMS] = { |
| 103 | { |
| 104 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xf2}, |
| 105 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xf2}, |
| 106 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 107 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xf2}, |
| 108 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xf2}, |
| 109 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 110 | }, |
| 111 | { |
| 112 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xf4}, |
| 113 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xf4}, |
| 114 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 115 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xf4}, |
| 116 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xf4}, |
| 117 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 118 | }, |
| 119 | { |
| 120 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xf7}, |
| 121 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xf7}, |
| 122 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x01}, |
| 123 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xf7}, |
| 124 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xf7}, |
| 125 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x01}, |
| 126 | }, |
| 127 | { |
| 128 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xf9}, |
| 129 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xf9}, |
| 130 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 131 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xf9}, |
| 132 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xf9}, |
| 133 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 134 | }, |
| 135 | { |
| 136 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xfa}, |
| 137 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xfa}, |
| 138 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 139 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xfa}, |
| 140 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xfa}, |
| 141 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 142 | }, |
| 143 | { |
| 144 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xfb}, |
| 145 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xfb}, |
| 146 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 147 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xfb}, |
| 148 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xfb}, |
| 149 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 150 | }, |
| 151 | { |
| 152 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xfc}, |
| 153 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xfc}, |
| 154 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 155 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xfc}, |
| 156 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xfc}, |
| 157 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 158 | }, |
| 159 | { |
| 160 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xfd}, |
| 161 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xfd}, |
| 162 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x00}, |
| 163 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xfd}, |
| 164 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd}, |
| 165 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x00}, |
| 166 | }, |
| 167 | { |
| 168 | {BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0xff, 0xfd}, |
| 169 | {BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0xff, 0xfd}, |
| 170 | {BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x01, 0x01}, |
| 171 | {BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0xff, 0xfd}, |
| 172 | {BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0xff, 0xfd}, |
| 173 | {BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x01, 0x01}, |
| 174 | }, |
| 175 | }; |
| 176 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 177 | enum { |
| 178 | INTERP_HPHL, |
| 179 | INTERP_HPHR, |
| 180 | INTERP_AUX, |
| 181 | INTERP_MAX |
| 182 | }; |
| 183 | |
| 184 | enum { |
| 185 | RX_MACRO_RX0, |
| 186 | RX_MACRO_RX1, |
| 187 | RX_MACRO_RX2, |
| 188 | RX_MACRO_RX3, |
| 189 | RX_MACRO_RX4, |
| 190 | RX_MACRO_RX5, |
| 191 | RX_MACRO_PORTS_MAX |
| 192 | }; |
| 193 | |
| 194 | enum { |
| 195 | RX_MACRO_COMP1, /* HPH_L */ |
| 196 | RX_MACRO_COMP2, /* HPH_R */ |
| 197 | RX_MACRO_COMP_MAX |
| 198 | }; |
| 199 | |
| 200 | enum { |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 201 | RX_MACRO_EC0_MUX = 0, |
| 202 | RX_MACRO_EC1_MUX, |
| 203 | RX_MACRO_EC2_MUX, |
| 204 | RX_MACRO_EC_MUX_MAX, |
| 205 | }; |
| 206 | |
| 207 | enum { |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 208 | INTn_1_INP_SEL_ZERO = 0, |
| 209 | INTn_1_INP_SEL_DEC0, |
| 210 | INTn_1_INP_SEL_DEC1, |
| 211 | INTn_1_INP_SEL_IIR0, |
| 212 | INTn_1_INP_SEL_IIR1, |
| 213 | INTn_1_INP_SEL_RX0, |
| 214 | INTn_1_INP_SEL_RX1, |
| 215 | INTn_1_INP_SEL_RX2, |
| 216 | INTn_1_INP_SEL_RX3, |
| 217 | INTn_1_INP_SEL_RX4, |
| 218 | INTn_1_INP_SEL_RX5, |
| 219 | }; |
| 220 | |
| 221 | enum { |
| 222 | INTn_2_INP_SEL_ZERO = 0, |
| 223 | INTn_2_INP_SEL_RX0, |
| 224 | INTn_2_INP_SEL_RX1, |
| 225 | INTn_2_INP_SEL_RX2, |
| 226 | INTn_2_INP_SEL_RX3, |
| 227 | INTn_2_INP_SEL_RX4, |
| 228 | INTn_2_INP_SEL_RX5, |
| 229 | }; |
| 230 | |
| 231 | enum { |
| 232 | INTERP_MAIN_PATH, |
| 233 | INTERP_MIX_PATH, |
| 234 | }; |
| 235 | |
| 236 | /* Codec supports 2 IIR filters */ |
| 237 | enum { |
| 238 | IIR0 = 0, |
| 239 | IIR1, |
| 240 | IIR_MAX, |
| 241 | }; |
| 242 | |
| 243 | /* Each IIR has 5 Filter Stages */ |
| 244 | enum { |
| 245 | BAND1 = 0, |
| 246 | BAND2, |
| 247 | BAND3, |
| 248 | BAND4, |
| 249 | BAND5, |
| 250 | BAND_MAX, |
| 251 | }; |
| 252 | |
| 253 | struct rx_macro_idle_detect_config { |
| 254 | u8 hph_idle_thr; |
| 255 | u8 hph_idle_detect_en; |
| 256 | }; |
| 257 | |
| 258 | struct interp_sample_rate { |
| 259 | int sample_rate; |
| 260 | int rate_val; |
| 261 | }; |
| 262 | |
| 263 | static struct interp_sample_rate sr_val_tbl[] = { |
| 264 | {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, |
| 265 | {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA}, |
| 266 | {176400, 0xB}, {352800, 0xC}, |
| 267 | }; |
| 268 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 269 | struct rx_macro_bcl_pmic_params { |
| 270 | u8 id; |
| 271 | u8 sid; |
| 272 | u8 ppid; |
| 273 | }; |
| 274 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 275 | static int rx_macro_hw_params(struct snd_pcm_substream *substream, |
| 276 | struct snd_pcm_hw_params *params, |
| 277 | struct snd_soc_dai *dai); |
| 278 | static int rx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 279 | unsigned int *tx_num, unsigned int *tx_slot, |
| 280 | unsigned int *rx_num, unsigned int *rx_slot); |
| 281 | static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, |
| 282 | struct snd_ctl_elem_value *ucontrol); |
| 283 | static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, |
| 284 | struct snd_ctl_elem_value *ucontrol); |
| 285 | static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, |
| 286 | struct snd_ctl_elem_value *ucontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 287 | static int rx_macro_enable_interp_clk(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 288 | int event, int interp_idx); |
| 289 | |
| 290 | /* Hold instance to soundwire platform device */ |
| 291 | struct rx_swr_ctrl_data { |
| 292 | struct platform_device *rx_swr_pdev; |
| 293 | }; |
| 294 | |
| 295 | struct rx_swr_ctrl_platform_data { |
| 296 | void *handle; /* holds codec private data */ |
| 297 | int (*read)(void *handle, int reg); |
| 298 | int (*write)(void *handle, int reg, int val); |
| 299 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 300 | int (*clk)(void *handle, bool enable); |
| 301 | int (*handle_irq)(void *handle, |
| 302 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 303 | void *data), |
| 304 | void *swrm_handle, |
| 305 | int action); |
| 306 | }; |
| 307 | |
| 308 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 309 | RX_MACRO_AIF_INVALID = 0, |
| 310 | RX_MACRO_AIF1_PB, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 311 | RX_MACRO_AIF2_PB, |
| 312 | RX_MACRO_AIF3_PB, |
| 313 | RX_MACRO_AIF4_PB, |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 314 | RX_MACRO_AIF_ECHO, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 315 | RX_MACRO_MAX_DAIS, |
| 316 | }; |
| 317 | |
| 318 | enum { |
| 319 | RX_MACRO_AIF1_CAP = 0, |
| 320 | RX_MACRO_AIF2_CAP, |
| 321 | RX_MACRO_AIF3_CAP, |
| 322 | RX_MACRO_MAX_AIF_CAP_DAIS |
| 323 | }; |
| 324 | /* |
| 325 | * @dev: rx macro device pointer |
| 326 | * @comp_enabled: compander enable mixer value set |
| 327 | * @prim_int_users: Users of interpolator |
| 328 | * @rx_mclk_users: RX MCLK users count |
| 329 | * @vi_feed_value: VI sense mask |
| 330 | * @swr_clk_lock: to lock swr master clock operations |
| 331 | * @swr_ctrl_data: SoundWire data structure |
| 332 | * @swr_plat_data: Soundwire platform data |
| 333 | * @rx_macro_add_child_devices_work: work for adding child devices |
| 334 | * @rx_swr_gpio_p: used by pinctrl API |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 335 | * @component: codec handle |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 336 | */ |
| 337 | struct rx_macro_priv { |
| 338 | struct device *dev; |
| 339 | int comp_enabled[RX_MACRO_COMP_MAX]; |
| 340 | /* Main path clock users count */ |
| 341 | int main_clk_users[INTERP_MAX]; |
| 342 | int rx_port_value[RX_MACRO_PORTS_MAX]; |
| 343 | u16 prim_int_users[INTERP_MAX]; |
| 344 | int rx_mclk_users; |
| 345 | int swr_clk_users; |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 346 | bool dapm_mclk_enable; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 347 | bool reset_swr; |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 348 | int clsh_users; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 349 | int rx_mclk_cnt; |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 350 | bool is_native_on; |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 351 | bool is_ear_mode_on; |
Laxminath Kasam | 701e358 | 2018-10-15 20:06:09 +0530 | [diff] [blame] | 352 | bool dev_up; |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 353 | bool hph_pwr_mode; |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 354 | bool hph_hd2_mode; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 355 | struct mutex mclk_lock; |
| 356 | struct mutex swr_clk_lock; |
| 357 | struct rx_swr_ctrl_data *swr_ctrl_data; |
| 358 | struct rx_swr_ctrl_platform_data swr_plat_data; |
| 359 | struct work_struct rx_macro_add_child_devices_work; |
| 360 | struct device_node *rx_swr_gpio_p; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 361 | struct snd_soc_component *component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 362 | unsigned long active_ch_mask[RX_MACRO_MAX_DAIS]; |
| 363 | unsigned long active_ch_cnt[RX_MACRO_MAX_DAIS]; |
| 364 | u16 bit_width[RX_MACRO_MAX_DAIS]; |
| 365 | char __iomem *rx_io_base; |
| 366 | char __iomem *rx_mclk_mode_muxsel; |
| 367 | struct rx_macro_idle_detect_config idle_det_cfg; |
| 368 | u8 sidetone_coeff_array[IIR_MAX][BAND_MAX] |
| 369 | [RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4]; |
| 370 | |
| 371 | struct platform_device *pdev_child_devices |
| 372 | [RX_MACRO_CHILD_DEVICES_MAX]; |
| 373 | int child_count; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 374 | int is_softclip_on; |
| 375 | int softclip_clk_users; |
| 376 | struct rx_macro_bcl_pmic_params bcl_pmic_params; |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 377 | u16 clk_id; |
| 378 | u16 default_clk_id; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 379 | }; |
| 380 | |
| 381 | static struct snd_soc_dai_driver rx_macro_dai[]; |
| 382 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 383 | |
| 384 | static const char * const rx_int_mix_mux_text[] = { |
| 385 | "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" |
| 386 | }; |
| 387 | |
| 388 | static const char * const rx_prim_mix_text[] = { |
| 389 | "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2", |
| 390 | "RX3", "RX4", "RX5" |
| 391 | }; |
| 392 | |
| 393 | static const char * const rx_sidetone_mix_text[] = { |
| 394 | "ZERO", "SRC0", "SRC1", "SRC_SUM" |
| 395 | }; |
| 396 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 397 | static const char * const iir_inp_mux_text[] = { |
| 398 | "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", |
| 399 | "RX0", "RX1", "RX2", "RX3", "RX4", "RX5" |
| 400 | }; |
| 401 | |
| 402 | static const char * const rx_int_dem_inp_mux_text[] = { |
| 403 | "NORMAL_DSM_OUT", "CLSH_DSM_OUT", |
| 404 | }; |
| 405 | |
| 406 | static const char * const rx_int0_1_interp_mux_text[] = { |
| 407 | "ZERO", "RX INT0_1 MIX1", |
| 408 | }; |
| 409 | |
| 410 | static const char * const rx_int1_1_interp_mux_text[] = { |
| 411 | "ZERO", "RX INT1_1 MIX1", |
| 412 | }; |
| 413 | |
| 414 | static const char * const rx_int2_1_interp_mux_text[] = { |
| 415 | "ZERO", "RX INT2_1 MIX1", |
| 416 | }; |
| 417 | |
| 418 | static const char * const rx_int0_2_interp_mux_text[] = { |
| 419 | "ZERO", "RX INT0_2 MUX", |
| 420 | }; |
| 421 | |
| 422 | static const char * const rx_int1_2_interp_mux_text[] = { |
| 423 | "ZERO", "RX INT1_2 MUX", |
| 424 | }; |
| 425 | |
| 426 | static const char * const rx_int2_2_interp_mux_text[] = { |
| 427 | "ZERO", "RX INT2_2 MUX", |
| 428 | }; |
| 429 | |
| 430 | static const char *const rx_macro_mux_text[] = { |
| 431 | "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB" |
| 432 | }; |
| 433 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 434 | static const char *const rx_macro_ear_mode_text[] = {"OFF", "ON"}; |
| 435 | static const struct soc_enum rx_macro_ear_mode_enum = |
| 436 | SOC_ENUM_SINGLE_EXT(2, rx_macro_ear_mode_text); |
| 437 | |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 438 | static const char *const rx_macro_hph_hd2_mode_text[] = {"OFF", "ON"}; |
| 439 | static const struct soc_enum rx_macro_hph_hd2_mode_enum = |
| 440 | SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_hd2_mode_text); |
| 441 | |
Laxminath Kasam | c21e98a | 2018-12-04 11:21:01 +0530 | [diff] [blame] | 442 | static const char *const rx_macro_hph_pwr_mode_text[] = {"ULP", "LOHIFI"}; |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 443 | static const struct soc_enum rx_macro_hph_pwr_mode_enum = |
| 444 | SOC_ENUM_SINGLE_EXT(2, rx_macro_hph_pwr_mode_text); |
| 445 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 446 | static const char * const rx_macro_vbat_bcl_gsm_mode_text[] = {"OFF", "ON"}; |
| 447 | static const struct soc_enum rx_macro_vbat_bcl_gsm_mode_enum = |
| 448 | SOC_ENUM_SINGLE_EXT(2, rx_macro_vbat_bcl_gsm_mode_text); |
| 449 | |
| 450 | static const struct snd_kcontrol_new rx_int2_1_vbat_mix_switch[] = { |
| 451 | SOC_DAPM_SINGLE("RX AUX VBAT Enable", SND_SOC_NOPM, 0, 1, 0) |
| 452 | }; |
| 453 | |
Vatsal Bucha | 8bcc97c | 2019-01-07 13:18:11 +0530 | [diff] [blame] | 454 | static const char * const hph_idle_detect_text[] = {"OFF", "ON"}; |
| 455 | |
| 456 | static SOC_ENUM_SINGLE_EXT_DECL(hph_idle_detect_enum, hph_idle_detect_text); |
| 457 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 458 | RX_MACRO_DAPM_ENUM(rx_int0_2, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, |
| 459 | rx_int_mix_mux_text); |
| 460 | RX_MACRO_DAPM_ENUM(rx_int1_2, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, |
| 461 | rx_int_mix_mux_text); |
| 462 | RX_MACRO_DAPM_ENUM(rx_int2_2, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, |
| 463 | rx_int_mix_mux_text); |
| 464 | |
| 465 | |
| 466 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, |
| 467 | rx_prim_mix_text); |
| 468 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, |
| 469 | rx_prim_mix_text); |
| 470 | RX_MACRO_DAPM_ENUM(rx_int0_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, |
| 471 | rx_prim_mix_text); |
| 472 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, |
| 473 | rx_prim_mix_text); |
| 474 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, |
| 475 | rx_prim_mix_text); |
| 476 | RX_MACRO_DAPM_ENUM(rx_int1_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, |
| 477 | rx_prim_mix_text); |
| 478 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp0, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, |
| 479 | rx_prim_mix_text); |
| 480 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp1, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, |
| 481 | rx_prim_mix_text); |
| 482 | RX_MACRO_DAPM_ENUM(rx_int2_1_mix_inp2, BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, |
| 483 | rx_prim_mix_text); |
| 484 | |
| 485 | RX_MACRO_DAPM_ENUM(rx_int0_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, |
| 486 | rx_sidetone_mix_text); |
| 487 | RX_MACRO_DAPM_ENUM(rx_int1_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, |
| 488 | rx_sidetone_mix_text); |
| 489 | RX_MACRO_DAPM_ENUM(rx_int2_mix2_inp, BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, |
| 490 | rx_sidetone_mix_text); |
| 491 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 492 | RX_MACRO_DAPM_ENUM(iir0_inp0, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0, |
| 493 | iir_inp_mux_text); |
| 494 | RX_MACRO_DAPM_ENUM(iir0_inp1, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0, |
| 495 | iir_inp_mux_text); |
| 496 | RX_MACRO_DAPM_ENUM(iir0_inp2, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0, |
| 497 | iir_inp_mux_text); |
| 498 | RX_MACRO_DAPM_ENUM(iir0_inp3, BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0, |
| 499 | iir_inp_mux_text); |
| 500 | RX_MACRO_DAPM_ENUM(iir1_inp0, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0, |
| 501 | iir_inp_mux_text); |
| 502 | RX_MACRO_DAPM_ENUM(iir1_inp1, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0, |
| 503 | iir_inp_mux_text); |
| 504 | RX_MACRO_DAPM_ENUM(iir1_inp2, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0, |
| 505 | iir_inp_mux_text); |
| 506 | RX_MACRO_DAPM_ENUM(iir1_inp3, BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0, |
| 507 | iir_inp_mux_text); |
| 508 | |
| 509 | RX_MACRO_DAPM_ENUM(rx_int0_1_interp, SND_SOC_NOPM, 0, |
| 510 | rx_int0_1_interp_mux_text); |
| 511 | RX_MACRO_DAPM_ENUM(rx_int1_1_interp, SND_SOC_NOPM, 0, |
| 512 | rx_int1_1_interp_mux_text); |
| 513 | RX_MACRO_DAPM_ENUM(rx_int2_1_interp, SND_SOC_NOPM, 0, |
| 514 | rx_int2_1_interp_mux_text); |
| 515 | |
| 516 | RX_MACRO_DAPM_ENUM(rx_int0_2_interp, SND_SOC_NOPM, 0, |
| 517 | rx_int0_2_interp_mux_text); |
| 518 | RX_MACRO_DAPM_ENUM(rx_int1_2_interp, SND_SOC_NOPM, 0, |
| 519 | rx_int1_2_interp_mux_text); |
| 520 | RX_MACRO_DAPM_ENUM(rx_int2_2_interp, SND_SOC_NOPM, 0, |
| 521 | rx_int2_2_interp_mux_text); |
| 522 | |
| 523 | RX_MACRO_DAPM_ENUM_EXT(rx_int0_dem_inp, BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0, |
| 524 | rx_int_dem_inp_mux_text, snd_soc_dapm_get_enum_double, |
| 525 | rx_macro_int_dem_inp_mux_put); |
| 526 | RX_MACRO_DAPM_ENUM_EXT(rx_int1_dem_inp, BOLERO_CDC_RX_RX1_RX_PATH_CFG1, 0, |
| 527 | rx_int_dem_inp_mux_text, snd_soc_dapm_get_enum_double, |
| 528 | rx_macro_int_dem_inp_mux_put); |
| 529 | |
| 530 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx0, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 531 | rx_macro_mux_get, rx_macro_mux_put); |
| 532 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx1, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 533 | rx_macro_mux_get, rx_macro_mux_put); |
| 534 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx2, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 535 | rx_macro_mux_get, rx_macro_mux_put); |
| 536 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx3, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 537 | rx_macro_mux_get, rx_macro_mux_put); |
| 538 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx4, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 539 | rx_macro_mux_get, rx_macro_mux_put); |
| 540 | RX_MACRO_DAPM_ENUM_EXT(rx_macro_rx5, SND_SOC_NOPM, 0, rx_macro_mux_text, |
| 541 | rx_macro_mux_get, rx_macro_mux_put); |
| 542 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 543 | static const char * const rx_echo_mux_text[] = { |
| 544 | "ZERO", "RX_MIX0", "RX_MIX1", "RX_MIX2" |
| 545 | }; |
| 546 | |
| 547 | static const struct soc_enum rx_mix_tx2_mux_enum = |
| 548 | SOC_ENUM_SINGLE(BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, |
| 549 | rx_echo_mux_text); |
| 550 | |
| 551 | static const struct snd_kcontrol_new rx_mix_tx2_mux = |
| 552 | SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum); |
| 553 | |
| 554 | static const struct soc_enum rx_mix_tx1_mux_enum = |
| 555 | SOC_ENUM_SINGLE(BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, |
| 556 | rx_echo_mux_text); |
| 557 | |
| 558 | static const struct snd_kcontrol_new rx_mix_tx1_mux = |
| 559 | SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum); |
| 560 | |
| 561 | static const struct soc_enum rx_mix_tx0_mux_enum = |
| 562 | SOC_ENUM_SINGLE(BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 4, 4, |
| 563 | rx_echo_mux_text); |
| 564 | |
| 565 | static const struct snd_kcontrol_new rx_mix_tx0_mux = |
| 566 | SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum); |
| 567 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 568 | static struct snd_soc_dai_ops rx_macro_dai_ops = { |
| 569 | .hw_params = rx_macro_hw_params, |
| 570 | .get_channel_map = rx_macro_get_channel_map, |
| 571 | }; |
| 572 | |
| 573 | static struct snd_soc_dai_driver rx_macro_dai[] = { |
| 574 | { |
| 575 | .name = "rx_macro_rx1", |
| 576 | .id = RX_MACRO_AIF1_PB, |
| 577 | .playback = { |
| 578 | .stream_name = "RX_MACRO_AIF1 Playback", |
| 579 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 580 | .formats = RX_MACRO_FORMATS, |
| 581 | .rate_max = 384000, |
| 582 | .rate_min = 8000, |
| 583 | .channels_min = 1, |
| 584 | .channels_max = 2, |
| 585 | }, |
| 586 | .ops = &rx_macro_dai_ops, |
| 587 | }, |
| 588 | { |
| 589 | .name = "rx_macro_rx2", |
| 590 | .id = RX_MACRO_AIF2_PB, |
| 591 | .playback = { |
| 592 | .stream_name = "RX_MACRO_AIF2 Playback", |
| 593 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 594 | .formats = RX_MACRO_FORMATS, |
| 595 | .rate_max = 384000, |
| 596 | .rate_min = 8000, |
| 597 | .channels_min = 1, |
| 598 | .channels_max = 2, |
| 599 | }, |
| 600 | .ops = &rx_macro_dai_ops, |
| 601 | }, |
| 602 | { |
| 603 | .name = "rx_macro_rx3", |
| 604 | .id = RX_MACRO_AIF3_PB, |
| 605 | .playback = { |
| 606 | .stream_name = "RX_MACRO_AIF3 Playback", |
| 607 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 608 | .formats = RX_MACRO_FORMATS, |
| 609 | .rate_max = 384000, |
| 610 | .rate_min = 8000, |
| 611 | .channels_min = 1, |
| 612 | .channels_max = 2, |
| 613 | }, |
| 614 | .ops = &rx_macro_dai_ops, |
| 615 | }, |
| 616 | { |
| 617 | .name = "rx_macro_rx4", |
| 618 | .id = RX_MACRO_AIF4_PB, |
| 619 | .playback = { |
| 620 | .stream_name = "RX_MACRO_AIF4 Playback", |
| 621 | .rates = RX_MACRO_RATES | RX_MACRO_FRAC_RATES, |
| 622 | .formats = RX_MACRO_FORMATS, |
| 623 | .rate_max = 384000, |
| 624 | .rate_min = 8000, |
| 625 | .channels_min = 1, |
| 626 | .channels_max = 2, |
| 627 | }, |
| 628 | .ops = &rx_macro_dai_ops, |
| 629 | }, |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 630 | { |
| 631 | .name = "rx_macro_echo", |
| 632 | .id = RX_MACRO_AIF_ECHO, |
| 633 | .capture = { |
| 634 | .stream_name = "RX_AIF_ECHO Capture", |
| 635 | .rates = RX_MACRO_ECHO_RATES, |
| 636 | .formats = RX_MACRO_ECHO_FORMATS, |
| 637 | .rate_max = 48000, |
| 638 | .rate_min = 8000, |
| 639 | .channels_min = 1, |
| 640 | .channels_max = 3, |
| 641 | }, |
| 642 | .ops = &rx_macro_dai_ops, |
| 643 | }, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 644 | }; |
| 645 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 646 | static int get_impedance_index(int imped) |
| 647 | { |
| 648 | int i = 0; |
| 649 | |
| 650 | if (imped < imped_index[i].imped_val) { |
| 651 | pr_debug("%s, detected impedance is less than %d Ohm\n", |
| 652 | __func__, imped_index[i].imped_val); |
| 653 | i = 0; |
| 654 | goto ret; |
| 655 | } |
| 656 | if (imped >= imped_index[ARRAY_SIZE(imped_index) - 1].imped_val) { |
| 657 | pr_debug("%s, detected impedance is greater than %d Ohm\n", |
| 658 | __func__, |
| 659 | imped_index[ARRAY_SIZE(imped_index) - 1].imped_val); |
| 660 | i = ARRAY_SIZE(imped_index) - 1; |
| 661 | goto ret; |
| 662 | } |
| 663 | for (i = 0; i < ARRAY_SIZE(imped_index) - 1; i++) { |
| 664 | if (imped >= imped_index[i].imped_val && |
| 665 | imped < imped_index[i + 1].imped_val) |
| 666 | break; |
| 667 | } |
| 668 | ret: |
| 669 | pr_debug("%s: selected impedance index = %d\n", |
| 670 | __func__, imped_index[i].index); |
| 671 | return imped_index[i].index; |
| 672 | } |
| 673 | |
| 674 | /* |
| 675 | * rx_macro_wcd_clsh_imped_config - |
| 676 | * This function updates HPHL and HPHR gain settings |
| 677 | * according to the impedance value. |
| 678 | * |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 679 | * @component: codec pointer handle |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 680 | * @imped: impedance value of HPHL/R |
| 681 | * @reset: bool variable to reset registers when teardown |
| 682 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 683 | static void rx_macro_wcd_clsh_imped_config(struct snd_soc_component *component, |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 684 | int imped, bool reset) |
| 685 | { |
| 686 | int i; |
| 687 | int index = 0; |
| 688 | int table_size; |
| 689 | |
| 690 | static const struct rx_macro_reg_mask_val |
| 691 | (*imped_table_ptr)[MAX_IMPED_PARAMS]; |
| 692 | |
| 693 | table_size = ARRAY_SIZE(imped_table); |
| 694 | imped_table_ptr = imped_table; |
| 695 | /* reset = 1, which means request is to reset the register values */ |
| 696 | if (reset) { |
| 697 | for (i = 0; i < MAX_IMPED_PARAMS; i++) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 698 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 699 | imped_table_ptr[index][i].reg, |
| 700 | imped_table_ptr[index][i].mask, 0); |
| 701 | return; |
| 702 | } |
| 703 | index = get_impedance_index(imped); |
| 704 | if (index >= (ARRAY_SIZE(imped_index) - 1)) { |
| 705 | pr_debug("%s, impedance not in range = %d\n", __func__, imped); |
| 706 | return; |
| 707 | } |
| 708 | if (index >= table_size) { |
| 709 | pr_debug("%s, impedance index not in range = %d\n", __func__, |
| 710 | index); |
| 711 | return; |
| 712 | } |
| 713 | for (i = 0; i < MAX_IMPED_PARAMS; i++) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 714 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 715 | imped_table_ptr[index][i].reg, |
| 716 | imped_table_ptr[index][i].mask, |
| 717 | imped_table_ptr[index][i].val); |
| 718 | } |
| 719 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 720 | static bool rx_macro_get_data(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 721 | struct device **rx_dev, |
| 722 | struct rx_macro_priv **rx_priv, |
| 723 | const char *func_name) |
| 724 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 725 | *rx_dev = bolero_get_device_ptr(component->dev, RX_MACRO); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 726 | |
| 727 | if (!(*rx_dev)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 728 | dev_err(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 729 | "%s: null device for macro!\n", func_name); |
| 730 | return false; |
| 731 | } |
| 732 | |
| 733 | *rx_priv = dev_get_drvdata((*rx_dev)); |
| 734 | if (!(*rx_priv)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 735 | dev_err(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 736 | "%s: priv is null for macro!\n", func_name); |
| 737 | return false; |
| 738 | } |
| 739 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 740 | if (!(*rx_priv)->component) { |
| 741 | dev_err(component->dev, |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 742 | "%s: rx_priv component is not initialized!\n", func_name); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 743 | return false; |
| 744 | } |
| 745 | |
| 746 | return true; |
| 747 | } |
| 748 | |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 749 | static int rx_macro_set_port_map(struct snd_soc_component *component, |
| 750 | u32 usecase, u32 size, void *data) |
| 751 | { |
| 752 | struct device *rx_dev = NULL; |
| 753 | struct rx_macro_priv *rx_priv = NULL; |
| 754 | struct swrm_port_config port_cfg; |
| 755 | int ret = 0; |
| 756 | |
| 757 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
| 758 | return -EINVAL; |
| 759 | |
| 760 | memset(&port_cfg, 0, sizeof(port_cfg)); |
| 761 | port_cfg.uc = usecase; |
| 762 | port_cfg.size = size; |
| 763 | port_cfg.params = data; |
| 764 | |
| 765 | ret = swrm_wcd_notify( |
| 766 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 767 | SWR_SET_PORT_MAP, &port_cfg); |
| 768 | |
| 769 | return ret; |
| 770 | } |
| 771 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 772 | static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, |
| 773 | struct snd_ctl_elem_value *ucontrol) |
| 774 | { |
| 775 | struct snd_soc_dapm_widget *widget = |
| 776 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 777 | struct snd_soc_component *component = |
| 778 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 779 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 780 | unsigned int val = 0; |
| 781 | unsigned short look_ahead_dly_reg = |
| 782 | BOLERO_CDC_RX_RX0_RX_PATH_CFG0; |
| 783 | |
| 784 | val = ucontrol->value.enumerated.item[0]; |
| 785 | if (val >= e->items) |
| 786 | return -EINVAL; |
| 787 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 788 | dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 789 | widget->name, val); |
| 790 | |
| 791 | if (e->reg == BOLERO_CDC_RX_RX0_RX_PATH_CFG1) |
| 792 | look_ahead_dly_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0; |
| 793 | else if (e->reg == BOLERO_CDC_RX_RX1_RX_PATH_CFG1) |
| 794 | look_ahead_dly_reg = BOLERO_CDC_RX_RX1_RX_PATH_CFG0; |
| 795 | |
| 796 | /* Set Look Ahead Delay */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 797 | snd_soc_component_update_bits(component, look_ahead_dly_reg, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 798 | 0x08, (val ? 0x08 : 0x00)); |
| 799 | /* Set DEM INP Select */ |
| 800 | return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 801 | } |
| 802 | |
| 803 | static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, |
| 804 | u8 rate_reg_val, |
| 805 | u32 sample_rate) |
| 806 | { |
| 807 | u8 int_1_mix1_inp = 0; |
| 808 | u32 j = 0, port = 0; |
| 809 | u16 int_mux_cfg0 = 0, int_mux_cfg1 = 0; |
| 810 | u16 int_fs_reg = 0; |
| 811 | u8 int_mux_cfg0_val = 0, int_mux_cfg1_val = 0; |
| 812 | u8 inp0_sel = 0, inp1_sel = 0, inp2_sel = 0; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 813 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 814 | struct device *rx_dev = NULL; |
| 815 | struct rx_macro_priv *rx_priv = NULL; |
| 816 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 817 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 818 | return -EINVAL; |
| 819 | |
| 820 | for_each_set_bit(port, &rx_priv->active_ch_mask[dai->id], |
| 821 | RX_MACRO_PORTS_MAX) { |
| 822 | int_1_mix1_inp = port; |
| 823 | if ((int_1_mix1_inp < RX_MACRO_RX0) || |
| 824 | (int_1_mix1_inp > RX_MACRO_PORTS_MAX)) { |
| 825 | pr_err("%s: Invalid RX port, Dai ID is %d\n", |
| 826 | __func__, dai->id); |
| 827 | return -EINVAL; |
| 828 | } |
| 829 | |
| 830 | int_mux_cfg0 = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0; |
| 831 | |
| 832 | /* |
| 833 | * Loop through all interpolator MUX inputs and find out |
| 834 | * to which interpolator input, the rx port |
| 835 | * is connected |
| 836 | */ |
| 837 | for (j = 0; j < INTERP_MAX; j++) { |
| 838 | int_mux_cfg1 = int_mux_cfg0 + 4; |
| 839 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 840 | int_mux_cfg0_val = snd_soc_component_read32( |
| 841 | component, int_mux_cfg0); |
| 842 | int_mux_cfg1_val = snd_soc_component_read32( |
| 843 | component, int_mux_cfg1); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 844 | inp0_sel = int_mux_cfg0_val & 0x07; |
| 845 | inp1_sel = (int_mux_cfg0_val >> 4) & 0x038; |
| 846 | inp2_sel = (int_mux_cfg1_val >> 4) & 0x038; |
| 847 | if ((inp0_sel == int_1_mix1_inp) || |
| 848 | (inp1_sel == int_1_mix1_inp) || |
| 849 | (inp2_sel == int_1_mix1_inp)) { |
| 850 | int_fs_reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + |
| 851 | 0x80 * j; |
| 852 | pr_debug("%s: AIF_PB DAI(%d) connected to INT%u_1\n", |
| 853 | __func__, dai->id, j); |
| 854 | pr_debug("%s: set INT%u_1 sample rate to %u\n", |
| 855 | __func__, j, sample_rate); |
| 856 | /* sample_rate is in Hz */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 857 | snd_soc_component_update_bits(component, |
| 858 | int_fs_reg, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 859 | 0x0F, rate_reg_val); |
| 860 | } |
| 861 | int_mux_cfg0 += 8; |
| 862 | } |
| 863 | } |
| 864 | |
| 865 | return 0; |
| 866 | } |
| 867 | |
| 868 | static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, |
| 869 | u8 rate_reg_val, |
| 870 | u32 sample_rate) |
| 871 | { |
| 872 | u8 int_2_inp = 0; |
| 873 | u32 j = 0, port = 0; |
| 874 | u16 int_mux_cfg1 = 0, int_fs_reg = 0; |
| 875 | u8 int_mux_cfg1_val = 0; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 876 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 877 | struct device *rx_dev = NULL; |
| 878 | struct rx_macro_priv *rx_priv = NULL; |
| 879 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 880 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 881 | return -EINVAL; |
| 882 | |
| 883 | for_each_set_bit(port, &rx_priv->active_ch_mask[dai->id], |
| 884 | RX_MACRO_PORTS_MAX) { |
| 885 | int_2_inp = port; |
| 886 | if ((int_2_inp < RX_MACRO_RX0) || |
| 887 | (int_2_inp > RX_MACRO_PORTS_MAX)) { |
| 888 | pr_err("%s: Invalid RX port, Dai ID is %d\n", |
| 889 | __func__, dai->id); |
| 890 | return -EINVAL; |
| 891 | } |
| 892 | |
| 893 | int_mux_cfg1 = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1; |
| 894 | for (j = 0; j < INTERP_MAX; j++) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 895 | int_mux_cfg1_val = snd_soc_component_read32( |
| 896 | component, int_mux_cfg1) & |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 897 | 0x07; |
| 898 | if (int_mux_cfg1_val == int_2_inp) { |
| 899 | int_fs_reg = BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL + |
| 900 | 0x80 * j; |
| 901 | pr_debug("%s: AIF_PB DAI(%d) connected to INT%u_2\n", |
| 902 | __func__, dai->id, j); |
| 903 | pr_debug("%s: set INT%u_2 sample rate to %u\n", |
| 904 | __func__, j, sample_rate); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 905 | snd_soc_component_update_bits( |
| 906 | component, int_fs_reg, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 907 | 0x0F, rate_reg_val); |
| 908 | } |
| 909 | int_mux_cfg1 += 8; |
| 910 | } |
| 911 | } |
| 912 | return 0; |
| 913 | } |
| 914 | |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 915 | static bool rx_macro_is_fractional_sample_rate(u32 sample_rate) |
| 916 | { |
| 917 | switch (sample_rate) { |
| 918 | case SAMPLING_RATE_44P1KHZ: |
| 919 | case SAMPLING_RATE_88P2KHZ: |
| 920 | case SAMPLING_RATE_176P4KHZ: |
| 921 | case SAMPLING_RATE_352P8KHZ: |
| 922 | return true; |
| 923 | default: |
| 924 | return false; |
| 925 | } |
| 926 | return false; |
| 927 | } |
| 928 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 929 | static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, |
| 930 | u32 sample_rate) |
| 931 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 932 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 933 | int rate_val = 0; |
| 934 | int i = 0, ret = 0; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 935 | struct device *rx_dev = NULL; |
| 936 | struct rx_macro_priv *rx_priv = NULL; |
| 937 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 938 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 939 | return -EINVAL; |
| 940 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 941 | |
| 942 | for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) { |
| 943 | if (sample_rate == sr_val_tbl[i].sample_rate) { |
| 944 | rate_val = sr_val_tbl[i].rate_val; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 945 | if (rx_macro_is_fractional_sample_rate(sample_rate)) |
| 946 | rx_priv->is_native_on = true; |
| 947 | else |
| 948 | rx_priv->is_native_on = false; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 949 | break; |
| 950 | } |
| 951 | } |
| 952 | if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 953 | dev_err(component->dev, "%s: Unsupported sample rate: %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 954 | __func__, sample_rate); |
| 955 | return -EINVAL; |
| 956 | } |
| 957 | |
| 958 | ret = rx_macro_set_prim_interpolator_rate(dai, (u8)rate_val, sample_rate); |
| 959 | if (ret) |
| 960 | return ret; |
| 961 | ret = rx_macro_set_mix_interpolator_rate(dai, (u8)rate_val, sample_rate); |
| 962 | if (ret) |
| 963 | return ret; |
| 964 | |
| 965 | return ret; |
| 966 | } |
| 967 | |
| 968 | static int rx_macro_hw_params(struct snd_pcm_substream *substream, |
| 969 | struct snd_pcm_hw_params *params, |
| 970 | struct snd_soc_dai *dai) |
| 971 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 972 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 973 | int ret = 0; |
| 974 | struct device *rx_dev = NULL; |
| 975 | struct rx_macro_priv *rx_priv = NULL; |
| 976 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 977 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 978 | return -EINVAL; |
| 979 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 980 | dev_dbg(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 981 | "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 982 | dai->name, dai->id, params_rate(params), |
| 983 | params_channels(params)); |
| 984 | |
| 985 | switch (substream->stream) { |
| 986 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 987 | ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); |
| 988 | if (ret) { |
| 989 | pr_err("%s: cannot set sample rate: %u\n", |
| 990 | __func__, params_rate(params)); |
| 991 | return ret; |
| 992 | } |
| 993 | rx_priv->bit_width[dai->id] = params_width(params); |
| 994 | break; |
| 995 | case SNDRV_PCM_STREAM_CAPTURE: |
| 996 | default: |
| 997 | break; |
| 998 | } |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static int rx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 1003 | unsigned int *tx_num, unsigned int *tx_slot, |
| 1004 | unsigned int *rx_num, unsigned int *rx_slot) |
| 1005 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1006 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1007 | struct device *rx_dev = NULL; |
| 1008 | struct rx_macro_priv *rx_priv = NULL; |
| 1009 | unsigned int temp = 0, ch_mask = 0; |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 1010 | u16 val = 0, mask = 0, cnt = 0, i = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1011 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1012 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1013 | return -EINVAL; |
| 1014 | |
| 1015 | switch (dai->id) { |
| 1016 | case RX_MACRO_AIF1_PB: |
| 1017 | case RX_MACRO_AIF2_PB: |
| 1018 | case RX_MACRO_AIF3_PB: |
| 1019 | case RX_MACRO_AIF4_PB: |
| 1020 | for_each_set_bit(temp, &rx_priv->active_ch_mask[dai->id], |
| 1021 | RX_MACRO_PORTS_MAX) { |
Vatsal Bucha | 1a96a61 | 2018-11-26 13:04:56 +0530 | [diff] [blame] | 1022 | ch_mask |= (1 << temp); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1023 | if (++i == RX_MACRO_MAX_DMA_CH_PER_PORT) |
| 1024 | break; |
| 1025 | } |
| 1026 | *rx_slot = ch_mask; |
| 1027 | *rx_num = rx_priv->active_ch_cnt[dai->id]; |
| 1028 | break; |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 1029 | case RX_MACRO_AIF_ECHO: |
| 1030 | val = snd_soc_component_read32(component, |
| 1031 | BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4); |
| 1032 | if (val & RX_MACRO_EC_MIX_TX0_MASK) { |
| 1033 | mask |= 0x1; |
| 1034 | cnt++; |
| 1035 | } |
| 1036 | if (val & RX_MACRO_EC_MIX_TX1_MASK) { |
| 1037 | mask |= 0x2; |
| 1038 | cnt++; |
| 1039 | } |
| 1040 | val = snd_soc_component_read32(component, |
| 1041 | BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5); |
| 1042 | if (val & RX_MACRO_EC_MIX_TX2_MASK) { |
| 1043 | mask |= 0x4; |
| 1044 | cnt++; |
| 1045 | } |
| 1046 | *tx_slot = mask; |
| 1047 | *tx_num = cnt; |
| 1048 | break; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1049 | default: |
| 1050 | dev_err(rx_dev, "%s: Invalid AIF\n", __func__); |
| 1051 | break; |
| 1052 | } |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
| 1056 | static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, |
| 1057 | bool mclk_enable, bool dapm) |
| 1058 | { |
| 1059 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1060 | int ret = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1061 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 1062 | if (regmap == NULL) { |
| 1063 | dev_err(rx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 1064 | return -EINVAL; |
| 1065 | } |
| 1066 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1067 | dev_dbg(rx_priv->dev, "%s: mclk_enable = %u, dapm = %d clk_users= %d\n", |
| 1068 | __func__, mclk_enable, dapm, rx_priv->rx_mclk_users); |
| 1069 | |
| 1070 | mutex_lock(&rx_priv->mclk_lock); |
| 1071 | if (mclk_enable) { |
| 1072 | if (rx_priv->rx_mclk_users == 0) { |
Laxminath Kasam | 7b9cdb6 | 2018-09-28 16:28:54 +0530 | [diff] [blame] | 1073 | if (rx_priv->is_native_on) |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1074 | rx_priv->clk_id = RX_CORE_CLK; |
| 1075 | ret = bolero_clk_rsc_request_clock(rx_priv->dev, |
| 1076 | rx_priv->default_clk_id, |
| 1077 | rx_priv->clk_id, |
| 1078 | true); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1079 | if (ret < 0) { |
| 1080 | dev_err(rx_priv->dev, |
| 1081 | "%s: rx request clock enable failed\n", |
| 1082 | __func__); |
| 1083 | goto exit; |
| 1084 | } |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1085 | bolero_clk_rsc_fs_gen_request(rx_priv->dev, |
| 1086 | true); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1087 | regcache_mark_dirty(regmap); |
| 1088 | regcache_sync_region(regmap, |
| 1089 | RX_START_OFFSET, |
| 1090 | RX_MAX_OFFSET); |
| 1091 | regmap_update_bits(regmap, |
| 1092 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 1093 | 0x01, 0x01); |
| 1094 | regmap_update_bits(regmap, |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 1095 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 1096 | 0x02, 0x02); |
| 1097 | regmap_update_bits(regmap, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1098 | BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 1099 | 0x01, 0x01); |
| 1100 | } |
| 1101 | rx_priv->rx_mclk_users++; |
| 1102 | } else { |
| 1103 | if (rx_priv->rx_mclk_users <= 0) { |
| 1104 | dev_err(rx_priv->dev, "%s: clock already disabled\n", |
| 1105 | __func__); |
| 1106 | rx_priv->rx_mclk_users = 0; |
| 1107 | goto exit; |
| 1108 | } |
| 1109 | rx_priv->rx_mclk_users--; |
| 1110 | if (rx_priv->rx_mclk_users == 0) { |
| 1111 | regmap_update_bits(regmap, |
| 1112 | BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 1113 | 0x01, 0x00); |
| 1114 | regmap_update_bits(regmap, |
| 1115 | BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, |
| 1116 | 0x01, 0x00); |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1117 | bolero_clk_rsc_fs_gen_request(rx_priv->dev, |
| 1118 | false); |
| 1119 | bolero_clk_rsc_request_clock(rx_priv->dev, |
| 1120 | rx_priv->default_clk_id, |
| 1121 | rx_priv->clk_id, |
| 1122 | false); |
| 1123 | rx_priv->clk_id = rx_priv->default_clk_id; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1124 | } |
| 1125 | } |
| 1126 | exit: |
| 1127 | mutex_unlock(&rx_priv->mclk_lock); |
| 1128 | return ret; |
| 1129 | } |
| 1130 | |
| 1131 | static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 1132 | struct snd_kcontrol *kcontrol, int event) |
| 1133 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1134 | struct snd_soc_component *component = |
| 1135 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1136 | int ret = 0; |
| 1137 | struct device *rx_dev = NULL; |
| 1138 | struct rx_macro_priv *rx_priv = NULL; |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 1139 | int mclk_freq = MCLK_FREQ; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1140 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1141 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1142 | return -EINVAL; |
| 1143 | |
| 1144 | dev_dbg(rx_dev, "%s: event = %d\n", __func__, event); |
| 1145 | switch (event) { |
| 1146 | case SND_SOC_DAPM_PRE_PMU: |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 1147 | /* if swr_clk_users > 0, call device down */ |
| 1148 | if (rx_priv->swr_clk_users > 0) { |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1149 | if ((rx_priv->clk_id == rx_priv->default_clk_id && |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 1150 | rx_priv->is_native_on) || |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1151 | (rx_priv->clk_id == RX_CORE_CLK && |
Laxminath Kasam | bee0819 | 2018-07-01 14:38:55 +0530 | [diff] [blame] | 1152 | !rx_priv->is_native_on)) { |
| 1153 | swrm_wcd_notify( |
| 1154 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 1155 | SWR_DEVICE_DOWN, NULL); |
| 1156 | } |
| 1157 | } |
Laxminath Kasam | ac396d5 | 2018-09-06 12:53:26 +0530 | [diff] [blame] | 1158 | if (rx_priv->is_native_on) |
| 1159 | mclk_freq = MCLK_FREQ_NATIVE; |
| 1160 | swrm_wcd_notify( |
| 1161 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 1162 | SWR_CLK_FREQ, &mclk_freq); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1163 | ret = rx_macro_mclk_enable(rx_priv, 1, true); |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 1164 | if (ret) |
| 1165 | rx_priv->dapm_mclk_enable = false; |
| 1166 | else |
| 1167 | rx_priv->dapm_mclk_enable = true; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1168 | break; |
| 1169 | case SND_SOC_DAPM_POST_PMD: |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 1170 | if (rx_priv->dapm_mclk_enable) |
| 1171 | ret = rx_macro_mclk_enable(rx_priv, 0, true); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1172 | break; |
| 1173 | default: |
| 1174 | dev_err(rx_priv->dev, |
| 1175 | "%s: invalid DAPM event %d\n", __func__, event); |
| 1176 | ret = -EINVAL; |
| 1177 | } |
| 1178 | return ret; |
| 1179 | } |
| 1180 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1181 | static int rx_macro_event_handler(struct snd_soc_component *component, |
| 1182 | u16 event, u32 data) |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1183 | { |
Vatsal Bucha | 53b4e14 | 2018-11-13 19:36:25 +0530 | [diff] [blame] | 1184 | u16 reg = 0, reg_mix = 0, rx_idx = 0, mute = 0x0, val = 0; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1185 | struct device *rx_dev = NULL; |
| 1186 | struct rx_macro_priv *rx_priv = NULL; |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1187 | int ret = 0; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1188 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1189 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1190 | return -EINVAL; |
| 1191 | |
| 1192 | switch (event) { |
| 1193 | case BOLERO_MACRO_EVT_RX_MUTE: |
| 1194 | rx_idx = data >> 0x10; |
| 1195 | mute = data & 0xffff; |
Vatsal Bucha | 53b4e14 | 2018-11-13 19:36:25 +0530 | [diff] [blame] | 1196 | val = mute ? 0x10 : 0x00; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1197 | reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + (rx_idx * |
| 1198 | RX_MACRO_RX_PATH_OFFSET); |
| 1199 | reg_mix = BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL + (rx_idx * |
| 1200 | RX_MACRO_RX_PATH_OFFSET); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1201 | snd_soc_component_update_bits(component, reg, |
| 1202 | 0x10, val); |
| 1203 | snd_soc_component_update_bits(component, reg_mix, |
| 1204 | 0x10, val); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1205 | break; |
| 1206 | case BOLERO_MACRO_EVT_IMPED_TRUE: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1207 | rx_macro_wcd_clsh_imped_config(component, data, true); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1208 | break; |
| 1209 | case BOLERO_MACRO_EVT_IMPED_FALSE: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1210 | rx_macro_wcd_clsh_imped_config(component, data, false); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1211 | break; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1212 | case BOLERO_MACRO_EVT_SSR_DOWN: |
Laxminath Kasam | 701e358 | 2018-10-15 20:06:09 +0530 | [diff] [blame] | 1213 | rx_priv->dev_up = false; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1214 | swrm_wcd_notify( |
| 1215 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
Ramprasad Katkam | 5ee54ae | 2018-12-19 18:56:00 +0530 | [diff] [blame] | 1216 | SWR_DEVICE_DOWN, NULL); |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1217 | swrm_wcd_notify( |
| 1218 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
Ramprasad Katkam | 5ee54ae | 2018-12-19 18:56:00 +0530 | [diff] [blame] | 1219 | SWR_DEVICE_SSR_DOWN, NULL); |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1220 | break; |
| 1221 | case BOLERO_MACRO_EVT_SSR_UP: |
Laxminath Kasam | 701e358 | 2018-10-15 20:06:09 +0530 | [diff] [blame] | 1222 | rx_priv->dev_up = true; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 1223 | /* reset swr after ssr/pdr */ |
| 1224 | rx_priv->reset_swr = true; |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1225 | /* enable&disable RX_CORE_CLK to reset GFMUX reg */ |
| 1226 | ret = bolero_clk_rsc_request_clock(rx_priv->dev, |
| 1227 | rx_priv->default_clk_id, |
| 1228 | RX_CORE_CLK, true); |
| 1229 | if (ret < 0) |
| 1230 | dev_err_ratelimited(rx_priv->dev, |
| 1231 | "%s, failed to enable clk, ret:%d\n", |
| 1232 | __func__, ret); |
| 1233 | else |
| 1234 | bolero_clk_rsc_request_clock(rx_priv->dev, |
| 1235 | rx_priv->default_clk_id, |
| 1236 | RX_CORE_CLK, false); |
| 1237 | |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 1238 | swrm_wcd_notify( |
| 1239 | rx_priv->swr_ctrl_data[0].rx_swr_pdev, |
| 1240 | SWR_DEVICE_SSR_UP, NULL); |
| 1241 | break; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1242 | } |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 1243 | return ret; |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 1244 | } |
| 1245 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1246 | static int rx_macro_find_playback_dai_id_for_port(int port_id, |
| 1247 | struct rx_macro_priv *rx_priv) |
| 1248 | { |
| 1249 | int i = 0; |
| 1250 | |
| 1251 | for (i = RX_MACRO_AIF1_PB; i < RX_MACRO_MAX_DAIS; i++) { |
| 1252 | if (test_bit(port_id, &rx_priv->active_ch_mask[i])) |
| 1253 | return i; |
| 1254 | } |
| 1255 | |
| 1256 | return -EINVAL; |
| 1257 | } |
| 1258 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1259 | static int rx_macro_set_idle_detect_thr(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1260 | struct rx_macro_priv *rx_priv, |
| 1261 | int interp, int path_type) |
| 1262 | { |
| 1263 | int port_id[4] = { 0, 0, 0, 0 }; |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 1264 | int *port_ptr = NULL; |
| 1265 | int num_ports = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1266 | int bit_width = 0, i = 0; |
| 1267 | int mux_reg = 0, mux_reg_val = 0; |
| 1268 | int dai_id = 0, idle_thr = 0; |
| 1269 | |
| 1270 | if ((interp != INTERP_HPHL) && (interp != INTERP_HPHR)) |
| 1271 | return 0; |
| 1272 | |
| 1273 | if (!rx_priv->idle_det_cfg.hph_idle_detect_en) |
| 1274 | return 0; |
| 1275 | |
| 1276 | port_ptr = &port_id[0]; |
| 1277 | num_ports = 0; |
| 1278 | |
| 1279 | /* |
| 1280 | * Read interpolator MUX input registers and find |
| 1281 | * which cdc_dma port is connected and store the port |
| 1282 | * numbers in port_id array. |
| 1283 | */ |
| 1284 | if (path_type == INTERP_MIX_PATH) { |
| 1285 | mux_reg = BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1 + |
| 1286 | 2 * interp; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1287 | mux_reg_val = snd_soc_component_read32(component, mux_reg) & |
| 1288 | 0x0f; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1289 | |
| 1290 | if ((mux_reg_val >= INTn_2_INP_SEL_RX0) && |
| 1291 | (mux_reg_val <= INTn_2_INP_SEL_RX5)) { |
| 1292 | *port_ptr++ = mux_reg_val - 1; |
| 1293 | num_ports++; |
| 1294 | } |
| 1295 | } |
| 1296 | |
| 1297 | if (path_type == INTERP_MAIN_PATH) { |
| 1298 | mux_reg = BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0 + |
| 1299 | 2 * (interp - 1); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1300 | mux_reg_val = snd_soc_component_read32(component, mux_reg) & |
| 1301 | 0x0f; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1302 | i = RX_MACRO_INTERP_MUX_NUM_INPUTS; |
| 1303 | |
| 1304 | while (i) { |
| 1305 | if ((mux_reg_val >= INTn_1_INP_SEL_RX0) && |
| 1306 | (mux_reg_val <= INTn_1_INP_SEL_RX5)) { |
| 1307 | *port_ptr++ = mux_reg_val - |
| 1308 | INTn_1_INP_SEL_RX0; |
| 1309 | num_ports++; |
| 1310 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1311 | mux_reg_val = |
| 1312 | (snd_soc_component_read32(component, mux_reg) & |
| 1313 | 0xf0) >> 4; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1314 | mux_reg += 1; |
| 1315 | i--; |
| 1316 | } |
| 1317 | } |
| 1318 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1319 | dev_dbg(component->dev, "%s: num_ports: %d, ports[%d %d %d %d]\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1320 | __func__, num_ports, port_id[0], port_id[1], |
| 1321 | port_id[2], port_id[3]); |
| 1322 | |
| 1323 | i = 0; |
| 1324 | while (num_ports) { |
| 1325 | dai_id = rx_macro_find_playback_dai_id_for_port(port_id[i++], |
| 1326 | rx_priv); |
| 1327 | |
| 1328 | if ((dai_id >= 0) && (dai_id < RX_MACRO_MAX_DAIS)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1329 | dev_dbg(component->dev, "%s: dai_id: %d bit_width: %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1330 | __func__, dai_id, |
| 1331 | rx_priv->bit_width[dai_id]); |
| 1332 | |
| 1333 | if (rx_priv->bit_width[dai_id] > bit_width) |
| 1334 | bit_width = rx_priv->bit_width[dai_id]; |
| 1335 | } |
| 1336 | num_ports--; |
| 1337 | } |
| 1338 | |
| 1339 | switch (bit_width) { |
| 1340 | case 16: |
| 1341 | idle_thr = 0xff; /* F16 */ |
| 1342 | break; |
| 1343 | case 24: |
| 1344 | case 32: |
| 1345 | idle_thr = 0x03; /* F22 */ |
| 1346 | break; |
| 1347 | default: |
| 1348 | idle_thr = 0x00; |
| 1349 | break; |
| 1350 | } |
| 1351 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1352 | dev_dbg(component->dev, "%s: (new) idle_thr: %d, (cur) idle_thr: %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1353 | __func__, idle_thr, rx_priv->idle_det_cfg.hph_idle_thr); |
| 1354 | |
| 1355 | if ((rx_priv->idle_det_cfg.hph_idle_thr == 0) || |
| 1356 | (idle_thr < rx_priv->idle_det_cfg.hph_idle_thr)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1357 | snd_soc_component_write(component, |
| 1358 | BOLERO_CDC_RX_IDLE_DETECT_CFG3, idle_thr); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1359 | rx_priv->idle_det_cfg.hph_idle_thr = idle_thr; |
| 1360 | } |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, |
| 1366 | struct snd_kcontrol *kcontrol, int event) |
| 1367 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1368 | struct snd_soc_component *component = |
| 1369 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1370 | u16 gain_reg = 0, mix_reg = 0; |
| 1371 | struct device *rx_dev = NULL; |
| 1372 | struct rx_macro_priv *rx_priv = NULL; |
| 1373 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1374 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1375 | return -EINVAL; |
| 1376 | |
| 1377 | if (w->shift >= INTERP_MAX) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1378 | dev_err(component->dev, "%s: Invalid Interpolator value %d for name %s\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1379 | __func__, w->shift, w->name); |
| 1380 | return -EINVAL; |
| 1381 | } |
| 1382 | |
| 1383 | gain_reg = BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL + |
| 1384 | (w->shift * RX_MACRO_RX_PATH_OFFSET); |
| 1385 | mix_reg = BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL + |
| 1386 | (w->shift * RX_MACRO_RX_PATH_OFFSET); |
| 1387 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1388 | dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1389 | |
| 1390 | switch (event) { |
| 1391 | case SND_SOC_DAPM_PRE_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1392 | rx_macro_set_idle_detect_thr(component, rx_priv, w->shift, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1393 | INTERP_MIX_PATH); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1394 | rx_macro_enable_interp_clk(component, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1395 | /* Clk enable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1396 | snd_soc_component_update_bits(component, mix_reg, 0x20, 0x20); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1397 | break; |
| 1398 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1399 | snd_soc_component_write(component, gain_reg, |
| 1400 | snd_soc_component_read32(component, gain_reg)); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1401 | break; |
| 1402 | case SND_SOC_DAPM_POST_PMD: |
| 1403 | /* Clk Disable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1404 | snd_soc_component_update_bits(component, mix_reg, 0x20, 0x00); |
| 1405 | rx_macro_enable_interp_clk(component, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1406 | /* Reset enable and disable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1407 | snd_soc_component_update_bits(component, mix_reg, 0x40, 0x40); |
| 1408 | snd_soc_component_update_bits(component, mix_reg, 0x40, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1409 | break; |
| 1410 | } |
| 1411 | |
| 1412 | return 0; |
| 1413 | } |
| 1414 | |
| 1415 | static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, |
| 1416 | struct snd_kcontrol *kcontrol, |
| 1417 | int event) |
| 1418 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1419 | struct snd_soc_component *component = |
| 1420 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1421 | u16 gain_reg = 0; |
| 1422 | u16 reg = 0; |
| 1423 | struct device *rx_dev = NULL; |
| 1424 | struct rx_macro_priv *rx_priv = NULL; |
| 1425 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1426 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1427 | return -EINVAL; |
| 1428 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1429 | dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1430 | |
| 1431 | if (w->shift >= INTERP_MAX) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1432 | dev_err(component->dev, "%s: Invalid Interpolator value %d for name %s\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1433 | __func__, w->shift, w->name); |
| 1434 | return -EINVAL; |
| 1435 | } |
| 1436 | |
| 1437 | reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + (w->shift * |
| 1438 | RX_MACRO_RX_PATH_OFFSET); |
| 1439 | gain_reg = BOLERO_CDC_RX_RX0_RX_VOL_CTL + (w->shift * |
| 1440 | RX_MACRO_RX_PATH_OFFSET); |
| 1441 | |
| 1442 | switch (event) { |
| 1443 | case SND_SOC_DAPM_PRE_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1444 | rx_macro_set_idle_detect_thr(component, rx_priv, w->shift, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1445 | INTERP_MAIN_PATH); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1446 | rx_macro_enable_interp_clk(component, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1447 | break; |
| 1448 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1449 | snd_soc_component_write(component, gain_reg, |
| 1450 | snd_soc_component_read32(component, gain_reg)); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1451 | break; |
| 1452 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1453 | rx_macro_enable_interp_clk(component, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1454 | break; |
| 1455 | } |
| 1456 | |
| 1457 | return 0; |
| 1458 | } |
| 1459 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1460 | static int rx_macro_config_compander(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1461 | struct rx_macro_priv *rx_priv, |
| 1462 | int interp_n, int event) |
| 1463 | { |
| 1464 | int comp = 0; |
| 1465 | u16 comp_ctl0_reg = 0, rx_path_cfg0_reg = 0; |
| 1466 | |
| 1467 | /* AUX does not have compander */ |
| 1468 | if (interp_n == INTERP_AUX) |
| 1469 | return 0; |
| 1470 | |
| 1471 | comp = interp_n; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1472 | dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1473 | __func__, event, comp + 1, rx_priv->comp_enabled[comp]); |
| 1474 | |
| 1475 | if (!rx_priv->comp_enabled[comp]) |
| 1476 | return 0; |
| 1477 | |
| 1478 | comp_ctl0_reg = BOLERO_CDC_RX_COMPANDER0_CTL0 + |
| 1479 | (comp * RX_MACRO_COMP_OFFSET); |
| 1480 | rx_path_cfg0_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0 + |
| 1481 | (comp * RX_MACRO_RX_PATH_OFFSET); |
| 1482 | |
| 1483 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1484 | /* Enable Compander Clock */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1485 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1486 | 0x01, 0x01); |
| 1487 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1488 | 0x02, 0x02); |
| 1489 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1490 | 0x02, 0x00); |
| 1491 | snd_soc_component_update_bits(component, rx_path_cfg0_reg, |
| 1492 | 0x02, 0x02); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1493 | } |
| 1494 | |
| 1495 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1496 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1497 | 0x04, 0x04); |
| 1498 | snd_soc_component_update_bits(component, rx_path_cfg0_reg, |
| 1499 | 0x02, 0x00); |
| 1500 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1501 | 0x01, 0x00); |
| 1502 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1503 | 0x04, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1504 | } |
| 1505 | |
| 1506 | return 0; |
| 1507 | } |
| 1508 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1509 | static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1510 | struct rx_macro_priv *rx_priv, |
| 1511 | bool enable) |
| 1512 | { |
| 1513 | if (enable) { |
| 1514 | if (rx_priv->softclip_clk_users == 0) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1515 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1516 | BOLERO_CDC_RX_SOFTCLIP_CRC, |
| 1517 | 0x01, 0x01); |
| 1518 | rx_priv->softclip_clk_users++; |
| 1519 | } else { |
| 1520 | rx_priv->softclip_clk_users--; |
| 1521 | if (rx_priv->softclip_clk_users == 0) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1522 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1523 | BOLERO_CDC_RX_SOFTCLIP_CRC, |
| 1524 | 0x01, 0x00); |
| 1525 | } |
| 1526 | } |
| 1527 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1528 | static int rx_macro_config_softclip(struct snd_soc_component *component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1529 | struct rx_macro_priv *rx_priv, |
| 1530 | int event) |
| 1531 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1532 | dev_dbg(component->dev, "%s: event %d, enabled %d\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1533 | __func__, event, rx_priv->is_softclip_on); |
| 1534 | |
| 1535 | if (!rx_priv->is_softclip_on) |
| 1536 | return 0; |
| 1537 | |
| 1538 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1539 | /* Enable Softclip clock */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1540 | rx_macro_enable_softclip_clk(component, rx_priv, true); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1541 | /* Enable Softclip control */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1542 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1543 | BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x01, 0x01); |
| 1544 | } |
| 1545 | |
| 1546 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1547 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1548 | BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x01, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1549 | rx_macro_enable_softclip_clk(component, rx_priv, false); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1550 | } |
| 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1555 | static inline void |
| 1556 | rx_macro_enable_clsh_block(struct rx_macro_priv *rx_priv, bool enable) |
| 1557 | { |
| 1558 | if ((enable && ++rx_priv->clsh_users == 1) || |
| 1559 | (!enable && --rx_priv->clsh_users == 0)) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1560 | snd_soc_component_update_bits(rx_priv->component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1561 | BOLERO_CDC_RX_CLSH_CRC, 0x01, |
| 1562 | (u8) enable); |
| 1563 | if (rx_priv->clsh_users < 0) |
| 1564 | rx_priv->clsh_users = 0; |
| 1565 | dev_dbg(rx_priv->dev, "%s: clsh_users %d, enable %d", __func__, |
| 1566 | rx_priv->clsh_users, enable); |
| 1567 | } |
| 1568 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1569 | static int rx_macro_config_classh(struct snd_soc_component *component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1570 | struct rx_macro_priv *rx_priv, |
| 1571 | int interp_n, int event) |
| 1572 | { |
| 1573 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 1574 | rx_macro_enable_clsh_block(rx_priv, false); |
| 1575 | return 0; |
| 1576 | } |
| 1577 | |
| 1578 | if (!SND_SOC_DAPM_EVENT_ON(event)) |
| 1579 | return 0; |
| 1580 | |
| 1581 | rx_macro_enable_clsh_block(rx_priv, true); |
| 1582 | if (interp_n == INTERP_HPHL || |
| 1583 | interp_n == INTERP_HPHR) { |
| 1584 | /* |
| 1585 | * These K1 values depend on the Headphone Impedance |
| 1586 | * For now it is assumed to be 16 ohm |
| 1587 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1588 | snd_soc_component_update_bits(component, |
| 1589 | BOLERO_CDC_RX_CLSH_K1_LSB, |
| 1590 | 0xFF, 0xC0); |
| 1591 | snd_soc_component_update_bits(component, |
| 1592 | BOLERO_CDC_RX_CLSH_K1_MSB, |
| 1593 | 0x0F, 0x00); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1594 | } |
| 1595 | switch (interp_n) { |
| 1596 | case INTERP_HPHL: |
| 1597 | if (rx_priv->is_ear_mode_on) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1598 | snd_soc_component_update_bits(component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1599 | BOLERO_CDC_RX_CLSH_HPH_V_PA, |
| 1600 | 0x3F, 0x39); |
| 1601 | else |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1602 | snd_soc_component_update_bits(component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1603 | BOLERO_CDC_RX_CLSH_HPH_V_PA, |
| 1604 | 0x3F, 0x1C); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1605 | snd_soc_component_update_bits(component, |
| 1606 | BOLERO_CDC_RX_CLSH_DECAY_CTRL, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1607 | 0x07, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1608 | snd_soc_component_update_bits(component, |
| 1609 | BOLERO_CDC_RX_RX0_RX_PATH_CFG0, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1610 | 0x40, 0x40); |
| 1611 | break; |
| 1612 | case INTERP_HPHR: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1613 | snd_soc_component_update_bits(component, |
| 1614 | BOLERO_CDC_RX_CLSH_HPH_V_PA, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1615 | 0x3F, 0x1C); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1616 | snd_soc_component_update_bits(component, |
| 1617 | BOLERO_CDC_RX_CLSH_DECAY_CTRL, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1618 | 0x07, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1619 | snd_soc_component_update_bits(component, |
| 1620 | BOLERO_CDC_RX_RX1_RX_PATH_CFG0, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1621 | 0x40, 0x40); |
| 1622 | break; |
| 1623 | case INTERP_AUX: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1624 | snd_soc_component_update_bits(component, |
| 1625 | BOLERO_CDC_RX_RX2_RX_PATH_CFG0, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1626 | 0x10, 0x10); |
| 1627 | break; |
| 1628 | } |
| 1629 | |
| 1630 | return 0; |
| 1631 | } |
| 1632 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1633 | static void rx_macro_hd2_control(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1634 | u16 interp_idx, int event) |
| 1635 | { |
| 1636 | u16 hd2_scale_reg = 0; |
| 1637 | u16 hd2_enable_reg = 0; |
| 1638 | |
| 1639 | switch (interp_idx) { |
| 1640 | case INTERP_HPHL: |
Laxminath Kasam | 7adc34e | 2018-11-09 11:24:38 +0530 | [diff] [blame] | 1641 | hd2_scale_reg = BOLERO_CDC_RX_RX0_RX_PATH_SEC3; |
| 1642 | hd2_enable_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1643 | break; |
| 1644 | case INTERP_HPHR: |
Laxminath Kasam | 7adc34e | 2018-11-09 11:24:38 +0530 | [diff] [blame] | 1645 | hd2_scale_reg = BOLERO_CDC_RX_RX1_RX_PATH_SEC3; |
| 1646 | hd2_enable_reg = BOLERO_CDC_RX_RX1_RX_PATH_CFG0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1647 | break; |
| 1648 | } |
| 1649 | |
| 1650 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1651 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1652 | 0x3C, 0x14); |
| 1653 | snd_soc_component_update_bits(component, hd2_enable_reg, |
| 1654 | 0x04, 0x04); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1655 | } |
| 1656 | |
| 1657 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1658 | snd_soc_component_update_bits(component, hd2_enable_reg, |
| 1659 | 0x04, 0x00); |
| 1660 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1661 | 0x3C, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1662 | } |
| 1663 | } |
| 1664 | |
Vatsal Bucha | 8bcc97c | 2019-01-07 13:18:11 +0530 | [diff] [blame] | 1665 | static int rx_macro_hph_idle_detect_get(struct snd_kcontrol *kcontrol, |
| 1666 | struct snd_ctl_elem_value *ucontrol) |
| 1667 | { |
| 1668 | struct snd_soc_component *component = |
| 1669 | snd_soc_kcontrol_component(kcontrol); |
| 1670 | struct rx_macro_priv *rx_priv = NULL; |
| 1671 | struct device *rx_dev = NULL; |
| 1672 | |
| 1673 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
| 1674 | return -EINVAL; |
| 1675 | |
| 1676 | ucontrol->value.integer.value[0] = |
| 1677 | rx_priv->idle_det_cfg.hph_idle_detect_en; |
| 1678 | |
| 1679 | return 0; |
| 1680 | } |
| 1681 | |
| 1682 | static int rx_macro_hph_idle_detect_put(struct snd_kcontrol *kcontrol, |
| 1683 | struct snd_ctl_elem_value *ucontrol) |
| 1684 | { |
| 1685 | struct snd_soc_component *component = |
| 1686 | snd_soc_kcontrol_component(kcontrol); |
| 1687 | struct rx_macro_priv *rx_priv = NULL; |
| 1688 | struct device *rx_dev = NULL; |
| 1689 | |
| 1690 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
| 1691 | return -EINVAL; |
| 1692 | |
| 1693 | rx_priv->idle_det_cfg.hph_idle_detect_en = |
| 1694 | ucontrol->value.integer.value[0]; |
| 1695 | |
| 1696 | return 0; |
| 1697 | } |
| 1698 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1699 | static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, |
| 1700 | struct snd_ctl_elem_value *ucontrol) |
| 1701 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1702 | struct snd_soc_component *component = |
| 1703 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1704 | int comp = ((struct soc_multi_mixer_control *) |
| 1705 | kcontrol->private_value)->shift; |
| 1706 | struct device *rx_dev = NULL; |
| 1707 | struct rx_macro_priv *rx_priv = NULL; |
| 1708 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1709 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1710 | return -EINVAL; |
| 1711 | |
| 1712 | ucontrol->value.integer.value[0] = rx_priv->comp_enabled[comp]; |
| 1713 | return 0; |
| 1714 | } |
| 1715 | |
| 1716 | static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, |
| 1717 | struct snd_ctl_elem_value *ucontrol) |
| 1718 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1719 | struct snd_soc_component *component = |
| 1720 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1721 | int comp = ((struct soc_multi_mixer_control *) |
| 1722 | kcontrol->private_value)->shift; |
| 1723 | int value = ucontrol->value.integer.value[0]; |
| 1724 | struct device *rx_dev = NULL; |
| 1725 | struct rx_macro_priv *rx_priv = NULL; |
| 1726 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1727 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1728 | return -EINVAL; |
| 1729 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1730 | dev_dbg(component->dev, "%s: Compander %d enable current %d, new %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1731 | __func__, comp + 1, rx_priv->comp_enabled[comp], value); |
| 1732 | rx_priv->comp_enabled[comp] = value; |
| 1733 | |
| 1734 | return 0; |
| 1735 | } |
| 1736 | |
| 1737 | static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, |
| 1738 | struct snd_ctl_elem_value *ucontrol) |
| 1739 | { |
| 1740 | struct snd_soc_dapm_widget *widget = |
| 1741 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1742 | struct snd_soc_component *component = |
| 1743 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1744 | struct device *rx_dev = NULL; |
| 1745 | struct rx_macro_priv *rx_priv = NULL; |
| 1746 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1747 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1748 | return -EINVAL; |
| 1749 | |
| 1750 | ucontrol->value.integer.value[0] = |
| 1751 | rx_priv->rx_port_value[widget->shift]; |
| 1752 | return 0; |
| 1753 | } |
| 1754 | |
| 1755 | static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, |
| 1756 | struct snd_ctl_elem_value *ucontrol) |
| 1757 | { |
| 1758 | struct snd_soc_dapm_widget *widget = |
| 1759 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1760 | struct snd_soc_component *component = |
| 1761 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1762 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1763 | struct snd_soc_dapm_update *update = NULL; |
| 1764 | u32 rx_port_value = ucontrol->value.integer.value[0]; |
| 1765 | u32 aif_rst = 0; |
| 1766 | struct device *rx_dev = NULL; |
| 1767 | struct rx_macro_priv *rx_priv = NULL; |
| 1768 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1769 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1770 | return -EINVAL; |
| 1771 | |
| 1772 | aif_rst = rx_priv->rx_port_value[widget->shift]; |
| 1773 | if (!rx_port_value) { |
| 1774 | if (aif_rst == 0) { |
| 1775 | dev_err(rx_dev, "%s:AIF reset already\n", __func__); |
| 1776 | return 0; |
| 1777 | } |
| 1778 | } |
| 1779 | rx_priv->rx_port_value[widget->shift] = rx_port_value; |
| 1780 | |
| 1781 | switch (rx_port_value) { |
| 1782 | case 0: |
| 1783 | clear_bit(widget->shift, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1784 | &rx_priv->active_ch_mask[aif_rst]); |
| 1785 | rx_priv->active_ch_cnt[aif_rst]--; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1786 | break; |
| 1787 | case 1: |
| 1788 | case 2: |
| 1789 | case 3: |
| 1790 | case 4: |
| 1791 | set_bit(widget->shift, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1792 | &rx_priv->active_ch_mask[rx_port_value]); |
| 1793 | rx_priv->active_ch_cnt[rx_port_value]++; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1794 | break; |
| 1795 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1796 | dev_err(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 1797 | "%s:Invalid AIF_ID for RX_MACRO MUX\n", __func__); |
| 1798 | goto err; |
| 1799 | } |
| 1800 | |
| 1801 | snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, |
| 1802 | rx_port_value, e, update); |
| 1803 | return 0; |
| 1804 | err: |
| 1805 | return -EINVAL; |
| 1806 | } |
| 1807 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1808 | static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, |
| 1809 | struct snd_ctl_elem_value *ucontrol) |
| 1810 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1811 | struct snd_soc_component *component = |
| 1812 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1813 | struct device *rx_dev = NULL; |
| 1814 | struct rx_macro_priv *rx_priv = NULL; |
| 1815 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1816 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1817 | return -EINVAL; |
| 1818 | |
| 1819 | ucontrol->value.integer.value[0] = rx_priv->is_ear_mode_on; |
| 1820 | return 0; |
| 1821 | } |
| 1822 | |
| 1823 | static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, |
| 1824 | struct snd_ctl_elem_value *ucontrol) |
| 1825 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1826 | struct snd_soc_component *component = |
| 1827 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1828 | struct device *rx_dev = NULL; |
| 1829 | struct rx_macro_priv *rx_priv = NULL; |
| 1830 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1831 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 1832 | return -EINVAL; |
| 1833 | |
| 1834 | rx_priv->is_ear_mode_on = |
| 1835 | (!ucontrol->value.integer.value[0] ? false : true); |
| 1836 | return 0; |
| 1837 | } |
| 1838 | |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 1839 | static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, |
| 1840 | struct snd_ctl_elem_value *ucontrol) |
| 1841 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1842 | struct snd_soc_component *component = |
| 1843 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 1844 | struct device *rx_dev = NULL; |
| 1845 | struct rx_macro_priv *rx_priv = NULL; |
| 1846 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1847 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 1848 | return -EINVAL; |
| 1849 | |
| 1850 | ucontrol->value.integer.value[0] = rx_priv->hph_hd2_mode; |
| 1851 | return 0; |
| 1852 | } |
| 1853 | |
| 1854 | static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, |
| 1855 | struct snd_ctl_elem_value *ucontrol) |
| 1856 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1857 | struct snd_soc_component *component = |
| 1858 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 1859 | struct device *rx_dev = NULL; |
| 1860 | struct rx_macro_priv *rx_priv = NULL; |
| 1861 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1862 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 1863 | return -EINVAL; |
| 1864 | |
| 1865 | rx_priv->hph_hd2_mode = ucontrol->value.integer.value[0]; |
| 1866 | return 0; |
| 1867 | } |
| 1868 | |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 1869 | static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, |
| 1870 | struct snd_ctl_elem_value *ucontrol) |
| 1871 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1872 | struct snd_soc_component *component = |
| 1873 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 1874 | struct device *rx_dev = NULL; |
| 1875 | struct rx_macro_priv *rx_priv = NULL; |
| 1876 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1877 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 1878 | return -EINVAL; |
| 1879 | |
| 1880 | ucontrol->value.integer.value[0] = rx_priv->hph_pwr_mode; |
| 1881 | return 0; |
| 1882 | } |
| 1883 | |
| 1884 | static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, |
| 1885 | struct snd_ctl_elem_value *ucontrol) |
| 1886 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1887 | struct snd_soc_component *component = |
| 1888 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 1889 | struct device *rx_dev = NULL; |
| 1890 | struct rx_macro_priv *rx_priv = NULL; |
| 1891 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1892 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 1893 | return -EINVAL; |
| 1894 | |
| 1895 | rx_priv->hph_pwr_mode = ucontrol->value.integer.value[0]; |
| 1896 | return 0; |
| 1897 | } |
| 1898 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1899 | static int rx_macro_vbat_bcl_gsm_mode_func_get(struct snd_kcontrol *kcontrol, |
| 1900 | struct snd_ctl_elem_value *ucontrol) |
| 1901 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1902 | struct snd_soc_component *component = |
| 1903 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1904 | |
| 1905 | ucontrol->value.integer.value[0] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1906 | ((snd_soc_component_read32( |
| 1907 | component, BOLERO_CDC_RX_BCL_VBAT_CFG) & 0x04) ? |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1908 | 1 : 0); |
| 1909 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1910 | dev_dbg(component->dev, "%s: value: %lu\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1911 | ucontrol->value.integer.value[0]); |
| 1912 | |
| 1913 | return 0; |
| 1914 | } |
| 1915 | |
| 1916 | static int rx_macro_vbat_bcl_gsm_mode_func_put(struct snd_kcontrol *kcontrol, |
| 1917 | struct snd_ctl_elem_value *ucontrol) |
| 1918 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1919 | struct snd_soc_component *component = |
| 1920 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1921 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1922 | dev_dbg(component->dev, "%s: value: %lu\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1923 | ucontrol->value.integer.value[0]); |
| 1924 | |
| 1925 | /* Set Vbat register configuration for GSM mode bit based on value */ |
| 1926 | if (ucontrol->value.integer.value[0]) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1927 | snd_soc_component_update_bits(component, |
| 1928 | BOLERO_CDC_RX_BCL_VBAT_CFG, |
| 1929 | 0x04, 0x04); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1930 | else |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1931 | snd_soc_component_update_bits(component, |
| 1932 | BOLERO_CDC_RX_BCL_VBAT_CFG, |
| 1933 | 0x04, 0x00); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1934 | |
| 1935 | return 0; |
| 1936 | } |
| 1937 | |
| 1938 | static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, |
| 1939 | struct snd_ctl_elem_value *ucontrol) |
| 1940 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1941 | struct snd_soc_component *component = |
| 1942 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1943 | struct device *rx_dev = NULL; |
| 1944 | struct rx_macro_priv *rx_priv = NULL; |
| 1945 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1946 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1947 | return -EINVAL; |
| 1948 | |
| 1949 | ucontrol->value.integer.value[0] = rx_priv->is_softclip_on; |
| 1950 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1951 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1952 | __func__, ucontrol->value.integer.value[0]); |
| 1953 | |
| 1954 | return 0; |
| 1955 | } |
| 1956 | |
| 1957 | static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, |
| 1958 | struct snd_ctl_elem_value *ucontrol) |
| 1959 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1960 | struct snd_soc_component *component = |
| 1961 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1962 | struct device *rx_dev = NULL; |
| 1963 | struct rx_macro_priv *rx_priv = NULL; |
| 1964 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1965 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1966 | return -EINVAL; |
| 1967 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1968 | rx_priv->is_softclip_on = ucontrol->value.integer.value[0]; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1969 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1970 | dev_dbg(component->dev, "%s: soft clip enable = %d\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1971 | rx_priv->is_softclip_on); |
| 1972 | |
| 1973 | return 0; |
| 1974 | } |
| 1975 | |
| 1976 | static int rx_macro_enable_vbat(struct snd_soc_dapm_widget *w, |
| 1977 | struct snd_kcontrol *kcontrol, |
| 1978 | int event) |
| 1979 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1980 | struct snd_soc_component *component = |
| 1981 | snd_soc_dapm_to_component(w->dapm); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1982 | struct device *rx_dev = NULL; |
| 1983 | struct rx_macro_priv *rx_priv = NULL; |
| 1984 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1985 | dev_dbg(component->dev, "%s %s %d\n", __func__, w->name, event); |
| 1986 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1987 | return -EINVAL; |
| 1988 | |
| 1989 | switch (event) { |
| 1990 | case SND_SOC_DAPM_PRE_PMU: |
| 1991 | /* Enable clock for VBAT block */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1992 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1993 | BOLERO_CDC_RX_BCL_VBAT_PATH_CTL, 0x10, 0x10); |
| 1994 | /* Enable VBAT block */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1995 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1996 | BOLERO_CDC_RX_BCL_VBAT_CFG, 0x01, 0x01); |
| 1997 | /* Update interpolator with 384K path */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1998 | snd_soc_component_update_bits(component, |
| 1999 | BOLERO_CDC_RX_RX2_RX_PATH_CFG1, 0x80, 0x80); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2000 | /* Update DSM FS rate */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2001 | snd_soc_component_update_bits(component, |
| 2002 | BOLERO_CDC_RX_RX2_RX_PATH_SEC7, 0x02, 0x02); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2003 | /* Use attenuation mode */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2004 | snd_soc_component_update_bits(component, |
| 2005 | BOLERO_CDC_RX_BCL_VBAT_CFG, 0x02, 0x00); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2006 | /* BCL block needs softclip clock to be enabled */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2007 | rx_macro_enable_softclip_clk(component, rx_priv, true); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2008 | /* Enable VBAT at channel level */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2009 | snd_soc_component_update_bits(component, |
| 2010 | BOLERO_CDC_RX_RX2_RX_PATH_CFG1, 0x02, 0x02); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2011 | /* Set the ATTK1 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2012 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2013 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, |
| 2014 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2015 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2016 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, |
| 2017 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2018 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2019 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, |
| 2020 | 0xFF, 0x00); |
| 2021 | /* Set the ATTK2 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2022 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2023 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, |
| 2024 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2025 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2026 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, |
| 2027 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2028 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2029 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, |
| 2030 | 0xFF, 0x00); |
| 2031 | /* Set the ATTK3 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2032 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2033 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, |
| 2034 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2035 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2036 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, |
| 2037 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2038 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2039 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, |
| 2040 | 0xFF, 0x00); |
| 2041 | break; |
| 2042 | |
| 2043 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2044 | snd_soc_component_update_bits(component, |
| 2045 | BOLERO_CDC_RX_RX2_RX_PATH_CFG1, |
| 2046 | 0x80, 0x00); |
| 2047 | snd_soc_component_update_bits(component, |
| 2048 | BOLERO_CDC_RX_RX2_RX_PATH_SEC7, |
| 2049 | 0x02, 0x00); |
| 2050 | snd_soc_component_update_bits(component, |
| 2051 | BOLERO_CDC_RX_BCL_VBAT_CFG, |
| 2052 | 0x02, 0x02); |
| 2053 | snd_soc_component_update_bits(component, |
| 2054 | BOLERO_CDC_RX_RX2_RX_PATH_CFG1, |
| 2055 | 0x02, 0x00); |
| 2056 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2057 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, |
| 2058 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2059 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2060 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, |
| 2061 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2062 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2063 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, |
| 2064 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2065 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2066 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, |
| 2067 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2068 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2069 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, |
| 2070 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2071 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2072 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, |
| 2073 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2074 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2075 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, |
| 2076 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2077 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2078 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, |
| 2079 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2080 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2081 | BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, |
| 2082 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2083 | rx_macro_enable_softclip_clk(component, rx_priv, false); |
| 2084 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2085 | BOLERO_CDC_RX_BCL_VBAT_CFG, 0x01, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2086 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2087 | BOLERO_CDC_RX_BCL_VBAT_PATH_CTL, 0x10, 0x00); |
| 2088 | break; |
| 2089 | default: |
| 2090 | dev_err(rx_dev, "%s: Invalid event %d\n", __func__, event); |
| 2091 | break; |
| 2092 | } |
| 2093 | return 0; |
| 2094 | } |
| 2095 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2096 | static void rx_macro_idle_detect_control(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2097 | struct rx_macro_priv *rx_priv, |
| 2098 | int interp, int event) |
| 2099 | { |
| 2100 | int reg = 0, mask = 0, val = 0; |
| 2101 | |
| 2102 | if (!rx_priv->idle_det_cfg.hph_idle_detect_en) |
| 2103 | return; |
| 2104 | |
| 2105 | if (interp == INTERP_HPHL) { |
| 2106 | reg = BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL; |
| 2107 | mask = 0x01; |
| 2108 | val = 0x01; |
| 2109 | } |
| 2110 | if (interp == INTERP_HPHR) { |
| 2111 | reg = BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL; |
| 2112 | mask = 0x02; |
| 2113 | val = 0x02; |
| 2114 | } |
| 2115 | |
| 2116 | if (reg && SND_SOC_DAPM_EVENT_ON(event)) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2117 | snd_soc_component_update_bits(component, reg, mask, val); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2118 | |
| 2119 | if (reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2120 | snd_soc_component_update_bits(component, reg, mask, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2121 | rx_priv->idle_det_cfg.hph_idle_thr = 0; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2122 | snd_soc_component_write(component, |
| 2123 | BOLERO_CDC_RX_IDLE_DETECT_CFG3, 0x0); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2124 | } |
| 2125 | } |
| 2126 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2127 | static void rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2128 | struct rx_macro_priv *rx_priv, |
| 2129 | u16 interp_idx, int event) |
| 2130 | { |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2131 | u16 hph_lut_bypass_reg = 0; |
| 2132 | u16 hph_comp_ctrl7 = 0; |
| 2133 | |
| 2134 | switch (interp_idx) { |
| 2135 | case INTERP_HPHL: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2136 | hph_lut_bypass_reg = BOLERO_CDC_RX_TOP_HPHL_COMP_LUT; |
| 2137 | hph_comp_ctrl7 = BOLERO_CDC_RX_COMPANDER0_CTL7; |
| 2138 | break; |
| 2139 | case INTERP_HPHR: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2140 | hph_lut_bypass_reg = BOLERO_CDC_RX_TOP_HPHR_COMP_LUT; |
| 2141 | hph_comp_ctrl7 = BOLERO_CDC_RX_COMPANDER1_CTL7; |
| 2142 | break; |
| 2143 | default: |
| 2144 | break; |
| 2145 | } |
| 2146 | |
| 2147 | if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_ON(event)) { |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2148 | if (interp_idx == INTERP_HPHL) { |
| 2149 | if (rx_priv->is_ear_mode_on) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2150 | snd_soc_component_update_bits(component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2151 | BOLERO_CDC_RX_RX0_RX_PATH_CFG1, |
| 2152 | 0x02, 0x02); |
| 2153 | else |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2154 | snd_soc_component_update_bits(component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2155 | hph_lut_bypass_reg, |
| 2156 | 0x80, 0x80); |
| 2157 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2158 | snd_soc_component_update_bits(component, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2159 | hph_lut_bypass_reg, |
| 2160 | 0x80, 0x80); |
| 2161 | } |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 2162 | if (rx_priv->hph_pwr_mode) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2163 | snd_soc_component_update_bits(component, |
| 2164 | hph_comp_ctrl7, |
| 2165 | 0x20, 0x00); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2166 | } |
| 2167 | |
| 2168 | if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2169 | snd_soc_component_update_bits(component, |
| 2170 | BOLERO_CDC_RX_RX0_RX_PATH_CFG1, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2171 | 0x02, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2172 | snd_soc_component_update_bits(component, hph_lut_bypass_reg, |
| 2173 | 0x80, 0x00); |
| 2174 | snd_soc_component_update_bits(component, hph_comp_ctrl7, |
| 2175 | 0x20, 0x0); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2176 | } |
| 2177 | } |
| 2178 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2179 | static int rx_macro_enable_interp_clk(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2180 | int event, int interp_idx) |
| 2181 | { |
Laxminath Kasam | 35849cc | 2018-11-14 20:36:08 +0530 | [diff] [blame] | 2182 | u16 main_reg = 0, dsm_reg = 0, rx_cfg2_reg = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2183 | struct device *rx_dev = NULL; |
| 2184 | struct rx_macro_priv *rx_priv = NULL; |
| 2185 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2186 | if (!component) { |
| 2187 | pr_err("%s: component is NULL\n", __func__); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2188 | return -EINVAL; |
| 2189 | } |
| 2190 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2191 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2192 | return -EINVAL; |
| 2193 | |
| 2194 | main_reg = BOLERO_CDC_RX_RX0_RX_PATH_CTL + |
| 2195 | (interp_idx * RX_MACRO_RX_PATH_OFFSET); |
Laxminath Kasam | 35849cc | 2018-11-14 20:36:08 +0530 | [diff] [blame] | 2196 | dsm_reg = BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL + |
| 2197 | (interp_idx * RX_MACRO_RX_PATH_OFFSET); |
| 2198 | rx_cfg2_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG2 + |
| 2199 | (interp_idx * RX_MACRO_RX_PATH_OFFSET); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2200 | |
| 2201 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 2202 | if (rx_priv->main_clk_users[interp_idx] == 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2203 | snd_soc_component_update_bits(component, dsm_reg, |
| 2204 | 0x01, 0x01); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2205 | /* Main path PGA mute enable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2206 | snd_soc_component_update_bits(component, main_reg, |
| 2207 | 0x10, 0x10); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2208 | /* Clk enable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2209 | snd_soc_component_update_bits(component, main_reg, |
| 2210 | 0x20, 0x20); |
| 2211 | snd_soc_component_update_bits(component, rx_cfg2_reg, |
| 2212 | 0x03, 0x03); |
| 2213 | rx_macro_idle_detect_control(component, rx_priv, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2214 | interp_idx, event); |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 2215 | if (rx_priv->hph_hd2_mode) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2216 | rx_macro_hd2_control( |
| 2217 | component, interp_idx, event); |
| 2218 | rx_macro_hphdelay_lutbypass(component, rx_priv, |
| 2219 | interp_idx, event); |
| 2220 | rx_macro_config_compander(component, rx_priv, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2221 | interp_idx, event); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2222 | if (interp_idx == INTERP_AUX) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2223 | rx_macro_config_softclip(component, rx_priv, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2224 | event); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2225 | rx_macro_config_classh(component, rx_priv, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2226 | interp_idx, event); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2227 | } |
| 2228 | rx_priv->main_clk_users[interp_idx]++; |
| 2229 | } |
| 2230 | |
| 2231 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
| 2232 | rx_priv->main_clk_users[interp_idx]--; |
| 2233 | if (rx_priv->main_clk_users[interp_idx] <= 0) { |
| 2234 | rx_priv->main_clk_users[interp_idx] = 0; |
Laxminath Kasam | 35849cc | 2018-11-14 20:36:08 +0530 | [diff] [blame] | 2235 | /* Clk Disable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2236 | snd_soc_component_update_bits(component, dsm_reg, |
| 2237 | 0x01, 0x00); |
| 2238 | snd_soc_component_update_bits(component, main_reg, |
| 2239 | 0x20, 0x00); |
Laxminath Kasam | 35849cc | 2018-11-14 20:36:08 +0530 | [diff] [blame] | 2240 | /* Reset enable and disable */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2241 | snd_soc_component_update_bits(component, main_reg, |
| 2242 | 0x40, 0x40); |
| 2243 | snd_soc_component_update_bits(component, main_reg, |
| 2244 | 0x40, 0x00); |
Laxminath Kasam | 35849cc | 2018-11-14 20:36:08 +0530 | [diff] [blame] | 2245 | /* Reset rate to 48K*/ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2246 | snd_soc_component_update_bits(component, main_reg, |
| 2247 | 0x0F, 0x04); |
| 2248 | snd_soc_component_update_bits(component, rx_cfg2_reg, |
| 2249 | 0x03, 0x00); |
| 2250 | rx_macro_config_classh(component, rx_priv, |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2251 | interp_idx, event); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2252 | rx_macro_config_compander(component, rx_priv, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2253 | interp_idx, event); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2254 | if (interp_idx == INTERP_AUX) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2255 | rx_macro_config_softclip(component, rx_priv, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2256 | event); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2257 | rx_macro_hphdelay_lutbypass(component, rx_priv, |
| 2258 | interp_idx, event); |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 2259 | if (rx_priv->hph_hd2_mode) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2260 | rx_macro_hd2_control(component, interp_idx, |
| 2261 | event); |
| 2262 | rx_macro_idle_detect_control(component, rx_priv, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2263 | interp_idx, event); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2264 | } |
| 2265 | } |
| 2266 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2267 | dev_dbg(component->dev, "%s event %d main_clk_users %d\n", |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2268 | __func__, event, rx_priv->main_clk_users[interp_idx]); |
| 2269 | |
| 2270 | return rx_priv->main_clk_users[interp_idx]; |
| 2271 | } |
| 2272 | |
| 2273 | static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, |
| 2274 | struct snd_kcontrol *kcontrol, int event) |
| 2275 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2276 | struct snd_soc_component *component = |
| 2277 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2278 | u16 sidetone_reg = 0; |
| 2279 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2280 | dev_dbg(component->dev, "%s %d %d\n", __func__, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2281 | sidetone_reg = BOLERO_CDC_RX_RX0_RX_PATH_CFG1 + |
| 2282 | RX_MACRO_RX_PATH_OFFSET * (w->shift); |
| 2283 | |
| 2284 | switch (event) { |
| 2285 | case SND_SOC_DAPM_PRE_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2286 | rx_macro_enable_interp_clk(component, event, w->shift); |
| 2287 | snd_soc_component_update_bits(component, sidetone_reg, |
| 2288 | 0x10, 0x10); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2289 | break; |
| 2290 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2291 | snd_soc_component_update_bits(component, sidetone_reg, |
| 2292 | 0x10, 0x00); |
| 2293 | rx_macro_enable_interp_clk(component, event, w->shift); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2294 | break; |
| 2295 | default: |
| 2296 | break; |
| 2297 | }; |
| 2298 | return 0; |
| 2299 | } |
| 2300 | |
| 2301 | static void rx_macro_restore_iir_coeff(struct rx_macro_priv *rx_priv, int iir_idx, |
| 2302 | int band_idx) |
| 2303 | { |
| 2304 | u16 reg_add = 0, coeff_idx = 0, idx = 0; |
| 2305 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
| 2306 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 2307 | if (regmap == NULL) { |
| 2308 | dev_err(rx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 2309 | return; |
| 2310 | } |
| 2311 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2312 | regmap_write(regmap, |
| 2313 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 2314 | (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); |
| 2315 | |
| 2316 | reg_add = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; |
| 2317 | |
| 2318 | /* 5 coefficients per band and 4 writes per coefficient */ |
| 2319 | for (coeff_idx = 0; coeff_idx < RX_MACRO_SIDETONE_IIR_COEFF_MAX; |
| 2320 | coeff_idx++) { |
| 2321 | /* Four 8 bit values(one 32 bit) per coefficient */ |
| 2322 | regmap_write(regmap, reg_add, |
| 2323 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 2324 | regmap_write(regmap, reg_add, |
| 2325 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 2326 | regmap_write(regmap, reg_add, |
| 2327 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 2328 | regmap_write(regmap, reg_add, |
| 2329 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++]); |
| 2330 | } |
| 2331 | } |
| 2332 | |
| 2333 | static int rx_macro_iir_enable_audio_mixer_get(struct snd_kcontrol *kcontrol, |
| 2334 | struct snd_ctl_elem_value *ucontrol) |
| 2335 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2336 | struct snd_soc_component *component = |
| 2337 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2338 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 2339 | kcontrol->private_value)->reg; |
| 2340 | int band_idx = ((struct soc_multi_mixer_control *) |
| 2341 | kcontrol->private_value)->shift; |
| 2342 | /* IIR filter band registers are at integer multiples of 0x80 */ |
| 2343 | u16 iir_reg = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL + 0x80 * iir_idx; |
| 2344 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2345 | ucontrol->value.integer.value[0] = ( |
| 2346 | snd_soc_component_read32(component, iir_reg) & |
| 2347 | (1 << band_idx)) != 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2348 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2349 | dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2350 | iir_idx, band_idx, |
| 2351 | (uint32_t)ucontrol->value.integer.value[0]); |
| 2352 | return 0; |
| 2353 | } |
| 2354 | |
| 2355 | static int rx_macro_iir_enable_audio_mixer_put(struct snd_kcontrol *kcontrol, |
| 2356 | struct snd_ctl_elem_value *ucontrol) |
| 2357 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2358 | struct snd_soc_component *component = |
| 2359 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2360 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 2361 | kcontrol->private_value)->reg; |
| 2362 | int band_idx = ((struct soc_multi_mixer_control *) |
| 2363 | kcontrol->private_value)->shift; |
| 2364 | bool iir_band_en_status = 0; |
| 2365 | int value = ucontrol->value.integer.value[0]; |
| 2366 | u16 iir_reg = BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL + 0x80 * iir_idx; |
| 2367 | struct device *rx_dev = NULL; |
| 2368 | struct rx_macro_priv *rx_priv = NULL; |
| 2369 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2370 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2371 | return -EINVAL; |
| 2372 | |
| 2373 | rx_macro_restore_iir_coeff(rx_priv, iir_idx, band_idx); |
| 2374 | |
| 2375 | /* Mask first 5 bits, 6-8 are reserved */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2376 | snd_soc_component_update_bits(component, iir_reg, (1 << band_idx), |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2377 | (value << band_idx)); |
| 2378 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2379 | iir_band_en_status = ((snd_soc_component_read32(component, iir_reg) & |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2380 | (1 << band_idx)) != 0); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2381 | dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2382 | iir_idx, band_idx, iir_band_en_status); |
| 2383 | return 0; |
| 2384 | } |
| 2385 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2386 | static uint32_t get_iir_band_coeff(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2387 | int iir_idx, int band_idx, |
| 2388 | int coeff_idx) |
| 2389 | { |
| 2390 | uint32_t value = 0; |
| 2391 | |
| 2392 | /* Address does not automatically update if reading */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2393 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2394 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 2395 | ((band_idx * BAND_MAX + coeff_idx) |
| 2396 | * sizeof(uint32_t)) & 0x7F); |
| 2397 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2398 | value |= snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2399 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx)); |
| 2400 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2401 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2402 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 2403 | ((band_idx * BAND_MAX + coeff_idx) |
| 2404 | * sizeof(uint32_t) + 1) & 0x7F); |
| 2405 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2406 | value |= (snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2407 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 2408 | 0x80 * iir_idx)) << 8); |
| 2409 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2410 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2411 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 2412 | ((band_idx * BAND_MAX + coeff_idx) |
| 2413 | * sizeof(uint32_t) + 2) & 0x7F); |
| 2414 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2415 | value |= (snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2416 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 2417 | 0x80 * iir_idx)) << 16); |
| 2418 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2419 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2420 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx), |
| 2421 | ((band_idx * BAND_MAX + coeff_idx) |
| 2422 | * sizeof(uint32_t) + 3) & 0x7F); |
| 2423 | |
| 2424 | /* Mask bits top 2 bits since they are reserved */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2425 | value |= ((snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2426 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + |
| 2427 | 16 * iir_idx)) & 0x3F) << 24); |
| 2428 | |
| 2429 | return value; |
| 2430 | } |
| 2431 | |
| 2432 | static int rx_macro_iir_band_audio_mixer_get(struct snd_kcontrol *kcontrol, |
| 2433 | struct snd_ctl_elem_value *ucontrol) |
| 2434 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2435 | struct snd_soc_component *component = |
| 2436 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2437 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 2438 | kcontrol->private_value)->reg; |
| 2439 | int band_idx = ((struct soc_multi_mixer_control *) |
| 2440 | kcontrol->private_value)->shift; |
| 2441 | |
| 2442 | ucontrol->value.integer.value[0] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2443 | get_iir_band_coeff(component, iir_idx, band_idx, 0); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2444 | ucontrol->value.integer.value[1] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2445 | get_iir_band_coeff(component, iir_idx, band_idx, 1); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2446 | ucontrol->value.integer.value[2] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2447 | get_iir_band_coeff(component, iir_idx, band_idx, 2); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2448 | ucontrol->value.integer.value[3] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2449 | get_iir_band_coeff(component, iir_idx, band_idx, 3); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2450 | ucontrol->value.integer.value[4] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2451 | get_iir_band_coeff(component, iir_idx, band_idx, 4); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2452 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2453 | dev_dbg(component->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2454 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 2455 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 2456 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 2457 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 2458 | __func__, iir_idx, band_idx, |
| 2459 | (uint32_t)ucontrol->value.integer.value[0], |
| 2460 | __func__, iir_idx, band_idx, |
| 2461 | (uint32_t)ucontrol->value.integer.value[1], |
| 2462 | __func__, iir_idx, band_idx, |
| 2463 | (uint32_t)ucontrol->value.integer.value[2], |
| 2464 | __func__, iir_idx, band_idx, |
| 2465 | (uint32_t)ucontrol->value.integer.value[3], |
| 2466 | __func__, iir_idx, band_idx, |
| 2467 | (uint32_t)ucontrol->value.integer.value[4]); |
| 2468 | return 0; |
| 2469 | } |
| 2470 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2471 | static void set_iir_band_coeff(struct snd_soc_component *component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2472 | int iir_idx, int band_idx, |
| 2473 | uint32_t value) |
| 2474 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2475 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2476 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 2477 | (value & 0xFF)); |
| 2478 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2479 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2480 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 2481 | (value >> 8) & 0xFF); |
| 2482 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2483 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2484 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 2485 | (value >> 16) & 0xFF); |
| 2486 | |
| 2487 | /* Mask top 2 bits, 7-8 are reserved */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2488 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2489 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx), |
| 2490 | (value >> 24) & 0x3F); |
| 2491 | } |
| 2492 | |
| 2493 | static int rx_macro_iir_band_audio_mixer_put(struct snd_kcontrol *kcontrol, |
| 2494 | struct snd_ctl_elem_value *ucontrol) |
| 2495 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2496 | struct snd_soc_component *component = |
| 2497 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2498 | int iir_idx = ((struct soc_multi_mixer_control *) |
| 2499 | kcontrol->private_value)->reg; |
| 2500 | int band_idx = ((struct soc_multi_mixer_control *) |
| 2501 | kcontrol->private_value)->shift; |
| 2502 | int coeff_idx, idx = 0; |
| 2503 | struct device *rx_dev = NULL; |
| 2504 | struct rx_macro_priv *rx_priv = NULL; |
| 2505 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2506 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2507 | return -EINVAL; |
| 2508 | |
| 2509 | /* |
| 2510 | * Mask top bit it is reserved |
| 2511 | * Updates addr automatically for each B2 write |
| 2512 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2513 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2514 | (BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx), |
| 2515 | (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); |
| 2516 | |
| 2517 | /* Store the coefficients in sidetone coeff array */ |
| 2518 | for (coeff_idx = 0; coeff_idx < RX_MACRO_SIDETONE_IIR_COEFF_MAX; |
| 2519 | coeff_idx++) { |
| 2520 | uint32_t value = ucontrol->value.integer.value[coeff_idx]; |
| 2521 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2522 | set_iir_band_coeff(component, iir_idx, band_idx, value); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2523 | |
| 2524 | /* Four 8 bit values(one 32 bit) per coefficient */ |
| 2525 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 2526 | (value & 0xFF); |
| 2527 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 2528 | (value >> 8) & 0xFF; |
| 2529 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 2530 | (value >> 16) & 0xFF; |
| 2531 | rx_priv->sidetone_coeff_array[iir_idx][band_idx][idx++] = |
| 2532 | (value >> 24) & 0xFF; |
| 2533 | } |
| 2534 | |
| 2535 | pr_debug("%s: IIR #%d band #%d b0 = 0x%x\n" |
| 2536 | "%s: IIR #%d band #%d b1 = 0x%x\n" |
| 2537 | "%s: IIR #%d band #%d b2 = 0x%x\n" |
| 2538 | "%s: IIR #%d band #%d a1 = 0x%x\n" |
| 2539 | "%s: IIR #%d band #%d a2 = 0x%x\n", |
| 2540 | __func__, iir_idx, band_idx, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2541 | get_iir_band_coeff(component, iir_idx, band_idx, 0), |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2542 | __func__, iir_idx, band_idx, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2543 | get_iir_band_coeff(component, iir_idx, band_idx, 1), |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2544 | __func__, iir_idx, band_idx, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2545 | get_iir_band_coeff(component, iir_idx, band_idx, 2), |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2546 | __func__, iir_idx, band_idx, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2547 | get_iir_band_coeff(component, iir_idx, band_idx, 3), |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2548 | __func__, iir_idx, band_idx, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2549 | get_iir_band_coeff(component, iir_idx, band_idx, 4)); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2550 | return 0; |
| 2551 | } |
| 2552 | |
| 2553 | static int rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w, |
| 2554 | struct snd_kcontrol *kcontrol, int event) |
| 2555 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2556 | struct snd_soc_component *component = |
| 2557 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2558 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2559 | dev_dbg(component->dev, "%s: event = %d\n", __func__, event); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2560 | |
| 2561 | switch (event) { |
| 2562 | case SND_SOC_DAPM_POST_PMU: /* fall through */ |
| 2563 | case SND_SOC_DAPM_PRE_PMD: |
| 2564 | if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2565 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2566 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2567 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2568 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2569 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2570 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2571 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2572 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2573 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2574 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2575 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2576 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2577 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2578 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2579 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2580 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL)); |
| 2581 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2582 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2583 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2584 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2585 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2586 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2587 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2588 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2589 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2590 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2591 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2592 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2593 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2594 | snd_soc_component_write(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2595 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2596 | snd_soc_component_read32(component, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2597 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL)); |
| 2598 | } |
| 2599 | break; |
| 2600 | } |
| 2601 | return 0; |
| 2602 | } |
| 2603 | |
| 2604 | static const struct snd_kcontrol_new rx_macro_snd_controls[] = { |
| 2605 | SOC_SINGLE_SX_TLV("RX_RX0 Digital Volume", |
| 2606 | BOLERO_CDC_RX_RX0_RX_VOL_CTL, |
| 2607 | 0, -84, 40, digital_gain), |
| 2608 | SOC_SINGLE_SX_TLV("RX_RX1 Digital Volume", |
| 2609 | BOLERO_CDC_RX_RX1_RX_VOL_CTL, |
| 2610 | 0, -84, 40, digital_gain), |
| 2611 | SOC_SINGLE_SX_TLV("RX_RX2 Digital Volume", |
| 2612 | BOLERO_CDC_RX_RX2_RX_VOL_CTL, |
| 2613 | 0, -84, 40, digital_gain), |
| 2614 | SOC_SINGLE_SX_TLV("RX_RX0 Mix Digital Volume", |
| 2615 | BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 2616 | SOC_SINGLE_SX_TLV("RX_RX1 Mix Digital Volume", |
| 2617 | BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 2618 | SOC_SINGLE_SX_TLV("RX_RX2 Mix Digital Volume", |
| 2619 | BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), |
| 2620 | |
| 2621 | SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0, |
| 2622 | rx_macro_get_compander, rx_macro_set_compander), |
| 2623 | SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0, |
| 2624 | rx_macro_get_compander, rx_macro_set_compander), |
| 2625 | |
Vatsal Bucha | 8bcc97c | 2019-01-07 13:18:11 +0530 | [diff] [blame] | 2626 | SOC_ENUM_EXT("HPH Idle Detect", hph_idle_detect_enum, |
| 2627 | rx_macro_hph_idle_detect_get, rx_macro_hph_idle_detect_put), |
| 2628 | |
Laxminath Kasam | d2d8d9f | 2018-08-06 18:10:14 +0530 | [diff] [blame] | 2629 | SOC_ENUM_EXT("RX_EAR Mode", rx_macro_ear_mode_enum, |
| 2630 | rx_macro_get_ear_mode, rx_macro_put_ear_mode), |
| 2631 | |
Laxminath Kasam | d3ffb33 | 2018-11-14 19:59:21 +0530 | [diff] [blame] | 2632 | SOC_ENUM_EXT("RX_HPH HD2 Mode", rx_macro_hph_hd2_mode_enum, |
| 2633 | rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode), |
| 2634 | |
Laxminath Kasam | de09dfb | 2018-11-09 13:00:30 +0530 | [diff] [blame] | 2635 | SOC_ENUM_EXT("RX_HPH_PWR_MODE", rx_macro_hph_pwr_mode_enum, |
| 2636 | rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode), |
| 2637 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2638 | SOC_ENUM_EXT("RX_GSM mode Enable", rx_macro_vbat_bcl_gsm_mode_enum, |
| 2639 | rx_macro_vbat_bcl_gsm_mode_func_get, |
| 2640 | rx_macro_vbat_bcl_gsm_mode_func_put), |
| 2641 | SOC_SINGLE_EXT("RX_Softclip Enable", SND_SOC_NOPM, 0, 1, 0, |
| 2642 | rx_macro_soft_clip_enable_get, |
| 2643 | rx_macro_soft_clip_enable_put), |
| 2644 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2645 | SOC_SINGLE_SX_TLV("IIR0 INP0 Volume", |
| 2646 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0, -84, 40, |
| 2647 | digital_gain), |
| 2648 | SOC_SINGLE_SX_TLV("IIR0 INP1 Volume", |
| 2649 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0, -84, 40, |
| 2650 | digital_gain), |
| 2651 | SOC_SINGLE_SX_TLV("IIR0 INP2 Volume", |
| 2652 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0, -84, 40, |
| 2653 | digital_gain), |
| 2654 | SOC_SINGLE_SX_TLV("IIR0 INP3 Volume", |
| 2655 | BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0, -84, 40, |
| 2656 | digital_gain), |
| 2657 | SOC_SINGLE_SX_TLV("IIR1 INP0 Volume", |
| 2658 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0, -84, 40, |
| 2659 | digital_gain), |
| 2660 | SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", |
| 2661 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0, -84, 40, |
| 2662 | digital_gain), |
| 2663 | SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", |
| 2664 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0, -84, 40, |
| 2665 | digital_gain), |
| 2666 | SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", |
| 2667 | BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0, -84, 40, |
| 2668 | digital_gain), |
| 2669 | |
| 2670 | SOC_SINGLE_EXT("IIR0 Enable Band1", IIR0, BAND1, 1, 0, |
| 2671 | rx_macro_iir_enable_audio_mixer_get, |
| 2672 | rx_macro_iir_enable_audio_mixer_put), |
| 2673 | SOC_SINGLE_EXT("IIR0 Enable Band2", IIR0, BAND2, 1, 0, |
| 2674 | rx_macro_iir_enable_audio_mixer_get, |
| 2675 | rx_macro_iir_enable_audio_mixer_put), |
| 2676 | SOC_SINGLE_EXT("IIR0 Enable Band3", IIR0, BAND3, 1, 0, |
| 2677 | rx_macro_iir_enable_audio_mixer_get, |
| 2678 | rx_macro_iir_enable_audio_mixer_put), |
| 2679 | SOC_SINGLE_EXT("IIR0 Enable Band4", IIR0, BAND4, 1, 0, |
| 2680 | rx_macro_iir_enable_audio_mixer_get, |
| 2681 | rx_macro_iir_enable_audio_mixer_put), |
| 2682 | SOC_SINGLE_EXT("IIR0 Enable Band5", IIR0, BAND5, 1, 0, |
| 2683 | rx_macro_iir_enable_audio_mixer_get, |
| 2684 | rx_macro_iir_enable_audio_mixer_put), |
| 2685 | SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, |
| 2686 | rx_macro_iir_enable_audio_mixer_get, |
| 2687 | rx_macro_iir_enable_audio_mixer_put), |
| 2688 | SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, |
| 2689 | rx_macro_iir_enable_audio_mixer_get, |
| 2690 | rx_macro_iir_enable_audio_mixer_put), |
| 2691 | SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, |
| 2692 | rx_macro_iir_enable_audio_mixer_get, |
| 2693 | rx_macro_iir_enable_audio_mixer_put), |
| 2694 | SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, |
| 2695 | rx_macro_iir_enable_audio_mixer_get, |
| 2696 | rx_macro_iir_enable_audio_mixer_put), |
| 2697 | SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, |
| 2698 | rx_macro_iir_enable_audio_mixer_get, |
| 2699 | rx_macro_iir_enable_audio_mixer_put), |
| 2700 | |
| 2701 | SOC_SINGLE_MULTI_EXT("IIR0 Band1", IIR0, BAND1, 255, 0, 5, |
| 2702 | rx_macro_iir_band_audio_mixer_get, |
| 2703 | rx_macro_iir_band_audio_mixer_put), |
| 2704 | SOC_SINGLE_MULTI_EXT("IIR0 Band2", IIR0, BAND2, 255, 0, 5, |
| 2705 | rx_macro_iir_band_audio_mixer_get, |
| 2706 | rx_macro_iir_band_audio_mixer_put), |
| 2707 | SOC_SINGLE_MULTI_EXT("IIR0 Band3", IIR0, BAND3, 255, 0, 5, |
| 2708 | rx_macro_iir_band_audio_mixer_get, |
| 2709 | rx_macro_iir_band_audio_mixer_put), |
| 2710 | SOC_SINGLE_MULTI_EXT("IIR0 Band4", IIR0, BAND4, 255, 0, 5, |
| 2711 | rx_macro_iir_band_audio_mixer_get, |
| 2712 | rx_macro_iir_band_audio_mixer_put), |
| 2713 | SOC_SINGLE_MULTI_EXT("IIR0 Band5", IIR0, BAND5, 255, 0, 5, |
| 2714 | rx_macro_iir_band_audio_mixer_get, |
| 2715 | rx_macro_iir_band_audio_mixer_put), |
| 2716 | SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, |
| 2717 | rx_macro_iir_band_audio_mixer_get, |
| 2718 | rx_macro_iir_band_audio_mixer_put), |
| 2719 | SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, |
| 2720 | rx_macro_iir_band_audio_mixer_get, |
| 2721 | rx_macro_iir_band_audio_mixer_put), |
| 2722 | SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, |
| 2723 | rx_macro_iir_band_audio_mixer_get, |
| 2724 | rx_macro_iir_band_audio_mixer_put), |
| 2725 | SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, |
| 2726 | rx_macro_iir_band_audio_mixer_get, |
| 2727 | rx_macro_iir_band_audio_mixer_put), |
| 2728 | SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, |
| 2729 | rx_macro_iir_band_audio_mixer_get, |
| 2730 | rx_macro_iir_band_audio_mixer_put), |
| 2731 | }; |
| 2732 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 2733 | static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, |
| 2734 | struct snd_kcontrol *kcontrol, |
| 2735 | int event) |
| 2736 | { |
| 2737 | struct snd_soc_component *component = |
| 2738 | snd_soc_dapm_to_component(w->dapm); |
| 2739 | struct device *rx_dev = NULL; |
| 2740 | struct rx_macro_priv *rx_priv = NULL; |
| 2741 | u16 val = 0, ec_hq_reg = 0; |
| 2742 | int ec_tx = 0; |
| 2743 | |
| 2744 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
| 2745 | return -EINVAL; |
| 2746 | |
| 2747 | dev_dbg(rx_dev, "%s %d %s\n", __func__, event, w->name); |
| 2748 | |
| 2749 | val = snd_soc_component_read32(component, |
| 2750 | BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4); |
| 2751 | if (!(strcmp(w->name, "RX MIX TX0 MUX"))) |
| 2752 | ec_tx = ((val & 0xf0) >> 0x4) - 1; |
| 2753 | else if (!(strcmp(w->name, "RX MIX TX1 MUX"))) |
| 2754 | ec_tx = (val & 0x0f) - 1; |
| 2755 | |
| 2756 | val = snd_soc_component_read32(component, |
| 2757 | BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5); |
| 2758 | if (!(strcmp(w->name, "RX MIX TX2 MUX"))) |
| 2759 | ec_tx = (val & 0x0f) - 1; |
| 2760 | |
| 2761 | if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) { |
| 2762 | dev_err(rx_dev, "%s: EC mix control not set correctly\n", |
| 2763 | __func__); |
| 2764 | return -EINVAL; |
| 2765 | } |
| 2766 | ec_hq_reg = BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL + |
| 2767 | 0x40 * ec_tx; |
| 2768 | snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); |
| 2769 | ec_hq_reg = BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 + |
| 2770 | 0x40 * ec_tx; |
| 2771 | /* default set to 48k */ |
| 2772 | snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); |
| 2773 | |
| 2774 | return 0; |
| 2775 | } |
| 2776 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2777 | static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { |
| 2778 | SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0, |
| 2779 | SND_SOC_NOPM, 0, 0), |
| 2780 | |
| 2781 | SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0, |
| 2782 | SND_SOC_NOPM, 0, 0), |
| 2783 | |
| 2784 | SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0, |
| 2785 | SND_SOC_NOPM, 0, 0), |
| 2786 | |
| 2787 | SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0, |
| 2788 | SND_SOC_NOPM, 0, 0), |
| 2789 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 2790 | SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0, |
| 2791 | SND_SOC_NOPM, 0, 0), |
| 2792 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2793 | RX_MACRO_DAPM_MUX("RX_MACRO RX0 MUX", RX_MACRO_RX0, rx_macro_rx0), |
| 2794 | RX_MACRO_DAPM_MUX("RX_MACRO RX1 MUX", RX_MACRO_RX1, rx_macro_rx1), |
| 2795 | RX_MACRO_DAPM_MUX("RX_MACRO RX2 MUX", RX_MACRO_RX2, rx_macro_rx2), |
| 2796 | RX_MACRO_DAPM_MUX("RX_MACRO RX3 MUX", RX_MACRO_RX3, rx_macro_rx3), |
| 2797 | RX_MACRO_DAPM_MUX("RX_MACRO RX4 MUX", RX_MACRO_RX4, rx_macro_rx4), |
| 2798 | RX_MACRO_DAPM_MUX("RX_MACRO RX5 MUX", RX_MACRO_RX5, rx_macro_rx5), |
| 2799 | |
| 2800 | SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2801 | SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2802 | SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2803 | SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2804 | SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2805 | SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2806 | |
| 2807 | RX_MACRO_DAPM_MUX("IIR0 INP0 MUX", 0, iir0_inp0), |
| 2808 | RX_MACRO_DAPM_MUX("IIR0 INP1 MUX", 0, iir0_inp1), |
| 2809 | RX_MACRO_DAPM_MUX("IIR0 INP2 MUX", 0, iir0_inp2), |
| 2810 | RX_MACRO_DAPM_MUX("IIR0 INP3 MUX", 0, iir0_inp3), |
| 2811 | RX_MACRO_DAPM_MUX("IIR1 INP0 MUX", 0, iir1_inp0), |
| 2812 | RX_MACRO_DAPM_MUX("IIR1 INP1 MUX", 0, iir1_inp1), |
| 2813 | RX_MACRO_DAPM_MUX("IIR1 INP2 MUX", 0, iir1_inp2), |
| 2814 | RX_MACRO_DAPM_MUX("IIR1 INP3 MUX", 0, iir1_inp3), |
| 2815 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 2816 | SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM, |
| 2817 | RX_MACRO_EC0_MUX, 0, |
| 2818 | &rx_mix_tx0_mux, rx_macro_enable_echo, |
| 2819 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2820 | SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM, |
| 2821 | RX_MACRO_EC1_MUX, 0, |
| 2822 | &rx_mix_tx1_mux, rx_macro_enable_echo, |
| 2823 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2824 | SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM, |
| 2825 | RX_MACRO_EC2_MUX, 0, |
| 2826 | &rx_mix_tx2_mux, rx_macro_enable_echo, |
| 2827 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2828 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2829 | SND_SOC_DAPM_MIXER_E("IIR0", BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, |
| 2830 | 4, 0, NULL, 0, rx_macro_set_iir_gain, |
| 2831 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 2832 | SND_SOC_DAPM_MIXER_E("IIR1", BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, |
| 2833 | 4, 0, NULL, 0, rx_macro_set_iir_gain, |
| 2834 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), |
| 2835 | SND_SOC_DAPM_MIXER("SRC0", BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, |
| 2836 | 4, 0, NULL, 0), |
| 2837 | SND_SOC_DAPM_MIXER("SRC1", BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, |
| 2838 | 4, 0, NULL, 0), |
| 2839 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2840 | RX_MACRO_DAPM_MUX("RX INT0 DEM MUX", 0, rx_int0_dem_inp), |
| 2841 | RX_MACRO_DAPM_MUX("RX INT1 DEM MUX", 0, rx_int1_dem_inp), |
| 2842 | |
| 2843 | SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0, |
| 2844 | &rx_int0_2_mux, rx_macro_enable_mix_path, |
| 2845 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2846 | SND_SOC_DAPM_POST_PMD), |
| 2847 | SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0, |
| 2848 | &rx_int1_2_mux, rx_macro_enable_mix_path, |
| 2849 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2850 | SND_SOC_DAPM_POST_PMD), |
| 2851 | SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0, |
| 2852 | &rx_int2_2_mux, rx_macro_enable_mix_path, |
| 2853 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2854 | SND_SOC_DAPM_POST_PMD), |
| 2855 | |
| 2856 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP0", 0, rx_int0_1_mix_inp0), |
| 2857 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP1", 0, rx_int0_1_mix_inp1), |
| 2858 | RX_MACRO_DAPM_MUX("RX INT0_1 MIX1 INP2", 0, rx_int0_1_mix_inp2), |
| 2859 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP0", 0, rx_int1_1_mix_inp0), |
| 2860 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP1", 0, rx_int1_1_mix_inp1), |
| 2861 | RX_MACRO_DAPM_MUX("RX INT1_1 MIX1 INP2", 0, rx_int1_1_mix_inp2), |
| 2862 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP0", 0, rx_int2_1_mix_inp0), |
| 2863 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP1", 0, rx_int2_1_mix_inp1), |
| 2864 | RX_MACRO_DAPM_MUX("RX INT2_1 MIX1 INP2", 0, rx_int2_1_mix_inp2), |
| 2865 | |
| 2866 | SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0, |
| 2867 | &rx_int0_1_interp_mux, rx_macro_enable_main_path, |
| 2868 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2869 | SND_SOC_DAPM_POST_PMD), |
| 2870 | SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0, |
| 2871 | &rx_int1_1_interp_mux, rx_macro_enable_main_path, |
| 2872 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2873 | SND_SOC_DAPM_POST_PMD), |
| 2874 | SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0, |
| 2875 | &rx_int2_1_interp_mux, rx_macro_enable_main_path, |
| 2876 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2877 | SND_SOC_DAPM_POST_PMD), |
| 2878 | |
| 2879 | RX_MACRO_DAPM_MUX("RX INT0_2 INTERP", 0, rx_int0_2_interp), |
| 2880 | RX_MACRO_DAPM_MUX("RX INT1_2 INTERP", 0, rx_int1_2_interp), |
| 2881 | RX_MACRO_DAPM_MUX("RX INT2_2 INTERP", 0, rx_int2_2_interp), |
| 2882 | |
| 2883 | SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2884 | SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2885 | SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2886 | SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2887 | SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2888 | SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2889 | |
| 2890 | SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL, |
| 2891 | 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2892 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2893 | SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR, |
| 2894 | 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2895 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2896 | SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX, |
| 2897 | 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, |
| 2898 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2899 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2900 | SND_SOC_DAPM_MIXER_E("RX INT2_1 VBAT", SND_SOC_NOPM, |
| 2901 | 0, 0, rx_int2_1_vbat_mix_switch, |
| 2902 | ARRAY_SIZE(rx_int2_1_vbat_mix_switch), |
| 2903 | rx_macro_enable_vbat, |
| 2904 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2905 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 2906 | SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2907 | SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2908 | SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2909 | |
| 2910 | SND_SOC_DAPM_OUTPUT("HPHL_OUT"), |
| 2911 | SND_SOC_DAPM_OUTPUT("HPHR_OUT"), |
| 2912 | SND_SOC_DAPM_OUTPUT("AUX_OUT"), |
| 2913 | |
| 2914 | SND_SOC_DAPM_INPUT("RX_TX DEC0_INP"), |
| 2915 | SND_SOC_DAPM_INPUT("RX_TX DEC1_INP"), |
| 2916 | SND_SOC_DAPM_INPUT("RX_TX DEC2_INP"), |
| 2917 | SND_SOC_DAPM_INPUT("RX_TX DEC3_INP"), |
| 2918 | |
| 2919 | SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 2920 | rx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2921 | }; |
| 2922 | |
| 2923 | static const struct snd_soc_dapm_route rx_audio_map[] = { |
| 2924 | {"RX AIF1 PB", NULL, "RX_MCLK"}, |
| 2925 | {"RX AIF2 PB", NULL, "RX_MCLK"}, |
| 2926 | {"RX AIF3 PB", NULL, "RX_MCLK"}, |
| 2927 | {"RX AIF4 PB", NULL, "RX_MCLK"}, |
| 2928 | |
| 2929 | {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2930 | {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2931 | {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2932 | {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2933 | {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2934 | {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"}, |
| 2935 | |
| 2936 | {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2937 | {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2938 | {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2939 | {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2940 | {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2941 | {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"}, |
| 2942 | |
| 2943 | {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2944 | {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2945 | {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2946 | {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2947 | {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2948 | {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"}, |
| 2949 | |
| 2950 | {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2951 | {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2952 | {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2953 | {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2954 | {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2955 | {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"}, |
| 2956 | |
| 2957 | {"RX_RX0", NULL, "RX_MACRO RX0 MUX"}, |
| 2958 | {"RX_RX1", NULL, "RX_MACRO RX1 MUX"}, |
| 2959 | {"RX_RX2", NULL, "RX_MACRO RX2 MUX"}, |
| 2960 | {"RX_RX3", NULL, "RX_MACRO RX3 MUX"}, |
| 2961 | {"RX_RX4", NULL, "RX_MACRO RX4 MUX"}, |
| 2962 | {"RX_RX5", NULL, "RX_MACRO RX5 MUX"}, |
| 2963 | |
| 2964 | {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 2965 | {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 2966 | {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 2967 | {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 2968 | {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 2969 | {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 2970 | {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 2971 | {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 2972 | {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 2973 | {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 2974 | {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 2975 | {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 2976 | {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 2977 | {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 2978 | {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 2979 | {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 2980 | {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 2981 | {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 2982 | {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 2983 | {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 2984 | {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 2985 | {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 2986 | {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 2987 | {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 2988 | |
| 2989 | {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 2990 | {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 2991 | {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 2992 | {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 2993 | {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 2994 | {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 2995 | {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 2996 | {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 2997 | {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 2998 | {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 2999 | {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 3000 | {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 3001 | {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 3002 | {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 3003 | {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 3004 | {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 3005 | {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 3006 | {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 3007 | {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 3008 | {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 3009 | {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 3010 | {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 3011 | {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 3012 | {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 3013 | |
| 3014 | {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"}, |
| 3015 | {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"}, |
| 3016 | {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"}, |
| 3017 | {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"}, |
| 3018 | {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"}, |
| 3019 | {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"}, |
| 3020 | {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"}, |
| 3021 | {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"}, |
| 3022 | {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"}, |
| 3023 | {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"}, |
| 3024 | {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"}, |
| 3025 | {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"}, |
| 3026 | {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"}, |
| 3027 | {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"}, |
| 3028 | {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"}, |
| 3029 | {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"}, |
| 3030 | {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"}, |
| 3031 | {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"}, |
| 3032 | {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"}, |
| 3033 | {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"}, |
| 3034 | {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"}, |
| 3035 | {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"}, |
| 3036 | {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"}, |
| 3037 | {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"}, |
| 3038 | |
| 3039 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"}, |
| 3040 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"}, |
| 3041 | {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"}, |
| 3042 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"}, |
| 3043 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"}, |
| 3044 | {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"}, |
| 3045 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"}, |
| 3046 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"}, |
| 3047 | {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"}, |
| 3048 | |
Vatsal Bucha | c2d6c22 | 2018-11-30 18:46:37 +0530 | [diff] [blame] | 3049 | {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, |
| 3050 | {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, |
| 3051 | {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, |
| 3052 | {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, |
| 3053 | {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, |
| 3054 | {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, |
| 3055 | {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"}, |
| 3056 | {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"}, |
| 3057 | {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"}, |
| 3058 | {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"}, |
| 3059 | {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"}, |
| 3060 | {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"}, |
| 3061 | {"RX AIF_ECHO", NULL, "RX_MCLK"}, |
| 3062 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3063 | /* Mixing path INT0 */ |
| 3064 | {"RX INT0_2 MUX", "RX0", "RX_RX0"}, |
| 3065 | {"RX INT0_2 MUX", "RX1", "RX_RX1"}, |
| 3066 | {"RX INT0_2 MUX", "RX2", "RX_RX2"}, |
| 3067 | {"RX INT0_2 MUX", "RX3", "RX_RX3"}, |
| 3068 | {"RX INT0_2 MUX", "RX4", "RX_RX4"}, |
| 3069 | {"RX INT0_2 MUX", "RX5", "RX_RX5"}, |
| 3070 | {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"}, |
| 3071 | {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"}, |
| 3072 | |
| 3073 | /* Mixing path INT1 */ |
| 3074 | {"RX INT1_2 MUX", "RX0", "RX_RX0"}, |
| 3075 | {"RX INT1_2 MUX", "RX1", "RX_RX1"}, |
| 3076 | {"RX INT1_2 MUX", "RX2", "RX_RX2"}, |
| 3077 | {"RX INT1_2 MUX", "RX3", "RX_RX3"}, |
| 3078 | {"RX INT1_2 MUX", "RX4", "RX_RX4"}, |
| 3079 | {"RX INT1_2 MUX", "RX5", "RX_RX5"}, |
| 3080 | {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"}, |
| 3081 | {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"}, |
| 3082 | |
| 3083 | /* Mixing path INT2 */ |
| 3084 | {"RX INT2_2 MUX", "RX0", "RX_RX0"}, |
| 3085 | {"RX INT2_2 MUX", "RX1", "RX_RX1"}, |
| 3086 | {"RX INT2_2 MUX", "RX2", "RX_RX2"}, |
| 3087 | {"RX INT2_2 MUX", "RX3", "RX_RX3"}, |
| 3088 | {"RX INT2_2 MUX", "RX4", "RX_RX4"}, |
| 3089 | {"RX INT2_2 MUX", "RX5", "RX_RX5"}, |
| 3090 | {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"}, |
| 3091 | {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"}, |
| 3092 | |
| 3093 | {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"}, |
| 3094 | {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"}, |
| 3095 | {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"}, |
| 3096 | {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"}, |
| 3097 | {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"}, |
| 3098 | {"HPHL_OUT", NULL, "RX INT0 DEM MUX"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 3099 | {"HPHL_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3100 | |
| 3101 | {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"}, |
| 3102 | {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"}, |
| 3103 | {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"}, |
| 3104 | {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"}, |
| 3105 | {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"}, |
| 3106 | {"HPHR_OUT", NULL, "RX INT1 DEM MUX"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 3107 | {"HPHR_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3108 | |
| 3109 | {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"}, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3110 | |
| 3111 | {"RX INT2_1 VBAT", "RX AUX VBAT Enable", "RX INT2_1 INTERP"}, |
| 3112 | {"RX INT2 SEC MIX", NULL, "RX INT2_1 VBAT"}, |
| 3113 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3114 | {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"}, |
| 3115 | {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"}, |
| 3116 | {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"}, |
| 3117 | {"AUX_OUT", NULL, "RX INT2 MIX2"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 3118 | {"AUX_OUT", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3119 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 3120 | {"IIR0", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3121 | {"IIR0", NULL, "IIR0 INP0 MUX"}, |
| 3122 | {"IIR0 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3123 | {"IIR0 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3124 | {"IIR0 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3125 | {"IIR0 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3126 | {"IIR0 INP0 MUX", "RX0", "RX_RX0"}, |
| 3127 | {"IIR0 INP0 MUX", "RX1", "RX_RX1"}, |
| 3128 | {"IIR0 INP0 MUX", "RX2", "RX_RX2"}, |
| 3129 | {"IIR0 INP0 MUX", "RX3", "RX_RX3"}, |
| 3130 | {"IIR0 INP0 MUX", "RX4", "RX_RX4"}, |
| 3131 | {"IIR0 INP0 MUX", "RX5", "RX_RX5"}, |
| 3132 | {"IIR0", NULL, "IIR0 INP1 MUX"}, |
| 3133 | {"IIR0 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3134 | {"IIR0 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3135 | {"IIR0 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3136 | {"IIR0 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3137 | {"IIR0 INP1 MUX", "RX0", "RX_RX0"}, |
| 3138 | {"IIR0 INP1 MUX", "RX1", "RX_RX1"}, |
| 3139 | {"IIR0 INP1 MUX", "RX2", "RX_RX2"}, |
| 3140 | {"IIR0 INP1 MUX", "RX3", "RX_RX3"}, |
| 3141 | {"IIR0 INP1 MUX", "RX4", "RX_RX4"}, |
| 3142 | {"IIR0 INP1 MUX", "RX5", "RX_RX5"}, |
| 3143 | {"IIR0", NULL, "IIR0 INP2 MUX"}, |
| 3144 | {"IIR0 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3145 | {"IIR0 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3146 | {"IIR0 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3147 | {"IIR0 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3148 | {"IIR0 INP2 MUX", "RX0", "RX_RX0"}, |
| 3149 | {"IIR0 INP2 MUX", "RX1", "RX_RX1"}, |
| 3150 | {"IIR0 INP2 MUX", "RX2", "RX_RX2"}, |
| 3151 | {"IIR0 INP2 MUX", "RX3", "RX_RX3"}, |
| 3152 | {"IIR0 INP2 MUX", "RX4", "RX_RX4"}, |
| 3153 | {"IIR0 INP2 MUX", "RX5", "RX_RX5"}, |
| 3154 | {"IIR0", NULL, "IIR0 INP3 MUX"}, |
| 3155 | {"IIR0 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3156 | {"IIR0 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3157 | {"IIR0 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3158 | {"IIR0 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3159 | {"IIR0 INP3 MUX", "RX0", "RX_RX0"}, |
| 3160 | {"IIR0 INP3 MUX", "RX1", "RX_RX1"}, |
| 3161 | {"IIR0 INP3 MUX", "RX2", "RX_RX2"}, |
| 3162 | {"IIR0 INP3 MUX", "RX3", "RX_RX3"}, |
| 3163 | {"IIR0 INP3 MUX", "RX4", "RX_RX4"}, |
| 3164 | {"IIR0 INP3 MUX", "RX5", "RX_RX5"}, |
| 3165 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 3166 | {"IIR1", NULL, "RX_MCLK"}, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3167 | {"IIR1", NULL, "IIR1 INP0 MUX"}, |
| 3168 | {"IIR1 INP0 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3169 | {"IIR1 INP0 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3170 | {"IIR1 INP0 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3171 | {"IIR1 INP0 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3172 | {"IIR1 INP0 MUX", "RX0", "RX_RX0"}, |
| 3173 | {"IIR1 INP0 MUX", "RX1", "RX_RX1"}, |
| 3174 | {"IIR1 INP0 MUX", "RX2", "RX_RX2"}, |
| 3175 | {"IIR1 INP0 MUX", "RX3", "RX_RX3"}, |
| 3176 | {"IIR1 INP0 MUX", "RX4", "RX_RX4"}, |
| 3177 | {"IIR1 INP0 MUX", "RX5", "RX_RX5"}, |
| 3178 | {"IIR1", NULL, "IIR1 INP1 MUX"}, |
| 3179 | {"IIR1 INP1 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3180 | {"IIR1 INP1 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3181 | {"IIR1 INP1 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3182 | {"IIR1 INP1 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3183 | {"IIR1 INP1 MUX", "RX0", "RX_RX0"}, |
| 3184 | {"IIR1 INP1 MUX", "RX1", "RX_RX1"}, |
| 3185 | {"IIR1 INP1 MUX", "RX2", "RX_RX2"}, |
| 3186 | {"IIR1 INP1 MUX", "RX3", "RX_RX3"}, |
| 3187 | {"IIR1 INP1 MUX", "RX4", "RX_RX4"}, |
| 3188 | {"IIR1 INP1 MUX", "RX5", "RX_RX5"}, |
| 3189 | {"IIR1", NULL, "IIR1 INP2 MUX"}, |
| 3190 | {"IIR1 INP2 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3191 | {"IIR1 INP2 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3192 | {"IIR1 INP2 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3193 | {"IIR1 INP2 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3194 | {"IIR1 INP2 MUX", "RX0", "RX_RX0"}, |
| 3195 | {"IIR1 INP2 MUX", "RX1", "RX_RX1"}, |
| 3196 | {"IIR1 INP2 MUX", "RX2", "RX_RX2"}, |
| 3197 | {"IIR1 INP2 MUX", "RX3", "RX_RX3"}, |
| 3198 | {"IIR1 INP2 MUX", "RX4", "RX_RX4"}, |
| 3199 | {"IIR1 INP2 MUX", "RX5", "RX_RX5"}, |
| 3200 | {"IIR1", NULL, "IIR1 INP3 MUX"}, |
| 3201 | {"IIR1 INP3 MUX", "DEC0", "RX_TX DEC0_INP"}, |
| 3202 | {"IIR1 INP3 MUX", "DEC1", "RX_TX DEC1_INP"}, |
| 3203 | {"IIR1 INP3 MUX", "DEC2", "RX_TX DEC2_INP"}, |
| 3204 | {"IIR1 INP3 MUX", "DEC3", "RX_TX DEC3_INP"}, |
| 3205 | {"IIR1 INP3 MUX", "RX0", "RX_RX0"}, |
| 3206 | {"IIR1 INP3 MUX", "RX1", "RX_RX1"}, |
| 3207 | {"IIR1 INP3 MUX", "RX2", "RX_RX2"}, |
| 3208 | {"IIR1 INP3 MUX", "RX3", "RX_RX3"}, |
| 3209 | {"IIR1 INP3 MUX", "RX4", "RX_RX4"}, |
| 3210 | {"IIR1 INP3 MUX", "RX5", "RX_RX5"}, |
| 3211 | |
| 3212 | {"SRC0", NULL, "IIR0"}, |
| 3213 | {"SRC1", NULL, "IIR1"}, |
| 3214 | {"RX INT0 MIX2 INP", "SRC0", "SRC0"}, |
| 3215 | {"RX INT0 MIX2 INP", "SRC1", "SRC1"}, |
| 3216 | {"RX INT1 MIX2 INP", "SRC0", "SRC0"}, |
| 3217 | {"RX INT1 MIX2 INP", "SRC1", "SRC1"}, |
| 3218 | {"RX INT2 MIX2 INP", "SRC0", "SRC0"}, |
| 3219 | {"RX INT2 MIX2 INP", "SRC1", "SRC1"}, |
| 3220 | }; |
| 3221 | |
| 3222 | static int rx_swrm_clock(void *handle, bool enable) |
| 3223 | { |
| 3224 | struct rx_macro_priv *rx_priv = (struct rx_macro_priv *) handle; |
| 3225 | struct regmap *regmap = dev_get_regmap(rx_priv->dev->parent, NULL); |
| 3226 | int ret = 0; |
| 3227 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 3228 | if (regmap == NULL) { |
| 3229 | dev_err(rx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 3230 | return -EINVAL; |
| 3231 | } |
| 3232 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3233 | mutex_lock(&rx_priv->swr_clk_lock); |
| 3234 | |
| 3235 | dev_dbg(rx_priv->dev, "%s: swrm clock %s\n", |
| 3236 | __func__, (enable ? "enable" : "disable")); |
| 3237 | if (enable) { |
| 3238 | if (rx_priv->swr_clk_users == 0) { |
Karthikeyan Mani | 01f1ba4 | 2019-02-26 18:48:15 -0800 | [diff] [blame] | 3239 | msm_cdc_pinctrl_select_active_state( |
| 3240 | rx_priv->rx_swr_gpio_p); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3241 | ret = rx_macro_mclk_enable(rx_priv, 1, true); |
| 3242 | if (ret < 0) { |
Karthikeyan Mani | 01f1ba4 | 2019-02-26 18:48:15 -0800 | [diff] [blame] | 3243 | msm_cdc_pinctrl_select_sleep_state( |
| 3244 | rx_priv->rx_swr_gpio_p); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3245 | dev_err(rx_priv->dev, |
| 3246 | "%s: rx request clock enable failed\n", |
| 3247 | __func__); |
| 3248 | goto exit; |
| 3249 | } |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 3250 | if (rx_priv->reset_swr) |
| 3251 | regmap_update_bits(regmap, |
| 3252 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
| 3253 | 0x02, 0x02); |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 3254 | regmap_update_bits(regmap, |
| 3255 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3256 | 0x01, 0x01); |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 3257 | if (rx_priv->reset_swr) |
| 3258 | regmap_update_bits(regmap, |
| 3259 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
| 3260 | 0x02, 0x00); |
| 3261 | rx_priv->reset_swr = false; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3262 | } |
| 3263 | rx_priv->swr_clk_users++; |
| 3264 | } else { |
| 3265 | if (rx_priv->swr_clk_users <= 0) { |
| 3266 | dev_err(rx_priv->dev, |
| 3267 | "%s: rx swrm clock users already reset\n", |
| 3268 | __func__); |
| 3269 | rx_priv->swr_clk_users = 0; |
| 3270 | goto exit; |
| 3271 | } |
| 3272 | rx_priv->swr_clk_users--; |
| 3273 | if (rx_priv->swr_clk_users == 0) { |
| 3274 | regmap_update_bits(regmap, |
| 3275 | BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, |
| 3276 | 0x01, 0x00); |
Karthikeyan Mani | 01f1ba4 | 2019-02-26 18:48:15 -0800 | [diff] [blame] | 3277 | rx_macro_mclk_enable(rx_priv, 0, true); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3278 | msm_cdc_pinctrl_select_sleep_state( |
| 3279 | rx_priv->rx_swr_gpio_p); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3280 | } |
| 3281 | } |
| 3282 | dev_dbg(rx_priv->dev, "%s: swrm clock users %d\n", |
| 3283 | __func__, rx_priv->swr_clk_users); |
| 3284 | exit: |
| 3285 | mutex_unlock(&rx_priv->swr_clk_lock); |
| 3286 | return ret; |
| 3287 | } |
| 3288 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3289 | static void rx_macro_init_bcl_pmic_reg(struct snd_soc_component *component) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3290 | { |
| 3291 | struct device *rx_dev = NULL; |
| 3292 | struct rx_macro_priv *rx_priv = NULL; |
| 3293 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3294 | if (!component) { |
| 3295 | pr_err("%s: NULL component pointer!\n", __func__); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3296 | return; |
| 3297 | } |
| 3298 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3299 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3300 | return; |
| 3301 | |
| 3302 | switch (rx_priv->bcl_pmic_params.id) { |
| 3303 | case 0: |
| 3304 | /* Enable ID0 to listen to respective PMIC group interrupts */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3305 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3306 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x02, 0x02); |
| 3307 | /* Update MC_SID0 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3308 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3309 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x0F, |
| 3310 | rx_priv->bcl_pmic_params.sid); |
| 3311 | /* Update MC_PPID0 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3312 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3313 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2, 0xFF, |
| 3314 | rx_priv->bcl_pmic_params.ppid); |
| 3315 | break; |
| 3316 | case 1: |
| 3317 | /* Enable ID1 to listen to respective PMIC group interrupts */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3318 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3319 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1, 0x01, 0x01); |
| 3320 | /* Update MC_SID1 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3321 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3322 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x0F, |
| 3323 | rx_priv->bcl_pmic_params.sid); |
| 3324 | /* Update MC_PPID1 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3325 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3326 | BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1, 0xFF, |
| 3327 | rx_priv->bcl_pmic_params.ppid); |
| 3328 | break; |
| 3329 | default: |
Md Mansoor Ahmed | 26d8bdd | 2018-11-20 10:56:01 +0530 | [diff] [blame] | 3330 | dev_err(rx_dev, "%s: PMIC ID is invalid %d\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3331 | __func__, rx_priv->bcl_pmic_params.id); |
| 3332 | break; |
| 3333 | } |
| 3334 | } |
| 3335 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3336 | static int rx_macro_init(struct snd_soc_component *component) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3337 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3338 | struct snd_soc_dapm_context *dapm = |
| 3339 | snd_soc_component_get_dapm(component); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3340 | int ret = 0; |
| 3341 | struct device *rx_dev = NULL; |
| 3342 | struct rx_macro_priv *rx_priv = NULL; |
| 3343 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3344 | rx_dev = bolero_get_device_ptr(component->dev, RX_MACRO); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3345 | if (!rx_dev) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3346 | dev_err(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3347 | "%s: null device for macro!\n", __func__); |
| 3348 | return -EINVAL; |
| 3349 | } |
| 3350 | rx_priv = dev_get_drvdata(rx_dev); |
| 3351 | if (!rx_priv) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3352 | dev_err(component->dev, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3353 | "%s: priv is null for macro!\n", __func__); |
| 3354 | return -EINVAL; |
| 3355 | } |
| 3356 | |
| 3357 | ret = snd_soc_dapm_new_controls(dapm, rx_macro_dapm_widgets, |
| 3358 | ARRAY_SIZE(rx_macro_dapm_widgets)); |
| 3359 | if (ret < 0) { |
| 3360 | dev_err(rx_dev, "%s: failed to add controls\n", __func__); |
| 3361 | return ret; |
| 3362 | } |
| 3363 | ret = snd_soc_dapm_add_routes(dapm, rx_audio_map, |
| 3364 | ARRAY_SIZE(rx_audio_map)); |
| 3365 | if (ret < 0) { |
| 3366 | dev_err(rx_dev, "%s: failed to add routes\n", __func__); |
| 3367 | return ret; |
| 3368 | } |
| 3369 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 3370 | if (ret < 0) { |
| 3371 | dev_err(rx_dev, "%s: failed to add widgets\n", __func__); |
| 3372 | return ret; |
| 3373 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3374 | ret = snd_soc_add_component_controls(component, rx_macro_snd_controls, |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3375 | ARRAY_SIZE(rx_macro_snd_controls)); |
| 3376 | if (ret < 0) { |
| 3377 | dev_err(rx_dev, "%s: failed to add snd_ctls\n", __func__); |
| 3378 | return ret; |
| 3379 | } |
Laxminath Kasam | 701e358 | 2018-10-15 20:06:09 +0530 | [diff] [blame] | 3380 | rx_priv->dev_up = true; |
Laxminath Kasam | 638b560 | 2018-09-24 13:19:52 +0530 | [diff] [blame] | 3381 | snd_soc_dapm_ignore_suspend(dapm, "RX_MACRO_AIF1 Playback"); |
| 3382 | snd_soc_dapm_ignore_suspend(dapm, "RX_MACRO_AIF2 Playback"); |
| 3383 | snd_soc_dapm_ignore_suspend(dapm, "RX_MACRO_AIF3 Playback"); |
| 3384 | snd_soc_dapm_ignore_suspend(dapm, "RX_MACRO_AIF4 Playback"); |
| 3385 | snd_soc_dapm_ignore_suspend(dapm, "HPHL_OUT"); |
| 3386 | snd_soc_dapm_ignore_suspend(dapm, "HPHR_OUT"); |
| 3387 | snd_soc_dapm_ignore_suspend(dapm, "AUX_OUT"); |
| 3388 | snd_soc_dapm_ignore_suspend(dapm, "RX_TX DEC0_INP"); |
| 3389 | snd_soc_dapm_ignore_suspend(dapm, "RX_TX DEC1_INP"); |
| 3390 | snd_soc_dapm_ignore_suspend(dapm, "RX_TX DEC2_INP"); |
| 3391 | snd_soc_dapm_ignore_suspend(dapm, "RX_TX DEC3_INP"); |
| 3392 | snd_soc_dapm_sync(dapm); |
| 3393 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3394 | snd_soc_component_update_bits(component, |
| 3395 | BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL, |
| 3396 | 0x01, 0x01); |
| 3397 | snd_soc_component_update_bits(component, |
| 3398 | BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL, |
| 3399 | 0x01, 0x01); |
| 3400 | snd_soc_component_update_bits(component, |
| 3401 | BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL, |
| 3402 | 0x01, 0x01); |
| 3403 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX0_RX_PATH_SEC7, |
| 3404 | 0x07, 0x02); |
| 3405 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX1_RX_PATH_SEC7, |
| 3406 | 0x07, 0x02); |
| 3407 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_SEC7, |
| 3408 | 0x07, 0x02); |
| 3409 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX0_RX_PATH_CFG3, |
| 3410 | 0x03, 0x02); |
| 3411 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX1_RX_PATH_CFG3, |
| 3412 | 0x03, 0x02); |
| 3413 | snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX2_RX_PATH_CFG3, |
| 3414 | 0x03, 0x02); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3415 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3416 | rx_priv->component = component; |
Vatsal Bucha | 39ead2c | 2018-12-14 12:22:46 +0530 | [diff] [blame] | 3417 | rx_macro_init_bcl_pmic_reg(component); |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3418 | |
| 3419 | return 0; |
| 3420 | } |
| 3421 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3422 | static int rx_macro_deinit(struct snd_soc_component *component) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3423 | { |
| 3424 | struct device *rx_dev = NULL; |
| 3425 | struct rx_macro_priv *rx_priv = NULL; |
| 3426 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3427 | if (!rx_macro_get_data(component, &rx_dev, &rx_priv, __func__)) |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3428 | return -EINVAL; |
| 3429 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 3430 | rx_priv->component = NULL; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3431 | |
| 3432 | return 0; |
| 3433 | } |
| 3434 | |
| 3435 | static void rx_macro_add_child_devices(struct work_struct *work) |
| 3436 | { |
| 3437 | struct rx_macro_priv *rx_priv = NULL; |
| 3438 | struct platform_device *pdev = NULL; |
| 3439 | struct device_node *node = NULL; |
| 3440 | struct rx_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; |
| 3441 | int ret = 0; |
| 3442 | u16 count = 0, ctrl_num = 0; |
| 3443 | struct rx_swr_ctrl_platform_data *platdata = NULL; |
| 3444 | char plat_dev_name[RX_SWR_STRING_LEN] = ""; |
| 3445 | bool rx_swr_master_node = false; |
| 3446 | |
| 3447 | rx_priv = container_of(work, struct rx_macro_priv, |
| 3448 | rx_macro_add_child_devices_work); |
| 3449 | if (!rx_priv) { |
| 3450 | pr_err("%s: Memory for rx_priv does not exist\n", |
| 3451 | __func__); |
| 3452 | return; |
| 3453 | } |
| 3454 | |
| 3455 | if (!rx_priv->dev) { |
| 3456 | pr_err("%s: RX device does not exist\n", __func__); |
| 3457 | return; |
| 3458 | } |
| 3459 | |
| 3460 | if(!rx_priv->dev->of_node) { |
| 3461 | dev_err(rx_priv->dev, |
| 3462 | "%s: DT node for RX dev does not exist\n", __func__); |
| 3463 | return; |
| 3464 | } |
| 3465 | |
| 3466 | platdata = &rx_priv->swr_plat_data; |
| 3467 | rx_priv->child_count = 0; |
| 3468 | |
| 3469 | for_each_available_child_of_node(rx_priv->dev->of_node, node) { |
| 3470 | rx_swr_master_node = false; |
| 3471 | if (strnstr(node->name, "rx_swr_master", |
| 3472 | strlen("rx_swr_master")) != NULL) |
| 3473 | rx_swr_master_node = true; |
| 3474 | |
| 3475 | if(rx_swr_master_node) |
| 3476 | strlcpy(plat_dev_name, "rx_swr_ctrl", |
| 3477 | (RX_SWR_STRING_LEN - 1)); |
| 3478 | else |
| 3479 | strlcpy(plat_dev_name, node->name, |
| 3480 | (RX_SWR_STRING_LEN - 1)); |
| 3481 | |
| 3482 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 3483 | if (!pdev) { |
| 3484 | dev_err(rx_priv->dev, "%s: pdev memory alloc failed\n", |
| 3485 | __func__); |
| 3486 | ret = -ENOMEM; |
| 3487 | goto err; |
| 3488 | } |
| 3489 | pdev->dev.parent = rx_priv->dev; |
| 3490 | pdev->dev.of_node = node; |
| 3491 | |
| 3492 | if (rx_swr_master_node) { |
| 3493 | ret = platform_device_add_data(pdev, platdata, |
| 3494 | sizeof(*platdata)); |
| 3495 | if (ret) { |
| 3496 | dev_err(&pdev->dev, |
| 3497 | "%s: cannot add plat data ctrl:%d\n", |
| 3498 | __func__, ctrl_num); |
| 3499 | goto fail_pdev_add; |
| 3500 | } |
| 3501 | } |
| 3502 | |
| 3503 | ret = platform_device_add(pdev); |
| 3504 | if (ret) { |
| 3505 | dev_err(&pdev->dev, |
| 3506 | "%s: Cannot add platform device\n", |
| 3507 | __func__); |
| 3508 | goto fail_pdev_add; |
| 3509 | } |
| 3510 | |
| 3511 | if (rx_swr_master_node) { |
| 3512 | temp = krealloc(swr_ctrl_data, |
| 3513 | (ctrl_num + 1) * sizeof( |
| 3514 | struct rx_swr_ctrl_data), |
| 3515 | GFP_KERNEL); |
| 3516 | if (!temp) { |
| 3517 | ret = -ENOMEM; |
| 3518 | goto fail_pdev_add; |
| 3519 | } |
| 3520 | swr_ctrl_data = temp; |
| 3521 | swr_ctrl_data[ctrl_num].rx_swr_pdev = pdev; |
| 3522 | ctrl_num++; |
| 3523 | dev_dbg(&pdev->dev, |
| 3524 | "%s: Added soundwire ctrl device(s)\n", |
| 3525 | __func__); |
| 3526 | rx_priv->swr_ctrl_data = swr_ctrl_data; |
| 3527 | } |
| 3528 | if (rx_priv->child_count < RX_MACRO_CHILD_DEVICES_MAX) |
| 3529 | rx_priv->pdev_child_devices[ |
| 3530 | rx_priv->child_count++] = pdev; |
| 3531 | else |
| 3532 | goto err; |
| 3533 | } |
| 3534 | return; |
| 3535 | fail_pdev_add: |
| 3536 | for (count = 0; count < rx_priv->child_count; count++) |
| 3537 | platform_device_put(rx_priv->pdev_child_devices[count]); |
| 3538 | err: |
| 3539 | return; |
| 3540 | } |
| 3541 | |
| 3542 | static void rx_macro_init_ops(struct macro_ops *ops, char __iomem *rx_io_base) |
| 3543 | { |
| 3544 | memset(ops, 0, sizeof(struct macro_ops)); |
| 3545 | ops->init = rx_macro_init; |
| 3546 | ops->exit = rx_macro_deinit; |
| 3547 | ops->io_base = rx_io_base; |
| 3548 | ops->dai_ptr = rx_macro_dai; |
| 3549 | ops->num_dais = ARRAY_SIZE(rx_macro_dai); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 3550 | ops->event_handler = rx_macro_event_handler; |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 3551 | ops->set_port_map = rx_macro_set_port_map; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3552 | } |
| 3553 | |
| 3554 | static int rx_macro_probe(struct platform_device *pdev) |
| 3555 | { |
| 3556 | struct macro_ops ops = {0}; |
| 3557 | struct rx_macro_priv *rx_priv = NULL; |
| 3558 | u32 rx_base_addr = 0, muxsel = 0; |
| 3559 | char __iomem *rx_io_base = NULL, *muxsel_io = NULL; |
| 3560 | int ret = 0; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3561 | u8 bcl_pmic_params[3]; |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 3562 | u32 default_clk_id = 0; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3563 | |
| 3564 | rx_priv = devm_kzalloc(&pdev->dev, sizeof(struct rx_macro_priv), |
| 3565 | GFP_KERNEL); |
| 3566 | if (!rx_priv) |
| 3567 | return -ENOMEM; |
| 3568 | |
| 3569 | rx_priv->dev = &pdev->dev; |
| 3570 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 3571 | &rx_base_addr); |
| 3572 | if (ret) { |
| 3573 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 3574 | __func__, "reg"); |
| 3575 | return ret; |
| 3576 | } |
| 3577 | ret = of_property_read_u32(pdev->dev.of_node, "qcom,rx_mclk_mode_muxsel", |
| 3578 | &muxsel); |
| 3579 | if (ret) { |
| 3580 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 3581 | __func__, "reg"); |
| 3582 | return ret; |
| 3583 | } |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 3584 | ret = of_property_read_u32(pdev->dev.of_node, "qcom,default-clk-id", |
| 3585 | &default_clk_id); |
| 3586 | if (ret) { |
| 3587 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 3588 | __func__, "qcom,default-clk-id"); |
| 3589 | default_clk_id = RX_CORE_CLK; |
| 3590 | } |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3591 | rx_priv->rx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 3592 | "qcom,rx-swr-gpios", 0); |
| 3593 | if (!rx_priv->rx_swr_gpio_p) { |
| 3594 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 3595 | __func__); |
| 3596 | return -EINVAL; |
| 3597 | } |
| 3598 | rx_io_base = devm_ioremap(&pdev->dev, rx_base_addr, |
| 3599 | RX_MACRO_MAX_OFFSET); |
| 3600 | if (!rx_io_base) { |
| 3601 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 3602 | return -ENOMEM; |
| 3603 | } |
| 3604 | rx_priv->rx_io_base = rx_io_base; |
| 3605 | muxsel_io = devm_ioremap(&pdev->dev, muxsel, 0x4); |
| 3606 | if (!muxsel_io) { |
| 3607 | dev_err(&pdev->dev, "%s: ioremap failed for muxsel\n", |
| 3608 | __func__); |
| 3609 | return -ENOMEM; |
| 3610 | } |
| 3611 | rx_priv->rx_mclk_mode_muxsel = muxsel_io; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 3612 | rx_priv->reset_swr = true; |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3613 | INIT_WORK(&rx_priv->rx_macro_add_child_devices_work, |
| 3614 | rx_macro_add_child_devices); |
| 3615 | rx_priv->swr_plat_data.handle = (void *) rx_priv; |
| 3616 | rx_priv->swr_plat_data.read = NULL; |
| 3617 | rx_priv->swr_plat_data.write = NULL; |
| 3618 | rx_priv->swr_plat_data.bulk_write = NULL; |
| 3619 | rx_priv->swr_plat_data.clk = rx_swrm_clock; |
| 3620 | rx_priv->swr_plat_data.handle_irq = NULL; |
| 3621 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3622 | ret = of_property_read_u8_array(pdev->dev.of_node, |
| 3623 | "qcom,rx-bcl-pmic-params", bcl_pmic_params, |
| 3624 | sizeof(bcl_pmic_params)); |
| 3625 | if (ret) { |
| 3626 | dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 3627 | __func__, "qcom,rx-bcl-pmic-params"); |
| 3628 | } else { |
| 3629 | rx_priv->bcl_pmic_params.id = bcl_pmic_params[0]; |
| 3630 | rx_priv->bcl_pmic_params.sid = bcl_pmic_params[1]; |
| 3631 | rx_priv->bcl_pmic_params.ppid = bcl_pmic_params[2]; |
| 3632 | } |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame^] | 3633 | rx_priv->clk_id = default_clk_id; |
| 3634 | rx_priv->default_clk_id = default_clk_id; |
| 3635 | ops.clk_id_req = rx_priv->clk_id; |
| 3636 | ops.default_clk_id = default_clk_id; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 3637 | |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 3638 | dev_set_drvdata(&pdev->dev, rx_priv); |
| 3639 | mutex_init(&rx_priv->mclk_lock); |
| 3640 | mutex_init(&rx_priv->swr_clk_lock); |
| 3641 | rx_macro_init_ops(&ops, rx_io_base); |
| 3642 | |
| 3643 | ret = bolero_register_macro(&pdev->dev, RX_MACRO, &ops); |
| 3644 | if (ret) { |
| 3645 | dev_err(&pdev->dev, |
| 3646 | "%s: register macro failed\n", __func__); |
| 3647 | goto err_reg_macro; |
| 3648 | } |
| 3649 | schedule_work(&rx_priv->rx_macro_add_child_devices_work); |
| 3650 | |
| 3651 | return 0; |
| 3652 | |
| 3653 | err_reg_macro: |
| 3654 | mutex_destroy(&rx_priv->mclk_lock); |
| 3655 | mutex_destroy(&rx_priv->swr_clk_lock); |
| 3656 | return ret; |
| 3657 | } |
| 3658 | |
| 3659 | static int rx_macro_remove(struct platform_device *pdev) |
| 3660 | { |
| 3661 | struct rx_macro_priv *rx_priv = NULL; |
| 3662 | u16 count = 0; |
| 3663 | |
| 3664 | rx_priv = dev_get_drvdata(&pdev->dev); |
| 3665 | |
| 3666 | if (!rx_priv) |
| 3667 | return -EINVAL; |
| 3668 | |
| 3669 | for (count = 0; count < rx_priv->child_count && |
| 3670 | count < RX_MACRO_CHILD_DEVICES_MAX; count++) |
| 3671 | platform_device_unregister(rx_priv->pdev_child_devices[count]); |
| 3672 | |
| 3673 | bolero_unregister_macro(&pdev->dev, RX_MACRO); |
| 3674 | mutex_destroy(&rx_priv->mclk_lock); |
| 3675 | mutex_destroy(&rx_priv->swr_clk_lock); |
| 3676 | kfree(rx_priv->swr_ctrl_data); |
| 3677 | return 0; |
| 3678 | } |
| 3679 | |
| 3680 | static const struct of_device_id rx_macro_dt_match[] = { |
| 3681 | {.compatible = "qcom,rx-macro"}, |
| 3682 | {} |
| 3683 | }; |
| 3684 | |
| 3685 | static struct platform_driver rx_macro_driver = { |
| 3686 | .driver = { |
| 3687 | .name = "rx_macro", |
| 3688 | .owner = THIS_MODULE, |
| 3689 | .of_match_table = rx_macro_dt_match, |
| 3690 | }, |
| 3691 | .probe = rx_macro_probe, |
| 3692 | .remove = rx_macro_remove, |
| 3693 | }; |
| 3694 | |
| 3695 | module_platform_driver(rx_macro_driver); |
| 3696 | |
| 3697 | MODULE_DESCRIPTION("RX macro driver"); |
| 3698 | MODULE_LICENSE("GPL v2"); |