Asish Bhattacharya | 366f750 | 2017-07-25 15:15:56 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/types.h> |
| 14 | #include "msm_sdw.h" |
| 15 | |
| 16 | const u8 msm_sdw_page_map[MSM_SDW_MAX_REGISTER] = { |
| 17 | [MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 0xa, |
| 18 | [MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 0xa, |
| 19 | [MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 0xa, |
| 20 | [MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 0xa, |
| 21 | [MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 0xa, |
| 22 | [MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 0xa, |
| 23 | [MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 0xa, |
| 24 | [MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 0xa, |
| 25 | [MSM_SDW_COMPANDER7_CTL0] = 0xb, |
| 26 | [MSM_SDW_COMPANDER7_CTL1] = 0xb, |
| 27 | [MSM_SDW_COMPANDER7_CTL2] = 0xb, |
| 28 | [MSM_SDW_COMPANDER7_CTL3] = 0xb, |
| 29 | [MSM_SDW_COMPANDER7_CTL4] = 0xb, |
| 30 | [MSM_SDW_COMPANDER7_CTL5] = 0xb, |
| 31 | [MSM_SDW_COMPANDER7_CTL6] = 0xb, |
| 32 | [MSM_SDW_COMPANDER7_CTL7] = 0xb, |
| 33 | [MSM_SDW_COMPANDER8_CTL0] = 0xb, |
| 34 | [MSM_SDW_COMPANDER8_CTL1] = 0xb, |
| 35 | [MSM_SDW_COMPANDER8_CTL2] = 0xb, |
| 36 | [MSM_SDW_COMPANDER8_CTL3] = 0xb, |
| 37 | [MSM_SDW_COMPANDER8_CTL4] = 0xb, |
| 38 | [MSM_SDW_COMPANDER8_CTL5] = 0xb, |
| 39 | [MSM_SDW_COMPANDER8_CTL6] = 0xb, |
| 40 | [MSM_SDW_COMPANDER8_CTL7] = 0xb, |
| 41 | [MSM_SDW_RX7_RX_PATH_CTL] = 0xb, |
| 42 | [MSM_SDW_RX7_RX_PATH_CFG0] = 0xb, |
| 43 | [MSM_SDW_RX7_RX_PATH_CFG1] = 0xb, |
| 44 | [MSM_SDW_RX7_RX_PATH_CFG2] = 0xb, |
| 45 | [MSM_SDW_RX7_RX_VOL_CTL] = 0xb, |
| 46 | [MSM_SDW_RX7_RX_PATH_MIX_CTL] = 0xb, |
| 47 | [MSM_SDW_RX7_RX_PATH_MIX_CFG] = 0xb, |
| 48 | [MSM_SDW_RX7_RX_VOL_MIX_CTL] = 0xb, |
| 49 | [MSM_SDW_RX7_RX_PATH_SEC0] = 0xb, |
| 50 | [MSM_SDW_RX7_RX_PATH_SEC1] = 0xb, |
| 51 | [MSM_SDW_RX7_RX_PATH_SEC2] = 0xb, |
| 52 | [MSM_SDW_RX7_RX_PATH_SEC3] = 0xb, |
| 53 | [MSM_SDW_RX7_RX_PATH_SEC5] = 0xb, |
| 54 | [MSM_SDW_RX7_RX_PATH_SEC6] = 0xb, |
| 55 | [MSM_SDW_RX7_RX_PATH_SEC7] = 0xb, |
| 56 | [MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 0xb, |
| 57 | [MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 0xb, |
| 58 | [MSM_SDW_RX8_RX_PATH_CTL] = 0xb, |
| 59 | [MSM_SDW_RX8_RX_PATH_CFG0] = 0xb, |
| 60 | [MSM_SDW_RX8_RX_PATH_CFG1] = 0xb, |
| 61 | [MSM_SDW_RX8_RX_PATH_CFG2] = 0xb, |
| 62 | [MSM_SDW_RX8_RX_VOL_CTL] = 0xb, |
| 63 | [MSM_SDW_RX8_RX_PATH_MIX_CTL] = 0xb, |
| 64 | [MSM_SDW_RX8_RX_PATH_MIX_CFG] = 0xb, |
| 65 | [MSM_SDW_RX8_RX_VOL_MIX_CTL] = 0xb, |
| 66 | [MSM_SDW_RX8_RX_PATH_SEC0] = 0xb, |
| 67 | [MSM_SDW_RX8_RX_PATH_SEC1] = 0xb, |
| 68 | [MSM_SDW_RX8_RX_PATH_SEC2] = 0xb, |
| 69 | [MSM_SDW_RX8_RX_PATH_SEC3] = 0xb, |
| 70 | [MSM_SDW_RX8_RX_PATH_SEC5] = 0xb, |
| 71 | [MSM_SDW_RX8_RX_PATH_SEC6] = 0xb, |
| 72 | [MSM_SDW_RX8_RX_PATH_SEC7] = 0xb, |
| 73 | [MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 0xb, |
| 74 | [MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 0xb, |
| 75 | [MSM_SDW_BOOST0_BOOST_PATH_CTL] = 0xc, |
| 76 | [MSM_SDW_BOOST0_BOOST_CTL] = 0xc, |
| 77 | [MSM_SDW_BOOST0_BOOST_CFG1] = 0xc, |
| 78 | [MSM_SDW_BOOST0_BOOST_CFG2] = 0xc, |
| 79 | [MSM_SDW_BOOST1_BOOST_PATH_CTL] = 0xc, |
| 80 | [MSM_SDW_BOOST1_BOOST_CTL] = 0xc, |
| 81 | [MSM_SDW_BOOST1_BOOST_CFG1] = 0xc, |
| 82 | [MSM_SDW_BOOST1_BOOST_CFG2] = 0xc, |
| 83 | [MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 0xc, |
| 84 | [MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 0xc, |
| 85 | [MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 0xc, |
| 86 | [MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 0xc, |
| 87 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 0xc, |
| 88 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 0xc, |
| 89 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 0xc, |
| 90 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 0xc, |
| 91 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 0xc, |
| 92 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 0xc, |
| 93 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 0xc, |
| 94 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 0xc, |
| 95 | [MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 0xc, |
| 96 | [MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 0xc, |
| 97 | [MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 0xc, |
| 98 | [MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 0xc, |
| 99 | [MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 0xc, |
| 100 | [MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 0xc, |
| 101 | [MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 0xd, |
| 102 | [MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 0xd, |
| 103 | [MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 0xd, |
| 104 | [MSM_SDW_TOP_TOP_CFG0] = 0xd, |
| 105 | [MSM_SDW_TOP_TOP_CFG1] = 0xd, |
| 106 | [MSM_SDW_TOP_RX_I2S_CTL] = 0xd, |
| 107 | [MSM_SDW_TOP_TX_I2S_CTL] = 0xd, |
| 108 | [MSM_SDW_TOP_I2S_CLK] = 0xd, |
| 109 | [MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 0xd, |
| 110 | [MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 0xd, |
| 111 | [MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 0xd, |
| 112 | [MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 0xd, |
| 113 | [MSM_SDW_TOP_FREQ_MCLK] = 0xd, |
| 114 | [MSM_SDW_TOP_DEBUG_BUS_SEL] = 0xd, |
| 115 | [MSM_SDW_TOP_DEBUG_EN] = 0xd, |
| 116 | [MSM_SDW_TOP_I2S_RESET] = 0xd, |
| 117 | [MSM_SDW_TOP_BLOCKS_RESET] = 0xd, |
| 118 | }; |
| 119 | |
| 120 | const u8 msm_sdw_reg_readable[MSM_SDW_MAX_REGISTER] = { |
| 121 | [MSM_SDW_PAGE_REGISTER] = 1, |
| 122 | [MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1, |
| 123 | [MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1, |
| 124 | [MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1, |
| 125 | [MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1, |
| 126 | [MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1, |
| 127 | [MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1, |
| 128 | [MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1, |
| 129 | [MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1, |
| 130 | [MSM_SDW_COMPANDER7_CTL0] = 1, |
| 131 | [MSM_SDW_COMPANDER7_CTL1] = 1, |
| 132 | [MSM_SDW_COMPANDER7_CTL2] = 1, |
| 133 | [MSM_SDW_COMPANDER7_CTL3] = 1, |
| 134 | [MSM_SDW_COMPANDER7_CTL4] = 1, |
| 135 | [MSM_SDW_COMPANDER7_CTL5] = 1, |
| 136 | [MSM_SDW_COMPANDER7_CTL6] = 1, |
| 137 | [MSM_SDW_COMPANDER7_CTL7] = 1, |
| 138 | [MSM_SDW_COMPANDER8_CTL0] = 1, |
| 139 | [MSM_SDW_COMPANDER8_CTL1] = 1, |
| 140 | [MSM_SDW_COMPANDER8_CTL2] = 1, |
| 141 | [MSM_SDW_COMPANDER8_CTL3] = 1, |
| 142 | [MSM_SDW_COMPANDER8_CTL4] = 1, |
| 143 | [MSM_SDW_COMPANDER8_CTL5] = 1, |
| 144 | [MSM_SDW_COMPANDER8_CTL6] = 1, |
| 145 | [MSM_SDW_COMPANDER8_CTL7] = 1, |
| 146 | [MSM_SDW_RX7_RX_PATH_CTL] = 1, |
| 147 | [MSM_SDW_RX7_RX_PATH_CFG0] = 1, |
| 148 | [MSM_SDW_RX7_RX_PATH_CFG1] = 1, |
| 149 | [MSM_SDW_RX7_RX_PATH_CFG2] = 1, |
| 150 | [MSM_SDW_RX7_RX_VOL_CTL] = 1, |
| 151 | [MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1, |
| 152 | [MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1, |
| 153 | [MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1, |
| 154 | [MSM_SDW_RX7_RX_PATH_SEC0] = 1, |
| 155 | [MSM_SDW_RX7_RX_PATH_SEC1] = 1, |
| 156 | [MSM_SDW_RX7_RX_PATH_SEC2] = 1, |
| 157 | [MSM_SDW_RX7_RX_PATH_SEC3] = 1, |
| 158 | [MSM_SDW_RX7_RX_PATH_SEC5] = 1, |
| 159 | [MSM_SDW_RX7_RX_PATH_SEC6] = 1, |
| 160 | [MSM_SDW_RX7_RX_PATH_SEC7] = 1, |
| 161 | [MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1, |
| 162 | [MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1, |
| 163 | [MSM_SDW_RX8_RX_PATH_CTL] = 1, |
| 164 | [MSM_SDW_RX8_RX_PATH_CFG0] = 1, |
| 165 | [MSM_SDW_RX8_RX_PATH_CFG1] = 1, |
| 166 | [MSM_SDW_RX8_RX_PATH_CFG2] = 1, |
| 167 | [MSM_SDW_RX8_RX_VOL_CTL] = 1, |
| 168 | [MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1, |
| 169 | [MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1, |
| 170 | [MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1, |
| 171 | [MSM_SDW_RX8_RX_PATH_SEC0] = 1, |
| 172 | [MSM_SDW_RX8_RX_PATH_SEC1] = 1, |
| 173 | [MSM_SDW_RX8_RX_PATH_SEC2] = 1, |
| 174 | [MSM_SDW_RX8_RX_PATH_SEC3] = 1, |
| 175 | [MSM_SDW_RX8_RX_PATH_SEC5] = 1, |
| 176 | [MSM_SDW_RX8_RX_PATH_SEC6] = 1, |
| 177 | [MSM_SDW_RX8_RX_PATH_SEC7] = 1, |
| 178 | [MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1, |
| 179 | [MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1, |
| 180 | [MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1, |
| 181 | [MSM_SDW_BOOST0_BOOST_CTL] = 1, |
| 182 | [MSM_SDW_BOOST0_BOOST_CFG1] = 1, |
| 183 | [MSM_SDW_BOOST0_BOOST_CFG2] = 1, |
| 184 | [MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1, |
| 185 | [MSM_SDW_BOOST1_BOOST_CTL] = 1, |
| 186 | [MSM_SDW_BOOST1_BOOST_CFG1] = 1, |
| 187 | [MSM_SDW_BOOST1_BOOST_CFG2] = 1, |
| 188 | [MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1, |
| 189 | [MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1, |
| 190 | [MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1, |
| 191 | [MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1, |
| 192 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1, |
| 193 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1, |
| 194 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1, |
| 195 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1, |
| 196 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1, |
| 197 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1, |
| 198 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1, |
| 199 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1, |
| 200 | [MSM_SDW_AHB_BRIDGE_RD_DATA_0] = 1, |
| 201 | [MSM_SDW_AHB_BRIDGE_RD_DATA_1] = 1, |
| 202 | [MSM_SDW_AHB_BRIDGE_RD_DATA_2] = 1, |
| 203 | [MSM_SDW_AHB_BRIDGE_RD_DATA_3] = 1, |
| 204 | [MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1, |
| 205 | [MSM_SDW_AHB_BRIDGE_ACCESS_STATUS] = 1, |
| 206 | [MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1, |
| 207 | [MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1, |
| 208 | [MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1, |
| 209 | [MSM_SDW_TOP_TOP_CFG0] = 1, |
| 210 | [MSM_SDW_TOP_TOP_CFG1] = 1, |
| 211 | [MSM_SDW_TOP_RX_I2S_CTL] = 1, |
| 212 | [MSM_SDW_TOP_TX_I2S_CTL] = 1, |
| 213 | [MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1, |
| 214 | [MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1, |
| 215 | [MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1, |
| 216 | [MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1, |
| 217 | [MSM_SDW_TOP_FREQ_MCLK] = 1, |
| 218 | [MSM_SDW_TOP_DEBUG_BUS_SEL] = 1, |
| 219 | [MSM_SDW_TOP_DEBUG_EN] = 1, |
| 220 | [MSM_SDW_TOP_I2S_RESET] = 1, |
| 221 | [MSM_SDW_TOP_BLOCKS_RESET] = 1, |
| 222 | }; |
| 223 | |
| 224 | const u8 msm_sdw_reg_writeable[MSM_SDW_MAX_REGISTER] = { |
| 225 | [MSM_SDW_PAGE_REGISTER] = 1, |
| 226 | [MSM_SDW_TX9_SPKR_PROT_PATH_CTL] = 1, |
| 227 | [MSM_SDW_TX9_SPKR_PROT_PATH_CFG0] = 1, |
| 228 | [MSM_SDW_TX10_SPKR_PROT_PATH_CTL] = 1, |
| 229 | [MSM_SDW_TX10_SPKR_PROT_PATH_CFG0] = 1, |
| 230 | [MSM_SDW_TX11_SPKR_PROT_PATH_CTL] = 1, |
| 231 | [MSM_SDW_TX11_SPKR_PROT_PATH_CFG0] = 1, |
| 232 | [MSM_SDW_TX12_SPKR_PROT_PATH_CTL] = 1, |
| 233 | [MSM_SDW_TX12_SPKR_PROT_PATH_CFG0] = 1, |
| 234 | [MSM_SDW_COMPANDER7_CTL0] = 1, |
| 235 | [MSM_SDW_COMPANDER7_CTL1] = 1, |
| 236 | [MSM_SDW_COMPANDER7_CTL2] = 1, |
| 237 | [MSM_SDW_COMPANDER7_CTL3] = 1, |
| 238 | [MSM_SDW_COMPANDER7_CTL4] = 1, |
| 239 | [MSM_SDW_COMPANDER7_CTL5] = 1, |
| 240 | [MSM_SDW_COMPANDER7_CTL7] = 1, |
| 241 | [MSM_SDW_COMPANDER8_CTL0] = 1, |
| 242 | [MSM_SDW_COMPANDER8_CTL1] = 1, |
| 243 | [MSM_SDW_COMPANDER8_CTL2] = 1, |
| 244 | [MSM_SDW_COMPANDER8_CTL3] = 1, |
| 245 | [MSM_SDW_COMPANDER8_CTL4] = 1, |
| 246 | [MSM_SDW_COMPANDER8_CTL5] = 1, |
| 247 | [MSM_SDW_COMPANDER8_CTL7] = 1, |
| 248 | [MSM_SDW_RX7_RX_PATH_CTL] = 1, |
| 249 | [MSM_SDW_RX7_RX_PATH_CFG0] = 1, |
| 250 | [MSM_SDW_RX7_RX_PATH_CFG1] = 1, |
| 251 | [MSM_SDW_RX7_RX_PATH_CFG2] = 1, |
| 252 | [MSM_SDW_RX7_RX_VOL_CTL] = 1, |
| 253 | [MSM_SDW_RX7_RX_PATH_MIX_CTL] = 1, |
| 254 | [MSM_SDW_RX7_RX_PATH_MIX_CFG] = 1, |
| 255 | [MSM_SDW_RX7_RX_VOL_MIX_CTL] = 1, |
| 256 | [MSM_SDW_RX7_RX_PATH_SEC0] = 1, |
| 257 | [MSM_SDW_RX7_RX_PATH_SEC1] = 1, |
| 258 | [MSM_SDW_RX7_RX_PATH_SEC2] = 1, |
| 259 | [MSM_SDW_RX7_RX_PATH_SEC3] = 1, |
| 260 | [MSM_SDW_RX7_RX_PATH_SEC5] = 1, |
| 261 | [MSM_SDW_RX7_RX_PATH_SEC6] = 1, |
| 262 | [MSM_SDW_RX7_RX_PATH_SEC7] = 1, |
| 263 | [MSM_SDW_RX7_RX_PATH_MIX_SEC0] = 1, |
| 264 | [MSM_SDW_RX7_RX_PATH_MIX_SEC1] = 1, |
| 265 | [MSM_SDW_RX8_RX_PATH_CTL] = 1, |
| 266 | [MSM_SDW_RX8_RX_PATH_CFG0] = 1, |
| 267 | [MSM_SDW_RX8_RX_PATH_CFG1] = 1, |
| 268 | [MSM_SDW_RX8_RX_PATH_CFG2] = 1, |
| 269 | [MSM_SDW_RX8_RX_VOL_CTL] = 1, |
| 270 | [MSM_SDW_RX8_RX_PATH_MIX_CTL] = 1, |
| 271 | [MSM_SDW_RX8_RX_PATH_MIX_CFG] = 1, |
| 272 | [MSM_SDW_RX8_RX_VOL_MIX_CTL] = 1, |
| 273 | [MSM_SDW_RX8_RX_PATH_SEC0] = 1, |
| 274 | [MSM_SDW_RX8_RX_PATH_SEC1] = 1, |
| 275 | [MSM_SDW_RX8_RX_PATH_SEC2] = 1, |
| 276 | [MSM_SDW_RX8_RX_PATH_SEC3] = 1, |
| 277 | [MSM_SDW_RX8_RX_PATH_SEC5] = 1, |
| 278 | [MSM_SDW_RX8_RX_PATH_SEC6] = 1, |
| 279 | [MSM_SDW_RX8_RX_PATH_SEC7] = 1, |
| 280 | [MSM_SDW_RX8_RX_PATH_MIX_SEC0] = 1, |
| 281 | [MSM_SDW_RX8_RX_PATH_MIX_SEC1] = 1, |
| 282 | [MSM_SDW_BOOST0_BOOST_PATH_CTL] = 1, |
| 283 | [MSM_SDW_BOOST0_BOOST_CTL] = 1, |
| 284 | [MSM_SDW_BOOST0_BOOST_CFG1] = 1, |
| 285 | [MSM_SDW_BOOST0_BOOST_CFG2] = 1, |
| 286 | [MSM_SDW_BOOST1_BOOST_PATH_CTL] = 1, |
| 287 | [MSM_SDW_BOOST1_BOOST_CTL] = 1, |
| 288 | [MSM_SDW_BOOST1_BOOST_CFG1] = 1, |
| 289 | [MSM_SDW_BOOST1_BOOST_CFG2] = 1, |
| 290 | [MSM_SDW_AHB_BRIDGE_WR_DATA_0] = 1, |
| 291 | [MSM_SDW_AHB_BRIDGE_WR_DATA_1] = 1, |
| 292 | [MSM_SDW_AHB_BRIDGE_WR_DATA_2] = 1, |
| 293 | [MSM_SDW_AHB_BRIDGE_WR_DATA_3] = 1, |
| 294 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_0] = 1, |
| 295 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_1] = 1, |
| 296 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_2] = 1, |
| 297 | [MSM_SDW_AHB_BRIDGE_WR_ADDR_3] = 1, |
| 298 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_0] = 1, |
| 299 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_1] = 1, |
| 300 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_2] = 1, |
| 301 | [MSM_SDW_AHB_BRIDGE_RD_ADDR_3] = 1, |
| 302 | [MSM_SDW_AHB_BRIDGE_ACCESS_CFG] = 1, |
| 303 | [MSM_SDW_CLK_RST_CTRL_MCLK_CONTROL] = 1, |
| 304 | [MSM_SDW_CLK_RST_CTRL_FS_CNT_CONTROL] = 1, |
| 305 | [MSM_SDW_CLK_RST_CTRL_SWR_CONTROL] = 1, |
| 306 | [MSM_SDW_TOP_TOP_CFG0] = 1, |
| 307 | [MSM_SDW_TOP_TOP_CFG1] = 1, |
| 308 | [MSM_SDW_TOP_RX_I2S_CTL] = 1, |
| 309 | [MSM_SDW_TOP_TX_I2S_CTL] = 1, |
| 310 | [MSM_SDW_TOP_RX7_PATH_INPUT0_MUX] = 1, |
| 311 | [MSM_SDW_TOP_RX7_PATH_INPUT1_MUX] = 1, |
| 312 | [MSM_SDW_TOP_RX8_PATH_INPUT0_MUX] = 1, |
| 313 | [MSM_SDW_TOP_RX8_PATH_INPUT1_MUX] = 1, |
| 314 | [MSM_SDW_TOP_FREQ_MCLK] = 1, |
| 315 | [MSM_SDW_TOP_DEBUG_BUS_SEL] = 1, |
| 316 | [MSM_SDW_TOP_DEBUG_EN] = 1, |
| 317 | [MSM_SDW_TOP_I2S_RESET] = 1, |
| 318 | [MSM_SDW_TOP_BLOCKS_RESET] = 1, |
| 319 | }; |