| Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #ifndef __WCD934X_DSP_CNTL_H__ |
| 15 | #define __WCD934X_DSP_CNTL_H__ |
| 16 | |
| 17 | #include <sound/soc.h> |
| 18 | #include <sound/wcd-dsp-mgr.h> |
| 19 | |
| 20 | enum cdc_ssr_event { |
| 21 | WCD_CDC_DOWN_EVENT, |
| 22 | WCD_CDC_UP_EVENT, |
| 23 | }; |
| 24 | |
| 25 | struct wcd_dsp_cdc_cb { |
| 26 | /* Callback to enable codec clock */ |
| 27 | int (*cdc_clk_en)(struct snd_soc_codec *, bool); |
| 28 | /* Callback to vote and unvote for SVS2 mode */ |
| 29 | void (*cdc_vote_svs)(struct snd_soc_codec *, bool); |
| 30 | }; |
| 31 | |
| 32 | struct wcd_dsp_irq_info { |
| 33 | /* IPC interrupt */ |
| 34 | int cpe_ipc1_irq; |
| 35 | |
| 36 | /* CPE error summary interrupt */ |
| 37 | int cpe_err_irq; |
| 38 | |
| 39 | /* |
| 40 | * Bit mask to indicate which of the |
| 41 | * error interrupts are to be considered |
| 42 | * as fatal. |
| 43 | */ |
| 44 | u16 fatal_irqs; |
| 45 | }; |
| 46 | |
| 47 | struct wcd_dsp_params { |
| 48 | struct wcd_dsp_cdc_cb *cb; |
| 49 | struct wcd_dsp_irq_info irqs; |
| 50 | |
| 51 | /* Rate at which the codec clock operates */ |
| 52 | u32 clk_rate; |
| 53 | |
| 54 | /* |
| 55 | * Represents the dsp instance, will be used |
| 56 | * to create sysfs and debugfs entries with |
| 57 | * directory wdsp<dsp-instance> |
| 58 | */ |
| 59 | u32 dsp_instance; |
| 60 | }; |
| 61 | |
| 62 | struct wdsp_ssr_entry { |
| 63 | u8 offline; |
| 64 | u8 offline_change; |
| 65 | wait_queue_head_t offline_poll_wait; |
| 66 | struct snd_info_entry *entry; |
| 67 | }; |
| 68 | |
| 69 | struct wcd_dsp_cntl { |
| 70 | /* Handle to codec */ |
| 71 | struct snd_soc_codec *codec; |
| 72 | |
| 73 | /* Clk rate of the codec clock */ |
| 74 | u32 clk_rate; |
| 75 | |
| 76 | /* Callbacks to codec driver */ |
| 77 | const struct wcd_dsp_cdc_cb *cdc_cb; |
| 78 | |
| 79 | /* Completion to indicate WDSP boot done */ |
| 80 | struct completion boot_complete; |
| 81 | |
| 82 | struct wcd_dsp_irq_info irqs; |
| 83 | u32 dsp_instance; |
| 84 | |
| 85 | /* Sysfs entries related */ |
| 86 | int boot_reqs; |
| 87 | struct kobject wcd_kobj; |
| 88 | |
| 89 | /* Debugfs related */ |
| 90 | struct dentry *entry; |
| 91 | u32 debug_mode; |
| 92 | bool ramdump_enable; |
| 93 | |
| 94 | /* WDSP manager drivers data */ |
| 95 | struct device *m_dev; |
| 96 | struct wdsp_mgr_ops *m_ops; |
| 97 | |
| 98 | /* clk related */ |
| 99 | struct mutex clk_mutex; |
| 100 | bool is_clk_enabled; |
| 101 | |
| 102 | /* Keep track of WDSP boot status */ |
| 103 | bool is_wdsp_booted; |
| 104 | |
| 105 | /* SSR related */ |
| 106 | struct wdsp_ssr_entry ssr_entry; |
| 107 | struct mutex ssr_mutex; |
| 108 | |
| 109 | /* Misc device related */ |
| 110 | char miscdev_name[256]; |
| 111 | struct miscdevice miscdev; |
| 112 | }; |
| 113 | |
| 114 | void wcd_dsp_cntl_init(struct snd_soc_codec *codec, |
| 115 | struct wcd_dsp_params *params, |
| 116 | struct wcd_dsp_cntl **cntl); |
| 117 | void wcd_dsp_cntl_deinit(struct wcd_dsp_cntl **cntl); |
| 118 | int wcd_dsp_ssr_event(struct wcd_dsp_cntl *cntl, enum cdc_ssr_event event); |
| 119 | #endif /* end __WCD_DSP_CONTROL_H__ */ |