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Asish Bhattacharya8e2277f2017-07-20 18:31:55 +05301/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef MSM_ANALOG_CDC_H
13#define MSM_ANALOG_CDC_H
14
15#include <sound/soc.h>
16#include <sound/jack.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +053017#include <dsp/q6afe-v2.h>
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053018#include "../wcd-mbhc-v2.h"
19#include "../wcdcal-hwdep.h"
20#include "sdm660-cdc-registers.h"
21
22#define MICBIAS_EXT_BYP_CAP 0x00
23#define MICBIAS_NO_EXT_BYP_CAP 0x01
24
25#define MSM89XX_NUM_IRQ_REGS 2
26#define MAX_REGULATOR 7
27#define MSM89XX_REG_VAL(reg, val) {reg, 0, val}
28
29#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
30
31#define DEFAULT_MULTIPLIER 800
32#define DEFAULT_GAIN 9
33#define DEFAULT_OFFSET 100
34
35extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE];
36extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE];
37extern struct regmap_config msm89xx_cdc_core_regmap_config;
38extern struct regmap_config msm89xx_pmic_cdc_regmap_config;
39
40enum wcd_curr_ref {
41 I_h4_UA = 0,
42 I_pt5_UA,
43 I_14_UA,
44 I_l4_UA,
45 I_1_UA,
46};
47
48enum wcd_mbhc_imp_det_pin {
49 WCD_MBHC_DET_NONE = 0,
50 WCD_MBHC_DET_HPHL,
51 WCD_MBHC_DET_HPHR,
52 WCD_MBHC_DET_BOTH,
53};
54
55
56/* Each micbias can be assigned to one of three cfilters
57 * Vbatt_min >= .15V + ldoh_v
58 * ldoh_v >= .15v + cfiltx_mv
59 * If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
60 * If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
61 * If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
62 * If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
63 */
64
65struct wcd_micbias_setting {
66 u8 ldoh_v;
67 u32 cfilt1_mv; /* in mv */
68 u32 cfilt2_mv; /* in mv */
69 u32 cfilt3_mv; /* in mv */
70 /* Different WCD9xxx series codecs may not
71 * have 4 mic biases. If a codec has fewer
72 * mic biases, some of these properties will
73 * not be used.
74 */
75 u8 bias1_cfilt_sel;
76 u8 bias2_cfilt_sel;
77 u8 bias3_cfilt_sel;
78 u8 bias4_cfilt_sel;
79 u8 bias1_cap_mode;
80 u8 bias2_cap_mode;
81 u8 bias3_cap_mode;
82 u8 bias4_cap_mode;
83 bool bias2_is_headset_only;
84};
85
86enum sdm660_cdc_pid_current {
87 MSM89XX_PID_MIC_2P5_UA,
88 MSM89XX_PID_MIC_5_UA,
89 MSM89XX_PID_MIC_10_UA,
90 MSM89XX_PID_MIC_20_UA,
91};
92
93struct sdm660_cdc_reg_mask_val {
94 u16 reg;
95 u8 mask;
96 u8 val;
97};
98
99enum {
100 /* INTR_REG 0 - Digital Periph */
101 MSM89XX_IRQ_SPKR_CNP = 0,
102 MSM89XX_IRQ_SPKR_CLIP,
103 MSM89XX_IRQ_SPKR_OCP,
104 MSM89XX_IRQ_MBHC_INSREM_DET1,
105 MSM89XX_IRQ_MBHC_RELEASE,
106 MSM89XX_IRQ_MBHC_PRESS,
107 MSM89XX_IRQ_MBHC_INSREM_DET,
108 MSM89XX_IRQ_MBHC_HS_DET,
109 /* INTR_REG 1 - Analog Periph */
110 MSM89XX_IRQ_EAR_OCP,
111 MSM89XX_IRQ_HPHR_OCP,
112 MSM89XX_IRQ_HPHL_OCP,
113 MSM89XX_IRQ_EAR_CNP,
114 MSM89XX_IRQ_HPHR_CNP,
115 MSM89XX_IRQ_HPHL_CNP,
116 MSM89XX_NUM_IRQS,
117};
118
119enum {
120 ON_DEMAND_MICBIAS = 0,
121 ON_DEMAND_SPKDRV,
122 ON_DEMAND_SUPPLIES_MAX,
123};
124
125/*
126 * The delay list is per codec HW specification.
127 * Please add delay in the list in the future instead
128 * of magic number
129 */
130enum {
131 CODEC_DELAY_1_MS = 1000,
132 CODEC_DELAY_1_1_MS = 1100,
133};
134
135struct sdm660_cdc_regulator {
136 const char *name;
137 int min_uv;
138 int max_uv;
139 int optimum_ua;
140 bool ondemand;
141 struct regulator *regulator;
142};
143
144struct on_demand_supply {
145 struct regulator *supply;
146 atomic_t ref;
147 int min_uv;
148 int max_uv;
149 int optimum_ua;
150};
151
152struct wcd_imped_i_ref {
153 enum wcd_curr_ref curr_ref;
154 int min_val;
155 int multiplier;
156 int gain_adj;
157 int offset;
158};
159
160enum sdm660_cdc_micbias_num {
161 MSM89XX_MICBIAS1 = 0,
162};
163
164/* Hold instance to digital codec platform device */
165struct msm_dig_ctrl_data {
166 struct platform_device *dig_pdev;
167};
168
169struct msm_dig_ctrl_platform_data {
170 void *handle;
Vatsal Bucha7be67e52017-10-12 09:14:03 +0530171 void (*set_compander_mode)(void *handle, int val);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530172 void (*update_clkdiv)(void *handle, int val);
173 int (*get_cdc_version)(void *handle);
174 int (*register_notifier)(void *handle,
175 struct notifier_block *nblock,
176 bool enable);
177};
178
179struct sdm660_cdc_priv {
180 struct device *dev;
181 u32 num_of_supplies;
182 struct regulator_bulk_data *supplies;
183 struct snd_soc_codec *codec;
184 struct work_struct msm_anlg_add_child_devices_work;
185 struct msm_dig_ctrl_platform_data dig_plat_data;
186 /* digital codec data structure */
187 struct msm_dig_ctrl_data *dig_ctrl_data;
188 struct blocking_notifier_head notifier;
189 u16 pmic_rev;
190 u16 codec_version;
191 u16 analog_major_rev;
192 u32 boost_voltage;
193 u32 adc_count;
194 u32 rx_bias_count;
195 bool int_mclk0_enabled;
196 u16 boost_option;
197 /* mode to select hd2 */
198 u32 hph_mode;
199 /* compander used for each rx chain */
200 bool spk_boost_set;
201 bool ear_pa_boost_set;
202 bool ext_spk_boost_set;
203 struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
204 struct regulator *spkdrv_reg;
205 struct blocking_notifier_head notifier_mbhc;
206 /* mbhc module */
207 struct wcd_mbhc mbhc;
208 /* cal info for codec */
209 struct fw_info *fw_data;
210 struct notifier_block audio_ssr_nb;
211 int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable);
212 unsigned long status_mask;
213 struct wcd_imped_i_ref imped_i_ref;
214 enum wcd_mbhc_imp_det_pin imped_det_pin;
215 /* Entry for version info */
216 struct snd_info_entry *entry;
217 struct snd_info_entry *version_entry;
218};
219
220struct sdm660_cdc_pdata {
221 struct wcd_micbias_setting micbias;
222 struct sdm660_cdc_regulator regulator[MAX_REGULATOR];
223};
224
Laxminath Kasam8b1366a2017-10-05 01:44:16 +0530225#if IS_ENABLED(CONFIG_SND_SOC_ANALOG_CDC)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530226extern int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
227 int mclk_enable, bool dapm);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530228extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
229 struct wcd_mbhc_config *mbhc_cfg);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530230extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530231extern void sdm660_cdc_update_int_spk_boost(bool enable);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530232extern void msm_anlg_cdc_spk_ext_pa_cb(
233 int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
234 int enable), struct snd_soc_codec *codec);
235int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
236 struct snd_soc_codec *codec);
Laxminath Kasam8b1366a2017-10-05 01:44:16 +0530237#else /* CONFIG_SND_SOC_ANALOG_CDC */
238static inline int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
239 int mclk_enable, bool dapm)
240{
241 return 0;
242}
243static inline int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
244 struct wcd_mbhc_config *mbhc_cfg)
245{
246 return 0;
247}
248static inline void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec)
249{
250
251}
252static inline void sdm660_cdc_update_int_spk_boost(bool enable)
253{
254
255}
256static inline void msm_anlg_cdc_spk_ext_pa_cb(
257 int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
258 int enable), struct snd_soc_codec *codec)
259{
260
261}
262static inline int msm_anlg_codec_info_create_codec_entry(
263 struct snd_info_entry *codec_root,
264 struct snd_soc_codec *codec)
265{
266 return 0;
267}
268#endif /* CONFIG_SND_SOC_ANALOG_CDC */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530269#endif