Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/clk.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/regmap.h> |
| 19 | #include <sound/soc.h> |
| 20 | #include <sound/soc-dapm.h> |
| 21 | #include <sound/tlv.h> |
| 22 | #include "bolero-cdc.h" |
| 23 | #include "bolero-cdc-registers.h" |
| 24 | #include "../msm-cdc-pinctrl.h" |
| 25 | |
| 26 | #define TX_MACRO_MAX_OFFSET 0x1000 |
| 27 | |
| 28 | #define NUM_DECIMATORS 8 |
| 29 | |
| 30 | #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 31 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 32 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| 33 | #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 34 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 35 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 36 | |
| 37 | #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 |
| 38 | #define CF_MIN_3DB_4HZ 0x0 |
| 39 | #define CF_MIN_3DB_75HZ 0x1 |
| 40 | #define CF_MIN_3DB_150HZ 0x2 |
| 41 | |
| 42 | #define TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0 |
| 43 | #define TX_MACRO_MCLK_FREQ 9600000 |
| 44 | #define TX_MACRO_TX_PATH_OFFSET 0x80 |
| 45 | |
| 46 | #define TX_MACRO_TX_UNMUTE_DELAY_MS 40 |
| 47 | |
| 48 | static int tx_unmute_delay = TX_MACRO_TX_UNMUTE_DELAY_MS; |
| 49 | module_param(tx_unmute_delay, int, 0664); |
| 50 | MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); |
| 51 | |
| 52 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 53 | |
| 54 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 55 | struct snd_pcm_hw_params *params, |
| 56 | struct snd_soc_dai *dai); |
| 57 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 58 | unsigned int *tx_num, unsigned int *tx_slot, |
| 59 | unsigned int *rx_num, unsigned int *rx_slot); |
| 60 | |
| 61 | #define TX_MACRO_SWR_STRING_LEN 80 |
| 62 | #define TX_MACRO_CHILD_DEVICES_MAX 3 |
| 63 | |
| 64 | /* Hold instance to soundwire platform device */ |
| 65 | struct tx_macro_swr_ctrl_data { |
| 66 | struct platform_device *tx_swr_pdev; |
| 67 | }; |
| 68 | |
| 69 | struct tx_macro_swr_ctrl_platform_data { |
| 70 | void *handle; /* holds codec private data */ |
| 71 | int (*read)(void *handle, int reg); |
| 72 | int (*write)(void *handle, int reg, int val); |
| 73 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 74 | int (*clk)(void *handle, bool enable); |
| 75 | int (*handle_irq)(void *handle, |
| 76 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 77 | void *data), |
| 78 | void *swrm_handle, |
| 79 | int action); |
| 80 | }; |
| 81 | |
| 82 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 83 | TX_MACRO_AIF_INVALID = 0, |
| 84 | TX_MACRO_AIF1_CAP, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 85 | TX_MACRO_AIF2_CAP, |
| 86 | TX_MACRO_MAX_DAIS |
| 87 | }; |
| 88 | |
| 89 | enum { |
| 90 | TX_MACRO_DEC0, |
| 91 | TX_MACRO_DEC1, |
| 92 | TX_MACRO_DEC2, |
| 93 | TX_MACRO_DEC3, |
| 94 | TX_MACRO_DEC4, |
| 95 | TX_MACRO_DEC5, |
| 96 | TX_MACRO_DEC6, |
| 97 | TX_MACRO_DEC7, |
| 98 | TX_MACRO_DEC_MAX, |
| 99 | }; |
| 100 | |
| 101 | enum { |
| 102 | TX_MACRO_CLK_DIV_2, |
| 103 | TX_MACRO_CLK_DIV_3, |
| 104 | TX_MACRO_CLK_DIV_4, |
| 105 | TX_MACRO_CLK_DIV_6, |
| 106 | TX_MACRO_CLK_DIV_8, |
| 107 | TX_MACRO_CLK_DIV_16, |
| 108 | }; |
| 109 | |
| 110 | struct tx_mute_work { |
| 111 | struct tx_macro_priv *tx_priv; |
| 112 | u32 decimator; |
| 113 | struct delayed_work dwork; |
| 114 | }; |
| 115 | |
| 116 | struct hpf_work { |
| 117 | struct tx_macro_priv *tx_priv; |
| 118 | u8 decimator; |
| 119 | u8 hpf_cut_off_freq; |
| 120 | struct delayed_work dwork; |
| 121 | }; |
| 122 | |
| 123 | struct tx_macro_priv { |
| 124 | struct device *dev; |
| 125 | bool dec_active[NUM_DECIMATORS]; |
| 126 | int tx_mclk_users; |
| 127 | int swr_clk_users; |
| 128 | struct clk *tx_core_clk; |
| 129 | struct clk *tx_npl_clk; |
| 130 | struct mutex mclk_lock; |
| 131 | struct mutex swr_clk_lock; |
| 132 | struct snd_soc_codec *codec; |
| 133 | struct device_node *tx_swr_gpio_p; |
| 134 | struct tx_macro_swr_ctrl_data *swr_ctrl_data; |
| 135 | struct tx_macro_swr_ctrl_platform_data swr_plat_data; |
| 136 | struct work_struct tx_macro_add_child_devices_work; |
| 137 | struct hpf_work tx_hpf_work[NUM_DECIMATORS]; |
| 138 | struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; |
| 139 | s32 dmic_0_1_clk_cnt; |
| 140 | s32 dmic_2_3_clk_cnt; |
| 141 | s32 dmic_4_5_clk_cnt; |
| 142 | s32 dmic_6_7_clk_cnt; |
| 143 | u16 dmic_clk_div; |
| 144 | unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; |
| 145 | unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; |
| 146 | char __iomem *tx_io_base; |
| 147 | struct platform_device *pdev_child_devices |
| 148 | [TX_MACRO_CHILD_DEVICES_MAX]; |
| 149 | int child_count; |
| 150 | }; |
| 151 | |
| 152 | static bool tx_macro_get_data(struct snd_soc_codec *codec, |
| 153 | struct device **tx_dev, |
| 154 | struct tx_macro_priv **tx_priv, |
| 155 | const char *func_name) |
| 156 | { |
| 157 | *tx_dev = bolero_get_device_ptr(codec->dev, TX_MACRO); |
| 158 | if (!(*tx_dev)) { |
| 159 | dev_err(codec->dev, |
| 160 | "%s: null device for macro!\n", func_name); |
| 161 | return false; |
| 162 | } |
| 163 | |
| 164 | *tx_priv = dev_get_drvdata((*tx_dev)); |
| 165 | if (!(*tx_priv)) { |
| 166 | dev_err(codec->dev, |
| 167 | "%s: priv is null for macro!\n", func_name); |
| 168 | return false; |
| 169 | } |
| 170 | |
| 171 | if (!(*tx_priv)->codec) { |
| 172 | dev_err(codec->dev, |
| 173 | "%s: tx_priv->codec not initialized!\n", func_name); |
| 174 | return false; |
| 175 | } |
| 176 | |
| 177 | return true; |
| 178 | } |
| 179 | |
| 180 | static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, |
| 181 | bool mclk_enable) |
| 182 | { |
| 183 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 184 | int ret = 0; |
| 185 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame^] | 186 | if (regmap == NULL) { |
| 187 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 188 | return -EINVAL; |
| 189 | } |
| 190 | |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 191 | dev_dbg(tx_priv->dev, "%s: mclk_enable = %u,clk_users= %d\n", |
| 192 | __func__, mclk_enable, tx_priv->tx_mclk_users); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 193 | |
| 194 | mutex_lock(&tx_priv->mclk_lock); |
| 195 | if (mclk_enable) { |
| 196 | if (tx_priv->tx_mclk_users == 0) { |
| 197 | ret = bolero_request_clock(tx_priv->dev, |
| 198 | TX_MACRO, MCLK_MUX0, true); |
| 199 | if (ret < 0) { |
| 200 | dev_err(tx_priv->dev, |
| 201 | "%s: request clock enable failed\n", |
| 202 | __func__); |
| 203 | goto exit; |
| 204 | } |
| 205 | regcache_mark_dirty(regmap); |
| 206 | regcache_sync_region(regmap, |
| 207 | TX_START_OFFSET, |
| 208 | TX_MAX_OFFSET); |
| 209 | /* 9.6MHz MCLK, set value 0x00 if other frequency */ |
| 210 | regmap_update_bits(regmap, |
| 211 | BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); |
| 212 | regmap_update_bits(regmap, |
| 213 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 214 | 0x01, 0x01); |
| 215 | regmap_update_bits(regmap, |
| 216 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 217 | 0x01, 0x01); |
| 218 | } |
| 219 | tx_priv->tx_mclk_users++; |
| 220 | } else { |
| 221 | if (tx_priv->tx_mclk_users <= 0) { |
| 222 | dev_err(tx_priv->dev, "%s: clock already disabled\n", |
| 223 | __func__); |
| 224 | tx_priv->tx_mclk_users = 0; |
| 225 | goto exit; |
| 226 | } |
| 227 | tx_priv->tx_mclk_users--; |
| 228 | if (tx_priv->tx_mclk_users == 0) { |
| 229 | regmap_update_bits(regmap, |
| 230 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 231 | 0x01, 0x00); |
| 232 | regmap_update_bits(regmap, |
| 233 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 234 | 0x01, 0x00); |
| 235 | bolero_request_clock(tx_priv->dev, |
| 236 | TX_MACRO, MCLK_MUX0, false); |
| 237 | } |
| 238 | } |
| 239 | exit: |
| 240 | mutex_unlock(&tx_priv->mclk_lock); |
| 241 | return ret; |
| 242 | } |
| 243 | |
| 244 | static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 245 | struct snd_kcontrol *kcontrol, int event) |
| 246 | { |
| 247 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 248 | int ret = 0; |
| 249 | struct device *tx_dev = NULL; |
| 250 | struct tx_macro_priv *tx_priv = NULL; |
| 251 | |
| 252 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 253 | return -EINVAL; |
| 254 | |
| 255 | dev_dbg(tx_dev, "%s: event = %d\n", __func__, event); |
| 256 | switch (event) { |
| 257 | case SND_SOC_DAPM_PRE_PMU: |
| 258 | ret = tx_macro_mclk_enable(tx_priv, 1); |
| 259 | break; |
| 260 | case SND_SOC_DAPM_POST_PMD: |
| 261 | ret = tx_macro_mclk_enable(tx_priv, 0); |
| 262 | break; |
| 263 | default: |
| 264 | dev_err(tx_priv->dev, |
| 265 | "%s: invalid DAPM event %d\n", __func__, event); |
| 266 | ret = -EINVAL; |
| 267 | } |
| 268 | return ret; |
| 269 | } |
| 270 | |
| 271 | static int tx_macro_mclk_ctrl(struct device *dev, bool enable) |
| 272 | { |
| 273 | struct tx_macro_priv *tx_priv = dev_get_drvdata(dev); |
| 274 | int ret = 0; |
| 275 | |
| 276 | if (enable) { |
| 277 | ret = clk_prepare_enable(tx_priv->tx_core_clk); |
| 278 | if (ret < 0) { |
| 279 | dev_err(dev, "%s:tx mclk enable failed\n", __func__); |
| 280 | goto exit; |
| 281 | } |
| 282 | ret = clk_prepare_enable(tx_priv->tx_npl_clk); |
| 283 | if (ret < 0) { |
| 284 | dev_err(dev, "%s:tx npl_clk enable failed\n", |
| 285 | __func__); |
| 286 | clk_disable_unprepare(tx_priv->tx_core_clk); |
| 287 | goto exit; |
| 288 | } |
| 289 | } else { |
| 290 | clk_disable_unprepare(tx_priv->tx_npl_clk); |
| 291 | clk_disable_unprepare(tx_priv->tx_core_clk); |
| 292 | } |
| 293 | |
| 294 | exit: |
| 295 | return ret; |
| 296 | } |
| 297 | |
| 298 | static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) |
| 299 | { |
| 300 | struct delayed_work *hpf_delayed_work = NULL; |
| 301 | struct hpf_work *hpf_work = NULL; |
| 302 | struct tx_macro_priv *tx_priv = NULL; |
| 303 | struct snd_soc_codec *codec = NULL; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 304 | u16 dec_cfg_reg = 0, hpf_gate_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 305 | u8 hpf_cut_off_freq = 0; |
| 306 | |
| 307 | hpf_delayed_work = to_delayed_work(work); |
| 308 | hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); |
| 309 | tx_priv = hpf_work->tx_priv; |
| 310 | codec = tx_priv->codec; |
| 311 | hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; |
| 312 | |
| 313 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 314 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 315 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 316 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 317 | |
| 318 | dev_dbg(codec->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n", |
| 319 | __func__, hpf_work->decimator, hpf_cut_off_freq); |
| 320 | |
| 321 | snd_soc_update_bits(codec, dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, |
| 322 | hpf_cut_off_freq << 5); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 323 | snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02); |
| 324 | /* Minimum 1 clk cycle delay is required as per HW spec */ |
| 325 | usleep_range(1000, 1010); |
| 326 | snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | static void tx_macro_mute_update_callback(struct work_struct *work) |
| 330 | { |
| 331 | struct tx_mute_work *tx_mute_dwork = NULL; |
| 332 | struct snd_soc_codec *codec = NULL; |
| 333 | struct tx_macro_priv *tx_priv = NULL; |
| 334 | struct delayed_work *delayed_work = NULL; |
| 335 | u16 tx_vol_ctl_reg = 0, hpf_gate_reg = 0; |
| 336 | u8 decimator = 0; |
| 337 | |
| 338 | delayed_work = to_delayed_work(work); |
| 339 | tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); |
| 340 | tx_priv = tx_mute_dwork->tx_priv; |
| 341 | codec = tx_priv->codec; |
| 342 | decimator = tx_mute_dwork->decimator; |
| 343 | |
| 344 | tx_vol_ctl_reg = |
| 345 | BOLERO_CDC_TX0_TX_PATH_CTL + |
| 346 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 347 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 348 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 349 | snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x01); |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 350 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 351 | dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n", |
| 352 | __func__, decimator); |
| 353 | } |
| 354 | |
| 355 | static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, |
| 356 | struct snd_ctl_elem_value *ucontrol) |
| 357 | { |
| 358 | struct snd_soc_dapm_widget *widget = |
| 359 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 360 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 361 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 362 | unsigned int val = 0; |
| 363 | u16 mic_sel_reg = 0; |
| 364 | |
| 365 | val = ucontrol->value.enumerated.item[0]; |
| 366 | if (val > e->items - 1) |
| 367 | return -EINVAL; |
| 368 | |
| 369 | dev_dbg(codec->dev, "%s: wname: %s, val: 0x%x\n", __func__, |
| 370 | widget->name, val); |
| 371 | |
| 372 | switch (e->reg) { |
| 373 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0: |
| 374 | mic_sel_reg = BOLERO_CDC_TX0_TX_PATH_CFG0; |
| 375 | break; |
| 376 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0: |
| 377 | mic_sel_reg = BOLERO_CDC_TX1_TX_PATH_CFG0; |
| 378 | break; |
| 379 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0: |
| 380 | mic_sel_reg = BOLERO_CDC_TX2_TX_PATH_CFG0; |
| 381 | break; |
| 382 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0: |
| 383 | mic_sel_reg = BOLERO_CDC_TX3_TX_PATH_CFG0; |
| 384 | break; |
| 385 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0: |
| 386 | mic_sel_reg = BOLERO_CDC_TX4_TX_PATH_CFG0; |
| 387 | break; |
| 388 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0: |
| 389 | mic_sel_reg = BOLERO_CDC_TX5_TX_PATH_CFG0; |
| 390 | break; |
| 391 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0: |
| 392 | mic_sel_reg = BOLERO_CDC_TX6_TX_PATH_CFG0; |
| 393 | break; |
| 394 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0: |
| 395 | mic_sel_reg = BOLERO_CDC_TX7_TX_PATH_CFG0; |
| 396 | break; |
| 397 | default: |
| 398 | dev_err(codec->dev, "%s: e->reg: 0x%x not expected\n", |
| 399 | __func__, e->reg); |
| 400 | return -EINVAL; |
| 401 | } |
| 402 | if (strnstr(widget->name, "smic", strlen(widget->name))) { |
| 403 | if (val != 0) { |
| 404 | if (val < 5) |
| 405 | snd_soc_update_bits(codec, mic_sel_reg, |
| 406 | 1 << 7, 0x0 << 7); |
| 407 | else |
| 408 | snd_soc_update_bits(codec, mic_sel_reg, |
| 409 | 1 << 7, 0x1 << 7); |
| 410 | } |
| 411 | } else { |
| 412 | /* DMIC selected */ |
| 413 | if (val != 0) |
| 414 | snd_soc_update_bits(codec, mic_sel_reg, 1 << 7, 1 << 7); |
| 415 | } |
| 416 | |
| 417 | return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 418 | } |
| 419 | |
| 420 | static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, |
| 421 | struct snd_ctl_elem_value *ucontrol) |
| 422 | { |
| 423 | struct snd_soc_dapm_widget *widget = |
| 424 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 425 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 426 | struct soc_multi_mixer_control *mixer = |
| 427 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 428 | u32 dai_id = widget->shift; |
| 429 | u32 dec_id = mixer->shift; |
| 430 | struct device *tx_dev = NULL; |
| 431 | struct tx_macro_priv *tx_priv = NULL; |
| 432 | |
| 433 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 434 | return -EINVAL; |
| 435 | |
| 436 | if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) |
| 437 | ucontrol->value.integer.value[0] = 1; |
| 438 | else |
| 439 | ucontrol->value.integer.value[0] = 0; |
| 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, |
| 444 | struct snd_ctl_elem_value *ucontrol) |
| 445 | { |
| 446 | struct snd_soc_dapm_widget *widget = |
| 447 | snd_soc_dapm_kcontrol_widget(kcontrol); |
| 448 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(widget->dapm); |
| 449 | struct snd_soc_dapm_update *update = NULL; |
| 450 | struct soc_multi_mixer_control *mixer = |
| 451 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 452 | u32 dai_id = widget->shift; |
| 453 | u32 dec_id = mixer->shift; |
| 454 | u32 enable = ucontrol->value.integer.value[0]; |
| 455 | struct device *tx_dev = NULL; |
| 456 | struct tx_macro_priv *tx_priv = NULL; |
| 457 | |
| 458 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 459 | return -EINVAL; |
| 460 | |
| 461 | if (enable) { |
| 462 | set_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 463 | tx_priv->active_ch_cnt[dai_id]++; |
| 464 | } else { |
| 465 | tx_priv->active_ch_cnt[dai_id]--; |
| 466 | clear_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 467 | } |
| 468 | snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); |
| 469 | |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static int tx_macro_enable_dmic(struct snd_soc_dapm_widget *w, |
| 474 | struct snd_kcontrol *kcontrol, int event) |
| 475 | { |
| 476 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 477 | u8 dmic_clk_en = 0x01; |
| 478 | u16 dmic_clk_reg = 0; |
| 479 | s32 *dmic_clk_cnt = NULL; |
| 480 | unsigned int dmic = 0; |
| 481 | int ret = 0; |
| 482 | char *wname = NULL; |
| 483 | struct device *tx_dev = NULL; |
| 484 | struct tx_macro_priv *tx_priv = NULL; |
| 485 | |
| 486 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 487 | return -EINVAL; |
| 488 | |
| 489 | wname = strpbrk(w->name, "01234567"); |
| 490 | if (!wname) { |
| 491 | dev_err(codec->dev, "%s: widget not found\n", __func__); |
| 492 | return -EINVAL; |
| 493 | } |
| 494 | |
| 495 | ret = kstrtouint(wname, 10, &dmic); |
| 496 | if (ret < 0) { |
| 497 | dev_err(codec->dev, "%s: Invalid DMIC line on the codec\n", |
| 498 | __func__); |
| 499 | return -EINVAL; |
| 500 | } |
| 501 | |
| 502 | switch (dmic) { |
| 503 | case 0: |
| 504 | case 1: |
| 505 | dmic_clk_cnt = &(tx_priv->dmic_0_1_clk_cnt); |
| 506 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL; |
| 507 | break; |
| 508 | case 2: |
| 509 | case 3: |
| 510 | dmic_clk_cnt = &(tx_priv->dmic_2_3_clk_cnt); |
| 511 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL; |
| 512 | break; |
| 513 | case 4: |
| 514 | case 5: |
| 515 | dmic_clk_cnt = &(tx_priv->dmic_4_5_clk_cnt); |
| 516 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL; |
| 517 | break; |
| 518 | case 6: |
| 519 | case 7: |
| 520 | dmic_clk_cnt = &(tx_priv->dmic_6_7_clk_cnt); |
| 521 | dmic_clk_reg = BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL; |
| 522 | break; |
| 523 | default: |
| 524 | dev_err(codec->dev, "%s: Invalid DMIC Selection\n", |
| 525 | __func__); |
| 526 | return -EINVAL; |
| 527 | } |
| 528 | dev_dbg(codec->dev, "%s: event %d DMIC%d dmic_clk_cnt %d\n", |
| 529 | __func__, event, dmic, *dmic_clk_cnt); |
| 530 | |
| 531 | switch (event) { |
| 532 | case SND_SOC_DAPM_PRE_PMU: |
| 533 | (*dmic_clk_cnt)++; |
| 534 | if (*dmic_clk_cnt == 1) { |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 535 | snd_soc_update_bits(codec, BOLERO_CDC_VA_TOP_CSR_DMIC_CFG, |
| 536 | 0x80, 0x00); |
| 537 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 538 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 539 | 0x0E, tx_priv->dmic_clk_div << 0x1); |
| 540 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 541 | dmic_clk_en, dmic_clk_en); |
| 542 | } |
| 543 | break; |
| 544 | case SND_SOC_DAPM_POST_PMD: |
| 545 | (*dmic_clk_cnt)--; |
| 546 | if (*dmic_clk_cnt == 0) |
| 547 | snd_soc_update_bits(codec, dmic_clk_reg, |
| 548 | dmic_clk_en, 0); |
| 549 | break; |
| 550 | } |
| 551 | |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, |
| 556 | struct snd_kcontrol *kcontrol, int event) |
| 557 | { |
| 558 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
| 559 | unsigned int decimator = 0; |
| 560 | u16 tx_vol_ctl_reg = 0; |
| 561 | u16 dec_cfg_reg = 0; |
| 562 | u16 hpf_gate_reg = 0; |
| 563 | u16 tx_gain_ctl_reg = 0; |
| 564 | u8 hpf_cut_off_freq = 0; |
| 565 | struct device *tx_dev = NULL; |
| 566 | struct tx_macro_priv *tx_priv = NULL; |
| 567 | |
| 568 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 569 | return -EINVAL; |
| 570 | |
| 571 | decimator = w->shift; |
| 572 | |
| 573 | dev_dbg(codec->dev, "%s(): widget = %s decimator = %u\n", __func__, |
| 574 | w->name, decimator); |
| 575 | |
| 576 | tx_vol_ctl_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 577 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 578 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 579 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 580 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 581 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 582 | tx_gain_ctl_reg = BOLERO_CDC_TX0_TX_VOL_CTL + |
| 583 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 584 | |
| 585 | switch (event) { |
| 586 | case SND_SOC_DAPM_PRE_PMU: |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 587 | /* Enable TX PGA Mute */ |
| 588 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10); |
| 589 | break; |
| 590 | case SND_SOC_DAPM_POST_PMU: |
| 591 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x20, 0x20); |
| 592 | snd_soc_update_bits(codec, hpf_gate_reg, 0x01, 0x00); |
| 593 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 594 | hpf_cut_off_freq = (snd_soc_read(codec, dec_cfg_reg) & |
| 595 | TX_HPF_CUT_OFF_FREQ_MASK) >> 5; |
| 596 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq = |
| 597 | hpf_cut_off_freq; |
| 598 | |
| 599 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) |
| 600 | snd_soc_update_bits(codec, dec_cfg_reg, |
| 601 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 602 | CF_MIN_3DB_150HZ << 5); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 603 | /* schedule work queue to Remove Mute */ |
| 604 | schedule_delayed_work(&tx_priv->tx_mute_dwork[decimator].dwork, |
| 605 | msecs_to_jiffies(tx_unmute_delay)); |
| 606 | if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq != |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 607 | CF_MIN_3DB_150HZ) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 608 | schedule_delayed_work( |
| 609 | &tx_priv->tx_hpf_work[decimator].dwork, |
| 610 | msecs_to_jiffies(300)); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 611 | snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x02); |
| 612 | /* |
| 613 | * Minimum 1 clk cycle delay is required as per HW spec |
| 614 | */ |
| 615 | usleep_range(1000, 1010); |
| 616 | snd_soc_update_bits(codec, hpf_gate_reg, 0x02, 0x00); |
| 617 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 618 | /* apply gain after decimator is enabled */ |
| 619 | snd_soc_write(codec, tx_gain_ctl_reg, |
| 620 | snd_soc_read(codec, tx_gain_ctl_reg)); |
| 621 | break; |
| 622 | case SND_SOC_DAPM_PRE_PMD: |
| 623 | hpf_cut_off_freq = |
| 624 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq; |
| 625 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x10); |
| 626 | if (cancel_delayed_work_sync( |
| 627 | &tx_priv->tx_hpf_work[decimator].dwork)) { |
| 628 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { |
| 629 | snd_soc_update_bits(codec, dec_cfg_reg, |
| 630 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 631 | hpf_cut_off_freq << 5); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 632 | snd_soc_update_bits(codec, hpf_gate_reg, |
| 633 | 0x02, 0x02); |
| 634 | /* |
| 635 | * Minimum 1 clk cycle delay is required |
| 636 | * as per HW spec |
| 637 | */ |
| 638 | usleep_range(1000, 1010); |
| 639 | snd_soc_update_bits(codec, hpf_gate_reg, |
| 640 | 0x02, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 641 | } |
| 642 | } |
| 643 | cancel_delayed_work_sync( |
| 644 | &tx_priv->tx_mute_dwork[decimator].dwork); |
| 645 | break; |
| 646 | case SND_SOC_DAPM_POST_PMD: |
Ramprasad Katkam | 9c2394a | 2018-08-23 13:13:48 +0530 | [diff] [blame] | 647 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x20, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 648 | snd_soc_update_bits(codec, tx_vol_ctl_reg, 0x10, 0x00); |
| 649 | break; |
| 650 | } |
| 651 | return 0; |
| 652 | } |
| 653 | |
| 654 | static int tx_macro_enable_micbias(struct snd_soc_dapm_widget *w, |
| 655 | struct snd_kcontrol *kcontrol, int event) |
| 656 | { |
| 657 | return 0; |
| 658 | } |
| 659 | |
| 660 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 661 | struct snd_pcm_hw_params *params, |
| 662 | struct snd_soc_dai *dai) |
| 663 | { |
| 664 | int tx_fs_rate = -EINVAL; |
| 665 | struct snd_soc_codec *codec = dai->codec; |
| 666 | u32 decimator = 0; |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 667 | u32 sample_rate = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 668 | u16 tx_fs_reg = 0; |
| 669 | struct device *tx_dev = NULL; |
| 670 | struct tx_macro_priv *tx_priv = NULL; |
| 671 | |
| 672 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 673 | return -EINVAL; |
| 674 | |
| 675 | pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 676 | dai->name, dai->id, params_rate(params), |
| 677 | params_channels(params)); |
| 678 | |
| 679 | sample_rate = params_rate(params); |
| 680 | switch (sample_rate) { |
| 681 | case 8000: |
| 682 | tx_fs_rate = 0; |
| 683 | break; |
| 684 | case 16000: |
| 685 | tx_fs_rate = 1; |
| 686 | break; |
| 687 | case 32000: |
| 688 | tx_fs_rate = 3; |
| 689 | break; |
| 690 | case 48000: |
| 691 | tx_fs_rate = 4; |
| 692 | break; |
| 693 | case 96000: |
| 694 | tx_fs_rate = 5; |
| 695 | break; |
| 696 | case 192000: |
| 697 | tx_fs_rate = 6; |
| 698 | break; |
| 699 | case 384000: |
| 700 | tx_fs_rate = 7; |
| 701 | break; |
| 702 | default: |
| 703 | dev_err(codec->dev, "%s: Invalid TX sample rate: %d\n", |
| 704 | __func__, params_rate(params)); |
| 705 | return -EINVAL; |
| 706 | } |
| 707 | for_each_set_bit(decimator, &tx_priv->active_ch_mask[dai->id], |
| 708 | TX_MACRO_DEC_MAX) { |
| 709 | if (decimator >= 0) { |
| 710 | tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 711 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 712 | dev_dbg(codec->dev, "%s: set DEC%u rate to %u\n", |
| 713 | __func__, decimator, sample_rate); |
| 714 | snd_soc_update_bits(codec, tx_fs_reg, 0x0F, |
| 715 | tx_fs_rate); |
| 716 | } else { |
| 717 | dev_err(codec->dev, |
| 718 | "%s: ERROR: Invalid decimator: %d\n", |
| 719 | __func__, decimator); |
| 720 | return -EINVAL; |
| 721 | } |
| 722 | } |
| 723 | return 0; |
| 724 | } |
| 725 | |
| 726 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 727 | unsigned int *tx_num, unsigned int *tx_slot, |
| 728 | unsigned int *rx_num, unsigned int *rx_slot) |
| 729 | { |
| 730 | struct snd_soc_codec *codec = dai->codec; |
| 731 | struct device *tx_dev = NULL; |
| 732 | struct tx_macro_priv *tx_priv = NULL; |
| 733 | |
| 734 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 735 | return -EINVAL; |
| 736 | |
| 737 | switch (dai->id) { |
| 738 | case TX_MACRO_AIF1_CAP: |
| 739 | case TX_MACRO_AIF2_CAP: |
| 740 | *tx_slot = tx_priv->active_ch_mask[dai->id]; |
| 741 | *tx_num = tx_priv->active_ch_cnt[dai->id]; |
| 742 | break; |
| 743 | default: |
| 744 | dev_err(tx_dev, "%s: Invalid AIF\n", __func__); |
| 745 | break; |
| 746 | } |
| 747 | return 0; |
| 748 | } |
| 749 | |
| 750 | static struct snd_soc_dai_ops tx_macro_dai_ops = { |
| 751 | .hw_params = tx_macro_hw_params, |
| 752 | .get_channel_map = tx_macro_get_channel_map, |
| 753 | }; |
| 754 | |
| 755 | static struct snd_soc_dai_driver tx_macro_dai[] = { |
| 756 | { |
| 757 | .name = "tx_macro_tx1", |
| 758 | .id = TX_MACRO_AIF1_CAP, |
| 759 | .capture = { |
| 760 | .stream_name = "TX_AIF1 Capture", |
| 761 | .rates = TX_MACRO_RATES, |
| 762 | .formats = TX_MACRO_FORMATS, |
| 763 | .rate_max = 192000, |
| 764 | .rate_min = 8000, |
| 765 | .channels_min = 1, |
| 766 | .channels_max = 8, |
| 767 | }, |
| 768 | .ops = &tx_macro_dai_ops, |
| 769 | }, |
| 770 | { |
| 771 | .name = "tx_macro_tx2", |
| 772 | .id = TX_MACRO_AIF2_CAP, |
| 773 | .capture = { |
| 774 | .stream_name = "TX_AIF2 Capture", |
| 775 | .rates = TX_MACRO_RATES, |
| 776 | .formats = TX_MACRO_FORMATS, |
| 777 | .rate_max = 192000, |
| 778 | .rate_min = 8000, |
| 779 | .channels_min = 1, |
| 780 | .channels_max = 8, |
| 781 | }, |
| 782 | .ops = &tx_macro_dai_ops, |
| 783 | }, |
| 784 | }; |
| 785 | |
| 786 | #define STRING(name) #name |
| 787 | #define TX_MACRO_DAPM_ENUM(name, reg, offset, text) \ |
| 788 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 789 | static const struct snd_kcontrol_new name##_mux = \ |
| 790 | SOC_DAPM_ENUM(STRING(name), name##_enum) |
| 791 | |
| 792 | #define TX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \ |
| 793 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 794 | static const struct snd_kcontrol_new name##_mux = \ |
| 795 | SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname) |
| 796 | |
| 797 | #define TX_MACRO_DAPM_MUX(name, shift, kctl) \ |
| 798 | SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux) |
| 799 | |
| 800 | static const char * const adc_mux_text[] = { |
| 801 | "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" |
| 802 | }; |
| 803 | |
| 804 | TX_MACRO_DAPM_ENUM(tx_dec0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1, |
| 805 | 0, adc_mux_text); |
| 806 | TX_MACRO_DAPM_ENUM(tx_dec1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1, |
| 807 | 0, adc_mux_text); |
| 808 | TX_MACRO_DAPM_ENUM(tx_dec2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1, |
| 809 | 0, adc_mux_text); |
| 810 | TX_MACRO_DAPM_ENUM(tx_dec3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1, |
| 811 | 0, adc_mux_text); |
| 812 | TX_MACRO_DAPM_ENUM(tx_dec4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1, |
| 813 | 0, adc_mux_text); |
| 814 | TX_MACRO_DAPM_ENUM(tx_dec5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1, |
| 815 | 0, adc_mux_text); |
| 816 | TX_MACRO_DAPM_ENUM(tx_dec6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1, |
| 817 | 0, adc_mux_text); |
| 818 | TX_MACRO_DAPM_ENUM(tx_dec7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1, |
| 819 | 0, adc_mux_text); |
| 820 | |
| 821 | |
| 822 | static const char * const dmic_mux_text[] = { |
| 823 | "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", |
| 824 | "DMIC4", "DMIC5", "DMIC6", "DMIC7" |
| 825 | }; |
| 826 | |
| 827 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 828 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 829 | tx_macro_put_dec_enum); |
| 830 | |
| 831 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 832 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 833 | tx_macro_put_dec_enum); |
| 834 | |
| 835 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 836 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 837 | tx_macro_put_dec_enum); |
| 838 | |
| 839 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 840 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 841 | tx_macro_put_dec_enum); |
| 842 | |
| 843 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 844 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 845 | tx_macro_put_dec_enum); |
| 846 | |
| 847 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 848 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 849 | tx_macro_put_dec_enum); |
| 850 | |
| 851 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 852 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 853 | tx_macro_put_dec_enum); |
| 854 | |
| 855 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 856 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 857 | tx_macro_put_dec_enum); |
| 858 | |
| 859 | static const char * const smic_mux_text[] = { |
| 860 | "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", |
| 861 | "SWR_DMIC0", "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", |
| 862 | "SWR_DMIC4", "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" |
| 863 | }; |
| 864 | |
| 865 | TX_MACRO_DAPM_ENUM_EXT(tx_smic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 866 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 867 | tx_macro_put_dec_enum); |
| 868 | |
| 869 | TX_MACRO_DAPM_ENUM_EXT(tx_smic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 870 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 871 | tx_macro_put_dec_enum); |
| 872 | |
| 873 | TX_MACRO_DAPM_ENUM_EXT(tx_smic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 874 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 875 | tx_macro_put_dec_enum); |
| 876 | |
| 877 | TX_MACRO_DAPM_ENUM_EXT(tx_smic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 878 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 879 | tx_macro_put_dec_enum); |
| 880 | |
| 881 | TX_MACRO_DAPM_ENUM_EXT(tx_smic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 882 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 883 | tx_macro_put_dec_enum); |
| 884 | |
| 885 | TX_MACRO_DAPM_ENUM_EXT(tx_smic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 886 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 887 | tx_macro_put_dec_enum); |
| 888 | |
| 889 | TX_MACRO_DAPM_ENUM_EXT(tx_smic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 890 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 891 | tx_macro_put_dec_enum); |
| 892 | |
| 893 | TX_MACRO_DAPM_ENUM_EXT(tx_smic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 894 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 895 | tx_macro_put_dec_enum); |
| 896 | |
| 897 | static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { |
| 898 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 899 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 900 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 901 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 902 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 903 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 904 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 905 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 906 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 907 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 908 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 909 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 910 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 911 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 912 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 913 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 914 | }; |
| 915 | |
| 916 | static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { |
| 917 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 918 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 919 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 920 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 921 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 922 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 923 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 924 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 925 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 926 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 927 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 928 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 929 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 930 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 931 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 932 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 933 | }; |
| 934 | |
| 935 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { |
| 936 | SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, |
| 937 | SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), |
| 938 | |
| 939 | SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, |
| 940 | SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), |
| 941 | |
| 942 | SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, |
| 943 | tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), |
| 944 | |
| 945 | SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, |
| 946 | tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), |
| 947 | |
| 948 | |
| 949 | TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), |
| 950 | TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), |
| 951 | TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), |
| 952 | TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), |
| 953 | TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), |
| 954 | TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), |
| 955 | TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), |
| 956 | TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), |
| 957 | |
| 958 | TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0), |
| 959 | TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1), |
| 960 | TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2), |
| 961 | TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3), |
| 962 | TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4), |
| 963 | TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5), |
| 964 | TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6), |
| 965 | TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7), |
| 966 | |
| 967 | SND_SOC_DAPM_MICBIAS_E("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, |
| 968 | tx_macro_enable_micbias, |
| 969 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 970 | SND_SOC_DAPM_ADC_E("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0, |
| 971 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 972 | SND_SOC_DAPM_POST_PMD), |
| 973 | |
| 974 | SND_SOC_DAPM_ADC_E("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
| 975 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 976 | SND_SOC_DAPM_POST_PMD), |
| 977 | |
| 978 | SND_SOC_DAPM_ADC_E("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
| 979 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 980 | SND_SOC_DAPM_POST_PMD), |
| 981 | |
| 982 | SND_SOC_DAPM_ADC_E("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0, |
| 983 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 984 | SND_SOC_DAPM_POST_PMD), |
| 985 | |
| 986 | SND_SOC_DAPM_ADC_E("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0, |
| 987 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 988 | SND_SOC_DAPM_POST_PMD), |
| 989 | |
| 990 | SND_SOC_DAPM_ADC_E("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0, |
| 991 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 992 | SND_SOC_DAPM_POST_PMD), |
| 993 | |
| 994 | SND_SOC_DAPM_ADC_E("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0, |
| 995 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 996 | SND_SOC_DAPM_POST_PMD), |
| 997 | |
| 998 | SND_SOC_DAPM_ADC_E("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0, |
| 999 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1000 | SND_SOC_DAPM_POST_PMD), |
| 1001 | |
| 1002 | SND_SOC_DAPM_INPUT("TX SWR_ADC0"), |
| 1003 | SND_SOC_DAPM_INPUT("TX SWR_ADC1"), |
| 1004 | SND_SOC_DAPM_INPUT("TX SWR_ADC2"), |
| 1005 | SND_SOC_DAPM_INPUT("TX SWR_ADC3"), |
| 1006 | SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), |
| 1007 | SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), |
| 1008 | SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), |
| 1009 | SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), |
| 1010 | SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), |
| 1011 | SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), |
| 1012 | SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), |
| 1013 | SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), |
| 1014 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1015 | SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1016 | TX_MACRO_DEC0, 0, |
| 1017 | &tx_dec0_mux, tx_macro_enable_dec, |
| 1018 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1019 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1020 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1021 | SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1022 | TX_MACRO_DEC1, 0, |
| 1023 | &tx_dec1_mux, tx_macro_enable_dec, |
| 1024 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1025 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1026 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1027 | SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1028 | TX_MACRO_DEC2, 0, |
| 1029 | &tx_dec2_mux, tx_macro_enable_dec, |
| 1030 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1031 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1032 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1033 | SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1034 | TX_MACRO_DEC3, 0, |
| 1035 | &tx_dec3_mux, tx_macro_enable_dec, |
| 1036 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1037 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1038 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1039 | SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1040 | TX_MACRO_DEC4, 0, |
| 1041 | &tx_dec4_mux, tx_macro_enable_dec, |
| 1042 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1043 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1044 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1045 | SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1046 | TX_MACRO_DEC5, 0, |
| 1047 | &tx_dec5_mux, tx_macro_enable_dec, |
| 1048 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1049 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1050 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1051 | SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1052 | TX_MACRO_DEC6, 0, |
| 1053 | &tx_dec6_mux, tx_macro_enable_dec, |
| 1054 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1055 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1056 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1057 | SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1058 | TX_MACRO_DEC7, 0, |
| 1059 | &tx_dec7_mux, tx_macro_enable_dec, |
| 1060 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1061 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1062 | |
| 1063 | SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 1064 | tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1065 | }; |
| 1066 | |
| 1067 | static const struct snd_soc_dapm_route tx_audio_map[] = { |
| 1068 | {"TX_AIF1 CAP", NULL, "TX_MCLK"}, |
| 1069 | {"TX_AIF2 CAP", NULL, "TX_MCLK"}, |
| 1070 | |
| 1071 | {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, |
| 1072 | {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, |
| 1073 | |
| 1074 | {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1075 | {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1076 | {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1077 | {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1078 | {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1079 | {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1080 | {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1081 | {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1082 | |
| 1083 | {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1084 | {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1085 | {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1086 | {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1087 | {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1088 | {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1089 | {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1090 | {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1091 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 1092 | {"TX DEC0 MUX", NULL, "TX_MCLK"}, |
| 1093 | {"TX DEC1 MUX", NULL, "TX_MCLK"}, |
| 1094 | {"TX DEC2 MUX", NULL, "TX_MCLK"}, |
| 1095 | {"TX DEC3 MUX", NULL, "TX_MCLK"}, |
| 1096 | {"TX DEC4 MUX", NULL, "TX_MCLK"}, |
| 1097 | {"TX DEC5 MUX", NULL, "TX_MCLK"}, |
| 1098 | {"TX DEC6 MUX", NULL, "TX_MCLK"}, |
| 1099 | {"TX DEC7 MUX", NULL, "TX_MCLK"}, |
| 1100 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1101 | {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, |
| 1102 | {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, |
| 1103 | {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, |
| 1104 | {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, |
| 1105 | {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, |
| 1106 | {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, |
| 1107 | {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, |
| 1108 | {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, |
| 1109 | {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, |
| 1110 | |
| 1111 | {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, |
| 1112 | {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, |
| 1113 | {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, |
| 1114 | {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, |
| 1115 | {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, |
| 1116 | {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1117 | {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1118 | {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1119 | {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1120 | {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1121 | {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1122 | {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1123 | {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1124 | |
| 1125 | {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, |
| 1126 | {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, |
| 1127 | {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, |
| 1128 | {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, |
| 1129 | {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, |
| 1130 | {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, |
| 1131 | {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, |
| 1132 | {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, |
| 1133 | {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, |
| 1134 | |
| 1135 | {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, |
| 1136 | {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, |
| 1137 | {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, |
| 1138 | {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, |
| 1139 | {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, |
| 1140 | {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1141 | {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1142 | {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1143 | {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1144 | {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1145 | {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1146 | {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1147 | {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1148 | |
| 1149 | {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, |
| 1150 | {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, |
| 1151 | {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, |
| 1152 | {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, |
| 1153 | {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, |
| 1154 | {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, |
| 1155 | {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, |
| 1156 | {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, |
| 1157 | {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, |
| 1158 | |
| 1159 | {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, |
| 1160 | {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, |
| 1161 | {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, |
| 1162 | {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, |
| 1163 | {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, |
| 1164 | {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1165 | {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1166 | {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1167 | {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1168 | {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1169 | {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1170 | {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1171 | {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1172 | |
| 1173 | {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, |
| 1174 | {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, |
| 1175 | {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, |
| 1176 | {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, |
| 1177 | {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, |
| 1178 | {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, |
| 1179 | {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, |
| 1180 | {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, |
| 1181 | {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, |
| 1182 | |
| 1183 | {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, |
| 1184 | {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, |
| 1185 | {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, |
| 1186 | {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, |
| 1187 | {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, |
| 1188 | {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1189 | {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1190 | {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1191 | {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1192 | {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1193 | {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1194 | {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1195 | {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1196 | |
| 1197 | {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, |
| 1198 | {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, |
| 1199 | {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, |
| 1200 | {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, |
| 1201 | {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, |
| 1202 | {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, |
| 1203 | {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, |
| 1204 | {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, |
| 1205 | {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, |
| 1206 | |
| 1207 | {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, |
| 1208 | {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, |
| 1209 | {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, |
| 1210 | {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, |
| 1211 | {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, |
| 1212 | {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1213 | {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1214 | {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1215 | {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1216 | {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1217 | {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1218 | {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1219 | {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1220 | |
| 1221 | {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, |
| 1222 | {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, |
| 1223 | {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, |
| 1224 | {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, |
| 1225 | {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, |
| 1226 | {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, |
| 1227 | {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, |
| 1228 | {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, |
| 1229 | {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, |
| 1230 | |
| 1231 | {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, |
| 1232 | {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, |
| 1233 | {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, |
| 1234 | {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, |
| 1235 | {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, |
| 1236 | {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1237 | {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1238 | {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1239 | {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1240 | {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1241 | {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1242 | {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1243 | {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1244 | |
| 1245 | {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, |
| 1246 | {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, |
| 1247 | {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, |
| 1248 | {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, |
| 1249 | {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, |
| 1250 | {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, |
| 1251 | {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, |
| 1252 | {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, |
| 1253 | {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, |
| 1254 | |
| 1255 | {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, |
| 1256 | {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, |
| 1257 | {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, |
| 1258 | {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, |
| 1259 | {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, |
| 1260 | {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1261 | {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1262 | {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1263 | {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1264 | {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1265 | {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1266 | {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1267 | {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1268 | |
| 1269 | {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, |
| 1270 | {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, |
| 1271 | {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, |
| 1272 | {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, |
| 1273 | {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, |
| 1274 | {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, |
| 1275 | {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, |
| 1276 | {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, |
| 1277 | {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, |
| 1278 | |
| 1279 | {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, |
| 1280 | {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, |
| 1281 | {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, |
| 1282 | {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, |
| 1283 | {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, |
| 1284 | {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1285 | {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1286 | {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 1287 | {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 1288 | {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 1289 | {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 1290 | {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 1291 | {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 1292 | }; |
| 1293 | |
| 1294 | static const struct snd_kcontrol_new tx_macro_snd_controls[] = { |
| 1295 | SOC_SINGLE_SX_TLV("TX_DEC0 Volume", |
| 1296 | BOLERO_CDC_TX0_TX_VOL_CTL, |
| 1297 | 0, -84, 40, digital_gain), |
| 1298 | SOC_SINGLE_SX_TLV("TX_DEC1 Volume", |
| 1299 | BOLERO_CDC_TX1_TX_VOL_CTL, |
| 1300 | 0, -84, 40, digital_gain), |
| 1301 | SOC_SINGLE_SX_TLV("TX_DEC2 Volume", |
| 1302 | BOLERO_CDC_TX2_TX_VOL_CTL, |
| 1303 | 0, -84, 40, digital_gain), |
| 1304 | SOC_SINGLE_SX_TLV("TX_DEC3 Volume", |
| 1305 | BOLERO_CDC_TX3_TX_VOL_CTL, |
| 1306 | 0, -84, 40, digital_gain), |
| 1307 | SOC_SINGLE_SX_TLV("TX_DEC4 Volume", |
| 1308 | BOLERO_CDC_TX4_TX_VOL_CTL, |
| 1309 | 0, -84, 40, digital_gain), |
| 1310 | SOC_SINGLE_SX_TLV("TX_DEC5 Volume", |
| 1311 | BOLERO_CDC_TX5_TX_VOL_CTL, |
| 1312 | 0, -84, 40, digital_gain), |
| 1313 | SOC_SINGLE_SX_TLV("TX_DEC6 Volume", |
| 1314 | BOLERO_CDC_TX6_TX_VOL_CTL, |
| 1315 | 0, -84, 40, digital_gain), |
| 1316 | SOC_SINGLE_SX_TLV("TX_DEC7 Volume", |
| 1317 | BOLERO_CDC_TX7_TX_VOL_CTL, |
| 1318 | 0, -84, 40, digital_gain), |
| 1319 | }; |
| 1320 | |
| 1321 | static int tx_macro_swrm_clock(void *handle, bool enable) |
| 1322 | { |
| 1323 | struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle; |
| 1324 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 1325 | int ret = 0; |
| 1326 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame^] | 1327 | if (regmap == NULL) { |
| 1328 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 1329 | return -EINVAL; |
| 1330 | } |
| 1331 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1332 | mutex_lock(&tx_priv->swr_clk_lock); |
| 1333 | |
| 1334 | dev_dbg(tx_priv->dev, "%s: swrm clock %s\n", |
| 1335 | __func__, (enable ? "enable" : "disable")); |
| 1336 | if (enable) { |
| 1337 | if (tx_priv->swr_clk_users == 0) { |
| 1338 | ret = tx_macro_mclk_enable(tx_priv, 1); |
| 1339 | if (ret < 0) { |
| 1340 | dev_err(tx_priv->dev, |
| 1341 | "%s: request clock enable failed\n", |
| 1342 | __func__); |
| 1343 | goto exit; |
| 1344 | } |
| 1345 | regmap_update_bits(regmap, |
| 1346 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1347 | 0x01, 0x01); |
| 1348 | regmap_update_bits(regmap, |
| 1349 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1350 | 0x1C, 0x0C); |
| 1351 | msm_cdc_pinctrl_select_active_state( |
| 1352 | tx_priv->tx_swr_gpio_p); |
| 1353 | } |
| 1354 | tx_priv->swr_clk_users++; |
| 1355 | } else { |
| 1356 | if (tx_priv->swr_clk_users <= 0) { |
| 1357 | dev_err(tx_priv->dev, |
| 1358 | "tx swrm clock users already 0\n"); |
| 1359 | tx_priv->swr_clk_users = 0; |
| 1360 | goto exit; |
| 1361 | } |
| 1362 | tx_priv->swr_clk_users--; |
| 1363 | if (tx_priv->swr_clk_users == 0) { |
| 1364 | regmap_update_bits(regmap, |
| 1365 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 1366 | 0x01, 0x00); |
| 1367 | msm_cdc_pinctrl_select_sleep_state( |
| 1368 | tx_priv->tx_swr_gpio_p); |
| 1369 | tx_macro_mclk_enable(tx_priv, 0); |
| 1370 | } |
| 1371 | } |
| 1372 | dev_dbg(tx_priv->dev, "%s: swrm clock users %d\n", |
| 1373 | __func__, tx_priv->swr_clk_users); |
| 1374 | exit: |
| 1375 | mutex_unlock(&tx_priv->swr_clk_lock); |
| 1376 | return ret; |
| 1377 | } |
| 1378 | |
| 1379 | static int tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, |
| 1380 | struct tx_macro_priv *tx_priv) |
| 1381 | { |
| 1382 | u32 div_factor = TX_MACRO_CLK_DIV_2; |
| 1383 | u32 mclk_rate = TX_MACRO_MCLK_FREQ; |
| 1384 | |
| 1385 | if (dmic_sample_rate == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED || |
| 1386 | mclk_rate % dmic_sample_rate != 0) |
| 1387 | goto undefined_rate; |
| 1388 | |
| 1389 | div_factor = mclk_rate / dmic_sample_rate; |
| 1390 | |
| 1391 | switch (div_factor) { |
| 1392 | case 2: |
| 1393 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 1394 | break; |
| 1395 | case 3: |
| 1396 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_3; |
| 1397 | break; |
| 1398 | case 4: |
| 1399 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_4; |
| 1400 | break; |
| 1401 | case 6: |
| 1402 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_6; |
| 1403 | break; |
| 1404 | case 8: |
| 1405 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_8; |
| 1406 | break; |
| 1407 | case 16: |
| 1408 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_16; |
| 1409 | break; |
| 1410 | default: |
| 1411 | /* Any other DIV factor is invalid */ |
| 1412 | goto undefined_rate; |
| 1413 | } |
| 1414 | |
| 1415 | /* Valid dmic DIV factors */ |
| 1416 | dev_dbg(tx_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n", |
| 1417 | __func__, div_factor, mclk_rate); |
| 1418 | |
| 1419 | return dmic_sample_rate; |
| 1420 | |
| 1421 | undefined_rate: |
| 1422 | dev_dbg(tx_priv->dev, "%s: Invalid rate %d, for mclk %d\n", |
| 1423 | __func__, dmic_sample_rate, mclk_rate); |
| 1424 | dmic_sample_rate = TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED; |
| 1425 | |
| 1426 | return dmic_sample_rate; |
| 1427 | } |
| 1428 | |
| 1429 | static int tx_macro_init(struct snd_soc_codec *codec) |
| 1430 | { |
| 1431 | struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); |
| 1432 | int ret = 0, i = 0; |
| 1433 | struct device *tx_dev = NULL; |
| 1434 | struct tx_macro_priv *tx_priv = NULL; |
| 1435 | |
| 1436 | tx_dev = bolero_get_device_ptr(codec->dev, TX_MACRO); |
| 1437 | if (!tx_dev) { |
| 1438 | dev_err(codec->dev, |
| 1439 | "%s: null device for macro!\n", __func__); |
| 1440 | return -EINVAL; |
| 1441 | } |
| 1442 | tx_priv = dev_get_drvdata(tx_dev); |
| 1443 | if (!tx_priv) { |
| 1444 | dev_err(codec->dev, |
| 1445 | "%s: priv is null for macro!\n", __func__); |
| 1446 | return -EINVAL; |
| 1447 | } |
| 1448 | ret = snd_soc_dapm_new_controls(dapm, tx_macro_dapm_widgets, |
| 1449 | ARRAY_SIZE(tx_macro_dapm_widgets)); |
| 1450 | if (ret < 0) { |
| 1451 | dev_err(tx_dev, "%s: Failed to add controls\n", __func__); |
| 1452 | return ret; |
| 1453 | } |
| 1454 | |
| 1455 | ret = snd_soc_dapm_add_routes(dapm, tx_audio_map, |
| 1456 | ARRAY_SIZE(tx_audio_map)); |
| 1457 | if (ret < 0) { |
| 1458 | dev_err(tx_dev, "%s: Failed to add routes\n", __func__); |
| 1459 | return ret; |
| 1460 | } |
| 1461 | |
| 1462 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 1463 | if (ret < 0) { |
| 1464 | dev_err(tx_dev, "%s: Failed to add widgets\n", __func__); |
| 1465 | return ret; |
| 1466 | } |
| 1467 | |
| 1468 | ret = snd_soc_add_codec_controls(codec, tx_macro_snd_controls, |
| 1469 | ARRAY_SIZE(tx_macro_snd_controls)); |
| 1470 | if (ret < 0) { |
| 1471 | dev_err(tx_dev, "%s: Failed to add snd_ctls\n", __func__); |
| 1472 | return ret; |
| 1473 | } |
| 1474 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1475 | tx_priv->tx_hpf_work[i].tx_priv = tx_priv; |
| 1476 | tx_priv->tx_hpf_work[i].decimator = i; |
| 1477 | INIT_DELAYED_WORK(&tx_priv->tx_hpf_work[i].dwork, |
| 1478 | tx_macro_tx_hpf_corner_freq_callback); |
| 1479 | } |
| 1480 | |
| 1481 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 1482 | tx_priv->tx_mute_dwork[i].tx_priv = tx_priv; |
| 1483 | tx_priv->tx_mute_dwork[i].decimator = i; |
| 1484 | INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork, |
| 1485 | tx_macro_mute_update_callback); |
| 1486 | } |
| 1487 | tx_priv->codec = codec; |
| 1488 | |
| 1489 | return 0; |
| 1490 | } |
| 1491 | |
| 1492 | static int tx_macro_deinit(struct snd_soc_codec *codec) |
| 1493 | { |
| 1494 | struct device *tx_dev = NULL; |
| 1495 | struct tx_macro_priv *tx_priv = NULL; |
| 1496 | |
| 1497 | if (!tx_macro_get_data(codec, &tx_dev, &tx_priv, __func__)) |
| 1498 | return -EINVAL; |
| 1499 | |
| 1500 | tx_priv->codec = NULL; |
| 1501 | return 0; |
| 1502 | } |
| 1503 | |
| 1504 | static void tx_macro_add_child_devices(struct work_struct *work) |
| 1505 | { |
| 1506 | struct tx_macro_priv *tx_priv = NULL; |
| 1507 | struct platform_device *pdev = NULL; |
| 1508 | struct device_node *node = NULL; |
| 1509 | struct tx_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; |
| 1510 | int ret = 0; |
| 1511 | u16 count = 0, ctrl_num = 0; |
| 1512 | struct tx_macro_swr_ctrl_platform_data *platdata = NULL; |
| 1513 | char plat_dev_name[TX_MACRO_SWR_STRING_LEN] = ""; |
| 1514 | bool tx_swr_master_node = false; |
| 1515 | |
| 1516 | tx_priv = container_of(work, struct tx_macro_priv, |
| 1517 | tx_macro_add_child_devices_work); |
| 1518 | if (!tx_priv) { |
| 1519 | pr_err("%s: Memory for tx_priv does not exist\n", |
| 1520 | __func__); |
| 1521 | return; |
| 1522 | } |
| 1523 | |
| 1524 | if (!tx_priv->dev) { |
| 1525 | pr_err("%s: tx dev does not exist\n", __func__); |
| 1526 | return; |
| 1527 | } |
| 1528 | |
| 1529 | if (!tx_priv->dev->of_node) { |
| 1530 | dev_err(tx_priv->dev, |
| 1531 | "%s: DT node for tx_priv does not exist\n", __func__); |
| 1532 | return; |
| 1533 | } |
| 1534 | |
| 1535 | platdata = &tx_priv->swr_plat_data; |
| 1536 | tx_priv->child_count = 0; |
| 1537 | |
| 1538 | for_each_available_child_of_node(tx_priv->dev->of_node, node) { |
| 1539 | tx_swr_master_node = false; |
| 1540 | if (strnstr(node->name, "tx_swr_master", |
| 1541 | strlen("tx_swr_master")) != NULL) |
| 1542 | tx_swr_master_node = true; |
| 1543 | |
| 1544 | if (tx_swr_master_node) |
| 1545 | strlcpy(plat_dev_name, "tx_swr_ctrl", |
| 1546 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 1547 | else |
| 1548 | strlcpy(plat_dev_name, node->name, |
| 1549 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 1550 | |
| 1551 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 1552 | if (!pdev) { |
| 1553 | dev_err(tx_priv->dev, "%s: pdev memory alloc failed\n", |
| 1554 | __func__); |
| 1555 | ret = -ENOMEM; |
| 1556 | goto err; |
| 1557 | } |
| 1558 | pdev->dev.parent = tx_priv->dev; |
| 1559 | pdev->dev.of_node = node; |
| 1560 | |
| 1561 | if (tx_swr_master_node) { |
| 1562 | ret = platform_device_add_data(pdev, platdata, |
| 1563 | sizeof(*platdata)); |
| 1564 | if (ret) { |
| 1565 | dev_err(&pdev->dev, |
| 1566 | "%s: cannot add plat data ctrl:%d\n", |
| 1567 | __func__, ctrl_num); |
| 1568 | goto fail_pdev_add; |
| 1569 | } |
| 1570 | } |
| 1571 | |
| 1572 | ret = platform_device_add(pdev); |
| 1573 | if (ret) { |
| 1574 | dev_err(&pdev->dev, |
| 1575 | "%s: Cannot add platform device\n", |
| 1576 | __func__); |
| 1577 | goto fail_pdev_add; |
| 1578 | } |
| 1579 | |
| 1580 | if (tx_swr_master_node) { |
| 1581 | temp = krealloc(swr_ctrl_data, |
| 1582 | (ctrl_num + 1) * sizeof( |
| 1583 | struct tx_macro_swr_ctrl_data), |
| 1584 | GFP_KERNEL); |
| 1585 | if (!temp) { |
| 1586 | ret = -ENOMEM; |
| 1587 | goto fail_pdev_add; |
| 1588 | } |
| 1589 | swr_ctrl_data = temp; |
| 1590 | swr_ctrl_data[ctrl_num].tx_swr_pdev = pdev; |
| 1591 | ctrl_num++; |
| 1592 | dev_dbg(&pdev->dev, |
| 1593 | "%s: Added soundwire ctrl device(s)\n", |
| 1594 | __func__); |
| 1595 | tx_priv->swr_ctrl_data = swr_ctrl_data; |
| 1596 | } |
| 1597 | if (tx_priv->child_count < TX_MACRO_CHILD_DEVICES_MAX) |
| 1598 | tx_priv->pdev_child_devices[ |
| 1599 | tx_priv->child_count++] = pdev; |
| 1600 | else |
| 1601 | goto err; |
| 1602 | } |
| 1603 | return; |
| 1604 | fail_pdev_add: |
| 1605 | for (count = 0; count < tx_priv->child_count; count++) |
| 1606 | platform_device_put(tx_priv->pdev_child_devices[count]); |
| 1607 | err: |
| 1608 | return; |
| 1609 | } |
| 1610 | |
| 1611 | static void tx_macro_init_ops(struct macro_ops *ops, |
| 1612 | char __iomem *tx_io_base) |
| 1613 | { |
| 1614 | memset(ops, 0, sizeof(struct macro_ops)); |
| 1615 | ops->init = tx_macro_init; |
| 1616 | ops->exit = tx_macro_deinit; |
| 1617 | ops->io_base = tx_io_base; |
| 1618 | ops->dai_ptr = tx_macro_dai; |
| 1619 | ops->num_dais = ARRAY_SIZE(tx_macro_dai); |
| 1620 | ops->mclk_fn = tx_macro_mclk_ctrl; |
| 1621 | } |
| 1622 | |
| 1623 | static int tx_macro_probe(struct platform_device *pdev) |
| 1624 | { |
| 1625 | struct macro_ops ops = {0}; |
| 1626 | struct tx_macro_priv *tx_priv = NULL; |
| 1627 | u32 tx_base_addr = 0, sample_rate = 0; |
| 1628 | char __iomem *tx_io_base = NULL; |
| 1629 | struct clk *tx_core_clk = NULL, *tx_npl_clk = NULL; |
| 1630 | int ret = 0; |
| 1631 | const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate"; |
| 1632 | |
| 1633 | tx_priv = devm_kzalloc(&pdev->dev, sizeof(struct tx_macro_priv), |
| 1634 | GFP_KERNEL); |
| 1635 | if (!tx_priv) |
| 1636 | return -ENOMEM; |
| 1637 | platform_set_drvdata(pdev, tx_priv); |
| 1638 | |
| 1639 | tx_priv->dev = &pdev->dev; |
| 1640 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 1641 | &tx_base_addr); |
| 1642 | if (ret) { |
| 1643 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 1644 | __func__, "reg"); |
| 1645 | return ret; |
| 1646 | } |
| 1647 | dev_set_drvdata(&pdev->dev, tx_priv); |
| 1648 | tx_priv->tx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 1649 | "qcom,tx-swr-gpios", 0); |
| 1650 | if (!tx_priv->tx_swr_gpio_p) { |
| 1651 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 1652 | __func__); |
| 1653 | return -EINVAL; |
| 1654 | } |
| 1655 | tx_io_base = devm_ioremap(&pdev->dev, |
| 1656 | tx_base_addr, TX_MACRO_MAX_OFFSET); |
| 1657 | if (!tx_io_base) { |
| 1658 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 1659 | return -ENOMEM; |
| 1660 | } |
| 1661 | tx_priv->tx_io_base = tx_io_base; |
| 1662 | ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate, |
| 1663 | &sample_rate); |
| 1664 | if (ret) { |
| 1665 | dev_err(&pdev->dev, |
| 1666 | "%s: could not find sample_rate entry in dt\n", |
| 1667 | __func__); |
| 1668 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 1669 | } else { |
| 1670 | if (tx_macro_validate_dmic_sample_rate( |
| 1671 | sample_rate, tx_priv) == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED) |
| 1672 | return -EINVAL; |
| 1673 | } |
| 1674 | |
| 1675 | INIT_WORK(&tx_priv->tx_macro_add_child_devices_work, |
| 1676 | tx_macro_add_child_devices); |
| 1677 | tx_priv->swr_plat_data.handle = (void *) tx_priv; |
| 1678 | tx_priv->swr_plat_data.read = NULL; |
| 1679 | tx_priv->swr_plat_data.write = NULL; |
| 1680 | tx_priv->swr_plat_data.bulk_write = NULL; |
| 1681 | tx_priv->swr_plat_data.clk = tx_macro_swrm_clock; |
| 1682 | tx_priv->swr_plat_data.handle_irq = NULL; |
| 1683 | /* Register MCLK for tx macro */ |
| 1684 | tx_core_clk = devm_clk_get(&pdev->dev, "tx_core_clk"); |
| 1685 | if (IS_ERR(tx_core_clk)) { |
| 1686 | ret = PTR_ERR(tx_core_clk); |
| 1687 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 1688 | __func__, "tx_core_clk", ret); |
| 1689 | return ret; |
| 1690 | } |
| 1691 | tx_priv->tx_core_clk = tx_core_clk; |
| 1692 | /* Register npl clk for soundwire */ |
| 1693 | tx_npl_clk = devm_clk_get(&pdev->dev, "tx_npl_clk"); |
| 1694 | if (IS_ERR(tx_npl_clk)) { |
| 1695 | ret = PTR_ERR(tx_npl_clk); |
| 1696 | dev_err(&pdev->dev, "%s: clk get %s failed %d\n", |
| 1697 | __func__, "tx_npl_clk", ret); |
| 1698 | return ret; |
| 1699 | } |
| 1700 | tx_priv->tx_npl_clk = tx_npl_clk; |
| 1701 | |
| 1702 | mutex_init(&tx_priv->mclk_lock); |
| 1703 | mutex_init(&tx_priv->swr_clk_lock); |
| 1704 | tx_macro_init_ops(&ops, tx_io_base); |
| 1705 | ret = bolero_register_macro(&pdev->dev, TX_MACRO, &ops); |
| 1706 | if (ret) { |
| 1707 | dev_err(&pdev->dev, |
| 1708 | "%s: register macro failed\n", __func__); |
| 1709 | goto err_reg_macro; |
| 1710 | } |
| 1711 | schedule_work(&tx_priv->tx_macro_add_child_devices_work); |
| 1712 | return 0; |
| 1713 | err_reg_macro: |
| 1714 | mutex_destroy(&tx_priv->mclk_lock); |
| 1715 | mutex_destroy(&tx_priv->swr_clk_lock); |
| 1716 | return ret; |
| 1717 | } |
| 1718 | |
| 1719 | static int tx_macro_remove(struct platform_device *pdev) |
| 1720 | { |
| 1721 | struct tx_macro_priv *tx_priv = NULL; |
| 1722 | u16 count = 0; |
| 1723 | |
| 1724 | tx_priv = platform_get_drvdata(pdev); |
| 1725 | |
| 1726 | if (!tx_priv) |
| 1727 | return -EINVAL; |
| 1728 | |
| 1729 | kfree(tx_priv->swr_ctrl_data); |
| 1730 | for (count = 0; count < tx_priv->child_count && |
| 1731 | count < TX_MACRO_CHILD_DEVICES_MAX; count++) |
| 1732 | platform_device_unregister(tx_priv->pdev_child_devices[count]); |
| 1733 | |
| 1734 | mutex_destroy(&tx_priv->mclk_lock); |
| 1735 | mutex_destroy(&tx_priv->swr_clk_lock); |
| 1736 | bolero_unregister_macro(&pdev->dev, TX_MACRO); |
| 1737 | return 0; |
| 1738 | } |
| 1739 | |
| 1740 | |
| 1741 | static const struct of_device_id tx_macro_dt_match[] = { |
| 1742 | {.compatible = "qcom,tx-macro"}, |
| 1743 | {} |
| 1744 | }; |
| 1745 | |
| 1746 | static struct platform_driver tx_macro_driver = { |
| 1747 | .driver = { |
| 1748 | .name = "tx_macro", |
| 1749 | .owner = THIS_MODULE, |
| 1750 | .of_match_table = tx_macro_dt_match, |
| 1751 | }, |
| 1752 | .probe = tx_macro_probe, |
| 1753 | .remove = tx_macro_remove, |
| 1754 | }; |
| 1755 | |
| 1756 | module_platform_driver(tx_macro_driver); |
| 1757 | |
| 1758 | MODULE_DESCRIPTION("TX macro driver"); |
| 1759 | MODULE_LICENSE("GPL v2"); |