Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / 8e2277f79f0fa54d5dc505881025ea27ecd6be6b / . / sound / soc / msm / qdsp6v2 / msm-pcm-routing-v2.h
blob: 19e726001d255b7255a6e3b615939966d9b8ef2f [file] [log] [blame]
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530[diff] [blame^]1/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#ifndef _MSM_PCM_ROUTING_H
13#define _MSM_PCM_ROUTING_H
14#include <sound/apr_audio-v2.h>
15
16/*
17 * These names are used by HAL to specify the BE. If any changes are
18 * made to the string names or the max name length corresponding
19 * changes need to be made in the HAL to ensure they still match.
20 */
21#define LPASS_BE_NAME_MAX_LENGTH 24
22#define LPASS_BE_PRI_I2S_RX "PRIMARY_I2S_RX"
23#define LPASS_BE_PRI_I2S_TX "PRIMARY_I2S_TX"
24#define LPASS_BE_SLIMBUS_0_RX "SLIMBUS_0_RX"
25#define LPASS_BE_SLIMBUS_0_TX "SLIMBUS_0_TX"
26#define LPASS_BE_HDMI "HDMI"
27#define LPASS_BE_DISPLAY_PORT "DISPLAY_PORT"
28#define LPASS_BE_INT_BT_SCO_RX "INT_BT_SCO_RX"
29#define LPASS_BE_INT_BT_SCO_TX "INT_BT_SCO_TX"
30#define LPASS_BE_INT_BT_A2DP_RX "INT_BT_A2DP_RX"
31#define LPASS_BE_INT_FM_RX "INT_FM_RX"
32#define LPASS_BE_INT_FM_TX "INT_FM_TX"
33#define LPASS_BE_AFE_PCM_RX "RT_PROXY_DAI_001_RX"
34#define LPASS_BE_AFE_PCM_TX "RT_PROXY_DAI_002_TX"
35#define LPASS_BE_AUXPCM_RX "AUX_PCM_RX"
36#define LPASS_BE_AUXPCM_TX "AUX_PCM_TX"
37#define LPASS_BE_SEC_AUXPCM_RX "SEC_AUX_PCM_RX"
38#define LPASS_BE_SEC_AUXPCM_TX "SEC_AUX_PCM_TX"
39#define LPASS_BE_TERT_AUXPCM_RX "TERT_AUX_PCM_RX"
40#define LPASS_BE_TERT_AUXPCM_TX "TERT_AUX_PCM_TX"
41#define LPASS_BE_QUAT_AUXPCM_RX "QUAT_AUX_PCM_RX"
42#define LPASS_BE_QUAT_AUXPCM_TX "QUAT_AUX_PCM_TX"
43#define LPASS_BE_VOICE_PLAYBACK_TX "VOICE_PLAYBACK_TX"
44#define LPASS_BE_VOICE2_PLAYBACK_TX "VOICE2_PLAYBACK_TX"
45#define LPASS_BE_INCALL_RECORD_RX "INCALL_RECORD_RX"
46#define LPASS_BE_INCALL_RECORD_TX "INCALL_RECORD_TX"
47#define LPASS_BE_SEC_I2S_RX "SECONDARY_I2S_RX"
48#define LPASS_BE_SPDIF_RX "SPDIF_RX"
49
50#define LPASS_BE_MI2S_RX "MI2S_RX"
51#define LPASS_BE_MI2S_TX "MI2S_TX"
52#define LPASS_BE_QUAT_MI2S_RX "QUAT_MI2S_RX"
53#define LPASS_BE_QUAT_MI2S_TX "QUAT_MI2S_TX"
54#define LPASS_BE_SEC_MI2S_RX "SEC_MI2S_RX"
55#define LPASS_BE_SEC_MI2S_RX_SD1 "SEC_MI2S_RX_SD1"
56#define LPASS_BE_SEC_MI2S_TX "SEC_MI2S_TX"
57#define LPASS_BE_PRI_MI2S_RX "PRI_MI2S_RX"
58#define LPASS_BE_PRI_MI2S_TX "PRI_MI2S_TX"
59#define LPASS_BE_TERT_MI2S_RX "TERTIARY_MI2S_RX"
60#define LPASS_BE_TERT_MI2S_TX "TERTIARY_MI2S_TX"
61#define LPASS_BE_AUDIO_I2S_RX "AUDIO_I2S_RX"
62#define LPASS_BE_STUB_RX "STUB_RX"
63#define LPASS_BE_STUB_TX "STUB_TX"
64#define LPASS_BE_SLIMBUS_1_RX "SLIMBUS_1_RX"
65#define LPASS_BE_SLIMBUS_1_TX "SLIMBUS_1_TX"
66#define LPASS_BE_STUB_1_TX "STUB_1_TX"
67#define LPASS_BE_SLIMBUS_2_RX "SLIMBUS_2_RX"
68#define LPASS_BE_SLIMBUS_2_TX "SLIMBUS_2_TX"
69#define LPASS_BE_SLIMBUS_3_RX "SLIMBUS_3_RX"
70#define LPASS_BE_SLIMBUS_3_TX "SLIMBUS_3_TX"
71#define LPASS_BE_SLIMBUS_4_RX "SLIMBUS_4_RX"
72#define LPASS_BE_SLIMBUS_4_TX "SLIMBUS_4_TX"
73#define LPASS_BE_SLIMBUS_TX_VI "SLIMBUS_TX_VI"
74#define LPASS_BE_SLIMBUS_5_RX "SLIMBUS_5_RX"
75#define LPASS_BE_SLIMBUS_5_TX "SLIMBUS_5_TX"
76#define LPASS_BE_SLIMBUS_6_RX "SLIMBUS_6_RX"
77#define LPASS_BE_SLIMBUS_6_TX "SLIMBUS_6_TX"
78#define LPASS_BE_QUIN_MI2S_RX "QUIN_MI2S_RX"
79#define LPASS_BE_QUIN_MI2S_TX "QUIN_MI2S_TX"
80#define LPASS_BE_SENARY_MI2S_TX "SENARY_MI2S_TX"
81
82#define LPASS_BE_PRI_TDM_RX_0 "PRI_TDM_RX_0"
83#define LPASS_BE_PRI_TDM_TX_0 "PRI_TDM_TX_0"
84#define LPASS_BE_PRI_TDM_RX_1 "PRI_TDM_RX_1"
85#define LPASS_BE_PRI_TDM_TX_1 "PRI_TDM_TX_1"
86#define LPASS_BE_PRI_TDM_RX_2 "PRI_TDM_RX_2"
87#define LPASS_BE_PRI_TDM_TX_2 "PRI_TDM_TX_2"
88#define LPASS_BE_PRI_TDM_RX_3 "PRI_TDM_RX_3"
89#define LPASS_BE_PRI_TDM_TX_3 "PRI_TDM_TX_3"
90#define LPASS_BE_PRI_TDM_RX_4 "PRI_TDM_RX_4"
91#define LPASS_BE_PRI_TDM_TX_4 "PRI_TDM_TX_4"
92#define LPASS_BE_PRI_TDM_RX_5 "PRI_TDM_RX_5"
93#define LPASS_BE_PRI_TDM_TX_5 "PRI_TDM_TX_5"
94#define LPASS_BE_PRI_TDM_RX_6 "PRI_TDM_RX_6"
95#define LPASS_BE_PRI_TDM_TX_6 "PRI_TDM_TX_6"
96#define LPASS_BE_PRI_TDM_RX_7 "PRI_TDM_RX_7"
97#define LPASS_BE_PRI_TDM_TX_7 "PRI_TDM_TX_7"
98#define LPASS_BE_SEC_TDM_RX_0 "SEC_TDM_RX_0"
99#define LPASS_BE_SEC_TDM_TX_0 "SEC_TDM_TX_0"
100#define LPASS_BE_SEC_TDM_RX_1 "SEC_TDM_RX_1"
101#define LPASS_BE_SEC_TDM_TX_1 "SEC_TDM_TX_1"
102#define LPASS_BE_SEC_TDM_RX_2 "SEC_TDM_RX_2"
103#define LPASS_BE_SEC_TDM_TX_2 "SEC_TDM_TX_2"
104#define LPASS_BE_SEC_TDM_RX_3 "SEC_TDM_RX_3"
105#define LPASS_BE_SEC_TDM_TX_3 "SEC_TDM_TX_3"
106#define LPASS_BE_SEC_TDM_RX_4 "SEC_TDM_RX_4"
107#define LPASS_BE_SEC_TDM_TX_4 "SEC_TDM_TX_4"
108#define LPASS_BE_SEC_TDM_RX_5 "SEC_TDM_RX_5"
109#define LPASS_BE_SEC_TDM_TX_5 "SEC_TDM_TX_5"
110#define LPASS_BE_SEC_TDM_RX_6 "SEC_TDM_RX_6"
111#define LPASS_BE_SEC_TDM_TX_6 "SEC_TDM_TX_6"
112#define LPASS_BE_SEC_TDM_RX_7 "SEC_TDM_RX_7"
113#define LPASS_BE_SEC_TDM_TX_7 "SEC_TDM_TX_7"
114#define LPASS_BE_TERT_TDM_RX_0 "TERT_TDM_RX_0"
115#define LPASS_BE_TERT_TDM_TX_0 "TERT_TDM_TX_0"
116#define LPASS_BE_TERT_TDM_RX_1 "TERT_TDM_RX_1"
117#define LPASS_BE_TERT_TDM_TX_1 "TERT_TDM_TX_1"
118#define LPASS_BE_TERT_TDM_RX_2 "TERT_TDM_RX_2"
119#define LPASS_BE_TERT_TDM_TX_2 "TERT_TDM_TX_2"
120#define LPASS_BE_TERT_TDM_RX_3 "TERT_TDM_RX_3"
121#define LPASS_BE_TERT_TDM_TX_3 "TERT_TDM_TX_3"
122#define LPASS_BE_TERT_TDM_RX_4 "TERT_TDM_RX_4"
123#define LPASS_BE_TERT_TDM_TX_4 "TERT_TDM_TX_4"
124#define LPASS_BE_TERT_TDM_RX_5 "TERT_TDM_RX_5"
125#define LPASS_BE_TERT_TDM_TX_5 "TERT_TDM_TX_5"
126#define LPASS_BE_TERT_TDM_RX_6 "TERT_TDM_RX_6"
127#define LPASS_BE_TERT_TDM_TX_6 "TERT_TDM_TX_6"
128#define LPASS_BE_TERT_TDM_RX_7 "TERT_TDM_RX_7"
129#define LPASS_BE_TERT_TDM_TX_7 "TERT_TDM_TX_7"
130#define LPASS_BE_QUAT_TDM_RX_0 "QUAT_TDM_RX_0"
131#define LPASS_BE_QUAT_TDM_TX_0 "QUAT_TDM_TX_0"
132#define LPASS_BE_QUAT_TDM_RX_1 "QUAT_TDM_RX_1"
133#define LPASS_BE_QUAT_TDM_TX_1 "QUAT_TDM_TX_1"
134#define LPASS_BE_QUAT_TDM_RX_2 "QUAT_TDM_RX_2"
135#define LPASS_BE_QUAT_TDM_TX_2 "QUAT_TDM_TX_2"
136#define LPASS_BE_QUAT_TDM_RX_3 "QUAT_TDM_RX_3"
137#define LPASS_BE_QUAT_TDM_TX_3 "QUAT_TDM_TX_3"
138#define LPASS_BE_QUAT_TDM_RX_4 "QUAT_TDM_RX_4"
139#define LPASS_BE_QUAT_TDM_TX_4 "QUAT_TDM_TX_4"
140#define LPASS_BE_QUAT_TDM_RX_5 "QUAT_TDM_RX_5"
141#define LPASS_BE_QUAT_TDM_TX_5 "QUAT_TDM_TX_5"
142#define LPASS_BE_QUAT_TDM_RX_6 "QUAT_TDM_RX_6"
143#define LPASS_BE_QUAT_TDM_TX_6 "QUAT_TDM_TX_6"
144#define LPASS_BE_QUAT_TDM_RX_7 "QUAT_TDM_RX_7"
145#define LPASS_BE_QUAT_TDM_TX_7 "QUAT_TDM_TX_7"
146
147#define LPASS_BE_SLIMBUS_7_RX "SLIMBUS_7_RX"
148#define LPASS_BE_SLIMBUS_7_TX "SLIMBUS_7_TX"
149#define LPASS_BE_SLIMBUS_8_RX "SLIMBUS_8_RX"
150#define LPASS_BE_SLIMBUS_8_TX "SLIMBUS_8_TX"
151
152#define LPASS_BE_USB_AUDIO_RX "USB_AUDIO_RX"
153#define LPASS_BE_USB_AUDIO_TX "USB_AUDIO_TX"
154
155#define LPASS_BE_INT0_MI2S_RX "INT0_MI2S_RX"
156#define LPASS_BE_INT0_MI2S_TX "INT0_MI2S_TX"
157#define LPASS_BE_INT1_MI2S_RX "INT1_MI2S_RX"
158#define LPASS_BE_INT1_MI2S_TX "INT1_MI2S_TX"
159#define LPASS_BE_INT2_MI2S_RX "INT2_MI2S_RX"
160#define LPASS_BE_INT2_MI2S_TX "INT2_MI2S_TX"
161#define LPASS_BE_INT3_MI2S_RX "INT3_MI2S_RX"
162#define LPASS_BE_INT3_MI2S_TX "INT3_MI2S_TX"
163#define LPASS_BE_INT4_MI2S_RX "INT4_MI2S_RX"
164#define LPASS_BE_INT4_MI2S_TX "INT4_MI2S_TX"
165#define LPASS_BE_INT5_MI2S_RX "INT5_MI2S_RX"
166#define LPASS_BE_INT5_MI2S_TX "INT5_MI2S_TX"
167#define LPASS_BE_INT6_MI2S_RX "INT6_MI2S_RX"
168#define LPASS_BE_INT6_MI2S_TX "INT6_MI2S_TX"
169/* For multimedia front-ends, asm session is allocated dynamically.
170 * Hence, asm session/multimedia front-end mapping has to be maintained.
171 * Due to this reason, additional multimedia front-end must be placed before
172 * non-multimedia front-ends.
173 */
174
175enum {
176 MSM_FRONTEND_DAI_MULTIMEDIA1 = 0,
177 MSM_FRONTEND_DAI_MULTIMEDIA2,
178 MSM_FRONTEND_DAI_MULTIMEDIA3,
179 MSM_FRONTEND_DAI_MULTIMEDIA4,
180 MSM_FRONTEND_DAI_MULTIMEDIA5,
181 MSM_FRONTEND_DAI_MULTIMEDIA6,
182 MSM_FRONTEND_DAI_MULTIMEDIA7,
183 MSM_FRONTEND_DAI_MULTIMEDIA8,
184 MSM_FRONTEND_DAI_MULTIMEDIA9,
185 MSM_FRONTEND_DAI_MULTIMEDIA10,
186 MSM_FRONTEND_DAI_MULTIMEDIA11,
187 MSM_FRONTEND_DAI_MULTIMEDIA12,
188 MSM_FRONTEND_DAI_MULTIMEDIA13,
189 MSM_FRONTEND_DAI_MULTIMEDIA14,
190 MSM_FRONTEND_DAI_MULTIMEDIA15,
191 MSM_FRONTEND_DAI_MULTIMEDIA16,
192 MSM_FRONTEND_DAI_MULTIMEDIA17,
193 MSM_FRONTEND_DAI_MULTIMEDIA18,
194 MSM_FRONTEND_DAI_MULTIMEDIA19,
195 MSM_FRONTEND_DAI_MULTIMEDIA20,
196 MSM_FRONTEND_DAI_CS_VOICE,
197 MSM_FRONTEND_DAI_VOIP,
198 MSM_FRONTEND_DAI_AFE_RX,
199 MSM_FRONTEND_DAI_AFE_TX,
200 MSM_FRONTEND_DAI_VOICE_STUB,
201 MSM_FRONTEND_DAI_VOLTE,
202 MSM_FRONTEND_DAI_DTMF_RX,
203 MSM_FRONTEND_DAI_VOICE2,
204 MSM_FRONTEND_DAI_QCHAT,
205 MSM_FRONTEND_DAI_VOLTE_STUB,
206 MSM_FRONTEND_DAI_LSM1,
207 MSM_FRONTEND_DAI_LSM2,
208 MSM_FRONTEND_DAI_LSM3,
209 MSM_FRONTEND_DAI_LSM4,
210 MSM_FRONTEND_DAI_LSM5,
211 MSM_FRONTEND_DAI_LSM6,
212 MSM_FRONTEND_DAI_LSM7,
213 MSM_FRONTEND_DAI_LSM8,
214 MSM_FRONTEND_DAI_VOICE2_STUB,
215 MSM_FRONTEND_DAI_VOWLAN,
216 MSM_FRONTEND_DAI_VOICEMMODE1,
217 MSM_FRONTEND_DAI_VOICEMMODE2,
218 MSM_FRONTEND_DAI_MAX,
219};
220
221#define MSM_FRONTEND_DAI_MM_SIZE (MSM_FRONTEND_DAI_MULTIMEDIA20 + 1)
222#define MSM_FRONTEND_DAI_MM_MAX_ID MSM_FRONTEND_DAI_MULTIMEDIA20
223
224enum {
225 MSM_BACKEND_DAI_PRI_I2S_RX = 0,
226 MSM_BACKEND_DAI_PRI_I2S_TX,
227 MSM_BACKEND_DAI_SLIMBUS_0_RX,
228 MSM_BACKEND_DAI_SLIMBUS_0_TX,
229 MSM_BACKEND_DAI_HDMI_RX,
230 MSM_BACKEND_DAI_INT_BT_SCO_RX,
231 MSM_BACKEND_DAI_INT_BT_SCO_TX,
232 MSM_BACKEND_DAI_INT_FM_RX,
233 MSM_BACKEND_DAI_INT_FM_TX,
234 MSM_BACKEND_DAI_AFE_PCM_RX,
235 MSM_BACKEND_DAI_AFE_PCM_TX,
236 MSM_BACKEND_DAI_AUXPCM_RX,
237 MSM_BACKEND_DAI_AUXPCM_TX,
238 MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
239 MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
240 MSM_BACKEND_DAI_INCALL_RECORD_RX,
241 MSM_BACKEND_DAI_INCALL_RECORD_TX,
242 MSM_BACKEND_DAI_MI2S_RX,
243 MSM_BACKEND_DAI_MI2S_TX,
244 MSM_BACKEND_DAI_SEC_I2S_RX,
245 MSM_BACKEND_DAI_SLIMBUS_1_RX,
246 MSM_BACKEND_DAI_SLIMBUS_1_TX,
247 MSM_BACKEND_DAI_SLIMBUS_2_RX,
248 MSM_BACKEND_DAI_SLIMBUS_2_TX,
249 MSM_BACKEND_DAI_SLIMBUS_3_RX,
250 MSM_BACKEND_DAI_SLIMBUS_3_TX,
251 MSM_BACKEND_DAI_SLIMBUS_4_RX,
252 MSM_BACKEND_DAI_SLIMBUS_4_TX,
253 MSM_BACKEND_DAI_SLIMBUS_5_RX,
254 MSM_BACKEND_DAI_SLIMBUS_5_TX,
255 MSM_BACKEND_DAI_SLIMBUS_6_RX,
256 MSM_BACKEND_DAI_SLIMBUS_6_TX,
257 MSM_BACKEND_DAI_SLIMBUS_7_RX,
258 MSM_BACKEND_DAI_SLIMBUS_7_TX,
259 MSM_BACKEND_DAI_SLIMBUS_8_RX,
260 MSM_BACKEND_DAI_SLIMBUS_8_TX,
261 MSM_BACKEND_DAI_EXTPROC_RX,
262 MSM_BACKEND_DAI_EXTPROC_TX,
263 MSM_BACKEND_DAI_EXTPROC_EC_TX,
264 MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
265 MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
266 MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
267 MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
268 MSM_BACKEND_DAI_PRI_MI2S_RX,
269 MSM_BACKEND_DAI_PRI_MI2S_TX,
270 MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
271 MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
272 MSM_BACKEND_DAI_AUDIO_I2S_RX,
273 MSM_BACKEND_DAI_SEC_AUXPCM_RX,
274 MSM_BACKEND_DAI_SEC_AUXPCM_TX,
275 MSM_BACKEND_DAI_SPDIF_RX,
276 MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1,
277 MSM_BACKEND_DAI_QUINARY_MI2S_RX,
278 MSM_BACKEND_DAI_QUINARY_MI2S_TX,
279 MSM_BACKEND_DAI_SENARY_MI2S_TX,
280 MSM_BACKEND_DAI_PRI_TDM_RX_0,
281 MSM_BACKEND_DAI_PRI_TDM_TX_0,
282 MSM_BACKEND_DAI_PRI_TDM_RX_1,
283 MSM_BACKEND_DAI_PRI_TDM_TX_1,
284 MSM_BACKEND_DAI_PRI_TDM_RX_2,
285 MSM_BACKEND_DAI_PRI_TDM_TX_2,
286 MSM_BACKEND_DAI_PRI_TDM_RX_3,
287 MSM_BACKEND_DAI_PRI_TDM_TX_3,
288 MSM_BACKEND_DAI_PRI_TDM_RX_4,
289 MSM_BACKEND_DAI_PRI_TDM_TX_4,
290 MSM_BACKEND_DAI_PRI_TDM_RX_5,
291 MSM_BACKEND_DAI_PRI_TDM_TX_5,
292 MSM_BACKEND_DAI_PRI_TDM_RX_6,
293 MSM_BACKEND_DAI_PRI_TDM_TX_6,
294 MSM_BACKEND_DAI_PRI_TDM_RX_7,
295 MSM_BACKEND_DAI_PRI_TDM_TX_7,
296 MSM_BACKEND_DAI_SEC_TDM_RX_0,
297 MSM_BACKEND_DAI_SEC_TDM_TX_0,
298 MSM_BACKEND_DAI_SEC_TDM_RX_1,
299 MSM_BACKEND_DAI_SEC_TDM_TX_1,
300 MSM_BACKEND_DAI_SEC_TDM_RX_2,
301 MSM_BACKEND_DAI_SEC_TDM_TX_2,
302 MSM_BACKEND_DAI_SEC_TDM_RX_3,
303 MSM_BACKEND_DAI_SEC_TDM_TX_3,
304 MSM_BACKEND_DAI_SEC_TDM_RX_4,
305 MSM_BACKEND_DAI_SEC_TDM_TX_4,
306 MSM_BACKEND_DAI_SEC_TDM_RX_5,
307 MSM_BACKEND_DAI_SEC_TDM_TX_5,
308 MSM_BACKEND_DAI_SEC_TDM_RX_6,
309 MSM_BACKEND_DAI_SEC_TDM_TX_6,
310 MSM_BACKEND_DAI_SEC_TDM_RX_7,
311 MSM_BACKEND_DAI_SEC_TDM_TX_7,
312 MSM_BACKEND_DAI_TERT_TDM_RX_0,
313 MSM_BACKEND_DAI_TERT_TDM_TX_0,
314 MSM_BACKEND_DAI_TERT_TDM_RX_1,
315 MSM_BACKEND_DAI_TERT_TDM_TX_1,
316 MSM_BACKEND_DAI_TERT_TDM_RX_2,
317 MSM_BACKEND_DAI_TERT_TDM_TX_2,
318 MSM_BACKEND_DAI_TERT_TDM_RX_3,
319 MSM_BACKEND_DAI_TERT_TDM_TX_3,
320 MSM_BACKEND_DAI_TERT_TDM_RX_4,
321 MSM_BACKEND_DAI_TERT_TDM_TX_4,
322 MSM_BACKEND_DAI_TERT_TDM_RX_5,
323 MSM_BACKEND_DAI_TERT_TDM_TX_5,
324 MSM_BACKEND_DAI_TERT_TDM_RX_6,
325 MSM_BACKEND_DAI_TERT_TDM_TX_6,
326 MSM_BACKEND_DAI_TERT_TDM_RX_7,
327 MSM_BACKEND_DAI_TERT_TDM_TX_7,
328 MSM_BACKEND_DAI_QUAT_TDM_RX_0,
329 MSM_BACKEND_DAI_QUAT_TDM_TX_0,
330 MSM_BACKEND_DAI_QUAT_TDM_RX_1,
331 MSM_BACKEND_DAI_QUAT_TDM_TX_1,
332 MSM_BACKEND_DAI_QUAT_TDM_RX_2,
333 MSM_BACKEND_DAI_QUAT_TDM_TX_2,
334 MSM_BACKEND_DAI_QUAT_TDM_RX_3,
335 MSM_BACKEND_DAI_QUAT_TDM_TX_3,
336 MSM_BACKEND_DAI_QUAT_TDM_RX_4,
337 MSM_BACKEND_DAI_QUAT_TDM_TX_4,
338 MSM_BACKEND_DAI_QUAT_TDM_RX_5,
339 MSM_BACKEND_DAI_QUAT_TDM_TX_5,
340 MSM_BACKEND_DAI_QUAT_TDM_RX_6,
341 MSM_BACKEND_DAI_QUAT_TDM_TX_6,
342 MSM_BACKEND_DAI_QUAT_TDM_RX_7,
343 MSM_BACKEND_DAI_QUAT_TDM_TX_7,
344 MSM_BACKEND_DAI_INT_BT_A2DP_RX,
345 MSM_BACKEND_DAI_USB_RX,
346 MSM_BACKEND_DAI_USB_TX,
347 MSM_BACKEND_DAI_DISPLAY_PORT_RX,
348 MSM_BACKEND_DAI_TERT_AUXPCM_RX,
349 MSM_BACKEND_DAI_TERT_AUXPCM_TX,
350 MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
351 MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
352 MSM_BACKEND_DAI_INT0_MI2S_RX,
353 MSM_BACKEND_DAI_INT0_MI2S_TX,
354 MSM_BACKEND_DAI_INT1_MI2S_RX,
355 MSM_BACKEND_DAI_INT1_MI2S_TX,
356 MSM_BACKEND_DAI_INT2_MI2S_RX,
357 MSM_BACKEND_DAI_INT2_MI2S_TX,
358 MSM_BACKEND_DAI_INT3_MI2S_RX,
359 MSM_BACKEND_DAI_INT3_MI2S_TX,
360 MSM_BACKEND_DAI_INT4_MI2S_RX,
361 MSM_BACKEND_DAI_INT4_MI2S_TX,
362 MSM_BACKEND_DAI_INT5_MI2S_RX,
363 MSM_BACKEND_DAI_INT5_MI2S_TX,
364 MSM_BACKEND_DAI_INT6_MI2S_RX,
365 MSM_BACKEND_DAI_INT6_MI2S_TX,
366 MSM_BACKEND_DAI_MAX,
367};
368
369enum msm_pcm_routing_event {
370 MSM_PCM_RT_EVT_BUF_RECFG,
371 MSM_PCM_RT_EVT_DEVSWITCH,
372 MSM_PCM_RT_EVT_MAX,
373};
374
375enum {
376 EXT_EC_REF_NONE = 0,
377 EXT_EC_REF_PRI_MI2S_TX,
378 EXT_EC_REF_SEC_MI2S_TX,
379 EXT_EC_REF_TERT_MI2S_TX,
380 EXT_EC_REF_QUAT_MI2S_TX,
381 EXT_EC_REF_QUIN_MI2S_TX,
382 EXT_EC_REF_SLIM_1_TX,
383};
384
385#define INVALID_SESSION -1
386#define SESSION_TYPE_RX 0
387#define SESSION_TYPE_TX 1
388#define MAX_SESSION_TYPES 2
389#define INT_RX_VOL_MAX_STEPS 0x2000
390#define INT_RX_VOL_GAIN 0x2000
391
392#define RELEASE_LOCK 0
393#define ACQUIRE_LOCK 1
394
395#define MSM_BACKEND_DAI_PP_PARAMS_REQ_MAX 2
396#define HDMI_RX_ID 0x8001
397#define ADM_PP_PARAM_MUTE_ID 0
398#define ADM_PP_PARAM_MUTE_BIT 1
399#define ADM_PP_PARAM_LATENCY_ID 1
400#define ADM_PP_PARAM_LATENCY_BIT 2
401#define BE_DAI_PORT_SESSIONS_IDX_MAX 4
402#define BE_DAI_FE_SESSIONS_IDX_MAX 2
403
404struct msm_pcm_routing_evt {
405 void (*event_func)(enum msm_pcm_routing_event, void *);
406 void *priv_data;
407};
408
409struct msm_pcm_routing_bdai_data {
410 u16 port_id; /* AFE port ID */
411 u8 active; /* track if this backend is enabled */
412
413 /* Front-end sessions */
414 unsigned long fe_sessions[BE_DAI_FE_SESSIONS_IDX_MAX];
415 /*
416 * Track Tx BE ports -> Rx BE ports.
417 * port_sessions[0] used to track BE 0 to BE 63.
418 * port_sessions[1] used to track BE 64 to BE 127.
419 * port_sessions[2] used to track BE 128 to BE 191.
420 * port_sessions[3] used to track BE 192 to BE 255.
421 */
422 u64 port_sessions[BE_DAI_PORT_SESSIONS_IDX_MAX];
423
424 unsigned int sample_rate;
425 unsigned int channel;
426 unsigned int format;
427 unsigned int adm_override_ch;
428 u32 passthr_mode[MSM_FRONTEND_DAI_MAX];
429 char *name;
430};
431
432struct msm_pcm_routing_fdai_data {
433 u16 be_srate; /* track prior backend sample rate for flushing purpose */
434 int strm_id; /* ASM stream ID */
435 int perf_mode;
436 struct msm_pcm_routing_evt event_info;
437};
438
439#define MAX_APP_TYPES 16
440struct msm_pcm_routing_app_type_data {
441 int app_type;
442 u32 sample_rate;
443 int bit_width;
444};
445
446struct msm_pcm_stream_app_type_cfg {
447 int app_type;
448 int acdb_dev_id;
449 int sample_rate;
450};
451
452/* dai_id: front-end ID,
453 * dspst_id: DSP audio stream ID
454 * stream_type: playback or capture
455 */
456int msm_pcm_routing_reg_phy_stream(int fedai_id, int perf_mode, int dspst_id,
457 int stream_type);
458void msm_pcm_routing_reg_psthr_stream(int fedai_id, int dspst_id,
459 int stream_type);
460int msm_pcm_routing_reg_phy_compr_stream(int fedai_id, int perf_mode,
461 int dspst_id, int stream_type,
462 uint32_t compr_passthr);
463
464int msm_pcm_routing_reg_phy_stream_v2(int fedai_id, int perf_mode,
465 int dspst_id, int stream_type,
466 struct msm_pcm_routing_evt event_info);
467
468void msm_pcm_routing_dereg_phy_stream(int fedai_id, int stream_type);
469
470int msm_routing_check_backend_enabled(int fedai_id);
471
472
473void msm_pcm_routing_get_bedai_info(int be_idx,
474 struct msm_pcm_routing_bdai_data *bedai);
475void msm_pcm_routing_get_fedai_info(int fe_idx, int sess_type,
476 struct msm_pcm_routing_fdai_data *fe_dai);
477void msm_pcm_routing_acquire_lock(void);
478void msm_pcm_routing_release_lock(void);
479
480int msm_pcm_routing_reg_stream_app_type_cfg(
481 int fedai_id, int session_type, int be_id,
482 struct msm_pcm_stream_app_type_cfg *cfg_data);
483int msm_pcm_routing_get_stream_app_type_cfg(
484 int fedai_id, int session_type, int *be_id,
485 struct msm_pcm_stream_app_type_cfg *cfg_data);
486#endif /*_MSM_PCM_H*/