Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 2 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/io.h> |
| 8 | #include <linux/platform_device.h> |
| 9 | #include <linux/clk.h> |
| 10 | #include <sound/soc.h> |
| 11 | #include <sound/soc-dapm.h> |
| 12 | #include <sound/tlv.h> |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 13 | #include <soc/swr-common.h> |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 14 | #include <soc/swr-wcd.h> |
| 15 | |
Meng Wang | 11a25cf | 2018-10-31 14:11:26 +0800 | [diff] [blame] | 16 | #include <asoc/msm-cdc-pinctrl.h> |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 17 | #include "bolero-cdc.h" |
| 18 | #include "bolero-cdc-registers.h" |
| 19 | #include "wsa-macro.h" |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 20 | |
| 21 | #define WSA_MACRO_MAX_OFFSET 0x1000 |
| 22 | |
| 23 | #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 24 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 25 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| 26 | #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ |
| 27 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| 28 | #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 29 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 30 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) |
| 31 | |
| 32 | #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 33 | SNDRV_PCM_RATE_48000) |
| 34 | #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 35 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 36 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 37 | |
| 38 | #define NUM_INTERPOLATORS 2 |
| 39 | |
| 40 | #define WSA_MACRO_MUX_INP_SHFT 0x3 |
| 41 | #define WSA_MACRO_MUX_INP_MASK1 0x38 |
| 42 | #define WSA_MACRO_MUX_INP_MASK2 0x38 |
| 43 | #define WSA_MACRO_MUX_CFG_OFFSET 0x8 |
| 44 | #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 |
| 45 | #define WSA_MACRO_RX_COMP_OFFSET 0x40 |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 46 | #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 47 | #define WSA_MACRO_RX_PATH_OFFSET 0x80 |
| 48 | #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 |
| 49 | #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C |
| 50 | #define WSA_MACRO_FS_RATE_MASK 0x0F |
Laxminath Kasam | 5d9ea8d | 2018-11-28 14:32:40 +0530 | [diff] [blame] | 51 | #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 |
| 52 | #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 |
| 53 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 54 | |
| 55 | enum { |
| 56 | WSA_MACRO_RX0 = 0, |
| 57 | WSA_MACRO_RX1, |
| 58 | WSA_MACRO_RX_MIX, |
| 59 | WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, |
| 60 | WSA_MACRO_RX_MIX1, |
| 61 | WSA_MACRO_RX_MAX, |
| 62 | }; |
| 63 | |
| 64 | enum { |
| 65 | WSA_MACRO_TX0 = 0, |
| 66 | WSA_MACRO_TX1, |
| 67 | WSA_MACRO_TX_MAX, |
| 68 | }; |
| 69 | |
| 70 | enum { |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 71 | WSA_MACRO_EC0_MUX = 0, |
| 72 | WSA_MACRO_EC1_MUX, |
| 73 | WSA_MACRO_EC_MUX_MAX, |
| 74 | }; |
| 75 | |
| 76 | enum { |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 77 | WSA_MACRO_COMP1, /* SPK_L */ |
| 78 | WSA_MACRO_COMP2, /* SPK_R */ |
| 79 | WSA_MACRO_COMP_MAX |
| 80 | }; |
| 81 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 82 | enum { |
| 83 | WSA_MACRO_SOFTCLIP0, /* RX0 */ |
| 84 | WSA_MACRO_SOFTCLIP1, /* RX1 */ |
| 85 | WSA_MACRO_SOFTCLIP_MAX |
| 86 | }; |
| 87 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 88 | struct interp_sample_rate { |
| 89 | int sample_rate; |
| 90 | int rate_val; |
| 91 | }; |
| 92 | |
| 93 | /* |
| 94 | * Structure used to update codec |
| 95 | * register defaults after reset |
| 96 | */ |
| 97 | struct wsa_macro_reg_mask_val { |
| 98 | u16 reg; |
| 99 | u8 mask; |
| 100 | u8 val; |
| 101 | }; |
| 102 | |
| 103 | static struct interp_sample_rate int_prim_sample_rate_val[] = { |
| 104 | {8000, 0x0}, /* 8K */ |
| 105 | {16000, 0x1}, /* 16K */ |
| 106 | {24000, -EINVAL},/* 24K */ |
| 107 | {32000, 0x3}, /* 32K */ |
| 108 | {48000, 0x4}, /* 48K */ |
| 109 | {96000, 0x5}, /* 96K */ |
| 110 | {192000, 0x6}, /* 192K */ |
| 111 | {384000, 0x7}, /* 384K */ |
| 112 | {44100, 0x8}, /* 44.1K */ |
| 113 | }; |
| 114 | |
| 115 | static struct interp_sample_rate int_mix_sample_rate_val[] = { |
| 116 | {48000, 0x4}, /* 48K */ |
| 117 | {96000, 0x5}, /* 96K */ |
| 118 | {192000, 0x6}, /* 192K */ |
| 119 | }; |
| 120 | |
| 121 | #define WSA_MACRO_SWR_STRING_LEN 80 |
| 122 | |
| 123 | static int wsa_macro_hw_params(struct snd_pcm_substream *substream, |
| 124 | struct snd_pcm_hw_params *params, |
| 125 | struct snd_soc_dai *dai); |
| 126 | static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, |
| 127 | unsigned int *tx_num, unsigned int *tx_slot, |
| 128 | unsigned int *rx_num, unsigned int *rx_slot); |
| 129 | /* Hold instance to soundwire platform device */ |
| 130 | struct wsa_macro_swr_ctrl_data { |
| 131 | struct platform_device *wsa_swr_pdev; |
| 132 | }; |
| 133 | |
| 134 | struct wsa_macro_swr_ctrl_platform_data { |
| 135 | void *handle; /* holds codec private data */ |
| 136 | int (*read)(void *handle, int reg); |
| 137 | int (*write)(void *handle, int reg, int val); |
| 138 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 139 | int (*clk)(void *handle, bool enable); |
| 140 | int (*handle_irq)(void *handle, |
| 141 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 142 | void *data), |
| 143 | void *swrm_handle, |
| 144 | int action); |
| 145 | }; |
| 146 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 147 | struct wsa_macro_bcl_pmic_params { |
| 148 | u8 id; |
| 149 | u8 sid; |
| 150 | u8 ppid; |
| 151 | }; |
| 152 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 153 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 154 | WSA_MACRO_AIF_INVALID = 0, |
| 155 | WSA_MACRO_AIF1_PB, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 156 | WSA_MACRO_AIF_MIX1_PB, |
| 157 | WSA_MACRO_AIF_VI, |
| 158 | WSA_MACRO_AIF_ECHO, |
| 159 | WSA_MACRO_MAX_DAIS, |
| 160 | }; |
| 161 | |
| 162 | #define WSA_MACRO_CHILD_DEVICES_MAX 3 |
| 163 | |
| 164 | /* |
| 165 | * @dev: wsa macro device pointer |
| 166 | * @comp_enabled: compander enable mixer value set |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 167 | * @ec_hq: echo HQ enable mixer value set |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 168 | * @prim_int_users: Users of interpolator |
| 169 | * @wsa_mclk_users: WSA MCLK users count |
| 170 | * @swr_clk_users: SWR clk users count |
| 171 | * @vi_feed_value: VI sense mask |
| 172 | * @mclk_lock: to lock mclk operations |
| 173 | * @swr_clk_lock: to lock swr master clock operations |
| 174 | * @swr_ctrl_data: SoundWire data structure |
| 175 | * @swr_plat_data: Soundwire platform data |
| 176 | * @wsa_macro_add_child_devices_work: work for adding child devices |
| 177 | * @wsa_swr_gpio_p: used by pinctrl API |
| 178 | * @wsa_core_clk: MCLK for wsa macro |
| 179 | * @wsa_npl_clk: NPL clock for WSA soundwire |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 180 | * @component: codec handle |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 181 | * @rx_0_count: RX0 interpolation users |
| 182 | * @rx_1_count: RX1 interpolation users |
| 183 | * @active_ch_mask: channel mask for all AIF DAIs |
| 184 | * @active_ch_cnt: channel count of all AIF DAIs |
| 185 | * @rx_port_value: mixer ctl value of WSA RX MUXes |
| 186 | * @wsa_io_base: Base address of WSA macro addr space |
| 187 | */ |
| 188 | struct wsa_macro_priv { |
| 189 | struct device *dev; |
| 190 | int comp_enabled[WSA_MACRO_COMP_MAX]; |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 191 | int ec_hq[WSA_MACRO_RX1 + 1]; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 192 | u16 prim_int_users[WSA_MACRO_RX1 + 1]; |
| 193 | u16 wsa_mclk_users; |
| 194 | u16 swr_clk_users; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 195 | bool reset_swr; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 196 | unsigned int vi_feed_value; |
| 197 | struct mutex mclk_lock; |
| 198 | struct mutex swr_clk_lock; |
| 199 | struct wsa_macro_swr_ctrl_data *swr_ctrl_data; |
| 200 | struct wsa_macro_swr_ctrl_platform_data swr_plat_data; |
| 201 | struct work_struct wsa_macro_add_child_devices_work; |
| 202 | struct device_node *wsa_swr_gpio_p; |
| 203 | struct clk *wsa_core_clk; |
| 204 | struct clk *wsa_npl_clk; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 205 | struct snd_soc_component *component; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 206 | int rx_0_count; |
| 207 | int rx_1_count; |
| 208 | unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; |
| 209 | unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; |
| 210 | int rx_port_value[WSA_MACRO_RX_MAX]; |
| 211 | char __iomem *wsa_io_base; |
| 212 | struct platform_device *pdev_child_devices |
| 213 | [WSA_MACRO_CHILD_DEVICES_MAX]; |
| 214 | int child_count; |
| 215 | int ear_spkr_gain; |
| 216 | int spkr_gain_offset; |
| 217 | int spkr_mode; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 218 | int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; |
| 219 | int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; |
| 220 | struct wsa_macro_bcl_pmic_params bcl_pmic_params; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 221 | }; |
| 222 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 223 | static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 224 | struct wsa_macro_priv *wsa_priv, |
| 225 | int event, int gain_reg); |
| 226 | static struct snd_soc_dai_driver wsa_macro_dai[]; |
| 227 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 228 | |
| 229 | static const char *const rx_text[] = { |
| 230 | "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1" |
| 231 | }; |
| 232 | |
| 233 | static const char *const rx_mix_text[] = { |
| 234 | "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1" |
| 235 | }; |
| 236 | |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 237 | static const char *const rx_mix_ec_text[] = { |
| 238 | "ZERO", "RX_MIX_TX0", "RX_MIX_TX1" |
| 239 | }; |
| 240 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 241 | static const char *const rx_mux_text[] = { |
| 242 | "ZERO", "AIF1_PB", "AIF_MIX1_PB" |
| 243 | }; |
| 244 | |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 245 | static const char *const rx_sidetone_mix_text[] = { |
| 246 | "ZERO", "SRC0" |
| 247 | }; |
| 248 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 249 | static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { |
| 250 | "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", |
| 251 | "G_4_DB", "G_5_DB", "G_6_DB" |
| 252 | }; |
| 253 | |
| 254 | static const char * const wsa_macro_speaker_boost_stage_text[] = { |
| 255 | "NO_MAX_STATE", "MAX_STATE_1", "MAX_STATE_2" |
| 256 | }; |
| 257 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 258 | static const char * const wsa_macro_vbat_bcl_gsm_mode_text[] = { |
| 259 | "OFF", "ON" |
| 260 | }; |
| 261 | |
| 262 | static const struct snd_kcontrol_new wsa_int0_vbat_mix_switch[] = { |
| 263 | SOC_DAPM_SINGLE("WSA RX0 VBAT Enable", SND_SOC_NOPM, 0, 1, 0) |
| 264 | }; |
| 265 | |
| 266 | static const struct snd_kcontrol_new wsa_int1_vbat_mix_switch[] = { |
| 267 | SOC_DAPM_SINGLE("WSA RX1 VBAT Enable", SND_SOC_NOPM, 0, 1, 0) |
| 268 | }; |
| 269 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 270 | static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, |
| 271 | wsa_macro_ear_spkr_pa_gain_text); |
| 272 | static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_spkr_boost_stage_enum, |
| 273 | wsa_macro_speaker_boost_stage_text); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 274 | static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_vbat_bcl_gsm_mode_enum, |
| 275 | wsa_macro_vbat_bcl_gsm_mode_text); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 276 | |
| 277 | /* RX INT0 */ |
| 278 | static const struct soc_enum rx0_prim_inp0_chain_enum = |
| 279 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, |
| 280 | 0, 7, rx_text); |
| 281 | |
| 282 | static const struct soc_enum rx0_prim_inp1_chain_enum = |
| 283 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, |
| 284 | 3, 7, rx_text); |
| 285 | |
| 286 | static const struct soc_enum rx0_prim_inp2_chain_enum = |
| 287 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, |
| 288 | 3, 7, rx_text); |
| 289 | |
| 290 | static const struct soc_enum rx0_mix_chain_enum = |
| 291 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, |
| 292 | 0, 5, rx_mix_text); |
| 293 | |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 294 | static const struct soc_enum rx0_sidetone_mix_enum = |
| 295 | SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text); |
| 296 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 297 | static const struct snd_kcontrol_new rx0_prim_inp0_mux = |
| 298 | SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum); |
| 299 | |
| 300 | static const struct snd_kcontrol_new rx0_prim_inp1_mux = |
| 301 | SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum); |
| 302 | |
| 303 | static const struct snd_kcontrol_new rx0_prim_inp2_mux = |
| 304 | SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum); |
| 305 | |
| 306 | static const struct snd_kcontrol_new rx0_mix_mux = |
| 307 | SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum); |
| 308 | |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 309 | static const struct snd_kcontrol_new rx0_sidetone_mix_mux = |
| 310 | SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum); |
| 311 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 312 | /* RX INT1 */ |
| 313 | static const struct soc_enum rx1_prim_inp0_chain_enum = |
| 314 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, |
| 315 | 0, 7, rx_text); |
| 316 | |
| 317 | static const struct soc_enum rx1_prim_inp1_chain_enum = |
| 318 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, |
| 319 | 3, 7, rx_text); |
| 320 | |
| 321 | static const struct soc_enum rx1_prim_inp2_chain_enum = |
| 322 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, |
| 323 | 3, 7, rx_text); |
| 324 | |
| 325 | static const struct soc_enum rx1_mix_chain_enum = |
| 326 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, |
| 327 | 0, 5, rx_mix_text); |
| 328 | |
| 329 | static const struct snd_kcontrol_new rx1_prim_inp0_mux = |
| 330 | SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum); |
| 331 | |
| 332 | static const struct snd_kcontrol_new rx1_prim_inp1_mux = |
| 333 | SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum); |
| 334 | |
| 335 | static const struct snd_kcontrol_new rx1_prim_inp2_mux = |
| 336 | SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum); |
| 337 | |
| 338 | static const struct snd_kcontrol_new rx1_mix_mux = |
| 339 | SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum); |
| 340 | |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 341 | static const struct soc_enum rx_mix_ec0_enum = |
| 342 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, |
| 343 | 0, 3, rx_mix_ec_text); |
| 344 | |
| 345 | static const struct soc_enum rx_mix_ec1_enum = |
| 346 | SOC_ENUM_SINGLE(BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, |
| 347 | 3, 3, rx_mix_ec_text); |
| 348 | |
| 349 | static const struct snd_kcontrol_new rx_mix_ec0_mux = |
| 350 | SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum); |
| 351 | |
| 352 | static const struct snd_kcontrol_new rx_mix_ec1_mux = |
| 353 | SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum); |
| 354 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 355 | static struct snd_soc_dai_ops wsa_macro_dai_ops = { |
| 356 | .hw_params = wsa_macro_hw_params, |
| 357 | .get_channel_map = wsa_macro_get_channel_map, |
| 358 | }; |
| 359 | |
| 360 | static struct snd_soc_dai_driver wsa_macro_dai[] = { |
| 361 | { |
| 362 | .name = "wsa_macro_rx1", |
| 363 | .id = WSA_MACRO_AIF1_PB, |
| 364 | .playback = { |
| 365 | .stream_name = "WSA_AIF1 Playback", |
| 366 | .rates = WSA_MACRO_RX_RATES, |
| 367 | .formats = WSA_MACRO_RX_FORMATS, |
| 368 | .rate_max = 384000, |
| 369 | .rate_min = 8000, |
| 370 | .channels_min = 1, |
| 371 | .channels_max = 2, |
| 372 | }, |
| 373 | .ops = &wsa_macro_dai_ops, |
| 374 | }, |
| 375 | { |
| 376 | .name = "wsa_macro_rx_mix", |
| 377 | .id = WSA_MACRO_AIF_MIX1_PB, |
| 378 | .playback = { |
| 379 | .stream_name = "WSA_AIF_MIX1 Playback", |
| 380 | .rates = WSA_MACRO_RX_MIX_RATES, |
| 381 | .formats = WSA_MACRO_RX_FORMATS, |
| 382 | .rate_max = 192000, |
| 383 | .rate_min = 48000, |
| 384 | .channels_min = 1, |
| 385 | .channels_max = 2, |
| 386 | }, |
| 387 | .ops = &wsa_macro_dai_ops, |
| 388 | }, |
| 389 | { |
| 390 | .name = "wsa_macro_vifeedback", |
| 391 | .id = WSA_MACRO_AIF_VI, |
| 392 | .capture = { |
| 393 | .stream_name = "WSA_AIF_VI Capture", |
Vatsal Bucha | d1b694d | 2018-08-31 11:47:32 +0530 | [diff] [blame] | 394 | .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, |
| 395 | .formats = WSA_MACRO_RX_FORMATS, |
| 396 | .rate_max = 48000, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 397 | .rate_min = 8000, |
| 398 | .channels_min = 1, |
Vatsal Bucha | d1b694d | 2018-08-31 11:47:32 +0530 | [diff] [blame] | 399 | .channels_max = 4, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 400 | }, |
| 401 | .ops = &wsa_macro_dai_ops, |
| 402 | }, |
| 403 | { |
| 404 | .name = "wsa_macro_echo", |
| 405 | .id = WSA_MACRO_AIF_ECHO, |
| 406 | .capture = { |
| 407 | .stream_name = "WSA_AIF_ECHO Capture", |
| 408 | .rates = WSA_MACRO_ECHO_RATES, |
| 409 | .formats = WSA_MACRO_ECHO_FORMATS, |
| 410 | .rate_max = 48000, |
| 411 | .rate_min = 8000, |
| 412 | .channels_min = 1, |
| 413 | .channels_max = 2, |
| 414 | }, |
| 415 | .ops = &wsa_macro_dai_ops, |
| 416 | }, |
| 417 | }; |
| 418 | |
| 419 | static const struct wsa_macro_reg_mask_val wsa_macro_spkr_default[] = { |
| 420 | {BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80}, |
| 421 | {BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80}, |
| 422 | {BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01}, |
| 423 | {BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01}, |
| 424 | {BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58}, |
| 425 | {BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58}, |
| 426 | }; |
| 427 | |
| 428 | static const struct wsa_macro_reg_mask_val wsa_macro_spkr_mode1[] = { |
| 429 | {BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00}, |
| 430 | {BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00}, |
| 431 | {BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00}, |
| 432 | {BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00}, |
| 433 | {BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44}, |
| 434 | {BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44}, |
| 435 | }; |
| 436 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 437 | static bool wsa_macro_get_data(struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 438 | struct device **wsa_dev, |
| 439 | struct wsa_macro_priv **wsa_priv, |
| 440 | const char *func_name) |
| 441 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 442 | *wsa_dev = bolero_get_device_ptr(component->dev, WSA_MACRO); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 443 | if (!(*wsa_dev)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 444 | dev_err(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 445 | "%s: null device for macro!\n", func_name); |
| 446 | return false; |
| 447 | } |
| 448 | *wsa_priv = dev_get_drvdata((*wsa_dev)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 449 | if (!(*wsa_priv) || !(*wsa_priv)->component) { |
| 450 | dev_err(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 451 | "%s: priv is null for macro!\n", func_name); |
| 452 | return false; |
| 453 | } |
| 454 | return true; |
| 455 | } |
| 456 | |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 457 | static int wsa_macro_set_port_map(struct snd_soc_component *component, |
| 458 | u32 usecase, u32 size, void *data) |
| 459 | { |
| 460 | struct device *wsa_dev = NULL; |
| 461 | struct wsa_macro_priv *wsa_priv = NULL; |
| 462 | struct swrm_port_config port_cfg; |
| 463 | int ret = 0; |
| 464 | |
| 465 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
| 466 | return -EINVAL; |
| 467 | |
| 468 | memset(&port_cfg, 0, sizeof(port_cfg)); |
| 469 | port_cfg.uc = usecase; |
| 470 | port_cfg.size = size; |
| 471 | port_cfg.params = data; |
| 472 | |
| 473 | ret = swrm_wcd_notify( |
| 474 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 475 | SWR_SET_PORT_MAP, &port_cfg); |
| 476 | |
| 477 | return ret; |
| 478 | } |
| 479 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 480 | /** |
| 481 | * wsa_macro_set_spkr_gain_offset - offset the speaker path |
| 482 | * gain with the given offset value. |
| 483 | * |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 484 | * @component: codec instance |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 485 | * @offset: Indicates speaker path gain offset value. |
| 486 | * |
| 487 | * Returns 0 on success or -EINVAL on error. |
| 488 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 489 | int wsa_macro_set_spkr_gain_offset(struct snd_soc_component *component, |
| 490 | int offset) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 491 | { |
| 492 | struct device *wsa_dev = NULL; |
| 493 | struct wsa_macro_priv *wsa_priv = NULL; |
| 494 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 495 | if (!component) { |
| 496 | pr_err("%s: NULL component pointer!\n", __func__); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 497 | return -EINVAL; |
| 498 | } |
| 499 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 500 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 501 | return -EINVAL; |
| 502 | |
| 503 | wsa_priv->spkr_gain_offset = offset; |
| 504 | return 0; |
| 505 | } |
| 506 | EXPORT_SYMBOL(wsa_macro_set_spkr_gain_offset); |
| 507 | |
| 508 | /** |
| 509 | * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost |
| 510 | * settings based on speaker mode. |
| 511 | * |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 512 | * @component: codec instance |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 513 | * @mode: Indicates speaker configuration mode. |
| 514 | * |
| 515 | * Returns 0 on success or -EINVAL on error. |
| 516 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 517 | int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 518 | { |
| 519 | int i; |
| 520 | const struct wsa_macro_reg_mask_val *regs; |
| 521 | int size; |
| 522 | struct device *wsa_dev = NULL; |
| 523 | struct wsa_macro_priv *wsa_priv = NULL; |
| 524 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 525 | if (!component) { |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 526 | pr_err("%s: NULL codec pointer!\n", __func__); |
| 527 | return -EINVAL; |
| 528 | } |
| 529 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 530 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 531 | return -EINVAL; |
| 532 | |
| 533 | switch (mode) { |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 534 | case WSA_MACRO_SPKR_MODE_1: |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 535 | regs = wsa_macro_spkr_mode1; |
| 536 | size = ARRAY_SIZE(wsa_macro_spkr_mode1); |
| 537 | break; |
| 538 | default: |
| 539 | regs = wsa_macro_spkr_default; |
| 540 | size = ARRAY_SIZE(wsa_macro_spkr_default); |
| 541 | break; |
| 542 | } |
| 543 | |
| 544 | wsa_priv->spkr_mode = mode; |
| 545 | for (i = 0; i < size; i++) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 546 | snd_soc_component_update_bits(component, regs[i].reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 547 | regs[i].mask, regs[i].val); |
| 548 | return 0; |
| 549 | } |
| 550 | EXPORT_SYMBOL(wsa_macro_set_spkr_mode); |
| 551 | |
| 552 | static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, |
| 553 | u8 int_prim_fs_rate_reg_val, |
| 554 | u32 sample_rate) |
| 555 | { |
| 556 | u8 int_1_mix1_inp; |
| 557 | u32 j, port; |
| 558 | u16 int_mux_cfg0, int_mux_cfg1; |
| 559 | u16 int_fs_reg; |
| 560 | u8 int_mux_cfg0_val, int_mux_cfg1_val; |
| 561 | u8 inp0_sel, inp1_sel, inp2_sel; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 562 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 563 | struct device *wsa_dev = NULL; |
| 564 | struct wsa_macro_priv *wsa_priv = NULL; |
| 565 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 566 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 567 | return -EINVAL; |
| 568 | |
| 569 | for_each_set_bit(port, &wsa_priv->active_ch_mask[dai->id], |
| 570 | WSA_MACRO_RX_MAX) { |
| 571 | int_1_mix1_inp = port; |
| 572 | if ((int_1_mix1_inp < WSA_MACRO_RX0) || |
| 573 | (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { |
| 574 | dev_err(wsa_dev, |
| 575 | "%s: Invalid RX port, Dai ID is %d\n", |
| 576 | __func__, dai->id); |
| 577 | return -EINVAL; |
| 578 | } |
| 579 | |
| 580 | int_mux_cfg0 = BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; |
| 581 | |
| 582 | /* |
| 583 | * Loop through all interpolator MUX inputs and find out |
| 584 | * to which interpolator input, the cdc_dma rx port |
| 585 | * is connected |
| 586 | */ |
| 587 | for (j = 0; j < NUM_INTERPOLATORS; j++) { |
| 588 | int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; |
| 589 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 590 | int_mux_cfg0_val = snd_soc_component_read32(component, |
| 591 | int_mux_cfg0); |
| 592 | int_mux_cfg1_val = snd_soc_component_read32(component, |
| 593 | int_mux_cfg1); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 594 | inp0_sel = int_mux_cfg0_val & WSA_MACRO_MUX_INP_MASK1; |
| 595 | inp1_sel = (int_mux_cfg0_val >> |
| 596 | WSA_MACRO_MUX_INP_SHFT) & |
| 597 | WSA_MACRO_MUX_INP_MASK2; |
| 598 | inp2_sel = (int_mux_cfg1_val >> |
| 599 | WSA_MACRO_MUX_INP_SHFT) & |
| 600 | WSA_MACRO_MUX_INP_MASK2; |
| 601 | if ((inp0_sel == int_1_mix1_inp) || |
| 602 | (inp1_sel == int_1_mix1_inp) || |
| 603 | (inp2_sel == int_1_mix1_inp)) { |
| 604 | int_fs_reg = BOLERO_CDC_WSA_RX0_RX_PATH_CTL + |
| 605 | WSA_MACRO_RX_PATH_OFFSET * j; |
| 606 | dev_dbg(wsa_dev, |
| 607 | "%s: AIF_PB DAI(%d) connected to INT%u_1\n", |
| 608 | __func__, dai->id, j); |
| 609 | dev_dbg(wsa_dev, |
| 610 | "%s: set INT%u_1 sample rate to %u\n", |
| 611 | __func__, j, sample_rate); |
| 612 | /* sample_rate is in Hz */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 613 | snd_soc_component_update_bits(component, |
| 614 | int_fs_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 615 | WSA_MACRO_FS_RATE_MASK, |
| 616 | int_prim_fs_rate_reg_val); |
| 617 | } |
| 618 | int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; |
| 619 | } |
| 620 | } |
| 621 | |
| 622 | return 0; |
| 623 | } |
| 624 | |
| 625 | static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, |
| 626 | u8 int_mix_fs_rate_reg_val, |
| 627 | u32 sample_rate) |
| 628 | { |
| 629 | u8 int_2_inp; |
| 630 | u32 j, port; |
| 631 | u16 int_mux_cfg1, int_fs_reg; |
| 632 | u8 int_mux_cfg1_val; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 633 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 634 | struct device *wsa_dev = NULL; |
| 635 | struct wsa_macro_priv *wsa_priv = NULL; |
| 636 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 637 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 638 | return -EINVAL; |
| 639 | |
| 640 | |
| 641 | for_each_set_bit(port, &wsa_priv->active_ch_mask[dai->id], |
| 642 | WSA_MACRO_RX_MAX) { |
| 643 | int_2_inp = port; |
| 644 | if ((int_2_inp < WSA_MACRO_RX0) || |
| 645 | (int_2_inp > WSA_MACRO_RX_MIX1)) { |
| 646 | dev_err(wsa_dev, |
| 647 | "%s: Invalid RX port, Dai ID is %d\n", |
| 648 | __func__, dai->id); |
| 649 | return -EINVAL; |
| 650 | } |
| 651 | |
| 652 | int_mux_cfg1 = BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; |
| 653 | for (j = 0; j < NUM_INTERPOLATORS; j++) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 654 | int_mux_cfg1_val = snd_soc_component_read32(component, |
| 655 | int_mux_cfg1) & |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 656 | WSA_MACRO_MUX_INP_MASK1; |
| 657 | if (int_mux_cfg1_val == int_2_inp) { |
| 658 | int_fs_reg = |
| 659 | BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL + |
| 660 | WSA_MACRO_RX_PATH_OFFSET * j; |
| 661 | |
| 662 | dev_dbg(wsa_dev, |
| 663 | "%s: AIF_PB DAI(%d) connected to INT%u_2\n", |
| 664 | __func__, dai->id, j); |
| 665 | dev_dbg(wsa_dev, |
| 666 | "%s: set INT%u_2 sample rate to %u\n", |
| 667 | __func__, j, sample_rate); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 668 | snd_soc_component_update_bits(component, |
| 669 | int_fs_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 670 | WSA_MACRO_FS_RATE_MASK, |
| 671 | int_mix_fs_rate_reg_val); |
| 672 | } |
| 673 | int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; |
| 674 | } |
| 675 | } |
| 676 | return 0; |
| 677 | } |
| 678 | |
| 679 | static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, |
| 680 | u32 sample_rate) |
| 681 | { |
| 682 | int rate_val = 0; |
| 683 | int i, ret; |
| 684 | |
| 685 | /* set mixing path rate */ |
| 686 | for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { |
| 687 | if (sample_rate == |
| 688 | int_mix_sample_rate_val[i].sample_rate) { |
| 689 | rate_val = |
| 690 | int_mix_sample_rate_val[i].rate_val; |
| 691 | break; |
| 692 | } |
| 693 | } |
| 694 | if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || |
| 695 | (rate_val < 0)) |
| 696 | goto prim_rate; |
| 697 | ret = wsa_macro_set_mix_interpolator_rate(dai, |
| 698 | (u8) rate_val, sample_rate); |
| 699 | prim_rate: |
| 700 | /* set primary path sample rate */ |
| 701 | for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { |
| 702 | if (sample_rate == |
| 703 | int_prim_sample_rate_val[i].sample_rate) { |
| 704 | rate_val = |
| 705 | int_prim_sample_rate_val[i].rate_val; |
| 706 | break; |
| 707 | } |
| 708 | } |
| 709 | if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || |
| 710 | (rate_val < 0)) |
| 711 | return -EINVAL; |
| 712 | ret = wsa_macro_set_prim_interpolator_rate(dai, |
| 713 | (u8) rate_val, sample_rate); |
| 714 | return ret; |
| 715 | } |
| 716 | |
| 717 | static int wsa_macro_hw_params(struct snd_pcm_substream *substream, |
| 718 | struct snd_pcm_hw_params *params, |
| 719 | struct snd_soc_dai *dai) |
| 720 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 721 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 722 | int ret; |
| 723 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 724 | dev_dbg(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 725 | "%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 726 | dai->name, dai->id, params_rate(params), |
| 727 | params_channels(params)); |
| 728 | |
| 729 | switch (substream->stream) { |
| 730 | case SNDRV_PCM_STREAM_PLAYBACK: |
| 731 | ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); |
| 732 | if (ret) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 733 | dev_err(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 734 | "%s: cannot set sample rate: %u\n", |
| 735 | __func__, params_rate(params)); |
| 736 | return ret; |
| 737 | } |
| 738 | break; |
| 739 | case SNDRV_PCM_STREAM_CAPTURE: |
| 740 | default: |
| 741 | break; |
| 742 | } |
| 743 | return 0; |
| 744 | } |
| 745 | |
| 746 | static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, |
| 747 | unsigned int *tx_num, unsigned int *tx_slot, |
| 748 | unsigned int *rx_num, unsigned int *rx_slot) |
| 749 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 750 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 751 | struct device *wsa_dev = NULL; |
| 752 | struct wsa_macro_priv *wsa_priv = NULL; |
Laxminath Kasam | 5d9ea8d | 2018-11-28 14:32:40 +0530 | [diff] [blame] | 753 | u16 val = 0, mask = 0, cnt = 0; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 754 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 755 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 756 | return -EINVAL; |
| 757 | |
| 758 | wsa_priv = dev_get_drvdata(wsa_dev); |
| 759 | if (!wsa_priv) |
| 760 | return -EINVAL; |
| 761 | |
| 762 | switch (dai->id) { |
| 763 | case WSA_MACRO_AIF_VI: |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 764 | *tx_slot = wsa_priv->active_ch_mask[dai->id]; |
| 765 | *tx_num = wsa_priv->active_ch_cnt[dai->id]; |
| 766 | break; |
| 767 | case WSA_MACRO_AIF1_PB: |
| 768 | case WSA_MACRO_AIF_MIX1_PB: |
| 769 | *rx_slot = wsa_priv->active_ch_mask[dai->id]; |
| 770 | *rx_num = wsa_priv->active_ch_cnt[dai->id]; |
| 771 | break; |
Laxminath Kasam | 5d9ea8d | 2018-11-28 14:32:40 +0530 | [diff] [blame] | 772 | case WSA_MACRO_AIF_ECHO: |
| 773 | val = snd_soc_component_read32(component, |
| 774 | BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); |
| 775 | if (val & WSA_MACRO_EC_MIX_TX1_MASK) { |
| 776 | mask |= 0x2; |
| 777 | cnt++; |
| 778 | } |
| 779 | if (val & WSA_MACRO_EC_MIX_TX0_MASK) { |
| 780 | mask |= 0x1; |
| 781 | cnt++; |
| 782 | } |
| 783 | *tx_slot = mask; |
| 784 | *tx_num = cnt; |
| 785 | break; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 786 | default: |
| 787 | dev_err(wsa_dev, "%s: Invalid AIF\n", __func__); |
| 788 | break; |
| 789 | } |
| 790 | return 0; |
| 791 | } |
| 792 | |
| 793 | static int wsa_macro_mclk_enable(struct wsa_macro_priv *wsa_priv, |
| 794 | bool mclk_enable, bool dapm) |
| 795 | { |
| 796 | struct regmap *regmap = dev_get_regmap(wsa_priv->dev->parent, NULL); |
| 797 | int ret = 0; |
| 798 | |
Tanya Dixit | ab8eba8 | 2018-10-05 15:07:37 +0530 | [diff] [blame] | 799 | if (regmap == NULL) { |
| 800 | dev_err(wsa_priv->dev, "%s: regmap is NULL\n", __func__); |
| 801 | return -EINVAL; |
| 802 | } |
| 803 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 804 | dev_dbg(wsa_priv->dev, "%s: mclk_enable = %u, dapm = %d clk_users= %d\n", |
| 805 | __func__, mclk_enable, dapm, wsa_priv->wsa_mclk_users); |
| 806 | |
| 807 | mutex_lock(&wsa_priv->mclk_lock); |
| 808 | if (mclk_enable) { |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 809 | if (wsa_priv->wsa_mclk_users == 0) { |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 810 | ret = bolero_request_clock(wsa_priv->dev, |
| 811 | WSA_MACRO, MCLK_MUX0, true); |
| 812 | if (ret < 0) { |
| 813 | dev_err(wsa_priv->dev, |
| 814 | "%s: wsa request clock enable failed\n", |
| 815 | __func__); |
| 816 | goto exit; |
| 817 | } |
| 818 | regcache_mark_dirty(regmap); |
| 819 | regcache_sync_region(regmap, |
| 820 | WSA_START_OFFSET, |
| 821 | WSA_MAX_OFFSET); |
| 822 | /* 9.6MHz MCLK, set value 0x00 if other frequency */ |
| 823 | regmap_update_bits(regmap, |
| 824 | BOLERO_CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); |
| 825 | regmap_update_bits(regmap, |
| 826 | BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, |
| 827 | 0x01, 0x01); |
| 828 | regmap_update_bits(regmap, |
| 829 | BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 830 | 0x01, 0x01); |
| 831 | } |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 832 | wsa_priv->wsa_mclk_users++; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 833 | } else { |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 834 | if (wsa_priv->wsa_mclk_users <= 0) { |
| 835 | dev_err(wsa_priv->dev, "%s: clock already disabled\n", |
| 836 | __func__); |
| 837 | wsa_priv->wsa_mclk_users = 0; |
| 838 | goto exit; |
| 839 | } |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 840 | wsa_priv->wsa_mclk_users--; |
| 841 | if (wsa_priv->wsa_mclk_users == 0) { |
| 842 | regmap_update_bits(regmap, |
| 843 | BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 844 | 0x01, 0x00); |
| 845 | regmap_update_bits(regmap, |
| 846 | BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, |
| 847 | 0x01, 0x00); |
| 848 | bolero_request_clock(wsa_priv->dev, |
| 849 | WSA_MACRO, MCLK_MUX0, false); |
| 850 | } |
| 851 | } |
| 852 | exit: |
| 853 | mutex_unlock(&wsa_priv->mclk_lock); |
| 854 | return ret; |
| 855 | } |
| 856 | |
| 857 | static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 858 | struct snd_kcontrol *kcontrol, int event) |
| 859 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 860 | struct snd_soc_component *component = |
| 861 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 862 | int ret = 0; |
| 863 | struct device *wsa_dev = NULL; |
| 864 | struct wsa_macro_priv *wsa_priv = NULL; |
| 865 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 866 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 867 | return -EINVAL; |
| 868 | |
| 869 | dev_dbg(wsa_dev, "%s: event = %d\n", __func__, event); |
| 870 | switch (event) { |
| 871 | case SND_SOC_DAPM_PRE_PMU: |
| 872 | ret = wsa_macro_mclk_enable(wsa_priv, 1, true); |
| 873 | break; |
| 874 | case SND_SOC_DAPM_POST_PMD: |
| 875 | wsa_macro_mclk_enable(wsa_priv, 0, true); |
| 876 | break; |
| 877 | default: |
| 878 | dev_err(wsa_priv->dev, |
| 879 | "%s: invalid DAPM event %d\n", __func__, event); |
| 880 | ret = -EINVAL; |
| 881 | } |
| 882 | return ret; |
| 883 | } |
| 884 | |
| 885 | static int wsa_macro_mclk_ctrl(struct device *dev, bool enable) |
| 886 | { |
| 887 | struct wsa_macro_priv *wsa_priv = dev_get_drvdata(dev); |
| 888 | int ret = 0; |
| 889 | |
| 890 | if (!wsa_priv) |
| 891 | return -EINVAL; |
| 892 | |
| 893 | if (enable) { |
| 894 | ret = clk_prepare_enable(wsa_priv->wsa_core_clk); |
| 895 | if (ret < 0) { |
| 896 | dev_err(dev, "%s:wsa mclk enable failed\n", __func__); |
| 897 | goto exit; |
| 898 | } |
| 899 | ret = clk_prepare_enable(wsa_priv->wsa_npl_clk); |
| 900 | if (ret < 0) { |
| 901 | dev_err(dev, "%s:wsa npl_clk enable failed\n", |
| 902 | __func__); |
| 903 | clk_disable_unprepare(wsa_priv->wsa_core_clk); |
| 904 | goto exit; |
| 905 | } |
| 906 | } else { |
| 907 | clk_disable_unprepare(wsa_priv->wsa_npl_clk); |
| 908 | clk_disable_unprepare(wsa_priv->wsa_core_clk); |
| 909 | } |
| 910 | exit: |
| 911 | return ret; |
| 912 | } |
| 913 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 914 | static int wsa_macro_event_handler(struct snd_soc_component *component, |
| 915 | u16 event, u32 data) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 916 | { |
| 917 | struct device *wsa_dev = NULL; |
| 918 | struct wsa_macro_priv *wsa_priv = NULL; |
| 919 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 920 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 921 | return -EINVAL; |
| 922 | |
| 923 | switch (event) { |
| 924 | case BOLERO_MACRO_EVT_SSR_DOWN: |
| 925 | swrm_wcd_notify( |
| 926 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 927 | SWR_DEVICE_SSR_DOWN, NULL); |
| 928 | swrm_wcd_notify( |
| 929 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 930 | SWR_DEVICE_DOWN, NULL); |
| 931 | break; |
| 932 | case BOLERO_MACRO_EVT_SSR_UP: |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 933 | /* reset swr after ssr/pdr */ |
| 934 | wsa_priv->reset_swr = true; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 935 | swrm_wcd_notify( |
| 936 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 937 | SWR_DEVICE_SSR_UP, NULL); |
| 938 | break; |
| 939 | } |
| 940 | return 0; |
| 941 | } |
| 942 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 943 | static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, |
| 944 | struct snd_kcontrol *kcontrol, |
| 945 | int event) |
| 946 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 947 | struct snd_soc_component *component = |
| 948 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 949 | struct device *wsa_dev = NULL; |
| 950 | struct wsa_macro_priv *wsa_priv = NULL; |
| 951 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 952 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 953 | return -EINVAL; |
| 954 | |
| 955 | switch (event) { |
| 956 | case SND_SOC_DAPM_POST_PMU: |
| 957 | if (test_bit(WSA_MACRO_TX0, |
| 958 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 959 | dev_dbg(wsa_dev, "%s: spkr1 enabled\n", __func__); |
| 960 | /* Enable V&I sensing */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 961 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 962 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 963 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 964 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 965 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 966 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 967 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 968 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 969 | 0x0F, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 970 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 971 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 972 | 0x0F, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 973 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 974 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 975 | 0x10, 0x10); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 976 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 977 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 978 | 0x10, 0x10); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 979 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 980 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 981 | 0x20, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 982 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 983 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 984 | 0x20, 0x00); |
| 985 | } |
| 986 | if (test_bit(WSA_MACRO_TX1, |
| 987 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 988 | dev_dbg(wsa_dev, "%s: spkr2 enabled\n", __func__); |
| 989 | /* Enable V&I sensing */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 990 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 991 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 992 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 993 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 994 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 995 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 996 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 997 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 998 | 0x0F, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 999 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1000 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 1001 | 0x0F, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1002 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1003 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 1004 | 0x10, 0x10); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1005 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1006 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 1007 | 0x10, 0x10); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1008 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1009 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 1010 | 0x20, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1011 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1012 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 1013 | 0x20, 0x00); |
| 1014 | } |
| 1015 | break; |
| 1016 | case SND_SOC_DAPM_POST_PMD: |
| 1017 | if (test_bit(WSA_MACRO_TX0, |
| 1018 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 1019 | /* Disable V&I sensing */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1020 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1021 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 1022 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1023 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1024 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 1025 | 0x20, 0x20); |
| 1026 | dev_dbg(wsa_dev, "%s: spkr1 disabled\n", __func__); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1027 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1028 | BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, |
| 1029 | 0x10, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1030 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1031 | BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, |
| 1032 | 0x10, 0x00); |
| 1033 | } |
| 1034 | if (test_bit(WSA_MACRO_TX1, |
| 1035 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 1036 | /* Disable V&I sensing */ |
| 1037 | dev_dbg(wsa_dev, "%s: spkr2 disabled\n", __func__); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1038 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1039 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 1040 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1041 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1042 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 1043 | 0x20, 0x20); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1044 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1045 | BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, |
| 1046 | 0x10, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1047 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1048 | BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, |
| 1049 | 0x10, 0x00); |
| 1050 | } |
| 1051 | break; |
| 1052 | } |
| 1053 | |
| 1054 | return 0; |
| 1055 | } |
| 1056 | |
| 1057 | static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, |
| 1058 | struct snd_kcontrol *kcontrol, int event) |
| 1059 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1060 | struct snd_soc_component *component = |
| 1061 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1062 | u16 gain_reg; |
| 1063 | int offset_val = 0; |
| 1064 | int val = 0; |
| 1065 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1066 | dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1067 | |
| 1068 | switch (w->reg) { |
| 1069 | case BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL: |
| 1070 | gain_reg = BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL; |
| 1071 | break; |
| 1072 | case BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL: |
| 1073 | gain_reg = BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL; |
| 1074 | break; |
| 1075 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1076 | dev_err(component->dev, "%s: No gain register avail for %s\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1077 | __func__, w->name); |
| 1078 | return 0; |
| 1079 | } |
| 1080 | |
| 1081 | switch (event) { |
| 1082 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1083 | val = snd_soc_component_read32(component, gain_reg); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1084 | val += offset_val; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1085 | snd_soc_component_write(component, gain_reg, val); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1086 | break; |
| 1087 | case SND_SOC_DAPM_POST_PMD: |
| 1088 | break; |
| 1089 | } |
| 1090 | |
| 1091 | return 0; |
| 1092 | } |
| 1093 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1094 | static void wsa_macro_hd2_control(struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1095 | u16 reg, int event) |
| 1096 | { |
| 1097 | u16 hd2_scale_reg; |
| 1098 | u16 hd2_enable_reg = 0; |
| 1099 | |
| 1100 | if (reg == BOLERO_CDC_WSA_RX0_RX_PATH_CTL) { |
| 1101 | hd2_scale_reg = BOLERO_CDC_WSA_RX0_RX_PATH_SEC3; |
| 1102 | hd2_enable_reg = BOLERO_CDC_WSA_RX0_RX_PATH_CFG0; |
| 1103 | } |
| 1104 | if (reg == BOLERO_CDC_WSA_RX1_RX_PATH_CTL) { |
| 1105 | hd2_scale_reg = BOLERO_CDC_WSA_RX1_RX_PATH_SEC3; |
| 1106 | hd2_enable_reg = BOLERO_CDC_WSA_RX1_RX_PATH_CFG0; |
| 1107 | } |
| 1108 | |
| 1109 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1110 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1111 | 0x3C, 0x10); |
| 1112 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1113 | 0x03, 0x01); |
| 1114 | snd_soc_component_update_bits(component, hd2_enable_reg, |
| 1115 | 0x04, 0x04); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1116 | } |
| 1117 | |
| 1118 | if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1119 | snd_soc_component_update_bits(component, hd2_enable_reg, |
| 1120 | 0x04, 0x00); |
| 1121 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1122 | 0x03, 0x00); |
| 1123 | snd_soc_component_update_bits(component, hd2_scale_reg, |
| 1124 | 0x3C, 0x00); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1125 | } |
| 1126 | } |
| 1127 | |
| 1128 | static int wsa_macro_enable_swr(struct snd_soc_dapm_widget *w, |
| 1129 | struct snd_kcontrol *kcontrol, int event) |
| 1130 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1131 | struct snd_soc_component *component = |
| 1132 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1133 | int ch_cnt; |
| 1134 | struct device *wsa_dev = NULL; |
| 1135 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1136 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1137 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1138 | return -EINVAL; |
| 1139 | |
| 1140 | switch (event) { |
| 1141 | case SND_SOC_DAPM_PRE_PMU: |
| 1142 | if (!(strnstr(w->name, "RX0", sizeof("WSA_RX0"))) && |
| 1143 | !wsa_priv->rx_0_count) |
| 1144 | wsa_priv->rx_0_count++; |
| 1145 | if (!(strnstr(w->name, "RX1", sizeof("WSA_RX1"))) && |
| 1146 | !wsa_priv->rx_1_count) |
| 1147 | wsa_priv->rx_1_count++; |
| 1148 | ch_cnt = wsa_priv->rx_0_count + wsa_priv->rx_1_count; |
| 1149 | |
| 1150 | swrm_wcd_notify( |
| 1151 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 1152 | SWR_DEVICE_UP, NULL); |
| 1153 | swrm_wcd_notify( |
| 1154 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 1155 | SWR_SET_NUM_RX_CH, &ch_cnt); |
| 1156 | break; |
| 1157 | case SND_SOC_DAPM_POST_PMD: |
| 1158 | if (!(strnstr(w->name, "RX0", sizeof("WSA_RX0"))) && |
| 1159 | wsa_priv->rx_0_count) |
| 1160 | wsa_priv->rx_0_count--; |
| 1161 | if (!(strnstr(w->name, "RX1", sizeof("WSA_RX1"))) && |
| 1162 | wsa_priv->rx_1_count) |
| 1163 | wsa_priv->rx_1_count--; |
| 1164 | ch_cnt = wsa_priv->rx_0_count + wsa_priv->rx_1_count; |
| 1165 | |
| 1166 | swrm_wcd_notify( |
| 1167 | wsa_priv->swr_ctrl_data[0].wsa_swr_pdev, |
| 1168 | SWR_SET_NUM_RX_CH, &ch_cnt); |
| 1169 | break; |
| 1170 | } |
| 1171 | dev_dbg(wsa_priv->dev, "%s: current swr ch cnt: %d\n", |
| 1172 | __func__, wsa_priv->rx_0_count + wsa_priv->rx_1_count); |
| 1173 | |
| 1174 | return 0; |
| 1175 | } |
| 1176 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1177 | static int wsa_macro_config_compander(struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1178 | int comp, int event) |
| 1179 | { |
| 1180 | u16 comp_ctl0_reg, rx_path_cfg0_reg; |
| 1181 | struct device *wsa_dev = NULL; |
| 1182 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1183 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1184 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1185 | return -EINVAL; |
| 1186 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1187 | dev_dbg(component->dev, "%s: event %d compander %d, enabled %d\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1188 | __func__, event, comp + 1, wsa_priv->comp_enabled[comp]); |
| 1189 | |
| 1190 | if (!wsa_priv->comp_enabled[comp]) |
| 1191 | return 0; |
| 1192 | |
| 1193 | comp_ctl0_reg = BOLERO_CDC_WSA_COMPANDER0_CTL0 + |
| 1194 | (comp * WSA_MACRO_RX_COMP_OFFSET); |
| 1195 | rx_path_cfg0_reg = BOLERO_CDC_WSA_RX0_RX_PATH_CFG0 + |
| 1196 | (comp * WSA_MACRO_RX_PATH_OFFSET); |
| 1197 | |
| 1198 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1199 | /* Enable Compander Clock */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1200 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1201 | 0x01, 0x01); |
| 1202 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1203 | 0x02, 0x02); |
| 1204 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1205 | 0x02, 0x00); |
| 1206 | snd_soc_component_update_bits(component, rx_path_cfg0_reg, |
| 1207 | 0x02, 0x02); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1208 | } |
| 1209 | |
| 1210 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1211 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1212 | 0x04, 0x04); |
| 1213 | snd_soc_component_update_bits(component, rx_path_cfg0_reg, |
| 1214 | 0x02, 0x00); |
| 1215 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1216 | 0x02, 0x02); |
| 1217 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1218 | 0x02, 0x00); |
| 1219 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1220 | 0x01, 0x00); |
| 1221 | snd_soc_component_update_bits(component, comp_ctl0_reg, |
| 1222 | 0x04, 0x00); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1223 | } |
| 1224 | |
| 1225 | return 0; |
| 1226 | } |
| 1227 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1228 | static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1229 | struct wsa_macro_priv *wsa_priv, |
| 1230 | int path, |
| 1231 | bool enable) |
| 1232 | { |
| 1233 | u16 softclip_clk_reg = BOLERO_CDC_WSA_SOFTCLIP0_CRC + |
| 1234 | (path * WSA_MACRO_RX_SOFTCLIP_OFFSET); |
| 1235 | u8 softclip_mux_mask = (1 << path); |
| 1236 | u8 softclip_mux_value = (1 << path); |
| 1237 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1238 | dev_dbg(component->dev, "%s: path %d, enable %d\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1239 | __func__, path, enable); |
| 1240 | if (enable) { |
| 1241 | if (wsa_priv->softclip_clk_users[path] == 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1242 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1243 | softclip_clk_reg, 0x01, 0x01); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1244 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1245 | BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, |
| 1246 | softclip_mux_mask, softclip_mux_value); |
| 1247 | } |
| 1248 | wsa_priv->softclip_clk_users[path]++; |
| 1249 | } else { |
| 1250 | wsa_priv->softclip_clk_users[path]--; |
| 1251 | if (wsa_priv->softclip_clk_users[path] == 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1252 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1253 | softclip_clk_reg, 0x01, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1254 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1255 | BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, |
| 1256 | softclip_mux_mask, 0x00); |
| 1257 | } |
| 1258 | } |
| 1259 | } |
| 1260 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1261 | static int wsa_macro_config_softclip(struct snd_soc_component *component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1262 | int path, int event) |
| 1263 | { |
| 1264 | u16 softclip_ctrl_reg = 0; |
| 1265 | struct device *wsa_dev = NULL; |
| 1266 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1267 | int softclip_path = 0; |
| 1268 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1269 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1270 | return -EINVAL; |
| 1271 | |
| 1272 | if (path == WSA_MACRO_COMP1) |
| 1273 | softclip_path = WSA_MACRO_SOFTCLIP0; |
| 1274 | else if (path == WSA_MACRO_COMP2) |
| 1275 | softclip_path = WSA_MACRO_SOFTCLIP1; |
| 1276 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1277 | dev_dbg(component->dev, "%s: event %d path %d, enabled %d\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1278 | __func__, event, softclip_path, |
| 1279 | wsa_priv->is_softclip_on[softclip_path]); |
| 1280 | |
| 1281 | if (!wsa_priv->is_softclip_on[softclip_path]) |
| 1282 | return 0; |
| 1283 | |
| 1284 | softclip_ctrl_reg = BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + |
| 1285 | (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET); |
| 1286 | |
| 1287 | if (SND_SOC_DAPM_EVENT_ON(event)) { |
| 1288 | /* Enable Softclip clock and mux */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1289 | wsa_macro_enable_softclip_clk(component, wsa_priv, |
| 1290 | softclip_path, true); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1291 | /* Enable Softclip control */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1292 | snd_soc_component_update_bits(component, softclip_ctrl_reg, |
| 1293 | 0x01, 0x01); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1294 | } |
| 1295 | |
| 1296 | if (SND_SOC_DAPM_EVENT_OFF(event)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1297 | snd_soc_component_update_bits(component, softclip_ctrl_reg, |
| 1298 | 0x01, 0x00); |
| 1299 | wsa_macro_enable_softclip_clk(component, wsa_priv, |
| 1300 | softclip_path, false); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1301 | } |
| 1302 | |
| 1303 | return 0; |
| 1304 | } |
| 1305 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1306 | static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) |
| 1307 | { |
| 1308 | u16 prim_int_reg = 0; |
| 1309 | |
| 1310 | switch (reg) { |
| 1311 | case BOLERO_CDC_WSA_RX0_RX_PATH_CTL: |
| 1312 | case BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL: |
| 1313 | prim_int_reg = BOLERO_CDC_WSA_RX0_RX_PATH_CTL; |
| 1314 | *ind = 0; |
| 1315 | break; |
| 1316 | case BOLERO_CDC_WSA_RX1_RX_PATH_CTL: |
| 1317 | case BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL: |
| 1318 | prim_int_reg = BOLERO_CDC_WSA_RX1_RX_PATH_CTL; |
| 1319 | *ind = 1; |
| 1320 | break; |
| 1321 | } |
| 1322 | |
| 1323 | return prim_int_reg; |
| 1324 | } |
| 1325 | |
| 1326 | static int wsa_macro_enable_prim_interpolator( |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1327 | struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1328 | u16 reg, int event) |
| 1329 | { |
| 1330 | u16 prim_int_reg; |
| 1331 | u16 ind = 0; |
| 1332 | struct device *wsa_dev = NULL; |
| 1333 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1334 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1335 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1336 | return -EINVAL; |
| 1337 | |
| 1338 | prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind); |
| 1339 | |
| 1340 | switch (event) { |
| 1341 | case SND_SOC_DAPM_PRE_PMU: |
| 1342 | wsa_priv->prim_int_users[ind]++; |
| 1343 | if (wsa_priv->prim_int_users[ind] == 1) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1344 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1345 | prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET, |
| 1346 | 0x03, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1347 | snd_soc_component_update_bits(component, prim_int_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1348 | 0x10, 0x10); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1349 | wsa_macro_hd2_control(component, prim_int_reg, event); |
| 1350 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1351 | prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, |
| 1352 | 0x1, 0x1); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1353 | snd_soc_component_update_bits(component, prim_int_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1354 | 1 << 0x5, 1 << 0x5); |
| 1355 | } |
| 1356 | if ((reg != prim_int_reg) && |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1357 | ((snd_soc_component_read32( |
| 1358 | component, prim_int_reg)) & 0x10)) |
| 1359 | snd_soc_component_update_bits(component, reg, |
| 1360 | 0x10, 0x10); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1361 | break; |
| 1362 | case SND_SOC_DAPM_POST_PMD: |
| 1363 | wsa_priv->prim_int_users[ind]--; |
| 1364 | if (wsa_priv->prim_int_users[ind] == 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1365 | snd_soc_component_update_bits(component, prim_int_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1366 | 1 << 0x5, 0 << 0x5); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1367 | snd_soc_component_update_bits(component, prim_int_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1368 | 0x40, 0x40); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1369 | snd_soc_component_update_bits(component, prim_int_reg, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1370 | 0x40, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1371 | wsa_macro_hd2_control(component, prim_int_reg, event); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1372 | } |
| 1373 | break; |
| 1374 | } |
| 1375 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1376 | dev_dbg(component->dev, "%s: primary interpolator: INT%d, users: %d\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1377 | __func__, ind, wsa_priv->prim_int_users[ind]); |
| 1378 | return 0; |
| 1379 | } |
| 1380 | |
| 1381 | static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, |
| 1382 | struct snd_kcontrol *kcontrol, |
| 1383 | int event) |
| 1384 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1385 | struct snd_soc_component *component = |
| 1386 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1387 | u16 gain_reg; |
| 1388 | u16 reg; |
| 1389 | int val; |
| 1390 | int offset_val = 0; |
| 1391 | struct device *wsa_dev = NULL; |
| 1392 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1393 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1394 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1395 | return -EINVAL; |
| 1396 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1397 | dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1398 | |
| 1399 | if (!(strcmp(w->name, "WSA_RX INT0 INTERP"))) { |
| 1400 | reg = BOLERO_CDC_WSA_RX0_RX_PATH_CTL; |
| 1401 | gain_reg = BOLERO_CDC_WSA_RX0_RX_VOL_CTL; |
| 1402 | } else if (!(strcmp(w->name, "WSA_RX INT1 INTERP"))) { |
| 1403 | reg = BOLERO_CDC_WSA_RX1_RX_PATH_CTL; |
| 1404 | gain_reg = BOLERO_CDC_WSA_RX1_RX_VOL_CTL; |
| 1405 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1406 | dev_err(component->dev, "%s: Interpolator reg not found\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1407 | __func__); |
| 1408 | return -EINVAL; |
| 1409 | } |
| 1410 | |
| 1411 | switch (event) { |
| 1412 | case SND_SOC_DAPM_PRE_PMU: |
| 1413 | /* Reset if needed */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1414 | wsa_macro_enable_prim_interpolator(component, reg, event); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1415 | break; |
| 1416 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1417 | wsa_macro_config_compander(component, w->shift, event); |
| 1418 | wsa_macro_config_softclip(component, w->shift, event); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1419 | /* apply gain after int clk is enabled */ |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 1420 | if ((wsa_priv->spkr_gain_offset == |
| 1421 | WSA_MACRO_GAIN_OFFSET_M1P5_DB) && |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1422 | (wsa_priv->comp_enabled[WSA_MACRO_COMP1] || |
| 1423 | wsa_priv->comp_enabled[WSA_MACRO_COMP2]) && |
| 1424 | (gain_reg == BOLERO_CDC_WSA_RX0_RX_VOL_CTL || |
| 1425 | gain_reg == BOLERO_CDC_WSA_RX1_RX_VOL_CTL)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1426 | snd_soc_component_update_bits(component, |
| 1427 | BOLERO_CDC_WSA_RX0_RX_PATH_SEC1, |
| 1428 | 0x01, 0x01); |
| 1429 | snd_soc_component_update_bits(component, |
| 1430 | BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0, |
| 1431 | 0x01, 0x01); |
| 1432 | snd_soc_component_update_bits(component, |
| 1433 | BOLERO_CDC_WSA_RX1_RX_PATH_SEC1, |
| 1434 | 0x01, 0x01); |
| 1435 | snd_soc_component_update_bits(component, |
| 1436 | BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0, |
| 1437 | 0x01, 0x01); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1438 | offset_val = -2; |
| 1439 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1440 | val = snd_soc_component_read32(component, gain_reg); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1441 | val += offset_val; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1442 | snd_soc_component_write(component, gain_reg, val); |
| 1443 | wsa_macro_config_ear_spkr_gain(component, wsa_priv, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1444 | event, gain_reg); |
| 1445 | break; |
| 1446 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1447 | wsa_macro_config_compander(component, w->shift, event); |
| 1448 | wsa_macro_config_softclip(component, w->shift, event); |
| 1449 | wsa_macro_enable_prim_interpolator(component, reg, event); |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 1450 | if ((wsa_priv->spkr_gain_offset == |
| 1451 | WSA_MACRO_GAIN_OFFSET_M1P5_DB) && |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1452 | (wsa_priv->comp_enabled[WSA_MACRO_COMP1] || |
| 1453 | wsa_priv->comp_enabled[WSA_MACRO_COMP2]) && |
| 1454 | (gain_reg == BOLERO_CDC_WSA_RX0_RX_VOL_CTL || |
| 1455 | gain_reg == BOLERO_CDC_WSA_RX1_RX_VOL_CTL)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1456 | snd_soc_component_update_bits(component, |
| 1457 | BOLERO_CDC_WSA_RX0_RX_PATH_SEC1, |
| 1458 | 0x01, 0x00); |
| 1459 | snd_soc_component_update_bits(component, |
| 1460 | BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0, |
| 1461 | 0x01, 0x00); |
| 1462 | snd_soc_component_update_bits(component, |
| 1463 | BOLERO_CDC_WSA_RX1_RX_PATH_SEC1, |
| 1464 | 0x01, 0x00); |
| 1465 | snd_soc_component_update_bits(component, |
| 1466 | BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0, |
| 1467 | 0x01, 0x00); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1468 | offset_val = 2; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1469 | val = snd_soc_component_read32(component, gain_reg); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1470 | val += offset_val; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1471 | snd_soc_component_write(component, gain_reg, val); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1472 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1473 | wsa_macro_config_ear_spkr_gain(component, wsa_priv, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1474 | event, gain_reg); |
| 1475 | break; |
| 1476 | } |
| 1477 | |
| 1478 | return 0; |
| 1479 | } |
| 1480 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1481 | static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1482 | struct wsa_macro_priv *wsa_priv, |
| 1483 | int event, int gain_reg) |
| 1484 | { |
| 1485 | int comp_gain_offset, val; |
| 1486 | |
| 1487 | switch (wsa_priv->spkr_mode) { |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 1488 | /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */ |
| 1489 | case WSA_MACRO_SPKR_MODE_1: |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1490 | comp_gain_offset = -12; |
| 1491 | break; |
| 1492 | /* Default case compander gain is 15 dB */ |
| 1493 | default: |
| 1494 | comp_gain_offset = -15; |
| 1495 | break; |
| 1496 | } |
| 1497 | |
| 1498 | switch (event) { |
| 1499 | case SND_SOC_DAPM_POST_PMU: |
| 1500 | /* Apply ear spkr gain only if compander is enabled */ |
| 1501 | if (wsa_priv->comp_enabled[WSA_MACRO_COMP1] && |
| 1502 | (gain_reg == BOLERO_CDC_WSA_RX0_RX_VOL_CTL) && |
| 1503 | (wsa_priv->ear_spkr_gain != 0)) { |
| 1504 | /* For example, val is -8(-12+5-1) for 4dB of gain */ |
| 1505 | val = comp_gain_offset + wsa_priv->ear_spkr_gain - 1; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1506 | snd_soc_component_write(component, gain_reg, val); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1507 | |
| 1508 | dev_dbg(wsa_priv->dev, "%s: RX0 Volume %d dB\n", |
| 1509 | __func__, val); |
| 1510 | } |
| 1511 | break; |
| 1512 | case SND_SOC_DAPM_POST_PMD: |
| 1513 | /* |
| 1514 | * Reset RX0 volume to 0 dB if compander is enabled and |
| 1515 | * ear_spkr_gain is non-zero. |
| 1516 | */ |
| 1517 | if (wsa_priv->comp_enabled[WSA_MACRO_COMP1] && |
| 1518 | (gain_reg == BOLERO_CDC_WSA_RX0_RX_VOL_CTL) && |
| 1519 | (wsa_priv->ear_spkr_gain != 0)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1520 | snd_soc_component_write(component, gain_reg, 0x0); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1521 | |
| 1522 | dev_dbg(wsa_priv->dev, "%s: Reset RX0 Volume to 0 dB\n", |
| 1523 | __func__); |
| 1524 | } |
| 1525 | break; |
| 1526 | } |
| 1527 | |
| 1528 | return 0; |
| 1529 | } |
| 1530 | |
| 1531 | static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, |
| 1532 | struct snd_kcontrol *kcontrol, |
| 1533 | int event) |
| 1534 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1535 | struct snd_soc_component *component = |
| 1536 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1537 | u16 boost_path_ctl, boost_path_cfg1; |
| 1538 | u16 reg, reg_mix; |
| 1539 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1540 | dev_dbg(component->dev, "%s %s %d\n", __func__, w->name, event); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1541 | |
| 1542 | if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) { |
| 1543 | boost_path_ctl = BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL; |
| 1544 | boost_path_cfg1 = BOLERO_CDC_WSA_RX0_RX_PATH_CFG1; |
| 1545 | reg = BOLERO_CDC_WSA_RX0_RX_PATH_CTL; |
| 1546 | reg_mix = BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL; |
| 1547 | } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) { |
| 1548 | boost_path_ctl = BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL; |
| 1549 | boost_path_cfg1 = BOLERO_CDC_WSA_RX1_RX_PATH_CFG1; |
| 1550 | reg = BOLERO_CDC_WSA_RX1_RX_PATH_CTL; |
| 1551 | reg_mix = BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL; |
| 1552 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1553 | dev_err(component->dev, "%s: unknown widget: %s\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1554 | __func__, w->name); |
| 1555 | return -EINVAL; |
| 1556 | } |
| 1557 | |
| 1558 | switch (event) { |
| 1559 | case SND_SOC_DAPM_PRE_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1560 | snd_soc_component_update_bits(component, boost_path_cfg1, |
| 1561 | 0x01, 0x01); |
| 1562 | snd_soc_component_update_bits(component, boost_path_ctl, |
| 1563 | 0x10, 0x10); |
| 1564 | if ((snd_soc_component_read32(component, reg_mix)) & 0x10) |
| 1565 | snd_soc_component_update_bits(component, reg_mix, |
| 1566 | 0x10, 0x00); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1567 | break; |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 1568 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1569 | snd_soc_component_update_bits(component, reg, 0x10, 0x00); |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 1570 | break; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1571 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1572 | snd_soc_component_update_bits(component, boost_path_ctl, |
| 1573 | 0x10, 0x00); |
| 1574 | snd_soc_component_update_bits(component, boost_path_cfg1, |
| 1575 | 0x01, 0x00); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1576 | break; |
| 1577 | } |
| 1578 | |
| 1579 | return 0; |
| 1580 | } |
| 1581 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1582 | |
| 1583 | static int wsa_macro_enable_vbat(struct snd_soc_dapm_widget *w, |
| 1584 | struct snd_kcontrol *kcontrol, |
| 1585 | int event) |
| 1586 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1587 | struct snd_soc_component *component = |
| 1588 | snd_soc_dapm_to_component(w->dapm); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1589 | struct device *wsa_dev = NULL; |
| 1590 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1591 | u16 vbat_path_cfg = 0; |
| 1592 | int softclip_path = 0; |
| 1593 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1594 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1595 | return -EINVAL; |
| 1596 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1597 | dev_dbg(component->dev, "%s %s %d\n", __func__, w->name, event); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1598 | if (!strcmp(w->name, "WSA_RX INT0 VBAT")) { |
| 1599 | vbat_path_cfg = BOLERO_CDC_WSA_RX0_RX_PATH_CFG1; |
| 1600 | softclip_path = WSA_MACRO_SOFTCLIP0; |
| 1601 | } else if (!strcmp(w->name, "WSA_RX INT1 VBAT")) { |
| 1602 | vbat_path_cfg = BOLERO_CDC_WSA_RX1_RX_PATH_CFG1; |
| 1603 | softclip_path = WSA_MACRO_SOFTCLIP1; |
| 1604 | } |
| 1605 | |
| 1606 | switch (event) { |
| 1607 | case SND_SOC_DAPM_PRE_PMU: |
| 1608 | /* Enable clock for VBAT block */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1609 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1610 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, 0x10, 0x10); |
| 1611 | /* Enable VBAT block */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1612 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1613 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x01, 0x01); |
| 1614 | /* Update interpolator with 384K path */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1615 | snd_soc_component_update_bits(component, vbat_path_cfg, |
| 1616 | 0x80, 0x80); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1617 | /* Use attenuation mode */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1618 | snd_soc_component_update_bits(component, |
| 1619 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x02, 0x00); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1620 | /* |
| 1621 | * BCL block needs softclip clock and mux config to be enabled |
| 1622 | */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1623 | wsa_macro_enable_softclip_clk(component, wsa_priv, |
| 1624 | softclip_path, true); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1625 | /* Enable VBAT at channel level */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1626 | snd_soc_component_update_bits(component, vbat_path_cfg, |
| 1627 | 0x02, 0x02); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1628 | /* Set the ATTK1 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1629 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1630 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1, |
| 1631 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1632 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1633 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2, |
| 1634 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1635 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1636 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3, |
| 1637 | 0xFF, 0x00); |
| 1638 | /* Set the ATTK2 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1639 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1640 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4, |
| 1641 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1642 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1643 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5, |
| 1644 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1645 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1646 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6, |
| 1647 | 0xFF, 0x00); |
| 1648 | /* Set the ATTK3 gain */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1649 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1650 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7, |
| 1651 | 0xFF, 0xFF); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1652 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1653 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8, |
| 1654 | 0xFF, 0x03); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1655 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1656 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9, |
| 1657 | 0xFF, 0x00); |
| 1658 | break; |
| 1659 | |
| 1660 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1661 | snd_soc_component_update_bits(component, vbat_path_cfg, |
| 1662 | 0x80, 0x00); |
| 1663 | snd_soc_component_update_bits(component, |
| 1664 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, |
| 1665 | 0x02, 0x02); |
| 1666 | snd_soc_component_update_bits(component, vbat_path_cfg, |
| 1667 | 0x02, 0x00); |
| 1668 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1669 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1, |
| 1670 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1671 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1672 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2, |
| 1673 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1674 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1675 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3, |
| 1676 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1677 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1678 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4, |
| 1679 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1680 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1681 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5, |
| 1682 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1683 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1684 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6, |
| 1685 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1686 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1687 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7, |
| 1688 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1689 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1690 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8, |
| 1691 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1692 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1693 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9, |
| 1694 | 0xFF, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1695 | wsa_macro_enable_softclip_clk(component, wsa_priv, |
| 1696 | softclip_path, false); |
| 1697 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1698 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x01, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1699 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 1700 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, 0x10, 0x00); |
| 1701 | break; |
| 1702 | default: |
| 1703 | dev_err(wsa_dev, "%s: Invalid event %d\n", __func__, event); |
| 1704 | break; |
| 1705 | } |
| 1706 | return 0; |
| 1707 | } |
| 1708 | |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1709 | static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, |
| 1710 | struct snd_kcontrol *kcontrol, |
| 1711 | int event) |
| 1712 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1713 | struct snd_soc_component *component = |
| 1714 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1715 | struct device *wsa_dev = NULL; |
| 1716 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1717 | u16 val, ec_tx = 0, ec_hq_reg; |
| 1718 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1719 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1720 | return -EINVAL; |
| 1721 | |
| 1722 | dev_dbg(wsa_dev, "%s %d %s\n", __func__, event, w->name); |
| 1723 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1724 | val = snd_soc_component_read32(component, |
| 1725 | BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1726 | if (!(strcmp(w->name, "WSA RX_MIX EC0_MUX"))) |
| 1727 | ec_tx = (val & 0x07) - 1; |
| 1728 | else |
| 1729 | ec_tx = ((val & 0x38) >> 0x3) - 1; |
| 1730 | |
| 1731 | if (ec_tx < 0 || ec_tx >= (WSA_MACRO_RX1 + 1)) { |
| 1732 | dev_err(wsa_dev, "%s: EC mix control not set correctly\n", |
| 1733 | __func__); |
| 1734 | return -EINVAL; |
| 1735 | } |
| 1736 | if (wsa_priv->ec_hq[ec_tx]) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1737 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1738 | BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, |
| 1739 | 0x1 << ec_tx, 0x1 << ec_tx); |
| 1740 | ec_hq_reg = BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + |
Laxminath Kasam | 5d9ea8d | 2018-11-28 14:32:40 +0530 | [diff] [blame] | 1741 | 0x40 * ec_tx; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1742 | snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1743 | ec_hq_reg = BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + |
Laxminath Kasam | 5d9ea8d | 2018-11-28 14:32:40 +0530 | [diff] [blame] | 1744 | 0x40 * ec_tx; |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1745 | /* default set to 48k */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1746 | snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1747 | } |
| 1748 | |
| 1749 | return 0; |
| 1750 | } |
| 1751 | |
| 1752 | static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, |
| 1753 | struct snd_ctl_elem_value *ucontrol) |
| 1754 | { |
| 1755 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1756 | struct snd_soc_component *component = |
| 1757 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1758 | int ec_tx = ((struct soc_multi_mixer_control *) |
| 1759 | kcontrol->private_value)->shift; |
| 1760 | struct device *wsa_dev = NULL; |
| 1761 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1762 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1763 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1764 | return -EINVAL; |
| 1765 | |
| 1766 | ucontrol->value.integer.value[0] = wsa_priv->ec_hq[ec_tx]; |
| 1767 | return 0; |
| 1768 | } |
| 1769 | |
| 1770 | static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, |
| 1771 | struct snd_ctl_elem_value *ucontrol) |
| 1772 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1773 | struct snd_soc_component *component = |
| 1774 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1775 | int ec_tx = ((struct soc_multi_mixer_control *) |
| 1776 | kcontrol->private_value)->shift; |
| 1777 | int value = ucontrol->value.integer.value[0]; |
| 1778 | struct device *wsa_dev = NULL; |
| 1779 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1780 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1781 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 1782 | return -EINVAL; |
| 1783 | |
| 1784 | dev_dbg(wsa_dev, "%s: enable current %d, new %d\n", |
| 1785 | __func__, wsa_priv->ec_hq[ec_tx], value); |
| 1786 | wsa_priv->ec_hq[ec_tx] = value; |
| 1787 | |
| 1788 | return 0; |
| 1789 | } |
| 1790 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1791 | static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, |
| 1792 | struct snd_ctl_elem_value *ucontrol) |
| 1793 | { |
| 1794 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1795 | struct snd_soc_component *component = |
| 1796 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1797 | int comp = ((struct soc_multi_mixer_control *) |
| 1798 | kcontrol->private_value)->shift; |
| 1799 | struct device *wsa_dev = NULL; |
| 1800 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1801 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1802 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1803 | return -EINVAL; |
| 1804 | |
| 1805 | ucontrol->value.integer.value[0] = wsa_priv->comp_enabled[comp]; |
| 1806 | return 0; |
| 1807 | } |
| 1808 | |
| 1809 | static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, |
| 1810 | struct snd_ctl_elem_value *ucontrol) |
| 1811 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1812 | struct snd_soc_component *component = |
| 1813 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1814 | int comp = ((struct soc_multi_mixer_control *) |
| 1815 | kcontrol->private_value)->shift; |
| 1816 | int value = ucontrol->value.integer.value[0]; |
| 1817 | struct device *wsa_dev = NULL; |
| 1818 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1819 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1820 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1821 | return -EINVAL; |
| 1822 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1823 | dev_dbg(component->dev, "%s: Compander %d enable current %d, new %d\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1824 | __func__, comp + 1, wsa_priv->comp_enabled[comp], value); |
| 1825 | wsa_priv->comp_enabled[comp] = value; |
| 1826 | |
| 1827 | return 0; |
| 1828 | } |
| 1829 | |
| 1830 | static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, |
| 1831 | struct snd_ctl_elem_value *ucontrol) |
| 1832 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1833 | struct snd_soc_component *component = |
| 1834 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1835 | struct device *wsa_dev = NULL; |
| 1836 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1837 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1838 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1839 | return -EINVAL; |
| 1840 | |
| 1841 | ucontrol->value.integer.value[0] = wsa_priv->ear_spkr_gain; |
| 1842 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1843 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1844 | __func__, ucontrol->value.integer.value[0]); |
| 1845 | |
| 1846 | return 0; |
| 1847 | } |
| 1848 | |
| 1849 | static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, |
| 1850 | struct snd_ctl_elem_value *ucontrol) |
| 1851 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1852 | struct snd_soc_component *component = |
| 1853 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1854 | struct device *wsa_dev = NULL; |
| 1855 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1856 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1857 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1858 | return -EINVAL; |
| 1859 | |
| 1860 | wsa_priv->ear_spkr_gain = ucontrol->value.integer.value[0]; |
| 1861 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1862 | dev_dbg(component->dev, "%s: gain = %d\n", __func__, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1863 | wsa_priv->ear_spkr_gain); |
| 1864 | |
| 1865 | return 0; |
| 1866 | } |
| 1867 | |
| 1868 | static int wsa_macro_spkr_left_boost_stage_get(struct snd_kcontrol *kcontrol, |
| 1869 | struct snd_ctl_elem_value *ucontrol) |
| 1870 | { |
| 1871 | u8 bst_state_max = 0; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1872 | struct snd_soc_component *component = |
| 1873 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1874 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1875 | bst_state_max = snd_soc_component_read32(component, |
| 1876 | BOLERO_CDC_WSA_BOOST0_BOOST_CTL); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1877 | bst_state_max = (bst_state_max & 0x0c) >> 2; |
| 1878 | ucontrol->value.integer.value[0] = bst_state_max; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1879 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1880 | __func__, ucontrol->value.integer.value[0]); |
| 1881 | |
| 1882 | return 0; |
| 1883 | } |
| 1884 | |
| 1885 | static int wsa_macro_spkr_left_boost_stage_put(struct snd_kcontrol *kcontrol, |
| 1886 | struct snd_ctl_elem_value *ucontrol) |
| 1887 | { |
| 1888 | u8 bst_state_max; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1889 | struct snd_soc_component *component = |
| 1890 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1891 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1892 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1893 | __func__, ucontrol->value.integer.value[0]); |
| 1894 | bst_state_max = ucontrol->value.integer.value[0] << 2; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1895 | snd_soc_component_update_bits(component, |
| 1896 | BOLERO_CDC_WSA_BOOST0_BOOST_CTL, |
| 1897 | 0x0c, bst_state_max); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1898 | |
| 1899 | return 0; |
| 1900 | } |
| 1901 | |
| 1902 | static int wsa_macro_spkr_right_boost_stage_get(struct snd_kcontrol *kcontrol, |
| 1903 | struct snd_ctl_elem_value *ucontrol) |
| 1904 | { |
| 1905 | u8 bst_state_max = 0; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1906 | struct snd_soc_component *component = |
| 1907 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1908 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1909 | bst_state_max = snd_soc_component_read32(component, |
| 1910 | BOLERO_CDC_WSA_BOOST1_BOOST_CTL); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1911 | bst_state_max = (bst_state_max & 0x0c) >> 2; |
| 1912 | ucontrol->value.integer.value[0] = bst_state_max; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1913 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1914 | __func__, ucontrol->value.integer.value[0]); |
| 1915 | |
| 1916 | return 0; |
| 1917 | } |
| 1918 | |
| 1919 | static int wsa_macro_spkr_right_boost_stage_put(struct snd_kcontrol *kcontrol, |
| 1920 | struct snd_ctl_elem_value *ucontrol) |
| 1921 | { |
| 1922 | u8 bst_state_max; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1923 | struct snd_soc_component *component = |
| 1924 | snd_soc_kcontrol_component(kcontrol); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1925 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1926 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1927 | __func__, ucontrol->value.integer.value[0]); |
| 1928 | bst_state_max = ucontrol->value.integer.value[0] << 2; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1929 | snd_soc_component_update_bits(component, |
| 1930 | BOLERO_CDC_WSA_BOOST1_BOOST_CTL, |
| 1931 | 0x0c, bst_state_max); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1932 | |
| 1933 | return 0; |
| 1934 | } |
| 1935 | |
| 1936 | static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, |
| 1937 | struct snd_ctl_elem_value *ucontrol) |
| 1938 | { |
| 1939 | struct snd_soc_dapm_widget *widget = |
| 1940 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1941 | struct snd_soc_component *component = |
| 1942 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1943 | struct device *wsa_dev = NULL; |
| 1944 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1945 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1946 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1947 | return -EINVAL; |
| 1948 | |
| 1949 | ucontrol->value.integer.value[0] = |
| 1950 | wsa_priv->rx_port_value[widget->shift]; |
| 1951 | return 0; |
| 1952 | } |
| 1953 | |
| 1954 | static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, |
| 1955 | struct snd_ctl_elem_value *ucontrol) |
| 1956 | { |
| 1957 | struct snd_soc_dapm_widget *widget = |
| 1958 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1959 | struct snd_soc_component *component = |
| 1960 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1961 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 1962 | struct snd_soc_dapm_update *update = NULL; |
| 1963 | u32 rx_port_value = ucontrol->value.integer.value[0]; |
| 1964 | u32 bit_input = 0; |
| 1965 | u32 aif_rst; |
| 1966 | struct device *wsa_dev = NULL; |
| 1967 | struct wsa_macro_priv *wsa_priv = NULL; |
| 1968 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1969 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1970 | return -EINVAL; |
| 1971 | |
| 1972 | aif_rst = wsa_priv->rx_port_value[widget->shift]; |
| 1973 | if (!rx_port_value) { |
| 1974 | if (aif_rst == 0) { |
| 1975 | dev_err(wsa_dev, "%s: AIF reset already\n", __func__); |
| 1976 | return 0; |
| 1977 | } |
| 1978 | } |
| 1979 | wsa_priv->rx_port_value[widget->shift] = rx_port_value; |
| 1980 | |
| 1981 | bit_input = widget->shift; |
| 1982 | if (widget->shift >= WSA_MACRO_RX_MIX) |
| 1983 | bit_input %= WSA_MACRO_RX_MIX; |
| 1984 | |
| 1985 | switch (rx_port_value) { |
| 1986 | case 0: |
| 1987 | clear_bit(bit_input, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1988 | &wsa_priv->active_ch_mask[aif_rst]); |
| 1989 | wsa_priv->active_ch_cnt[aif_rst]--; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1990 | break; |
| 1991 | case 1: |
| 1992 | case 2: |
| 1993 | set_bit(bit_input, |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 1994 | &wsa_priv->active_ch_mask[rx_port_value]); |
| 1995 | wsa_priv->active_ch_cnt[rx_port_value]++; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 1996 | break; |
| 1997 | default: |
| 1998 | dev_err(wsa_dev, |
| 1999 | "%s: Invalid AIF_ID for WSA RX MUX\n", __func__); |
| 2000 | return -EINVAL; |
| 2001 | } |
| 2002 | |
| 2003 | snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, |
| 2004 | rx_port_value, e, update); |
| 2005 | return 0; |
| 2006 | } |
| 2007 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2008 | static int wsa_macro_vbat_bcl_gsm_mode_func_get(struct snd_kcontrol *kcontrol, |
| 2009 | struct snd_ctl_elem_value *ucontrol) |
| 2010 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2011 | struct snd_soc_component *component = |
| 2012 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2013 | |
| 2014 | ucontrol->value.integer.value[0] = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2015 | ((snd_soc_component_read32( |
| 2016 | component, BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG) & 0x04) ? |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2017 | 1 : 0); |
| 2018 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2019 | dev_dbg(component->dev, "%s: value: %lu\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2020 | ucontrol->value.integer.value[0]); |
| 2021 | |
| 2022 | return 0; |
| 2023 | } |
| 2024 | |
| 2025 | static int wsa_macro_vbat_bcl_gsm_mode_func_put(struct snd_kcontrol *kcontrol, |
| 2026 | struct snd_ctl_elem_value *ucontrol) |
| 2027 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2028 | struct snd_soc_component *component = |
| 2029 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2030 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2031 | dev_dbg(component->dev, "%s: value: %lu\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2032 | ucontrol->value.integer.value[0]); |
| 2033 | |
| 2034 | /* Set Vbat register configuration for GSM mode bit based on value */ |
| 2035 | if (ucontrol->value.integer.value[0]) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2036 | snd_soc_component_update_bits(component, |
| 2037 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, |
| 2038 | 0x04, 0x04); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2039 | else |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2040 | snd_soc_component_update_bits(component, |
| 2041 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, |
| 2042 | 0x04, 0x00); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2043 | |
| 2044 | return 0; |
| 2045 | } |
| 2046 | |
| 2047 | static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, |
| 2048 | struct snd_ctl_elem_value *ucontrol) |
| 2049 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2050 | struct snd_soc_component *component = |
| 2051 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2052 | struct device *wsa_dev = NULL; |
| 2053 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2054 | int path = ((struct soc_multi_mixer_control *) |
| 2055 | kcontrol->private_value)->shift; |
| 2056 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2057 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2058 | return -EINVAL; |
| 2059 | |
| 2060 | ucontrol->value.integer.value[0] = wsa_priv->is_softclip_on[path]; |
| 2061 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2062 | dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2063 | __func__, ucontrol->value.integer.value[0]); |
| 2064 | |
| 2065 | return 0; |
| 2066 | } |
| 2067 | |
| 2068 | static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, |
| 2069 | struct snd_ctl_elem_value *ucontrol) |
| 2070 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2071 | struct snd_soc_component *component = |
| 2072 | snd_soc_kcontrol_component(kcontrol); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2073 | struct device *wsa_dev = NULL; |
| 2074 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2075 | int path = ((struct soc_multi_mixer_control *) |
| 2076 | kcontrol->private_value)->shift; |
| 2077 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2078 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2079 | return -EINVAL; |
| 2080 | |
| 2081 | wsa_priv->is_softclip_on[path] = ucontrol->value.integer.value[0]; |
| 2082 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2083 | dev_dbg(component->dev, "%s: soft clip enable for %d: %d\n", __func__, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2084 | path, wsa_priv->is_softclip_on[path]); |
| 2085 | |
| 2086 | return 0; |
| 2087 | } |
| 2088 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2089 | static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { |
| 2090 | SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, |
| 2091 | wsa_macro_ear_spkr_pa_gain_get, |
| 2092 | wsa_macro_ear_spkr_pa_gain_put), |
| 2093 | SOC_ENUM_EXT("SPKR Left Boost Max State", |
| 2094 | wsa_macro_spkr_boost_stage_enum, |
| 2095 | wsa_macro_spkr_left_boost_stage_get, |
| 2096 | wsa_macro_spkr_left_boost_stage_put), |
| 2097 | SOC_ENUM_EXT("SPKR Right Boost Max State", |
| 2098 | wsa_macro_spkr_boost_stage_enum, |
| 2099 | wsa_macro_spkr_right_boost_stage_get, |
| 2100 | wsa_macro_spkr_right_boost_stage_put), |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2101 | SOC_ENUM_EXT("GSM mode Enable", wsa_macro_vbat_bcl_gsm_mode_enum, |
| 2102 | wsa_macro_vbat_bcl_gsm_mode_func_get, |
| 2103 | wsa_macro_vbat_bcl_gsm_mode_func_put), |
| 2104 | SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, |
| 2105 | WSA_MACRO_SOFTCLIP0, 1, 0, |
| 2106 | wsa_macro_soft_clip_enable_get, |
| 2107 | wsa_macro_soft_clip_enable_put), |
| 2108 | SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, |
| 2109 | WSA_MACRO_SOFTCLIP1, 1, 0, |
| 2110 | wsa_macro_soft_clip_enable_get, |
| 2111 | wsa_macro_soft_clip_enable_put), |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2112 | SOC_SINGLE_SX_TLV("WSA_RX0 Digital Volume", |
| 2113 | BOLERO_CDC_WSA_RX0_RX_VOL_CTL, |
| 2114 | 0, -84, 40, digital_gain), |
| 2115 | SOC_SINGLE_SX_TLV("WSA_RX1 Digital Volume", |
| 2116 | BOLERO_CDC_WSA_RX1_RX_VOL_CTL, |
| 2117 | 0, -84, 40, digital_gain), |
| 2118 | SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, |
| 2119 | wsa_macro_get_compander, wsa_macro_set_compander), |
| 2120 | SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, |
| 2121 | wsa_macro_get_compander, wsa_macro_set_compander), |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 2122 | SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, |
| 2123 | 1, 0, wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), |
| 2124 | SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, |
| 2125 | 1, 0, wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2126 | }; |
| 2127 | |
| 2128 | static const struct soc_enum rx_mux_enum = |
| 2129 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text); |
| 2130 | |
| 2131 | static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = { |
| 2132 | SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum, |
| 2133 | wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), |
| 2134 | SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum, |
| 2135 | wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), |
| 2136 | SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum, |
| 2137 | wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), |
| 2138 | SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum, |
| 2139 | wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), |
| 2140 | }; |
| 2141 | |
| 2142 | static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, |
| 2143 | struct snd_ctl_elem_value *ucontrol) |
| 2144 | { |
| 2145 | struct snd_soc_dapm_widget *widget = |
| 2146 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2147 | struct snd_soc_component *component = |
| 2148 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2149 | struct soc_multi_mixer_control *mixer = |
| 2150 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 2151 | u32 dai_id = widget->shift; |
| 2152 | u32 spk_tx_id = mixer->shift; |
| 2153 | struct device *wsa_dev = NULL; |
| 2154 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2155 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2156 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2157 | return -EINVAL; |
| 2158 | |
| 2159 | if (test_bit(spk_tx_id, &wsa_priv->active_ch_mask[dai_id])) |
| 2160 | ucontrol->value.integer.value[0] = 1; |
| 2161 | else |
| 2162 | ucontrol->value.integer.value[0] = 0; |
| 2163 | |
| 2164 | return 0; |
| 2165 | } |
| 2166 | |
| 2167 | static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, |
| 2168 | struct snd_ctl_elem_value *ucontrol) |
| 2169 | { |
| 2170 | struct snd_soc_dapm_widget *widget = |
| 2171 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2172 | struct snd_soc_component *component = |
| 2173 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2174 | struct soc_multi_mixer_control *mixer = |
| 2175 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 2176 | u32 spk_tx_id = mixer->shift; |
| 2177 | u32 enable = ucontrol->value.integer.value[0]; |
| 2178 | struct device *wsa_dev = NULL; |
| 2179 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2180 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2181 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2182 | return -EINVAL; |
| 2183 | |
| 2184 | wsa_priv->vi_feed_value = ucontrol->value.integer.value[0]; |
| 2185 | |
| 2186 | if (enable) { |
| 2187 | if (spk_tx_id == WSA_MACRO_TX0 && |
| 2188 | !test_bit(WSA_MACRO_TX0, |
| 2189 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 2190 | set_bit(WSA_MACRO_TX0, |
| 2191 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI]); |
| 2192 | wsa_priv->active_ch_cnt[WSA_MACRO_AIF_VI]++; |
| 2193 | } |
| 2194 | if (spk_tx_id == WSA_MACRO_TX1 && |
| 2195 | !test_bit(WSA_MACRO_TX1, |
| 2196 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 2197 | set_bit(WSA_MACRO_TX1, |
| 2198 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI]); |
| 2199 | wsa_priv->active_ch_cnt[WSA_MACRO_AIF_VI]++; |
| 2200 | } |
| 2201 | } else { |
| 2202 | if (spk_tx_id == WSA_MACRO_TX0 && |
| 2203 | test_bit(WSA_MACRO_TX0, |
| 2204 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 2205 | clear_bit(WSA_MACRO_TX0, |
| 2206 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI]); |
| 2207 | wsa_priv->active_ch_cnt[WSA_MACRO_AIF_VI]--; |
| 2208 | } |
| 2209 | if (spk_tx_id == WSA_MACRO_TX1 && |
| 2210 | test_bit(WSA_MACRO_TX1, |
| 2211 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI])) { |
| 2212 | clear_bit(WSA_MACRO_TX1, |
| 2213 | &wsa_priv->active_ch_mask[WSA_MACRO_AIF_VI]); |
| 2214 | wsa_priv->active_ch_cnt[WSA_MACRO_AIF_VI]--; |
| 2215 | } |
| 2216 | } |
| 2217 | snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL); |
| 2218 | |
| 2219 | return 0; |
| 2220 | } |
| 2221 | |
| 2222 | static const struct snd_kcontrol_new aif_vi_mixer[] = { |
| 2223 | SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0, |
| 2224 | wsa_macro_vi_feed_mixer_get, |
| 2225 | wsa_macro_vi_feed_mixer_put), |
| 2226 | SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0, |
| 2227 | wsa_macro_vi_feed_mixer_get, |
| 2228 | wsa_macro_vi_feed_mixer_put), |
| 2229 | }; |
| 2230 | |
| 2231 | static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { |
| 2232 | SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0, |
| 2233 | SND_SOC_NOPM, 0, 0), |
| 2234 | |
| 2235 | SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0, |
| 2236 | SND_SOC_NOPM, 0, 0), |
| 2237 | |
| 2238 | SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0, |
| 2239 | SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, |
| 2240 | wsa_macro_enable_vi_feedback, |
| 2241 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
| 2242 | |
| 2243 | SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, |
| 2244 | SND_SOC_NOPM, 0, 0), |
| 2245 | |
| 2246 | SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, |
| 2247 | 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 2248 | SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM, |
| 2249 | WSA_MACRO_EC0_MUX, 0, |
| 2250 | &rx_mix_ec0_mux, wsa_macro_enable_echo, |
| 2251 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2252 | SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM, |
| 2253 | WSA_MACRO_EC1_MUX, 0, |
| 2254 | &rx_mix_ec1_mux, wsa_macro_enable_echo, |
| 2255 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2256 | |
| 2257 | SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0, |
| 2258 | &rx_mux[WSA_MACRO_RX0]), |
| 2259 | SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0, |
| 2260 | &rx_mux[WSA_MACRO_RX1]), |
| 2261 | SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0, |
| 2262 | &rx_mux[WSA_MACRO_RX_MIX0]), |
| 2263 | SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0, |
| 2264 | &rx_mux[WSA_MACRO_RX_MIX1]), |
| 2265 | |
| 2266 | SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2267 | SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2268 | SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2269 | SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2270 | |
| 2271 | SND_SOC_DAPM_MUX_E("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, |
| 2272 | &rx0_prim_inp0_mux, wsa_macro_enable_swr, |
| 2273 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2274 | SND_SOC_DAPM_MUX_E("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, |
| 2275 | &rx0_prim_inp1_mux, wsa_macro_enable_swr, |
| 2276 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2277 | SND_SOC_DAPM_MUX_E("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, |
| 2278 | &rx0_prim_inp2_mux, wsa_macro_enable_swr, |
| 2279 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2280 | SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, 0, 0, |
| 2281 | &rx0_mix_mux, wsa_macro_enable_mix_path, |
| 2282 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2283 | SND_SOC_DAPM_MUX_E("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, |
| 2284 | &rx1_prim_inp0_mux, wsa_macro_enable_swr, |
| 2285 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2286 | SND_SOC_DAPM_MUX_E("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, |
| 2287 | &rx1_prim_inp1_mux, wsa_macro_enable_swr, |
| 2288 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2289 | SND_SOC_DAPM_MUX_E("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, |
| 2290 | &rx1_prim_inp2_mux, wsa_macro_enable_swr, |
| 2291 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2292 | SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, 0, 0, |
| 2293 | &rx1_mix_mux, wsa_macro_enable_mix_path, |
| 2294 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2295 | SND_SOC_DAPM_MIXER("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2296 | SND_SOC_DAPM_MIXER("WSA_RX INT1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2297 | SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2298 | SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), |
| 2299 | |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2300 | SND_SOC_DAPM_MUX_E("WSA_RX0 INT0 SIDETONE MIX", |
| 2301 | BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 4, 0, |
| 2302 | &rx0_sidetone_mix_mux, wsa_macro_enable_swr, |
| 2303 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2304 | SND_SOC_DAPM_INPUT("WSA SRC0_INP"), |
| 2305 | |
| 2306 | SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"), |
| 2307 | SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"), |
| 2308 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2309 | SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM, |
| 2310 | WSA_MACRO_COMP1, 0, NULL, 0, wsa_macro_enable_interpolator, |
| 2311 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2312 | SND_SOC_DAPM_POST_PMD), |
| 2313 | SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM, |
| 2314 | WSA_MACRO_COMP2, 0, NULL, 0, wsa_macro_enable_interpolator, |
| 2315 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2316 | SND_SOC_DAPM_POST_PMD), |
| 2317 | |
| 2318 | SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, |
| 2319 | NULL, 0, wsa_macro_spk_boost_event, |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 2320 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2321 | SND_SOC_DAPM_POST_PMD), |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2322 | SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0, |
| 2323 | NULL, 0, wsa_macro_spk_boost_event, |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 2324 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 2325 | SND_SOC_DAPM_POST_PMD), |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2326 | |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2327 | SND_SOC_DAPM_MIXER_E("WSA_RX INT0 VBAT", SND_SOC_NOPM, |
| 2328 | 0, 0, wsa_int0_vbat_mix_switch, |
| 2329 | ARRAY_SIZE(wsa_int0_vbat_mix_switch), |
| 2330 | wsa_macro_enable_vbat, |
| 2331 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2332 | SND_SOC_DAPM_MIXER_E("WSA_RX INT1 VBAT", SND_SOC_NOPM, |
| 2333 | 0, 0, wsa_int1_vbat_mix_switch, |
| 2334 | ARRAY_SIZE(wsa_int1_vbat_mix_switch), |
| 2335 | wsa_macro_enable_vbat, |
| 2336 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2337 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2338 | SND_SOC_DAPM_INPUT("VIINPUT_WSA"), |
| 2339 | |
| 2340 | SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), |
| 2341 | SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), |
| 2342 | |
| 2343 | SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 2344 | wsa_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 2345 | }; |
| 2346 | |
| 2347 | static const struct snd_soc_dapm_route wsa_audio_map[] = { |
| 2348 | /* VI Feedback */ |
| 2349 | {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"}, |
| 2350 | {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"}, |
| 2351 | {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, |
| 2352 | {"WSA AIF_VI", NULL, "WSA_MCLK"}, |
| 2353 | |
Laxminath Kasam | 36ab7bb | 2018-06-18 18:43:46 +0530 | [diff] [blame] | 2354 | {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, |
| 2355 | {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, |
| 2356 | {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, |
| 2357 | {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, |
| 2358 | {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"}, |
| 2359 | {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"}, |
| 2360 | {"WSA AIF_ECHO", NULL, "WSA_MCLK"}, |
| 2361 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2362 | {"WSA AIF1 PB", NULL, "WSA_MCLK"}, |
| 2363 | {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"}, |
| 2364 | |
| 2365 | {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, |
| 2366 | {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, |
| 2367 | {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, |
| 2368 | {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, |
| 2369 | |
| 2370 | {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, |
| 2371 | {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, |
| 2372 | {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, |
| 2373 | {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, |
| 2374 | |
| 2375 | {"WSA RX0", NULL, "WSA RX0 MUX"}, |
| 2376 | {"WSA RX1", NULL, "WSA RX1 MUX"}, |
| 2377 | {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"}, |
| 2378 | {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"}, |
| 2379 | |
| 2380 | {"WSA_RX0 INP0", "RX0", "WSA RX0"}, |
| 2381 | {"WSA_RX0 INP0", "RX1", "WSA RX1"}, |
| 2382 | {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"}, |
| 2383 | {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2384 | {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"}, |
| 2385 | {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2386 | {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"}, |
| 2387 | |
| 2388 | {"WSA_RX0 INP1", "RX0", "WSA RX0"}, |
| 2389 | {"WSA_RX0 INP1", "RX1", "WSA RX1"}, |
| 2390 | {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"}, |
| 2391 | {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2392 | {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"}, |
| 2393 | {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2394 | {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"}, |
| 2395 | |
| 2396 | {"WSA_RX0 INP2", "RX0", "WSA RX0"}, |
| 2397 | {"WSA_RX0 INP2", "RX1", "WSA RX1"}, |
| 2398 | {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"}, |
| 2399 | {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2400 | {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"}, |
| 2401 | {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2402 | {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"}, |
| 2403 | |
| 2404 | {"WSA_RX0 MIX INP", "RX0", "WSA RX0"}, |
| 2405 | {"WSA_RX0 MIX INP", "RX1", "WSA RX1"}, |
| 2406 | {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, |
| 2407 | {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, |
| 2408 | {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"}, |
| 2409 | |
| 2410 | {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"}, |
| 2411 | {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2412 | {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, |
| 2413 | {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2414 | {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2415 | |
| 2416 | {"WSA_RX INT0 VBAT", "WSA RX0 VBAT Enable", "WSA_RX INT0 INTERP"}, |
| 2417 | {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 VBAT"}, |
| 2418 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2419 | {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2420 | {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2421 | |
| 2422 | {"WSA_RX1 INP0", "RX0", "WSA RX0"}, |
| 2423 | {"WSA_RX1 INP0", "RX1", "WSA RX1"}, |
| 2424 | {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"}, |
| 2425 | {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2426 | {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"}, |
| 2427 | {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2428 | {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"}, |
| 2429 | |
| 2430 | {"WSA_RX1 INP1", "RX0", "WSA RX0"}, |
| 2431 | {"WSA_RX1 INP1", "RX1", "WSA RX1"}, |
| 2432 | {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"}, |
| 2433 | {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2434 | {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"}, |
| 2435 | {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2436 | {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"}, |
| 2437 | |
| 2438 | {"WSA_RX1 INP2", "RX0", "WSA RX0"}, |
| 2439 | {"WSA_RX1 INP2", "RX1", "WSA RX1"}, |
| 2440 | {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"}, |
| 2441 | {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"}, |
Laxminath Kasam | 6fc2e74 | 2018-08-26 23:32:57 +0530 | [diff] [blame] | 2442 | {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"}, |
| 2443 | {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2444 | {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"}, |
| 2445 | |
| 2446 | {"WSA_RX1 MIX INP", "RX0", "WSA RX0"}, |
| 2447 | {"WSA_RX1 MIX INP", "RX1", "WSA RX1"}, |
| 2448 | {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, |
| 2449 | {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, |
| 2450 | {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"}, |
| 2451 | |
| 2452 | {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, |
| 2453 | {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2454 | |
| 2455 | {"WSA_RX INT1 VBAT", "WSA RX1 VBAT Enable", "WSA_RX INT1 INTERP"}, |
| 2456 | {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 VBAT"}, |
| 2457 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2458 | {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, |
| 2459 | {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 2460 | {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2461 | }; |
| 2462 | |
| 2463 | static const struct wsa_macro_reg_mask_val wsa_macro_reg_init[] = { |
| 2464 | {BOLERO_CDC_WSA_BOOST0_BOOST_CFG1, 0x3F, 0x12}, |
| 2465 | {BOLERO_CDC_WSA_BOOST0_BOOST_CFG2, 0x1C, 0x08}, |
| 2466 | {BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x1E, 0x18}, |
| 2467 | {BOLERO_CDC_WSA_BOOST1_BOOST_CFG1, 0x3F, 0x12}, |
| 2468 | {BOLERO_CDC_WSA_BOOST1_BOOST_CFG2, 0x1C, 0x08}, |
| 2469 | {BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x1E, 0x18}, |
| 2470 | {BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0x70, 0x58}, |
| 2471 | {BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0x70, 0x58}, |
| 2472 | {BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x08}, |
| 2473 | {BOLERO_CDC_WSA_RX1_RX_PATH_CFG1, 0x08, 0x08}, |
| 2474 | {BOLERO_CDC_WSA_TOP_TOP_CFG1, 0x02, 0x02}, |
| 2475 | {BOLERO_CDC_WSA_TOP_TOP_CFG1, 0x01, 0x01}, |
| 2476 | {BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, |
| 2477 | {BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, |
| 2478 | {BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, |
| 2479 | {BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x01, 0x01}, |
| 2480 | {BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80}, |
| 2481 | {BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80}, |
| 2482 | {BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01}, |
| 2483 | {BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01}, |
| 2484 | {BOLERO_CDC_WSA_RX0_RX_PATH_CFG0, 0x01, 0x01}, |
| 2485 | {BOLERO_CDC_WSA_RX1_RX_PATH_CFG0, 0x01, 0x01}, |
| 2486 | {BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x01, 0x01}, |
| 2487 | {BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x01, 0x01}, |
| 2488 | }; |
| 2489 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2490 | static void wsa_macro_init_bcl_pmic_reg(struct snd_soc_component *component) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2491 | { |
| 2492 | struct device *wsa_dev = NULL; |
| 2493 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2494 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2495 | if (!component) { |
| 2496 | pr_err("%s: NULL component pointer!\n", __func__); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2497 | return; |
| 2498 | } |
| 2499 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2500 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2501 | return; |
| 2502 | |
| 2503 | switch (wsa_priv->bcl_pmic_params.id) { |
| 2504 | case 0: |
| 2505 | /* Enable ID0 to listen to respective PMIC group interrupts */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2506 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2507 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x02, 0x02); |
| 2508 | /* Update MC_SID0 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2509 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2510 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x0F, |
| 2511 | wsa_priv->bcl_pmic_params.sid); |
| 2512 | /* Update MC_PPID0 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2513 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2514 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0xFF, |
| 2515 | wsa_priv->bcl_pmic_params.ppid); |
| 2516 | break; |
| 2517 | case 1: |
| 2518 | /* Enable ID1 to listen to respective PMIC group interrupts */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2519 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2520 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0x01, 0x01); |
| 2521 | /* Update MC_SID1 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2522 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2523 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x0F, |
| 2524 | wsa_priv->bcl_pmic_params.sid); |
| 2525 | /* Update MC_PPID1 */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2526 | snd_soc_component_update_bits(component, |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2527 | BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0xFF, |
| 2528 | wsa_priv->bcl_pmic_params.ppid); |
| 2529 | break; |
| 2530 | default: |
| 2531 | dev_err(wsa_dev, "%s: PMIC ID is invalid %d\n", |
| 2532 | __func__, wsa_priv->bcl_pmic_params.id); |
| 2533 | break; |
| 2534 | } |
| 2535 | } |
| 2536 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2537 | static void wsa_macro_init_reg(struct snd_soc_component *component) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2538 | { |
| 2539 | int i; |
| 2540 | |
| 2541 | for (i = 0; i < ARRAY_SIZE(wsa_macro_reg_init); i++) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2542 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2543 | wsa_macro_reg_init[i].reg, |
| 2544 | wsa_macro_reg_init[i].mask, |
| 2545 | wsa_macro_reg_init[i].val); |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2546 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2547 | wsa_macro_init_bcl_pmic_reg(component); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2548 | } |
| 2549 | |
| 2550 | static int wsa_swrm_clock(void *handle, bool enable) |
| 2551 | { |
| 2552 | struct wsa_macro_priv *wsa_priv = (struct wsa_macro_priv *) handle; |
| 2553 | struct regmap *regmap = dev_get_regmap(wsa_priv->dev->parent, NULL); |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2554 | int ret = 0; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2555 | |
Tanya Dixit | ab8eba8 | 2018-10-05 15:07:37 +0530 | [diff] [blame] | 2556 | if (regmap == NULL) { |
| 2557 | dev_err(wsa_priv->dev, "%s: regmap is NULL\n", __func__); |
| 2558 | return -EINVAL; |
| 2559 | } |
| 2560 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2561 | mutex_lock(&wsa_priv->swr_clk_lock); |
| 2562 | |
| 2563 | dev_dbg(wsa_priv->dev, "%s: swrm clock %s\n", |
| 2564 | __func__, (enable ? "enable" : "disable")); |
| 2565 | if (enable) { |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2566 | if (wsa_priv->swr_clk_users == 0) { |
| 2567 | ret = wsa_macro_mclk_enable(wsa_priv, 1, true); |
| 2568 | if (ret < 0) { |
| 2569 | dev_err(wsa_priv->dev, |
| 2570 | "%s: wsa request clock enable failed\n", |
| 2571 | __func__); |
| 2572 | goto exit; |
| 2573 | } |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 2574 | if (wsa_priv->reset_swr) |
| 2575 | regmap_update_bits(regmap, |
| 2576 | BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, |
| 2577 | 0x02, 0x02); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2578 | regmap_update_bits(regmap, |
| 2579 | BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, |
| 2580 | 0x01, 0x01); |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 2581 | if (wsa_priv->reset_swr) |
| 2582 | regmap_update_bits(regmap, |
| 2583 | BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, |
| 2584 | 0x02, 0x00); |
| 2585 | wsa_priv->reset_swr = false; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2586 | regmap_update_bits(regmap, |
| 2587 | BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, |
| 2588 | 0x1C, 0x0C); |
| 2589 | msm_cdc_pinctrl_select_active_state( |
| 2590 | wsa_priv->wsa_swr_gpio_p); |
| 2591 | } |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2592 | wsa_priv->swr_clk_users++; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2593 | } else { |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2594 | if (wsa_priv->swr_clk_users <= 0) { |
| 2595 | dev_err(wsa_priv->dev, "%s: clock already disabled\n", |
| 2596 | __func__); |
| 2597 | wsa_priv->swr_clk_users = 0; |
| 2598 | goto exit; |
| 2599 | } |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2600 | wsa_priv->swr_clk_users--; |
| 2601 | if (wsa_priv->swr_clk_users == 0) { |
| 2602 | regmap_update_bits(regmap, |
| 2603 | BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, |
| 2604 | 0x01, 0x00); |
| 2605 | msm_cdc_pinctrl_select_sleep_state( |
| 2606 | wsa_priv->wsa_swr_gpio_p); |
| 2607 | wsa_macro_mclk_enable(wsa_priv, 0, true); |
| 2608 | } |
| 2609 | } |
| 2610 | dev_dbg(wsa_priv->dev, "%s: swrm clock users %d\n", |
| 2611 | __func__, wsa_priv->swr_clk_users); |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2612 | exit: |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2613 | mutex_unlock(&wsa_priv->swr_clk_lock); |
Aditya Bavanari | c496ed2 | 2018-11-16 15:50:40 +0530 | [diff] [blame] | 2614 | return ret; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2615 | } |
| 2616 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2617 | static int wsa_macro_init(struct snd_soc_component *component) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2618 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2619 | struct snd_soc_dapm_context *dapm = |
| 2620 | snd_soc_component_get_dapm(component); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2621 | int ret; |
| 2622 | struct device *wsa_dev = NULL; |
| 2623 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2624 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2625 | wsa_dev = bolero_get_device_ptr(component->dev, WSA_MACRO); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2626 | if (!wsa_dev) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2627 | dev_err(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2628 | "%s: null device for macro!\n", __func__); |
| 2629 | return -EINVAL; |
| 2630 | } |
| 2631 | wsa_priv = dev_get_drvdata(wsa_dev); |
| 2632 | if (!wsa_priv) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2633 | dev_err(component->dev, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2634 | "%s: priv is null for macro!\n", __func__); |
| 2635 | return -EINVAL; |
| 2636 | } |
| 2637 | |
| 2638 | ret = snd_soc_dapm_new_controls(dapm, wsa_macro_dapm_widgets, |
| 2639 | ARRAY_SIZE(wsa_macro_dapm_widgets)); |
| 2640 | if (ret < 0) { |
| 2641 | dev_err(wsa_dev, "%s: Failed to add controls\n", __func__); |
| 2642 | return ret; |
| 2643 | } |
| 2644 | |
| 2645 | ret = snd_soc_dapm_add_routes(dapm, wsa_audio_map, |
| 2646 | ARRAY_SIZE(wsa_audio_map)); |
| 2647 | if (ret < 0) { |
| 2648 | dev_err(wsa_dev, "%s: Failed to add routes\n", __func__); |
| 2649 | return ret; |
| 2650 | } |
| 2651 | |
| 2652 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 2653 | if (ret < 0) { |
| 2654 | dev_err(wsa_dev, "%s: Failed to add widgets\n", __func__); |
| 2655 | return ret; |
| 2656 | } |
| 2657 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2658 | ret = snd_soc_add_component_controls(component, wsa_macro_snd_controls, |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2659 | ARRAY_SIZE(wsa_macro_snd_controls)); |
| 2660 | if (ret < 0) { |
| 2661 | dev_err(wsa_dev, "%s: Failed to add snd_ctls\n", __func__); |
| 2662 | return ret; |
| 2663 | } |
Laxminath Kasam | 638b560 | 2018-09-24 13:19:52 +0530 | [diff] [blame] | 2664 | snd_soc_dapm_ignore_suspend(dapm, "WSA_AIF1 Playback"); |
| 2665 | snd_soc_dapm_ignore_suspend(dapm, "WSA_AIF_MIX1 Playback"); |
| 2666 | snd_soc_dapm_ignore_suspend(dapm, "WSA_AIF_VI Capture"); |
| 2667 | snd_soc_dapm_ignore_suspend(dapm, "WSA_AIF_ECHO Capture"); |
| 2668 | snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT"); |
| 2669 | snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT"); |
| 2670 | snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA"); |
| 2671 | snd_soc_dapm_ignore_suspend(dapm, "WSA SRC0_INP"); |
| 2672 | snd_soc_dapm_ignore_suspend(dapm, "WSA_TX DEC0_INP"); |
| 2673 | snd_soc_dapm_ignore_suspend(dapm, "WSA_TX DEC1_INP"); |
| 2674 | snd_soc_dapm_sync(dapm); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2675 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2676 | wsa_priv->component = component; |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 2677 | wsa_priv->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_0_DB; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2678 | wsa_macro_init_reg(component); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2679 | |
| 2680 | return 0; |
| 2681 | } |
| 2682 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2683 | static int wsa_macro_deinit(struct snd_soc_component *component) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2684 | { |
| 2685 | struct device *wsa_dev = NULL; |
| 2686 | struct wsa_macro_priv *wsa_priv = NULL; |
| 2687 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2688 | if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__)) |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2689 | return -EINVAL; |
| 2690 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2691 | wsa_priv->component = NULL; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2692 | |
| 2693 | return 0; |
| 2694 | } |
| 2695 | |
| 2696 | static void wsa_macro_add_child_devices(struct work_struct *work) |
| 2697 | { |
| 2698 | struct wsa_macro_priv *wsa_priv; |
| 2699 | struct platform_device *pdev; |
| 2700 | struct device_node *node; |
| 2701 | struct wsa_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp; |
| 2702 | int ret; |
| 2703 | u16 count = 0, ctrl_num = 0; |
| 2704 | struct wsa_macro_swr_ctrl_platform_data *platdata; |
| 2705 | char plat_dev_name[WSA_MACRO_SWR_STRING_LEN]; |
| 2706 | |
| 2707 | wsa_priv = container_of(work, struct wsa_macro_priv, |
| 2708 | wsa_macro_add_child_devices_work); |
| 2709 | if (!wsa_priv) { |
| 2710 | pr_err("%s: Memory for wsa_priv does not exist\n", |
| 2711 | __func__); |
| 2712 | return; |
| 2713 | } |
Laxminath Kasam | 21c8b22 | 2018-06-21 18:47:22 +0530 | [diff] [blame] | 2714 | if (!wsa_priv->dev || !wsa_priv->dev->of_node) { |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2715 | dev_err(wsa_priv->dev, |
| 2716 | "%s: DT node for wsa_priv does not exist\n", __func__); |
| 2717 | return; |
| 2718 | } |
| 2719 | |
| 2720 | platdata = &wsa_priv->swr_plat_data; |
| 2721 | wsa_priv->child_count = 0; |
| 2722 | |
| 2723 | for_each_available_child_of_node(wsa_priv->dev->of_node, node) { |
| 2724 | if (strnstr(node->name, "wsa_swr_master", |
| 2725 | strlen("wsa_swr_master")) != NULL) |
| 2726 | strlcpy(plat_dev_name, "wsa_swr_ctrl", |
| 2727 | (WSA_MACRO_SWR_STRING_LEN - 1)); |
| 2728 | else if (strnstr(node->name, "msm_cdc_pinctrl", |
| 2729 | strlen("msm_cdc_pinctrl")) != NULL) |
| 2730 | strlcpy(plat_dev_name, node->name, |
| 2731 | (WSA_MACRO_SWR_STRING_LEN - 1)); |
| 2732 | else |
| 2733 | continue; |
| 2734 | |
| 2735 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 2736 | if (!pdev) { |
| 2737 | dev_err(wsa_priv->dev, "%s: pdev memory alloc failed\n", |
| 2738 | __func__); |
| 2739 | ret = -ENOMEM; |
| 2740 | goto err; |
| 2741 | } |
| 2742 | pdev->dev.parent = wsa_priv->dev; |
| 2743 | pdev->dev.of_node = node; |
| 2744 | |
| 2745 | if (strnstr(node->name, "wsa_swr_master", |
| 2746 | strlen("wsa_swr_master")) != NULL) { |
| 2747 | ret = platform_device_add_data(pdev, platdata, |
| 2748 | sizeof(*platdata)); |
| 2749 | if (ret) { |
| 2750 | dev_err(&pdev->dev, |
| 2751 | "%s: cannot add plat data ctrl:%d\n", |
| 2752 | __func__, ctrl_num); |
| 2753 | goto fail_pdev_add; |
| 2754 | } |
| 2755 | } |
| 2756 | |
| 2757 | ret = platform_device_add(pdev); |
| 2758 | if (ret) { |
| 2759 | dev_err(&pdev->dev, |
| 2760 | "%s: Cannot add platform device\n", |
| 2761 | __func__); |
| 2762 | goto fail_pdev_add; |
| 2763 | } |
| 2764 | |
| 2765 | if (!strcmp(node->name, "wsa_swr_master")) { |
| 2766 | temp = krealloc(swr_ctrl_data, |
| 2767 | (ctrl_num + 1) * sizeof( |
| 2768 | struct wsa_macro_swr_ctrl_data), |
| 2769 | GFP_KERNEL); |
| 2770 | if (!temp) { |
| 2771 | dev_err(&pdev->dev, "out of memory\n"); |
| 2772 | ret = -ENOMEM; |
| 2773 | goto err; |
| 2774 | } |
| 2775 | swr_ctrl_data = temp; |
| 2776 | swr_ctrl_data[ctrl_num].wsa_swr_pdev = pdev; |
| 2777 | ctrl_num++; |
| 2778 | dev_dbg(&pdev->dev, |
| 2779 | "%s: Added soundwire ctrl device(s)\n", |
| 2780 | __func__); |
| 2781 | wsa_priv->swr_ctrl_data = swr_ctrl_data; |
| 2782 | } |
| 2783 | if (wsa_priv->child_count < WSA_MACRO_CHILD_DEVICES_MAX) |
| 2784 | wsa_priv->pdev_child_devices[ |
| 2785 | wsa_priv->child_count++] = pdev; |
| 2786 | else |
| 2787 | goto err; |
| 2788 | } |
| 2789 | |
| 2790 | return; |
| 2791 | fail_pdev_add: |
| 2792 | for (count = 0; count < wsa_priv->child_count; count++) |
| 2793 | platform_device_put(wsa_priv->pdev_child_devices[count]); |
| 2794 | err: |
| 2795 | return; |
| 2796 | } |
| 2797 | |
| 2798 | static void wsa_macro_init_ops(struct macro_ops *ops, |
| 2799 | char __iomem *wsa_io_base) |
| 2800 | { |
| 2801 | memset(ops, 0, sizeof(struct macro_ops)); |
| 2802 | ops->init = wsa_macro_init; |
| 2803 | ops->exit = wsa_macro_deinit; |
| 2804 | ops->io_base = wsa_io_base; |
| 2805 | ops->dai_ptr = wsa_macro_dai; |
| 2806 | ops->num_dais = ARRAY_SIZE(wsa_macro_dai); |
| 2807 | ops->mclk_fn = wsa_macro_mclk_ctrl; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 2808 | ops->event_handler = wsa_macro_event_handler; |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 2809 | ops->set_port_map = wsa_macro_set_port_map; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2810 | } |
| 2811 | |
| 2812 | static int wsa_macro_probe(struct platform_device *pdev) |
| 2813 | { |
| 2814 | struct macro_ops ops; |
| 2815 | struct wsa_macro_priv *wsa_priv; |
| 2816 | u32 wsa_base_addr; |
| 2817 | char __iomem *wsa_io_base; |
| 2818 | int ret = 0; |
| 2819 | struct clk *wsa_core_clk, *wsa_npl_clk; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2820 | u8 bcl_pmic_params[3]; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2821 | |
| 2822 | wsa_priv = devm_kzalloc(&pdev->dev, sizeof(struct wsa_macro_priv), |
| 2823 | GFP_KERNEL); |
| 2824 | if (!wsa_priv) |
| 2825 | return -ENOMEM; |
| 2826 | |
| 2827 | wsa_priv->dev = &pdev->dev; |
| 2828 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 2829 | &wsa_base_addr); |
| 2830 | if (ret) { |
| 2831 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 2832 | __func__, "reg"); |
| 2833 | return ret; |
| 2834 | } |
| 2835 | wsa_priv->wsa_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 2836 | "qcom,wsa-swr-gpios", 0); |
| 2837 | if (!wsa_priv->wsa_swr_gpio_p) { |
| 2838 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 2839 | __func__); |
| 2840 | return -EINVAL; |
| 2841 | } |
| 2842 | wsa_io_base = devm_ioremap(&pdev->dev, |
| 2843 | wsa_base_addr, WSA_MACRO_MAX_OFFSET); |
| 2844 | if (!wsa_io_base) { |
| 2845 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 2846 | return -EINVAL; |
| 2847 | } |
| 2848 | wsa_priv->wsa_io_base = wsa_io_base; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame^] | 2849 | wsa_priv->reset_swr = true; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2850 | INIT_WORK(&wsa_priv->wsa_macro_add_child_devices_work, |
| 2851 | wsa_macro_add_child_devices); |
| 2852 | wsa_priv->swr_plat_data.handle = (void *) wsa_priv; |
| 2853 | wsa_priv->swr_plat_data.read = NULL; |
| 2854 | wsa_priv->swr_plat_data.write = NULL; |
| 2855 | wsa_priv->swr_plat_data.bulk_write = NULL; |
| 2856 | wsa_priv->swr_plat_data.clk = wsa_swrm_clock; |
| 2857 | wsa_priv->swr_plat_data.handle_irq = NULL; |
| 2858 | |
| 2859 | /* Register MCLK for wsa macro */ |
| 2860 | wsa_core_clk = devm_clk_get(&pdev->dev, "wsa_core_clk"); |
| 2861 | if (IS_ERR(wsa_core_clk)) { |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 2862 | ret = PTR_ERR(wsa_core_clk); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2863 | dev_err(&pdev->dev, "%s: clk get %s failed\n", |
| 2864 | __func__, "wsa_core_clk"); |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 2865 | return ret; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2866 | } |
| 2867 | wsa_priv->wsa_core_clk = wsa_core_clk; |
| 2868 | /* Register npl clk for soundwire */ |
| 2869 | wsa_npl_clk = devm_clk_get(&pdev->dev, "wsa_npl_clk"); |
| 2870 | if (IS_ERR(wsa_npl_clk)) { |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 2871 | ret = PTR_ERR(wsa_npl_clk); |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2872 | dev_err(&pdev->dev, "%s: clk get %s failed\n", |
| 2873 | __func__, "wsa_npl_clk"); |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 2874 | return ret; |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2875 | } |
| 2876 | wsa_priv->wsa_npl_clk = wsa_npl_clk; |
Aditya Bavanari | 4f3d564 | 2018-09-18 22:19:10 +0530 | [diff] [blame] | 2877 | |
| 2878 | ret = of_property_read_u8_array(pdev->dev.of_node, |
| 2879 | "qcom,wsa-bcl-pmic-params", bcl_pmic_params, |
| 2880 | sizeof(bcl_pmic_params)); |
| 2881 | if (ret) { |
| 2882 | dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 2883 | __func__, "qcom,wsa-bcl-pmic-params"); |
| 2884 | } else { |
| 2885 | wsa_priv->bcl_pmic_params.id = bcl_pmic_params[0]; |
| 2886 | wsa_priv->bcl_pmic_params.sid = bcl_pmic_params[1]; |
| 2887 | wsa_priv->bcl_pmic_params.ppid = bcl_pmic_params[2]; |
| 2888 | } |
| 2889 | |
Laxminath Kasam | 243e275 | 2018-04-12 00:40:19 +0530 | [diff] [blame] | 2890 | dev_set_drvdata(&pdev->dev, wsa_priv); |
| 2891 | mutex_init(&wsa_priv->mclk_lock); |
| 2892 | mutex_init(&wsa_priv->swr_clk_lock); |
| 2893 | wsa_macro_init_ops(&ops, wsa_io_base); |
| 2894 | ret = bolero_register_macro(&pdev->dev, WSA_MACRO, &ops); |
| 2895 | if (ret < 0) { |
| 2896 | dev_err(&pdev->dev, "%s: register macro failed\n", __func__); |
| 2897 | goto reg_macro_fail; |
| 2898 | } |
| 2899 | schedule_work(&wsa_priv->wsa_macro_add_child_devices_work); |
| 2900 | return ret; |
| 2901 | reg_macro_fail: |
| 2902 | mutex_destroy(&wsa_priv->mclk_lock); |
| 2903 | mutex_destroy(&wsa_priv->swr_clk_lock); |
| 2904 | return ret; |
| 2905 | } |
| 2906 | |
| 2907 | static int wsa_macro_remove(struct platform_device *pdev) |
| 2908 | { |
| 2909 | struct wsa_macro_priv *wsa_priv; |
| 2910 | u16 count = 0; |
| 2911 | |
| 2912 | wsa_priv = dev_get_drvdata(&pdev->dev); |
| 2913 | |
| 2914 | if (!wsa_priv) |
| 2915 | return -EINVAL; |
| 2916 | |
| 2917 | for (count = 0; count < wsa_priv->child_count && |
| 2918 | count < WSA_MACRO_CHILD_DEVICES_MAX; count++) |
| 2919 | platform_device_unregister(wsa_priv->pdev_child_devices[count]); |
| 2920 | |
| 2921 | bolero_unregister_macro(&pdev->dev, WSA_MACRO); |
| 2922 | mutex_destroy(&wsa_priv->mclk_lock); |
| 2923 | mutex_destroy(&wsa_priv->swr_clk_lock); |
| 2924 | return 0; |
| 2925 | } |
| 2926 | |
| 2927 | static const struct of_device_id wsa_macro_dt_match[] = { |
| 2928 | {.compatible = "qcom,wsa-macro"}, |
| 2929 | {} |
| 2930 | }; |
| 2931 | |
| 2932 | static struct platform_driver wsa_macro_driver = { |
| 2933 | .driver = { |
| 2934 | .name = "wsa_macro", |
| 2935 | .owner = THIS_MODULE, |
| 2936 | .of_match_table = wsa_macro_dt_match, |
| 2937 | }, |
| 2938 | .probe = wsa_macro_probe, |
| 2939 | .remove = wsa_macro_remove, |
| 2940 | }; |
| 2941 | |
| 2942 | module_platform_driver(wsa_macro_driver); |
| 2943 | |
| 2944 | MODULE_DESCRIPTION("WSA macro driver"); |
| 2945 | MODULE_LICENSE("GPL v2"); |