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Soumya Managolibbeb8ee2019-03-18 17:05:29 +05301/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __MSM_COMMON
14#define __MSM_COMMON
15
16#include <sound/soc.h>
Laxminath Kasam605b42f2017-08-01 22:02:15 +053017#include <dsp/q6afe-v2.h>
18#include "codecs/wcd-mbhc-v2.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053019
Vatsal Bucha1b70f5b2017-10-23 16:17:49 +053020#define DEFAULT_MCLK_RATE 9600000
21#define NATIVE_MCLK_RATE 11289600
22
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053023#define SAMPLING_RATE_8KHZ 8000
24#define SAMPLING_RATE_11P025KHZ 11025
25#define SAMPLING_RATE_16KHZ 16000
26#define SAMPLING_RATE_22P05KHZ 22050
27#define SAMPLING_RATE_32KHZ 32000
28#define SAMPLING_RATE_44P1KHZ 44100
29#define SAMPLING_RATE_48KHZ 48000
30#define SAMPLING_RATE_88P2KHZ 88200
31#define SAMPLING_RATE_96KHZ 96000
32#define SAMPLING_RATE_176P4KHZ 176400
33#define SAMPLING_RATE_192KHZ 192000
34#define SAMPLING_RATE_352P8KHZ 352800
35#define SAMPLING_RATE_384KHZ 384000
36
37#define TDM_CHANNEL_MAX 8
38#define TDM_SLOT_OFFSET_MAX 8
39
40enum {
41 TDM_0 = 0,
42 TDM_1,
43 TDM_2,
44 TDM_3,
45 TDM_4,
46 TDM_5,
47 TDM_6,
48 TDM_7,
49 TDM_PORT_MAX,
50};
51
52enum {
53 TDM_PRI = 0,
54 TDM_SEC,
55 TDM_TERT,
56 TDM_QUAT,
Rohit Kumard1754482017-09-10 22:57:39 +053057 TDM_QUIN,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053058 TDM_INTERFACE_MAX,
59};
60
61struct tdm_port {
62 u32 mode;
63 u32 channel;
64};
65
66enum {
Rohit Kumaraf88e4c2017-10-04 13:47:10 +053067 PRIM_MI2S = 0,
68 SEC_MI2S,
69 TERT_MI2S,
70 QUAT_MI2S,
71 QUIN_MI2S,
72 MI2S_MAX,
73};
74
75enum {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053076 DIG_CDC,
77 ANA_CDC,
78 CODECS_MAX,
79};
80
81extern const struct snd_kcontrol_new msm_common_snd_controls[];
82extern bool codec_reg_done;
83struct sdm660_codec {
84 void* (*get_afe_config_fn)(struct snd_soc_codec *codec,
85 enum afe_config_type config_type);
86};
87
88enum {
89 INT_SND_CARD,
Viraja Kommaraju6521c6e2018-01-02 23:29:45 +053090 INT_DIG_SND_CARD,
91 INT_MAX_SND_CARD = INT_DIG_SND_CARD,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053092 EXT_SND_CARD_TASHA,
93 EXT_SND_CARD_TAVIL,
94};
95
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053096struct msm_asoc_mach_data {
97 int us_euro_gpio; /* used by gpio driver API */
Vatsal Bucha42dd4022017-12-07 14:35:59 +053098 int usbc_en2_gpio; /* used by gpio driver API */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053099 int hph_en1_gpio;
100 int hph_en0_gpio;
101 struct device_node *us_euro_gpio_p; /* used by pinctrl API */
Vatsal Bucha42dd4022017-12-07 14:35:59 +0530102 struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530103 struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
104 struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
105 struct device_node *pdm_gpio_p; /* used by pinctrl API */
106 struct device_node *comp_gpio_p; /* used by pinctrl API */
107 struct device_node *dmic_gpio_p; /* used by pinctrl API */
108 struct device_node *ext_spk_gpio_p; /* used by pinctrl API */
Rohit Kumaraf88e4c2017-10-04 13:47:10 +0530109 struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530110 struct snd_soc_codec *codec;
111 struct sdm660_codec sdm660_codec_fn;
112 struct snd_info_entry *codec_root;
113 int spk_ext_pa_gpio;
114 int mclk_freq;
115 bool native_clk_set;
116 int lb_mode;
117 int snd_card_val;
118 u8 micbias1_cap_mode;
119 u8 micbias2_cap_mode;
120 atomic_t int_mclk0_rsc_ref;
121 atomic_t int_mclk0_enabled;
122 struct mutex cdc_int_mclk0_mutex;
123 struct delayed_work disable_int_mclk0_work;
124 struct afe_clk_set digital_cdc_core_clk;
Surendar Karka813c3d22018-11-05 13:46:17 +0530125 int gpio_linein_det;
126 int gpio_lineout_det;
127 int linein_det_swh;
128 int lineout_det_swh;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530129};
130
131int msm_common_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
132 struct snd_pcm_hw_params *params);
133int msm_aux_pcm_snd_startup(struct snd_pcm_substream *substream);
134void msm_aux_pcm_snd_shutdown(struct snd_pcm_substream *substream);
135int msm_mi2s_snd_startup(struct snd_pcm_substream *substream);
136void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream);
Soumya Managolibbeb8ee2019-03-18 17:05:29 +0530137int msm_tdm_snd_startup(struct snd_pcm_substream *substream);
138void msm_tdm_snd_shutdown(struct snd_pcm_substream *substream);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530139int msm_common_snd_controls_size(void);
Laxminath Kasam38070be2017-08-17 18:21:59 +0530140void msm_set_codec_reg_done(bool done);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530141#endif