blob: df8e73a479c8b261b6f7b3090a0c8f0bbe0ec110 [file] [log] [blame]
Soumya Managoli35868f72018-02-23 12:49:24 +05301/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/err.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/clk.h>
19#include <linux/clk/msm-clk-provider.h>
20#include <linux/clk/msm-clk.h>
21#include <linux/platform_device.h>
22#include <linux/gpio.h>
23#include <linux/of_gpio.h>
Soumya Managoli4c201f42018-02-24 15:49:54 +053024#include <dt-bindings/clock/msm-clocks-8996.h>
Soumya Managoli35868f72018-02-23 12:49:24 +053025#include <dsp/q6afe-v2.h>
26#include "audio-ext-clk.h"
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053027
Raja Mallike1b2f792018-06-01 13:17:36 +053028#define clk_audio_lpass_mclk 0x575ec22b
29
Soumya Managoli4c201f42018-02-24 15:49:54 +053030enum audio_clk_mux {
31 PMI_CLK,
32 AP_CLK2,
33 LPASS_MCLK,
34};
35
Raja Mallike1b2f792018-06-01 13:17:36 +053036enum clk_enablement {
37 CLK_DISABLE = 0,
38 CLK_ENABLE,
39};
40
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053041struct pinctrl_info {
42 struct pinctrl *pinctrl;
43 struct pinctrl_state *sleep;
44 struct pinctrl_state *active;
45};
46
47struct audio_ext_ap_clk {
48 bool enabled;
49 int gpio;
50 struct clk c;
51};
52
Soumya Managoli4c201f42018-02-24 15:49:54 +053053struct audio_ext_ap_clk2 {
54 bool enabled;
55 struct pinctrl_info pnctrl_info;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053056 struct clk c;
57};
58
Soumya Managoli4c201f42018-02-24 15:49:54 +053059struct audio_ext_pmi_clk {
60 int gpio;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053061 bool enabled;
62 struct pinctrl_info pnctrl_info;
63 struct clk c;
64};
65
Raja Mallike1b2f792018-06-01 13:17:36 +053066struct audio_ext_lpass_mclk {
67 struct pinctrl_info pnctrl_info;
68 struct clk c;
69 u32 lpass_clock;
70 void __iomem *lpass_csr_gpio_mux_spkrctl_vaddr;
71};
72
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +053073static struct afe_clk_set clk2_config = {
74 Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
75 Q6AFE_LPASS_CLK_ID_SPEAKER_I2S_OSR,
76 Q6AFE_LPASS_IBIT_CLK_11_P2896_MHZ,
77 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
78 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
79 0,
80};
81
Raja Mallike1b2f792018-06-01 13:17:36 +053082static struct afe_clk_set digital_cdc_core_clk = {
83 Q6AFE_LPASS_CLK_CONFIG_API_VERSION,
84 Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE,
85 Q6AFE_LPASS_OSR_CLK_9_P600_MHZ,
86 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
87 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
88 0,
89};
90
91static int audio_ext_set_lpass_mclk_v2(struct clk *clk,
92 enum clk_enablement enable)
93{
94 struct audio_ext_lpass_mclk *audio_lpass_mclk;
95 int ret, val;
96
97 pr_debug("%s: Setting clock using v2, enable(%d)\n", __func__, enable);
98
99 audio_lpass_mclk = container_of(clk, struct audio_ext_lpass_mclk, c);
100 if (audio_lpass_mclk == NULL) {
101 pr_err("%s: audio_lpass_mclk is NULL\n", __func__);
102 ret = -EINVAL;
103 goto done;
104 }
105
106 if (audio_lpass_mclk->lpass_csr_gpio_mux_spkrctl_vaddr &&
107 enable) {
108 val = ioread32(audio_lpass_mclk->
109 lpass_csr_gpio_mux_spkrctl_vaddr);
110 val = val | 0x00000002;
111 iowrite32(val, audio_lpass_mclk->
112 lpass_csr_gpio_mux_spkrctl_vaddr);
113 }
114
115 digital_cdc_core_clk.enable = enable;
116 ret = afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX,
117 &digital_cdc_core_clk);
118 if (ret < 0) {
119 pr_err("%s: afe_set_digital_codec_core_clock failed\n"
120 " with ret %d\n", __func__, ret);
121 goto done;
122 }
123
124done:
125 return ret;
126}
127
128static int audio_ext_lpass_mclk_prepare(struct clk *clk)
129{
130 struct audio_ext_lpass_mclk *audio_lpass_mclk;
131 struct pinctrl_info *pnctrl_info;
132 enum lpass_clk_ver lpass_clk_ver;
133 int ret;
134
135 audio_lpass_mclk = container_of(clk, struct audio_ext_lpass_mclk, c);
136 if (audio_lpass_mclk == NULL) {
137 pr_err("%s: audio_lpass_mclk is NULL\n", __func__);
138 ret = -EINVAL;
139 goto done;
140 }
141
142 pnctrl_info = &audio_lpass_mclk->pnctrl_info;
143 if (pnctrl_info && pnctrl_info->pinctrl) {
144 ret = pinctrl_select_state(pnctrl_info->pinctrl,
145 pnctrl_info->active);
146 if (ret) {
147 pr_err("%s: pinctrl active state selection failed with %d\n",
148 __func__, ret);
149 ret = -EIO;
150 goto done;
151 }
152 }
153
154 lpass_clk_ver = afe_get_lpass_clk_ver();
155
156 if (lpass_clk_ver >= LPASS_CLK_VER_2)
157 ret = audio_ext_set_lpass_mclk_v2(clk, CLK_ENABLE);
158done:
159 return ret;
160}
161
162static void audio_ext_lpass_mclk_unprepare(struct clk *clk)
163{
164 struct audio_ext_lpass_mclk *audio_lpass_mclk;
165 struct pinctrl_info *pnctrl_info;
166 enum lpass_clk_ver lpass_clk_ver;
167 int ret;
168
169 audio_lpass_mclk = container_of(clk, struct audio_ext_lpass_mclk, c);
170 if (audio_lpass_mclk == NULL) {
171 pr_err("%s: audio_lpass_mclk is NULL\n", __func__);
172 ret = -EINVAL;
173 goto done;
174 }
175
176 pnctrl_info = &audio_lpass_mclk->pnctrl_info;
177 if (pnctrl_info && pnctrl_info->pinctrl) {
178 ret = pinctrl_select_state(pnctrl_info->pinctrl,
179 pnctrl_info->sleep);
180 if (ret) {
181 pr_err("%s: pinctrl sleep state selection failed with %d\n",
182 __func__, ret);
183 ret = -EIO;
184 goto done;
185 }
186 }
187
188 lpass_clk_ver = afe_get_lpass_clk_ver();
189
190 if (lpass_clk_ver >= LPASS_CLK_VER_2)
191 ret = audio_ext_set_lpass_mclk_v2(clk, CLK_DISABLE);
192done:
193 pr_debug("%s: Unprepare of mclk exiting with %d\n", __func__, ret);
194}
195
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530196static inline struct audio_ext_ap_clk *to_audio_ap_clk(struct clk *clk)
197{
198 return container_of(clk, struct audio_ext_ap_clk, c);
199}
200
Soumya Managoli4c201f42018-02-24 15:49:54 +0530201static inline struct audio_ext_pmi_clk *to_audio_pmi_clk(struct clk *clk)
202{
203 return container_of(clk, struct audio_ext_pmi_clk, c);
204}
205
206static int audio_ext_pmi_clk_prepare(struct clk *clk)
207{
208 struct audio_ext_pmi_clk *audio_pmi_clk = to_audio_pmi_clk(clk);
209 struct pinctrl_info *pnctrl_info = &audio_pmi_clk->pnctrl_info;
210 int ret;
211
212 if (!pnctrl_info->pinctrl || !pnctrl_info->active) {
213 pr_err("%s: pinctrl state not defined\n", __func__);
214 return -EINVAL;
215 }
216
217 ret = pinctrl_select_state(pnctrl_info->pinctrl,
218 pnctrl_info->active);
219 if (ret) {
220 pr_err("%s: active state select failed with %d\n",
221 __func__, ret);
222 return -EIO;
223 }
224 return 0;
225}
226
227static void audio_ext_pmi_clk_unprepare(struct clk *clk)
228{
229 struct audio_ext_pmi_clk *audio_pmi_clk = to_audio_pmi_clk(clk);
230 struct pinctrl_info *pnctrl_info = &audio_pmi_clk->pnctrl_info;
231 int ret;
232
Vaishnavi Kommarajua14b0d72018-03-27 16:43:27 +0530233 if (!pnctrl_info->pinctrl || !pnctrl_info->active) {
Soumya Managoli4c201f42018-02-24 15:49:54 +0530234 pr_err("%s: pinctrl state not defined\n", __func__);
Vaishnavi Kommarajua14b0d72018-03-27 16:43:27 +0530235 return;
236 }
Soumya Managoli4c201f42018-02-24 15:49:54 +0530237
238 ret = pinctrl_select_state(pnctrl_info->pinctrl,
239 pnctrl_info->sleep);
240 if (ret)
241 pr_err("%s: sleep state select failed with %d\n",
242 __func__, ret);
243}
244
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530245static int audio_ext_clk_prepare(struct clk *clk)
246{
247 struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(clk);
248
249 pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
250 if (gpio_is_valid(audio_clk->gpio))
251 return gpio_direction_output(audio_clk->gpio, 1);
252 return 0;
253}
254
255static void audio_ext_clk_unprepare(struct clk *clk)
256{
257 struct audio_ext_ap_clk *audio_clk = to_audio_ap_clk(clk);
258
259 pr_debug("%s: gpio: %d\n", __func__, audio_clk->gpio);
260 if (gpio_is_valid(audio_clk->gpio))
261 gpio_direction_output(audio_clk->gpio, 0);
262}
263
264static inline struct audio_ext_ap_clk2 *to_audio_ap_clk2(struct clk *clk)
265{
266 return container_of(clk, struct audio_ext_ap_clk2, c);
267}
268
269static int audio_ext_clk2_prepare(struct clk *clk)
270{
271 struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(clk);
272 struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
273 int ret;
274
275
276 if (!pnctrl_info->pinctrl || !pnctrl_info->active)
277 return 0;
278
279 ret = pinctrl_select_state(pnctrl_info->pinctrl,
280 pnctrl_info->active);
281 if (ret) {
282 pr_err("%s: active state select failed with %d\n",
283 __func__, ret);
284 return -EIO;
285 }
286
287 clk2_config.enable = 1;
288 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
289 if (ret < 0) {
290 pr_err("%s: failed to set clock, ret = %d\n", __func__, ret);
291 return -EINVAL;
292 }
293
294 return 0;
295}
296
297static void audio_ext_clk2_unprepare(struct clk *clk)
298{
299 struct audio_ext_ap_clk2 *audio_clk2 = to_audio_ap_clk2(clk);
300 struct pinctrl_info *pnctrl_info = &audio_clk2->pnctrl_info;
301 int ret;
302
303 if (!pnctrl_info->pinctrl || !pnctrl_info->sleep)
304 return;
305
306 ret = pinctrl_select_state(pnctrl_info->pinctrl,
307 pnctrl_info->sleep);
308 if (ret)
309 pr_err("%s: sleep state select failed with %d\n",
310 __func__, ret);
311
312 clk2_config.enable = 0;
313 ret = afe_set_lpass_clk_cfg(IDX_RSVD_3, &clk2_config);
314 if (ret < 0)
315 pr_err("%s: failed to reset clock, ret = %d\n", __func__, ret);
316}
317
318static const struct clk_ops audio_ext_ap_clk_ops = {
319 .prepare = audio_ext_clk_prepare,
320 .unprepare = audio_ext_clk_unprepare,
321};
322
323static const struct clk_ops audio_ext_ap_clk2_ops = {
324 .prepare = audio_ext_clk2_prepare,
325 .unprepare = audio_ext_clk2_unprepare,
326};
327
Soumya Managoli4c201f42018-02-24 15:49:54 +0530328static const struct clk_ops audio_ext_pmi_clk_ops = {
329 .prepare = audio_ext_pmi_clk_prepare,
330 .unprepare = audio_ext_pmi_clk_unprepare,
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530331};
Raja Mallike1b2f792018-06-01 13:17:36 +0530332
333static struct clk_ops audio_ext_lpass_mclk_ops = {
334 .prepare = audio_ext_lpass_mclk_prepare,
335 .unprepare = audio_ext_lpass_mclk_unprepare,
336};
337
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530338static struct audio_ext_pmi_clk audio_pmi_lnbb_clk = {
339 .gpio = -EINVAL,
340 .c = {
341 .dbg_name = "audio_ext_pmi_lnbb_clk",
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530342 CLK_INIT(audio_pmi_lnbb_clk.c),
343 },
344};
345
346static struct audio_ext_ap_clk audio_ap_clk = {
347 .gpio = -EINVAL,
348 .c = {
349 .dbg_name = "audio_ext_ap_clk",
350 .ops = &audio_ext_ap_clk_ops,
351 CLK_INIT(audio_ap_clk.c),
352 },
353};
354
355static struct audio_ext_ap_clk2 audio_ap_clk2 = {
356 .c = {
357 .dbg_name = "audio_ext_ap_clk2",
358 .ops = &audio_ext_ap_clk2_ops,
359 CLK_INIT(audio_ap_clk2.c),
360 },
361};
362
Soumya Managoli4c201f42018-02-24 15:49:54 +0530363static struct audio_ext_pmi_clk audio_pmi_clk = {
364 .c = {
365 .dbg_name = "audio_ext_pmi_clk",
366 .ops = &audio_ext_pmi_clk_ops,
367 CLK_INIT(audio_pmi_clk.c),
368 },
369};
370
Raja Mallike1b2f792018-06-01 13:17:36 +0530371static struct audio_ext_lpass_mclk audio_lpass_mclk = {
372 .c = {
373 .dbg_name = "audio_ext_lpass_mclk",
374 .ops = &audio_ext_lpass_mclk_ops,
375 CLK_INIT(audio_lpass_mclk.c),
376 },
377};
378
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530379static struct clk_lookup audio_ref_clock[] = {
380 CLK_LIST(audio_ap_clk),
381 CLK_LIST(audio_pmi_clk),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530382 CLK_LIST(audio_ap_clk2),
Raja Mallike1b2f792018-06-01 13:17:36 +0530383 CLK_LIST(audio_lpass_mclk),
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530384};
385
Soumya Managoli4c201f42018-02-24 15:49:54 +0530386static int audio_get_pinctrl(struct platform_device *pdev,
387 enum audio_clk_mux mux)
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530388{
Soumya Managoli4c201f42018-02-24 15:49:54 +0530389 struct device *dev = &pdev->dev;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530390 struct pinctrl_info *pnctrl_info;
391 struct pinctrl *pinctrl;
392 int ret;
393
Soumya Managoli4c201f42018-02-24 15:49:54 +0530394 switch (mux) {
395 case PMI_CLK:
396 pnctrl_info = &audio_pmi_clk.pnctrl_info;
397 break;
398 case AP_CLK2:
399 pnctrl_info = &audio_ap_clk2.pnctrl_info;
400 break;
Raja Mallike1b2f792018-06-01 13:17:36 +0530401 case LPASS_MCLK:
402 pnctrl_info = &audio_lpass_mclk.pnctrl_info;
403 break;
Soumya Managoli4c201f42018-02-24 15:49:54 +0530404 default:
405 dev_err(dev, "%s Not a valid MUX ID: %d\n",
406 __func__, mux);
407 return -EINVAL;
408 }
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530409
410 if (pnctrl_info->pinctrl) {
411 dev_dbg(&pdev->dev, "%s: already requested before\n",
412 __func__);
413 return -EINVAL;
414 }
415
416 pinctrl = devm_pinctrl_get(&pdev->dev);
417 if (IS_ERR_OR_NULL(pinctrl)) {
418 dev_dbg(&pdev->dev, "%s: Unable to get pinctrl handle\n",
419 __func__);
420 return -EINVAL;
421 }
422 pnctrl_info->pinctrl = pinctrl;
423 /* get all state handles from Device Tree */
424 pnctrl_info->sleep = pinctrl_lookup_state(pinctrl, "sleep");
425 if (IS_ERR(pnctrl_info->sleep)) {
426 dev_err(&pdev->dev, "%s: could not get sleep pinstate\n",
427 __func__);
428 goto err;
429 }
430 pnctrl_info->active = pinctrl_lookup_state(pinctrl, "active");
431 if (IS_ERR(pnctrl_info->active)) {
432 dev_err(&pdev->dev, "%s: could not get active pinstate\n",
433 __func__);
434 goto err;
435 }
436 /* Reset the TLMM pins to a default state */
437 ret = pinctrl_select_state(pnctrl_info->pinctrl,
438 pnctrl_info->sleep);
439 if (ret) {
440 dev_err(&pdev->dev, "%s: Disable TLMM pins failed with %d\n",
441 __func__, ret);
442 goto err;
443 }
444 return 0;
445
446err:
447 devm_pinctrl_put(pnctrl_info->pinctrl);
448 return -EINVAL;
449}
450
451static int audio_ref_clk_probe(struct platform_device *pdev)
452{
453 int clk_gpio;
454 int ret;
Soumya Managoli4c201f42018-02-24 15:49:54 +0530455 struct clk *div_clk1;
Raja Mallike1b2f792018-06-01 13:17:36 +0530456 u32 lpass_csr_gpio_mux_spkrctl_reg = 0;
457
458 ret = of_property_read_u32(pdev->dev.of_node,
459 "qcom,lpass-clock",
460 &audio_lpass_mclk.lpass_clock);
461 if (ret)
462 dev_dbg(&pdev->dev, "%s: qcom,lpass-clock is undefined\n",
463 __func__);
464
465 if (audio_lpass_mclk.lpass_clock) {
466
467 ret = of_property_read_u32(pdev->dev.of_node, "reg",
468 &lpass_csr_gpio_mux_spkrctl_reg);
469 if (!ret) {
470 audio_lpass_mclk.lpass_csr_gpio_mux_spkrctl_vaddr =
471 devm_ioremap(&pdev->dev, lpass_csr_gpio_mux_spkrctl_reg, 4);
472 if (audio_lpass_mclk.lpass_csr_gpio_mux_spkrctl_vaddr == NULL) {
473 dev_err(&pdev->dev, "%s devm_ioremap failed\n", __func__);
474 return -ENOMEM;
475 }
476 }
477
478 ret = audio_get_pinctrl(pdev, LPASS_MCLK);
479 if (ret)
480 dev_err(&pdev->dev, "%s: Parsing pinctrl %s failed\n",
481 __func__, "LPASS_MCLK");
482
483 ret = of_msm_clock_register(pdev->dev.of_node, audio_ref_clock,
484 ARRAY_SIZE(audio_ref_clock));
485 if (ret)
486 dev_err(&pdev->dev, "%s: clock register failed\n",
487 __func__);
488 return ret;
489 }
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530490
491 clk_gpio = of_get_named_gpio(pdev->dev.of_node,
492 "qcom,audio-ref-clk-gpio", 0);
493 if (clk_gpio > 0) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530494 if (of_property_read_bool(pdev->dev.of_node,
495 "qcom,node_has_rpm_clock")) {
Soumya Managoli4c201f42018-02-24 15:49:54 +0530496 div_clk1 = clk_get(&pdev->dev, "osr_clk");
497 if (IS_ERR(div_clk1)) {
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530498 dev_err(&pdev->dev, "Failed to get RPM div clk\n");
Soumya Managoli4c201f42018-02-24 15:49:54 +0530499 ret = PTR_ERR(div_clk1);
500 goto err_clk_register;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530501 }
Soumya Managoli4c201f42018-02-24 15:49:54 +0530502 audio_pmi_clk.c.parent = div_clk1;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530503 audio_pmi_clk.gpio = clk_gpio;
Soumya Managoli4c201f42018-02-24 15:49:54 +0530504 ret = audio_get_pinctrl(pdev, PMI_CLK);
505 if (ret) {
506 dev_err(&pdev->dev, "%s: Parsing pinctrl %s failed\n",
507 __func__, "PMI_CLK");
508 goto err_clk_register;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530509 }
Soumya Managoli4c201f42018-02-24 15:49:54 +0530510 }
511 ret = audio_get_pinctrl(pdev, AP_CLK2);
512 if (ret) {
513 dev_err(&pdev->dev, "%s: Parsing pinctrl %s failed\n",
514 __func__, "AP_CLK2");
515 goto err_clk_register;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530516 }
517 }
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530518 ret = of_msm_clock_register(pdev->dev.of_node, audio_ref_clock,
Soumya Managoli4c201f42018-02-24 15:49:54 +0530519 ARRAY_SIZE(audio_ref_clock));
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530520 if (ret) {
Soumya Managoli4c201f42018-02-24 15:49:54 +0530521 dev_err(&pdev->dev, "%s: clock register failed\n", __func__);
522 goto err_clk_register;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530523 }
Soumya Managoli4c201f42018-02-24 15:49:54 +0530524err_clk_register:
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530525 return ret;
526}
527
528static int audio_ref_clk_remove(struct platform_device *pdev)
529{
530 struct pinctrl_info *pnctrl_info = &audio_ap_clk2.pnctrl_info;
Raja Mallike1b2f792018-06-01 13:17:36 +0530531 struct pinctrl_info *lpass_pnctrl_info = &audio_lpass_mclk.pnctrl_info;
Soumya Managoli4c201f42018-02-24 15:49:54 +0530532 struct pinctrl_info *pmi_pnctrl_info = &audio_pmi_clk.pnctrl_info;
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530533
534 if (audio_pmi_clk.gpio > 0)
535 gpio_free(audio_pmi_clk.gpio);
536 else if (audio_ap_clk.gpio > 0)
537 gpio_free(audio_ap_clk.gpio);
538
539 if (pnctrl_info->pinctrl) {
540 devm_pinctrl_put(pnctrl_info->pinctrl);
541 pnctrl_info->pinctrl = NULL;
542 }
543
Raja Mallike1b2f792018-06-01 13:17:36 +0530544 if (lpass_pnctrl_info->pinctrl) {
545 devm_pinctrl_put(lpass_pnctrl_info->pinctrl);
546 lpass_pnctrl_info->pinctrl = NULL;
547 }
548
Soumya Managoli4c201f42018-02-24 15:49:54 +0530549 if (pmi_pnctrl_info->pinctrl) {
550 devm_pinctrl_put(pmi_pnctrl_info->pinctrl);
551 pmi_pnctrl_info->pinctrl = NULL;
552 }
553
Raja Mallike1b2f792018-06-01 13:17:36 +0530554 if (audio_lpass_mclk.lpass_csr_gpio_mux_spkrctl_vaddr)
555 devm_iounmap(&pdev->dev,
556 audio_lpass_mclk.lpass_csr_gpio_mux_spkrctl_vaddr);
Asish Bhattacharya8e2277f2017-07-20 18:31:55 +0530557 return 0;
558}
559
560static const struct of_device_id audio_ref_clk_match[] = {
561 {.compatible = "qcom,audio-ref-clk"},
562 {}
563};
564MODULE_DEVICE_TABLE(of, audio_ref_clk_match);
565
566static struct platform_driver audio_ref_clk_driver = {
567 .driver = {
568 .name = "audio-ref-clk",
569 .owner = THIS_MODULE,
570 .of_match_table = audio_ref_clk_match,
571 },
572 .probe = audio_ref_clk_probe,
573 .remove = audio_ref_clk_remove,
574};
575
576int audio_ref_clk_platform_init(void)
577{
578 return platform_driver_register(&audio_ref_clk_driver);
579}
580
581void audio_ref_clk_platform_exit(void)
582{
583 platform_driver_unregister(&audio_ref_clk_driver);
584}
585
586MODULE_DESCRIPTION("Audio Ref Clock module platform driver");
587MODULE_LICENSE("GPL v2");