Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Aditya Bavanari | f8be8bd | 2019-10-01 00:54:57 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <linux/regmap.h> |
Laxminath Kasam | 89438f3 | 2018-06-07 12:44:17 +0530 | [diff] [blame] | 6 | #include "bolero-cdc.h" |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 7 | #include "internal.h" |
| 8 | |
| 9 | static const struct reg_default bolero_defaults[] = { |
| 10 | /* TX Macro */ |
| 11 | { BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 }, |
| 12 | { BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 }, |
| 13 | { BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, |
| 14 | { BOLERO_CDC_TX_TOP_CSR_TOP_CFG0, 0x00}, |
| 15 | { BOLERO_CDC_TX_TOP_CSR_ANC_CFG, 0x00}, |
| 16 | { BOLERO_CDC_TX_TOP_CSR_SWR_CTRL, 0x00}, |
| 17 | { BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x00}, |
| 18 | { BOLERO_CDC_TX_TOP_CSR_DEBUG_BUS, 0x00}, |
| 19 | { BOLERO_CDC_TX_TOP_CSR_DEBUG_EN, 0x00}, |
| 20 | { BOLERO_CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C}, |
| 21 | { BOLERO_CDC_TX_TOP_CSR_I2S_CLK, 0x00}, |
| 22 | { BOLERO_CDC_TX_TOP_CSR_I2S_RESET, 0x00}, |
| 23 | { BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00}, |
| 24 | { BOLERO_CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00}, |
| 25 | { BOLERO_CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00}, |
| 26 | { BOLERO_CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00}, |
| 27 | { BOLERO_CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00}, |
| 28 | { BOLERO_CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00}, |
| 29 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00}, |
| 30 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00}, |
| 31 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00}, |
| 32 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00}, |
| 33 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00}, |
| 34 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00}, |
| 35 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00}, |
| 36 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00}, |
| 37 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00}, |
| 38 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00}, |
| 39 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00}, |
| 40 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00}, |
| 41 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00}, |
| 42 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00}, |
| 43 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00}, |
| 44 | { BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00}, |
| 45 | { BOLERO_CDC_TX_ANC0_CLK_RESET_CTL, 0x00}, |
| 46 | { BOLERO_CDC_TX_ANC0_MODE_1_CTL, 0x00}, |
| 47 | { BOLERO_CDC_TX_ANC0_MODE_2_CTL, 0x00}, |
| 48 | { BOLERO_CDC_TX_ANC0_FF_SHIFT, 0x00}, |
| 49 | { BOLERO_CDC_TX_ANC0_FB_SHIFT, 0x00}, |
| 50 | { BOLERO_CDC_TX_ANC0_LPF_FF_A_CTL, 0x00}, |
| 51 | { BOLERO_CDC_TX_ANC0_LPF_FF_B_CTL, 0x00}, |
| 52 | { BOLERO_CDC_TX_ANC0_LPF_FB_CTL, 0x00}, |
| 53 | { BOLERO_CDC_TX_ANC0_SMLPF_CTL, 0x00}, |
| 54 | { BOLERO_CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00}, |
| 55 | { BOLERO_CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00}, |
| 56 | { BOLERO_CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00}, |
| 57 | { BOLERO_CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00}, |
| 58 | { BOLERO_CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00}, |
| 59 | { BOLERO_CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00}, |
| 60 | { BOLERO_CDC_TX_ANC0_FB_GAIN_CTL, 0x00}, |
| 61 | { BOLERO_CDC_TX0_TX_PATH_CTL, 0x04}, |
| 62 | { BOLERO_CDC_TX0_TX_PATH_CFG0, 0x10}, |
| 63 | { BOLERO_CDC_TX0_TX_PATH_CFG1, 0x0B}, |
| 64 | { BOLERO_CDC_TX0_TX_VOL_CTL, 0x00}, |
| 65 | { BOLERO_CDC_TX0_TX_PATH_SEC0, 0x00}, |
| 66 | { BOLERO_CDC_TX0_TX_PATH_SEC1, 0x00}, |
| 67 | { BOLERO_CDC_TX0_TX_PATH_SEC2, 0x01}, |
| 68 | { BOLERO_CDC_TX0_TX_PATH_SEC3, 0x3C}, |
| 69 | { BOLERO_CDC_TX0_TX_PATH_SEC4, 0x20}, |
| 70 | { BOLERO_CDC_TX0_TX_PATH_SEC5, 0x00}, |
| 71 | { BOLERO_CDC_TX0_TX_PATH_SEC6, 0x00}, |
| 72 | { BOLERO_CDC_TX0_TX_PATH_SEC7, 0x25}, |
| 73 | { BOLERO_CDC_TX1_TX_PATH_CTL, 0x04}, |
| 74 | { BOLERO_CDC_TX1_TX_PATH_CFG0, 0x10}, |
| 75 | { BOLERO_CDC_TX1_TX_PATH_CFG1, 0x0B}, |
| 76 | { BOLERO_CDC_TX1_TX_VOL_CTL, 0x00}, |
| 77 | { BOLERO_CDC_TX1_TX_PATH_SEC0, 0x00}, |
| 78 | { BOLERO_CDC_TX1_TX_PATH_SEC1, 0x00}, |
| 79 | { BOLERO_CDC_TX1_TX_PATH_SEC2, 0x01}, |
| 80 | { BOLERO_CDC_TX1_TX_PATH_SEC3, 0x3C}, |
| 81 | { BOLERO_CDC_TX1_TX_PATH_SEC4, 0x20}, |
| 82 | { BOLERO_CDC_TX1_TX_PATH_SEC5, 0x00}, |
| 83 | { BOLERO_CDC_TX1_TX_PATH_SEC6, 0x00}, |
| 84 | { BOLERO_CDC_TX2_TX_PATH_CTL, 0x04}, |
| 85 | { BOLERO_CDC_TX2_TX_PATH_CFG0, 0x10}, |
| 86 | { BOLERO_CDC_TX2_TX_PATH_CFG1, 0x0B}, |
| 87 | { BOLERO_CDC_TX2_TX_VOL_CTL, 0x00}, |
| 88 | { BOLERO_CDC_TX2_TX_PATH_SEC0, 0x00}, |
| 89 | { BOLERO_CDC_TX2_TX_PATH_SEC1, 0x00}, |
| 90 | { BOLERO_CDC_TX2_TX_PATH_SEC2, 0x01}, |
| 91 | { BOLERO_CDC_TX2_TX_PATH_SEC3, 0x3C}, |
| 92 | { BOLERO_CDC_TX2_TX_PATH_SEC4, 0x20}, |
| 93 | { BOLERO_CDC_TX2_TX_PATH_SEC5, 0x00}, |
| 94 | { BOLERO_CDC_TX2_TX_PATH_SEC6, 0x00}, |
| 95 | { BOLERO_CDC_TX3_TX_PATH_CTL, 0x04}, |
| 96 | { BOLERO_CDC_TX3_TX_PATH_CFG0, 0x10}, |
| 97 | { BOLERO_CDC_TX3_TX_PATH_CFG1, 0x0B}, |
| 98 | { BOLERO_CDC_TX3_TX_VOL_CTL, 0x00}, |
| 99 | { BOLERO_CDC_TX3_TX_PATH_SEC0, 0x00}, |
| 100 | { BOLERO_CDC_TX3_TX_PATH_SEC1, 0x00}, |
| 101 | { BOLERO_CDC_TX3_TX_PATH_SEC2, 0x01}, |
| 102 | { BOLERO_CDC_TX3_TX_PATH_SEC3, 0x3C}, |
| 103 | { BOLERO_CDC_TX3_TX_PATH_SEC4, 0x20}, |
| 104 | { BOLERO_CDC_TX3_TX_PATH_SEC5, 0x00}, |
| 105 | { BOLERO_CDC_TX3_TX_PATH_SEC6, 0x00}, |
| 106 | { BOLERO_CDC_TX4_TX_PATH_CTL, 0x04}, |
| 107 | { BOLERO_CDC_TX4_TX_PATH_CFG0, 0x10}, |
| 108 | { BOLERO_CDC_TX4_TX_PATH_CFG1, 0x0B}, |
| 109 | { BOLERO_CDC_TX4_TX_VOL_CTL, 0x00}, |
| 110 | { BOLERO_CDC_TX4_TX_PATH_SEC0, 0x00}, |
| 111 | { BOLERO_CDC_TX4_TX_PATH_SEC1, 0x00}, |
| 112 | { BOLERO_CDC_TX4_TX_PATH_SEC2, 0x01}, |
| 113 | { BOLERO_CDC_TX4_TX_PATH_SEC3, 0x3C}, |
| 114 | { BOLERO_CDC_TX4_TX_PATH_SEC4, 0x20}, |
| 115 | { BOLERO_CDC_TX4_TX_PATH_SEC5, 0x00}, |
| 116 | { BOLERO_CDC_TX4_TX_PATH_SEC6, 0x00}, |
| 117 | { BOLERO_CDC_TX5_TX_PATH_CTL, 0x04}, |
| 118 | { BOLERO_CDC_TX5_TX_PATH_CFG0, 0x10}, |
| 119 | { BOLERO_CDC_TX5_TX_PATH_CFG1, 0x0B}, |
| 120 | { BOLERO_CDC_TX5_TX_VOL_CTL, 0x00}, |
| 121 | { BOLERO_CDC_TX5_TX_PATH_SEC0, 0x00}, |
| 122 | { BOLERO_CDC_TX5_TX_PATH_SEC1, 0x00}, |
| 123 | { BOLERO_CDC_TX5_TX_PATH_SEC2, 0x01}, |
| 124 | { BOLERO_CDC_TX5_TX_PATH_SEC3, 0x3C}, |
| 125 | { BOLERO_CDC_TX5_TX_PATH_SEC4, 0x20}, |
| 126 | { BOLERO_CDC_TX5_TX_PATH_SEC5, 0x00}, |
| 127 | { BOLERO_CDC_TX5_TX_PATH_SEC6, 0x00}, |
| 128 | { BOLERO_CDC_TX6_TX_PATH_CTL, 0x04}, |
| 129 | { BOLERO_CDC_TX6_TX_PATH_CFG0, 0x10}, |
| 130 | { BOLERO_CDC_TX6_TX_PATH_CFG1, 0x0B}, |
| 131 | { BOLERO_CDC_TX6_TX_VOL_CTL, 0x00}, |
| 132 | { BOLERO_CDC_TX6_TX_PATH_SEC0, 0x00}, |
| 133 | { BOLERO_CDC_TX6_TX_PATH_SEC1, 0x00}, |
| 134 | { BOLERO_CDC_TX6_TX_PATH_SEC2, 0x01}, |
| 135 | { BOLERO_CDC_TX6_TX_PATH_SEC3, 0x3C}, |
| 136 | { BOLERO_CDC_TX6_TX_PATH_SEC4, 0x20}, |
| 137 | { BOLERO_CDC_TX6_TX_PATH_SEC5, 0x00}, |
| 138 | { BOLERO_CDC_TX6_TX_PATH_SEC6, 0x00}, |
| 139 | { BOLERO_CDC_TX7_TX_PATH_CTL, 0x04}, |
| 140 | { BOLERO_CDC_TX7_TX_PATH_CFG0, 0x10}, |
| 141 | { BOLERO_CDC_TX7_TX_PATH_CFG1, 0x0B}, |
| 142 | { BOLERO_CDC_TX7_TX_VOL_CTL, 0x00}, |
| 143 | { BOLERO_CDC_TX7_TX_PATH_SEC0, 0x00}, |
| 144 | { BOLERO_CDC_TX7_TX_PATH_SEC1, 0x00}, |
| 145 | { BOLERO_CDC_TX7_TX_PATH_SEC2, 0x01}, |
| 146 | { BOLERO_CDC_TX7_TX_PATH_SEC3, 0x3C}, |
| 147 | { BOLERO_CDC_TX7_TX_PATH_SEC4, 0x20}, |
| 148 | { BOLERO_CDC_TX7_TX_PATH_SEC5, 0x00}, |
| 149 | { BOLERO_CDC_TX7_TX_PATH_SEC6, 0x00}, |
| 150 | |
| 151 | /* RX Macro */ |
| 152 | { BOLERO_CDC_RX_TOP_TOP_CFG0, 0x00}, |
| 153 | { BOLERO_CDC_RX_TOP_SWR_CTRL, 0x00}, |
| 154 | { BOLERO_CDC_RX_TOP_DEBUG, 0x00}, |
| 155 | { BOLERO_CDC_RX_TOP_DEBUG_BUS, 0x00}, |
| 156 | { BOLERO_CDC_RX_TOP_DEBUG_EN0, 0x00}, |
| 157 | { BOLERO_CDC_RX_TOP_DEBUG_EN1, 0x00}, |
| 158 | { BOLERO_CDC_RX_TOP_DEBUG_EN2, 0x00}, |
| 159 | { BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00}, |
| 160 | { BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00}, |
| 161 | { BOLERO_CDC_RX_TOP_HPHL_COMP_LUT, 0x00}, |
| 162 | { BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00}, |
| 163 | { BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00}, |
| 164 | { BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00}, |
| 165 | { BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00}, |
| 166 | { BOLERO_CDC_RX_TOP_HPHR_COMP_LUT, 0x00}, |
| 167 | { BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00}, |
| 168 | { BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00}, |
| 169 | { BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11}, |
| 170 | { BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20}, |
| 171 | { BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00}, |
| 172 | { BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00}, |
| 173 | { BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11}, |
| 174 | { BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20}, |
| 175 | { BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00}, |
| 176 | { BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00}, |
| 177 | { BOLERO_CDC_RX_TOP_RX_I2S_CTL, 0x0C}, |
| 178 | { BOLERO_CDC_RX_TOP_TX_I2S2_CTL, 0x0C}, |
| 179 | { BOLERO_CDC_RX_TOP_I2S_CLK, 0x0C}, |
| 180 | { BOLERO_CDC_RX_TOP_I2S_RESET, 0x00}, |
| 181 | { BOLERO_CDC_RX_TOP_I2S_MUX, 0x00}, |
| 182 | { BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, |
| 183 | { BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, |
| 184 | { BOLERO_CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00}, |
| 185 | { BOLERO_CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00}, |
| 186 | { BOLERO_CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08}, |
| 187 | { BOLERO_CDC_RX_SOFTCLIP_CRC, 0x00}, |
| 188 | { BOLERO_CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38}, |
| 189 | { BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00}, |
| 190 | { BOLERO_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00}, |
| 191 | { BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00}, |
| 192 | { BOLERO_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00}, |
| 193 | { BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00}, |
| 194 | { BOLERO_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00}, |
| 195 | { BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00}, |
| 196 | { BOLERO_CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00}, |
| 197 | { BOLERO_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00}, |
| 198 | { BOLERO_CDC_RX_CLSH_CRC, 0x00}, |
| 199 | { BOLERO_CDC_RX_CLSH_DLY_CTRL, 0x03}, |
| 200 | { BOLERO_CDC_RX_CLSH_DECAY_CTRL, 0x02}, |
| 201 | { BOLERO_CDC_RX_CLSH_HPH_V_PA, 0x1C}, |
| 202 | { BOLERO_CDC_RX_CLSH_EAR_V_PA, 0x39}, |
| 203 | { BOLERO_CDC_RX_CLSH_HPH_V_HD, 0x0C}, |
| 204 | { BOLERO_CDC_RX_CLSH_EAR_V_HD, 0x0C}, |
| 205 | { BOLERO_CDC_RX_CLSH_K1_MSB, 0x01}, |
| 206 | { BOLERO_CDC_RX_CLSH_K1_LSB, 0x00}, |
| 207 | { BOLERO_CDC_RX_CLSH_K2_MSB, 0x00}, |
| 208 | { BOLERO_CDC_RX_CLSH_K2_LSB, 0x80}, |
| 209 | { BOLERO_CDC_RX_CLSH_IDLE_CTRL, 0x00}, |
| 210 | { BOLERO_CDC_RX_CLSH_IDLE_HPH, 0x00}, |
| 211 | { BOLERO_CDC_RX_CLSH_IDLE_EAR, 0x00}, |
| 212 | { BOLERO_CDC_RX_CLSH_TEST0, 0x07}, |
| 213 | { BOLERO_CDC_RX_CLSH_TEST1, 0x00}, |
| 214 | { BOLERO_CDC_RX_CLSH_OVR_VREF, 0x00}, |
| 215 | { BOLERO_CDC_RX_CLSH_CLSG_CTL, 0x02}, |
| 216 | { BOLERO_CDC_RX_CLSH_CLSG_CFG1, 0x9A}, |
| 217 | { BOLERO_CDC_RX_CLSH_CLSG_CFG2, 0x10}, |
| 218 | { BOLERO_CDC_RX_BCL_VBAT_PATH_CTL, 0x00}, |
| 219 | { BOLERO_CDC_RX_BCL_VBAT_CFG, 0x10}, |
| 220 | { BOLERO_CDC_RX_BCL_VBAT_ADC_CAL1, 0x00}, |
| 221 | { BOLERO_CDC_RX_BCL_VBAT_ADC_CAL2, 0x00}, |
| 222 | { BOLERO_CDC_RX_BCL_VBAT_ADC_CAL3, 0x04}, |
| 223 | { BOLERO_CDC_RX_BCL_VBAT_PK_EST1, 0xE0}, |
| 224 | { BOLERO_CDC_RX_BCL_VBAT_PK_EST2, 0x01}, |
| 225 | { BOLERO_CDC_RX_BCL_VBAT_PK_EST3, 0x40}, |
| 226 | { BOLERO_CDC_RX_BCL_VBAT_RF_PROC1, 0x2A}, |
| 227 | { BOLERO_CDC_RX_BCL_VBAT_RF_PROC1, 0x00}, |
| 228 | { BOLERO_CDC_RX_BCL_VBAT_TAC1, 0x00}, |
| 229 | { BOLERO_CDC_RX_BCL_VBAT_TAC2, 0x18}, |
| 230 | { BOLERO_CDC_RX_BCL_VBAT_TAC3, 0x18}, |
| 231 | { BOLERO_CDC_RX_BCL_VBAT_TAC4, 0x03}, |
| 232 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01}, |
| 233 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00}, |
| 234 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00}, |
| 235 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64}, |
| 236 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01}, |
| 237 | { BOLERO_CDC_RX_BCL_VBAT_DEBUG1, 0x00}, |
| 238 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00}, |
| 239 | { BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00}, |
| 240 | { BOLERO_CDC_RX_BCL_VBAT_BAN, 0x0C}, |
| 241 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00}, |
| 242 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77}, |
| 243 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01}, |
| 244 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00}, |
| 245 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B}, |
| 246 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00}, |
| 247 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01}, |
| 248 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00}, |
| 249 | { BOLERO_CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00}, |
| 250 | { BOLERO_CDC_RX_BCL_VBAT_ATTN1, 0x04}, |
| 251 | { BOLERO_CDC_RX_BCL_VBAT_ATTN2, 0x08}, |
| 252 | { BOLERO_CDC_RX_BCL_VBAT_ATTN3, 0x0C}, |
| 253 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0}, |
| 254 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00}, |
| 255 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00}, |
| 256 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00}, |
| 257 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00}, |
| 258 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00}, |
| 259 | { BOLERO_CDC_RX_BCL_VBAT_DECODE_ST, 0x00}, |
| 260 | { BOLERO_CDC_RX_INTR_CTRL_CFG, 0x00}, |
| 261 | { BOLERO_CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00}, |
| 262 | { BOLERO_CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF}, |
| 263 | { BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00}, |
| 264 | { BOLERO_CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00}, |
| 265 | { BOLERO_CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF}, |
| 266 | { BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00}, |
| 267 | { BOLERO_CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00}, |
| 268 | { BOLERO_CDC_RX_INTR_CTRL_LEVEL0, 0x00}, |
| 269 | { BOLERO_CDC_RX_INTR_CTRL_BYPASS0, 0x00}, |
| 270 | { BOLERO_CDC_RX_INTR_CTRL_SET0, 0x00}, |
| 271 | { BOLERO_CDC_RX_RX0_RX_PATH_CTL, 0x04}, |
| 272 | { BOLERO_CDC_RX_RX0_RX_PATH_CFG0, 0x00}, |
| 273 | { BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0x64}, |
| 274 | { BOLERO_CDC_RX_RX0_RX_PATH_CFG2, 0x8F}, |
| 275 | { BOLERO_CDC_RX_RX0_RX_PATH_CFG3, 0x00}, |
| 276 | { BOLERO_CDC_RX_RX0_RX_VOL_CTL, 0x00}, |
| 277 | { BOLERO_CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04}, |
| 278 | { BOLERO_CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E}, |
| 279 | { BOLERO_CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00}, |
| 280 | { BOLERO_CDC_RX_RX0_RX_PATH_SEC1, 0x08}, |
| 281 | { BOLERO_CDC_RX_RX0_RX_PATH_SEC2, 0x00}, |
| 282 | { BOLERO_CDC_RX_RX0_RX_PATH_SEC3, 0x00}, |
| 283 | { BOLERO_CDC_RX_RX0_RX_PATH_SEC4, 0x00}, |
| 284 | { BOLERO_CDC_RX_RX0_RX_PATH_SEC7, 0x00}, |
| 285 | { BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08}, |
| 286 | { BOLERO_CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00}, |
| 287 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08}, |
| 288 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00}, |
| 289 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00}, |
| 290 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00}, |
| 291 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55}, |
| 292 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55}, |
| 293 | { BOLERO_CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55}, |
| 294 | { BOLERO_CDC_RX_RX1_RX_PATH_CTL, 0x04}, |
| 295 | { BOLERO_CDC_RX_RX1_RX_PATH_CFG0, 0x00}, |
| 296 | { BOLERO_CDC_RX_RX1_RX_PATH_CFG1, 0x64}, |
| 297 | { BOLERO_CDC_RX_RX1_RX_PATH_CFG2, 0x8F}, |
| 298 | { BOLERO_CDC_RX_RX1_RX_PATH_CFG3, 0x00}, |
| 299 | { BOLERO_CDC_RX_RX1_RX_VOL_CTL, 0x00}, |
| 300 | { BOLERO_CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04}, |
| 301 | { BOLERO_CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E}, |
| 302 | { BOLERO_CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00}, |
| 303 | { BOLERO_CDC_RX_RX1_RX_PATH_SEC1, 0x08}, |
| 304 | { BOLERO_CDC_RX_RX1_RX_PATH_SEC2, 0x00}, |
| 305 | { BOLERO_CDC_RX_RX1_RX_PATH_SEC3, 0x00}, |
| 306 | { BOLERO_CDC_RX_RX1_RX_PATH_SEC4, 0x00}, |
| 307 | { BOLERO_CDC_RX_RX1_RX_PATH_SEC7, 0x00}, |
| 308 | { BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08}, |
| 309 | { BOLERO_CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00}, |
| 310 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08}, |
| 311 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00}, |
| 312 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00}, |
| 313 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00}, |
| 314 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55}, |
| 315 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55}, |
| 316 | { BOLERO_CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55}, |
| 317 | { BOLERO_CDC_RX_RX2_RX_PATH_CTL, 0x04}, |
| 318 | { BOLERO_CDC_RX_RX2_RX_PATH_CFG0, 0x00}, |
| 319 | { BOLERO_CDC_RX_RX2_RX_PATH_CFG1, 0x64}, |
| 320 | { BOLERO_CDC_RX_RX2_RX_PATH_CFG2, 0x8F}, |
| 321 | { BOLERO_CDC_RX_RX2_RX_PATH_CFG3, 0x00}, |
| 322 | { BOLERO_CDC_RX_RX2_RX_VOL_CTL, 0x00}, |
| 323 | { BOLERO_CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04}, |
| 324 | { BOLERO_CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E}, |
| 325 | { BOLERO_CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00}, |
| 326 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC0, 0x04}, |
| 327 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC1, 0x08}, |
| 328 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC2, 0x00}, |
| 329 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC3, 0x00}, |
| 330 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC4, 0x00}, |
| 331 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC5, 0x00}, |
| 332 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC6, 0x00}, |
| 333 | { BOLERO_CDC_RX_RX2_RX_PATH_SEC7, 0x00}, |
| 334 | { BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08}, |
| 335 | { BOLERO_CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00}, |
| 336 | { BOLERO_CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00}, |
| 337 | { BOLERO_CDC_RX_IDLE_DETECT_PATH_CTL, 0x00}, |
| 338 | { BOLERO_CDC_RX_IDLE_DETECT_CFG0, 0x07}, |
| 339 | { BOLERO_CDC_RX_IDLE_DETECT_CFG1, 0x3C}, |
| 340 | { BOLERO_CDC_RX_IDLE_DETECT_CFG2, 0x00}, |
| 341 | { BOLERO_CDC_RX_IDLE_DETECT_CFG3, 0x00}, |
| 342 | { BOLERO_CDC_RX_COMPANDER0_CTL0, 0x60}, |
| 343 | { BOLERO_CDC_RX_COMPANDER0_CTL1, 0xDB}, |
| 344 | { BOLERO_CDC_RX_COMPANDER0_CTL2, 0xFF}, |
| 345 | { BOLERO_CDC_RX_COMPANDER0_CTL3, 0x35}, |
| 346 | { BOLERO_CDC_RX_COMPANDER0_CTL4, 0xFF}, |
| 347 | { BOLERO_CDC_RX_COMPANDER0_CTL5, 0x00}, |
| 348 | { BOLERO_CDC_RX_COMPANDER0_CTL6, 0x01}, |
| 349 | { BOLERO_CDC_RX_COMPANDER0_CTL7, 0x28}, |
| 350 | { BOLERO_CDC_RX_COMPANDER1_CTL0, 0x60}, |
| 351 | { BOLERO_CDC_RX_COMPANDER1_CTL1, 0xDB}, |
| 352 | { BOLERO_CDC_RX_COMPANDER1_CTL2, 0xFF}, |
| 353 | { BOLERO_CDC_RX_COMPANDER1_CTL3, 0x35}, |
| 354 | { BOLERO_CDC_RX_COMPANDER1_CTL4, 0xFF}, |
| 355 | { BOLERO_CDC_RX_COMPANDER1_CTL5, 0x00}, |
| 356 | { BOLERO_CDC_RX_COMPANDER1_CTL6, 0x01}, |
| 357 | { BOLERO_CDC_RX_COMPANDER1_CTL7, 0x28}, |
| 358 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00}, |
| 359 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00}, |
| 360 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00}, |
| 361 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00}, |
| 362 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00}, |
| 363 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00}, |
| 364 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00}, |
| 365 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00}, |
| 366 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00}, |
| 367 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40}, |
| 368 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00}, |
| 369 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00}, |
| 370 | { BOLERO_CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00}, |
| 371 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00}, |
| 372 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00}, |
| 373 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00}, |
| 374 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00}, |
| 375 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00}, |
| 376 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00}, |
| 377 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00}, |
| 378 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00}, |
| 379 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00}, |
| 380 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40}, |
| 381 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00}, |
| 382 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00}, |
| 383 | { BOLERO_CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00}, |
| 384 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00}, |
| 385 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00}, |
| 386 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00}, |
| 387 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00}, |
| 388 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00}, |
| 389 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00}, |
| 390 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00}, |
| 391 | { BOLERO_CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00}, |
| 392 | { BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04}, |
| 393 | { BOLERO_CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00}, |
| 394 | { BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04}, |
| 395 | { BOLERO_CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00}, |
| 396 | { BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, |
| 397 | { BOLERO_CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01}, |
| 398 | { BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, |
| 399 | { BOLERO_CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01}, |
| 400 | { BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00}, |
| 401 | { BOLERO_CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01}, |
| 402 | { BOLERO_CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00}, |
| 403 | { BOLERO_CDC_RX_EC_ASRC0_CTL0, 0x00}, |
| 404 | { BOLERO_CDC_RX_EC_ASRC0_CTL1, 0x00}, |
| 405 | { BOLERO_CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8}, |
| 406 | { BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, |
| 407 | { BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, |
| 408 | { BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, |
| 409 | { BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, |
| 410 | { BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00}, |
| 411 | { BOLERO_CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00}, |
| 412 | { BOLERO_CDC_RX_EC_ASRC1_CTL0, 0x00}, |
| 413 | { BOLERO_CDC_RX_EC_ASRC1_CTL1, 0x00}, |
| 414 | { BOLERO_CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8}, |
| 415 | { BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, |
| 416 | { BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, |
| 417 | { BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, |
| 418 | { BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, |
| 419 | { BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00}, |
| 420 | { BOLERO_CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00}, |
| 421 | { BOLERO_CDC_RX_EC_ASRC2_CTL0, 0x00}, |
| 422 | { BOLERO_CDC_RX_EC_ASRC2_CTL1, 0x00}, |
| 423 | { BOLERO_CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8}, |
| 424 | { BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00}, |
| 425 | { BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00}, |
| 426 | { BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00}, |
| 427 | { BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00}, |
| 428 | { BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00}, |
| 429 | { BOLERO_CDC_RX_DSD0_PATH_CTL, 0x00}, |
| 430 | { BOLERO_CDC_RX_DSD0_CFG0, 0x00}, |
| 431 | { BOLERO_CDC_RX_DSD0_CFG1, 0x62}, |
| 432 | { BOLERO_CDC_RX_DSD0_CFG2, 0x96}, |
| 433 | { BOLERO_CDC_RX_DSD1_PATH_CTL, 0x00}, |
| 434 | { BOLERO_CDC_RX_DSD1_CFG0, 0x00}, |
| 435 | { BOLERO_CDC_RX_DSD1_CFG1, 0x62}, |
| 436 | { BOLERO_CDC_RX_DSD1_CFG2, 0x96}, |
| 437 | |
| 438 | /* WSA Macro */ |
| 439 | { BOLERO_CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, |
| 440 | { BOLERO_CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, |
| 441 | { BOLERO_CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, |
| 442 | { BOLERO_CDC_WSA_TOP_TOP_CFG0, 0x00}, |
| 443 | { BOLERO_CDC_WSA_TOP_TOP_CFG1, 0x00}, |
| 444 | { BOLERO_CDC_WSA_TOP_FREQ_MCLK, 0x00}, |
| 445 | { BOLERO_CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, |
| 446 | { BOLERO_CDC_WSA_TOP_DEBUG_EN0, 0x00}, |
| 447 | { BOLERO_CDC_WSA_TOP_DEBUG_EN1, 0x00}, |
| 448 | { BOLERO_CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, |
| 449 | { BOLERO_CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, |
| 450 | { BOLERO_CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, |
| 451 | { BOLERO_CDC_WSA_TOP_I2S_CLK, 0x02}, |
| 452 | { BOLERO_CDC_WSA_TOP_I2S_RESET, 0x00}, |
| 453 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, |
| 454 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, |
| 455 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, |
| 456 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, |
| 457 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, |
| 458 | { BOLERO_CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, |
| 459 | { BOLERO_CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, |
| 460 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_PATH_CTL, 0x00}, |
| 461 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_CFG, 0x10}, |
| 462 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL1, 0x00}, |
| 463 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL2, 0x00}, |
| 464 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_ADC_CAL3, 0x04}, |
| 465 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST1, 0xE0}, |
| 466 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST2, 0x01}, |
| 467 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_PK_EST3, 0x40}, |
| 468 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC1, 0x2A}, |
| 469 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_RF_PROC2, 0x00}, |
| 470 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC1, 0x00}, |
| 471 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC2, 0x18}, |
| 472 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC3, 0x18}, |
| 473 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_TAC4, 0x03}, |
| 474 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD1, 0x01}, |
| 475 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD2, 0x00}, |
| 476 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD3, 0x00}, |
| 477 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD4, 0x64}, |
| 478 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD5, 0x01}, |
| 479 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DEBUG1, 0x00}, |
| 480 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_UPD_MON, 0x00}, |
| 481 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL, 0x00}, |
| 482 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BAN, 0x0C}, |
| 483 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD1, 0x00}, |
| 484 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD2, 0x77}, |
| 485 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD3, 0x01}, |
| 486 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD4, 0x00}, |
| 487 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD5, 0x4B}, |
| 488 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD6, 0x00}, |
| 489 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD7, 0x01}, |
| 490 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD8, 0x00}, |
| 491 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_GAIN_UPD9, 0x00}, |
| 492 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN1, 0x04}, |
| 493 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN2, 0x08}, |
| 494 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_BCL_ATTN3, 0x0C}, |
| 495 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL1, 0xE0}, |
| 496 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CTL2, 0x00}, |
| 497 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG1, 0x00}, |
| 498 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG2, 0x00}, |
| 499 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG3, 0x00}, |
| 500 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_CFG4, 0x00}, |
| 501 | { BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST, 0x00}, |
| 502 | { BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, |
| 503 | { BOLERO_CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, |
| 504 | { BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, |
| 505 | { BOLERO_CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, |
| 506 | { BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, |
| 507 | { BOLERO_CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, |
| 508 | { BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, |
| 509 | { BOLERO_CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, |
| 510 | { BOLERO_CDC_WSA_INTR_CTRL_CFG, 0x00}, |
| 511 | { BOLERO_CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, |
| 512 | { BOLERO_CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, |
| 513 | { BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, |
| 514 | { BOLERO_CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, |
| 515 | { BOLERO_CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, |
| 516 | { BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, |
| 517 | { BOLERO_CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, |
| 518 | { BOLERO_CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, |
| 519 | { BOLERO_CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, |
| 520 | { BOLERO_CDC_WSA_INTR_CTRL_SET0, 0x00}, |
| 521 | { BOLERO_CDC_WSA_RX0_RX_PATH_CTL, 0x04}, |
| 522 | { BOLERO_CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, |
| 523 | { BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, |
| 524 | { BOLERO_CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, |
| 525 | { BOLERO_CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, |
| 526 | { BOLERO_CDC_WSA_RX0_RX_VOL_CTL, 0x00}, |
| 527 | { BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, |
| 528 | { BOLERO_CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, |
| 529 | { BOLERO_CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, |
| 530 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, |
| 531 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, |
| 532 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, |
| 533 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, |
| 534 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, |
| 535 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, |
| 536 | { BOLERO_CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, |
| 537 | { BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, |
| 538 | { BOLERO_CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, |
| 539 | { BOLERO_CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, |
| 540 | { BOLERO_CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, |
| 541 | { BOLERO_CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, |
| 542 | { BOLERO_CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, |
| 543 | { BOLERO_CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, |
| 544 | { BOLERO_CDC_WSA_RX1_RX_VOL_CTL, 0x00}, |
| 545 | { BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, |
| 546 | { BOLERO_CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, |
| 547 | { BOLERO_CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, |
| 548 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, |
| 549 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, |
| 550 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, |
| 551 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, |
| 552 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, |
| 553 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, |
| 554 | { BOLERO_CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, |
| 555 | { BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, |
| 556 | { BOLERO_CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, |
| 557 | { BOLERO_CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, |
| 558 | { BOLERO_CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, |
| 559 | { BOLERO_CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, |
| 560 | { BOLERO_CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, |
| 561 | { BOLERO_CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, |
| 562 | { BOLERO_CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, |
| 563 | { BOLERO_CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, |
| 564 | { BOLERO_CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, |
| 565 | { BOLERO_CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, |
| 566 | { BOLERO_CDC_WSA_COMPANDER0_CTL0, 0x60}, |
| 567 | { BOLERO_CDC_WSA_COMPANDER0_CTL1, 0xDB}, |
| 568 | { BOLERO_CDC_WSA_COMPANDER0_CTL2, 0xFF}, |
| 569 | { BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x35}, |
| 570 | { BOLERO_CDC_WSA_COMPANDER0_CTL4, 0xFF}, |
| 571 | { BOLERO_CDC_WSA_COMPANDER0_CTL5, 0x00}, |
| 572 | { BOLERO_CDC_WSA_COMPANDER0_CTL6, 0x01}, |
| 573 | { BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x28}, |
| 574 | { BOLERO_CDC_WSA_COMPANDER1_CTL0, 0x60}, |
| 575 | { BOLERO_CDC_WSA_COMPANDER1_CTL1, 0xDB}, |
| 576 | { BOLERO_CDC_WSA_COMPANDER1_CTL2, 0xFF}, |
| 577 | { BOLERO_CDC_WSA_COMPANDER1_CTL3, 0x35}, |
| 578 | { BOLERO_CDC_WSA_COMPANDER1_CTL4, 0xFF}, |
| 579 | { BOLERO_CDC_WSA_COMPANDER1_CTL5, 0x00}, |
| 580 | { BOLERO_CDC_WSA_COMPANDER1_CTL6, 0x01}, |
| 581 | { BOLERO_CDC_WSA_COMPANDER1_CTL7, 0x28}, |
| 582 | { BOLERO_CDC_WSA_SOFTCLIP0_CRC, 0x00}, |
| 583 | { BOLERO_CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, |
| 584 | { BOLERO_CDC_WSA_SOFTCLIP1_CRC, 0x00}, |
| 585 | { BOLERO_CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, |
| 586 | { BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, |
| 587 | { BOLERO_CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, |
| 588 | { BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, |
| 589 | { BOLERO_CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, |
| 590 | { BOLERO_CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, |
| 591 | { BOLERO_CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, |
| 592 | { BOLERO_CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, |
| 593 | { BOLERO_CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, |
| 594 | { BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, |
| 595 | { BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, |
| 596 | { BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, |
| 597 | { BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, |
| 598 | { BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, |
| 599 | { BOLERO_CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, |
| 600 | { BOLERO_CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, |
| 601 | { BOLERO_CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, |
| 602 | { BOLERO_CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, |
| 603 | { BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, |
| 604 | { BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, |
| 605 | { BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, |
| 606 | { BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, |
| 607 | { BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, |
| 608 | |
| 609 | /* VA macro */ |
| 610 | { BOLERO_CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, |
| 611 | { BOLERO_CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 612 | { BOLERO_CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 613 | { BOLERO_CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, |
| 614 | { BOLERO_CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, |
| 615 | { BOLERO_CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, |
| 616 | { BOLERO_CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, |
| 617 | { BOLERO_CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, |
| 618 | { BOLERO_CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, |
| 619 | { BOLERO_CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, |
| 620 | { BOLERO_CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, |
| 621 | { BOLERO_CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, |
| 622 | { BOLERO_CDC_VA_TOP_CSR_I2S_CLK, 0x00}, |
| 623 | { BOLERO_CDC_VA_TOP_CSR_I2S_RESET, 0x00}, |
| 624 | { BOLERO_CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, |
| 625 | { BOLERO_CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, |
| 626 | { BOLERO_CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, |
| 627 | { BOLERO_CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, |
Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame^] | 628 | { BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, |
| 629 | { BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, |
| 630 | { BOLERO_CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, |
| 631 | { BOLERO_CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 632 | |
| 633 | /* VA core */ |
| 634 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, |
| 635 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, |
| 636 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, |
| 637 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, |
| 638 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, |
| 639 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, |
| 640 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, |
| 641 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, |
| 642 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG0, 0x00}, |
| 643 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX4_CFG1, 0x00}, |
| 644 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG0, 0x00}, |
| 645 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX5_CFG1, 0x00}, |
| 646 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG0, 0x00}, |
| 647 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX6_CFG1, 0x00}, |
| 648 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG0, 0x00}, |
| 649 | { BOLERO_CDC_VA_INP_MUX_ADC_MUX7_CFG1, 0x00}, |
| 650 | { BOLERO_CDC_VA_TX0_TX_PATH_CTL, 0x04}, |
| 651 | { BOLERO_CDC_VA_TX0_TX_PATH_CFG0, 0x10}, |
| 652 | { BOLERO_CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, |
| 653 | { BOLERO_CDC_VA_TX0_TX_VOL_CTL, 0x00}, |
| 654 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC0, 0x00}, |
| 655 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC1, 0x00}, |
| 656 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC2, 0x01}, |
| 657 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, |
| 658 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC4, 0x20}, |
| 659 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC5, 0x00}, |
| 660 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC6, 0x00}, |
| 661 | { BOLERO_CDC_VA_TX0_TX_PATH_SEC7, 0x25}, |
| 662 | { BOLERO_CDC_VA_TX1_TX_PATH_CTL, 0x04}, |
| 663 | { BOLERO_CDC_VA_TX1_TX_PATH_CFG0, 0x10}, |
| 664 | { BOLERO_CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, |
| 665 | { BOLERO_CDC_VA_TX1_TX_VOL_CTL, 0x00}, |
| 666 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC0, 0x00}, |
| 667 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC1, 0x00}, |
| 668 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC2, 0x01}, |
| 669 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, |
| 670 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC4, 0x20}, |
| 671 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC5, 0x00}, |
| 672 | { BOLERO_CDC_VA_TX1_TX_PATH_SEC6, 0x00}, |
| 673 | { BOLERO_CDC_VA_TX2_TX_PATH_CTL, 0x04}, |
| 674 | { BOLERO_CDC_VA_TX2_TX_PATH_CFG0, 0x10}, |
| 675 | { BOLERO_CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, |
| 676 | { BOLERO_CDC_VA_TX2_TX_VOL_CTL, 0x00}, |
| 677 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC0, 0x00}, |
| 678 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC1, 0x00}, |
| 679 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC2, 0x01}, |
| 680 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, |
| 681 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC4, 0x20}, |
| 682 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC5, 0x00}, |
| 683 | { BOLERO_CDC_VA_TX2_TX_PATH_SEC6, 0x00}, |
| 684 | { BOLERO_CDC_VA_TX3_TX_PATH_CTL, 0x04}, |
| 685 | { BOLERO_CDC_VA_TX3_TX_PATH_CFG0, 0x10}, |
| 686 | { BOLERO_CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, |
| 687 | { BOLERO_CDC_VA_TX3_TX_VOL_CTL, 0x00}, |
| 688 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC0, 0x00}, |
| 689 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC1, 0x00}, |
| 690 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC2, 0x01}, |
| 691 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, |
| 692 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC4, 0x20}, |
| 693 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC5, 0x00}, |
| 694 | { BOLERO_CDC_VA_TX3_TX_PATH_SEC6, 0x00}, |
| 695 | { BOLERO_CDC_VA_TX4_TX_PATH_CTL, 0x04}, |
| 696 | { BOLERO_CDC_VA_TX4_TX_PATH_CFG0, 0x10}, |
| 697 | { BOLERO_CDC_VA_TX4_TX_PATH_CFG1, 0x0B}, |
| 698 | { BOLERO_CDC_VA_TX4_TX_VOL_CTL, 0x00}, |
| 699 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC0, 0x00}, |
| 700 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC1, 0x00}, |
| 701 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC2, 0x01}, |
| 702 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC3, 0x3C}, |
| 703 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC4, 0x20}, |
| 704 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC5, 0x00}, |
| 705 | { BOLERO_CDC_VA_TX4_TX_PATH_SEC6, 0x00}, |
| 706 | { BOLERO_CDC_VA_TX5_TX_PATH_CTL, 0x04}, |
| 707 | { BOLERO_CDC_VA_TX5_TX_PATH_CFG0, 0x10}, |
| 708 | { BOLERO_CDC_VA_TX5_TX_PATH_CFG1, 0x0B}, |
| 709 | { BOLERO_CDC_VA_TX5_TX_VOL_CTL, 0x00}, |
| 710 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC0, 0x00}, |
| 711 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC1, 0x00}, |
| 712 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC2, 0x01}, |
| 713 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC3, 0x3C}, |
| 714 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC4, 0x20}, |
| 715 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC5, 0x00}, |
| 716 | { BOLERO_CDC_VA_TX5_TX_PATH_SEC6, 0x00}, |
| 717 | { BOLERO_CDC_VA_TX6_TX_PATH_CTL, 0x04}, |
| 718 | { BOLERO_CDC_VA_TX6_TX_PATH_CFG0, 0x10}, |
| 719 | { BOLERO_CDC_VA_TX6_TX_PATH_CFG1, 0x0B}, |
| 720 | { BOLERO_CDC_VA_TX6_TX_VOL_CTL, 0x00}, |
| 721 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC0, 0x00}, |
| 722 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC1, 0x00}, |
| 723 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC2, 0x01}, |
| 724 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC3, 0x3C}, |
| 725 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC4, 0x20}, |
| 726 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC5, 0x00}, |
| 727 | { BOLERO_CDC_VA_TX6_TX_PATH_SEC6, 0x00}, |
| 728 | { BOLERO_CDC_VA_TX7_TX_PATH_CTL, 0x04}, |
| 729 | { BOLERO_CDC_VA_TX7_TX_PATH_CFG0, 0x10}, |
| 730 | { BOLERO_CDC_VA_TX7_TX_PATH_CFG1, 0x0B}, |
| 731 | { BOLERO_CDC_VA_TX7_TX_VOL_CTL, 0x00}, |
| 732 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC0, 0x00}, |
| 733 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC1, 0x00}, |
| 734 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC2, 0x01}, |
| 735 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC3, 0x3C}, |
| 736 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC4, 0x20}, |
| 737 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC5, 0x00}, |
| 738 | { BOLERO_CDC_VA_TX7_TX_PATH_SEC6, 0x00}, |
| 739 | }; |
| 740 | |
| 741 | static bool bolero_is_readable_register(struct device *dev, |
| 742 | unsigned int reg) |
| 743 | { |
| 744 | struct bolero_priv *priv = dev_get_drvdata(dev); |
| 745 | u16 reg_offset; |
| 746 | int macro_id; |
| 747 | u8 *reg_tbl = NULL; |
| 748 | |
| 749 | if (!priv) |
| 750 | return false; |
| 751 | |
| 752 | macro_id = bolero_get_macro_id(priv->va_without_decimation, |
| 753 | reg); |
| 754 | if (macro_id < 0 || !priv->macros_supported[macro_id]) |
| 755 | return false; |
| 756 | |
| 757 | reg_tbl = bolero_reg_access[macro_id]; |
Mangesh Kunchamwar | a9c6919 | 2018-07-03 18:00:40 +0530 | [diff] [blame] | 758 | reg_offset = (reg - macro_id_base_offset[macro_id])/4; |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 759 | |
| 760 | if (reg_tbl) |
| 761 | return (reg_tbl[reg_offset] & RD_REG); |
| 762 | |
| 763 | return false; |
| 764 | } |
| 765 | |
| 766 | static bool bolero_is_writeable_register(struct device *dev, |
| 767 | unsigned int reg) |
| 768 | { |
| 769 | struct bolero_priv *priv = dev_get_drvdata(dev); |
| 770 | u16 reg_offset; |
| 771 | int macro_id; |
| 772 | const u8 *reg_tbl = NULL; |
| 773 | |
| 774 | if (!priv) |
| 775 | return false; |
| 776 | |
| 777 | macro_id = bolero_get_macro_id(priv->va_without_decimation, |
| 778 | reg); |
| 779 | if (macro_id < 0 || !priv->macros_supported[macro_id]) |
| 780 | return false; |
| 781 | |
| 782 | reg_tbl = bolero_reg_access[macro_id]; |
Mangesh Kunchamwar | a9c6919 | 2018-07-03 18:00:40 +0530 | [diff] [blame] | 783 | reg_offset = (reg - macro_id_base_offset[macro_id])/4; |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 784 | |
| 785 | if (reg_tbl) |
| 786 | return (reg_tbl[reg_offset] & WR_REG); |
| 787 | |
| 788 | return false; |
| 789 | } |
| 790 | |
| 791 | static bool bolero_is_volatile_register(struct device *dev, |
| 792 | unsigned int reg) |
| 793 | { |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 794 | /* Update volatile list for rx/tx macros */ |
| 795 | switch (reg) { |
| 796 | case BOLERO_CDC_VA_TOP_CSR_CORE_ID_0: |
| 797 | case BOLERO_CDC_VA_TOP_CSR_CORE_ID_1: |
| 798 | case BOLERO_CDC_VA_TOP_CSR_CORE_ID_2: |
| 799 | case BOLERO_CDC_VA_TOP_CSR_CORE_ID_3: |
| 800 | case BOLERO_CDC_WSA_VBAT_BCL_VBAT_GAIN_MON_VAL: |
| 801 | case BOLERO_CDC_WSA_VBAT_BCL_VBAT_DECODE_ST: |
| 802 | case BOLERO_CDC_WSA_INTR_CTRL_PIN1_STATUS0: |
| 803 | case BOLERO_CDC_WSA_INTR_CTRL_PIN2_STATUS0: |
| 804 | case BOLERO_CDC_WSA_COMPANDER0_CTL6: |
| 805 | case BOLERO_CDC_WSA_COMPANDER1_CTL6: |
| 806 | case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: |
| 807 | case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: |
| 808 | case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: |
| 809 | case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: |
| 810 | case BOLERO_CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: |
| 811 | case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: |
| 812 | case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: |
| 813 | case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: |
| 814 | case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: |
| 815 | case BOLERO_CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 816 | case BOLERO_CDC_RX_TOP_HPHL_COMP_RD_LSB: |
Aditya Bavanari | f8be8bd | 2019-10-01 00:54:57 +0530 | [diff] [blame] | 817 | case BOLERO_CDC_RX_TOP_HPHL_COMP_WR_LSB: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 818 | case BOLERO_CDC_RX_TOP_HPHL_COMP_RD_MSB: |
Aditya Bavanari | f8be8bd | 2019-10-01 00:54:57 +0530 | [diff] [blame] | 819 | case BOLERO_CDC_RX_TOP_HPHL_COMP_WR_MSB: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 820 | case BOLERO_CDC_RX_TOP_HPHR_COMP_RD_LSB: |
Aditya Bavanari | f8be8bd | 2019-10-01 00:54:57 +0530 | [diff] [blame] | 821 | case BOLERO_CDC_RX_TOP_HPHR_COMP_WR_LSB: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 822 | case BOLERO_CDC_RX_TOP_HPHR_COMP_RD_MSB: |
Aditya Bavanari | f8be8bd | 2019-10-01 00:54:57 +0530 | [diff] [blame] | 823 | case BOLERO_CDC_RX_TOP_HPHR_COMP_WR_MSB: |
Laxminath Kasam | a7ecc58 | 2018-06-15 16:55:02 +0530 | [diff] [blame] | 824 | case BOLERO_CDC_RX_TOP_DSD0_DEBUG_CFG2: |
| 825 | case BOLERO_CDC_RX_TOP_DSD1_DEBUG_CFG2: |
| 826 | case BOLERO_CDC_RX_BCL_VBAT_GAIN_MON_VAL: |
| 827 | case BOLERO_CDC_RX_BCL_VBAT_DECODE_ST: |
| 828 | case BOLERO_CDC_RX_INTR_CTRL_PIN1_STATUS0: |
| 829 | case BOLERO_CDC_RX_INTR_CTRL_PIN2_STATUS0: |
| 830 | case BOLERO_CDC_RX_COMPANDER0_CTL6: |
| 831 | case BOLERO_CDC_RX_COMPANDER1_CTL6: |
| 832 | case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB: |
| 833 | case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB: |
| 834 | case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB: |
| 835 | case BOLERO_CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB: |
| 836 | case BOLERO_CDC_RX_EC_ASRC0_STATUS_FIFO: |
| 837 | case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB: |
| 838 | case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB: |
| 839 | case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB: |
| 840 | case BOLERO_CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB: |
| 841 | case BOLERO_CDC_RX_EC_ASRC1_STATUS_FIFO: |
| 842 | case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB: |
| 843 | case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB: |
| 844 | case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB: |
| 845 | case BOLERO_CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB: |
| 846 | case BOLERO_CDC_RX_EC_ASRC2_STATUS_FIFO: |
Laxminath Kasam | 0c85700 | 2018-07-17 23:47:17 +0530 | [diff] [blame] | 847 | return true; |
| 848 | } |
| 849 | return false; |
Laxminath Kasam | e562a36 | 2018-04-12 00:39:08 +0530 | [diff] [blame] | 850 | } |
| 851 | |
| 852 | const struct regmap_config bolero_regmap_config = { |
| 853 | .reg_bits = 16, |
| 854 | .val_bits = 8, |
| 855 | .reg_stride = 4, |
| 856 | .cache_type = REGCACHE_RBTREE, |
| 857 | .reg_defaults = bolero_defaults, |
| 858 | .num_reg_defaults = ARRAY_SIZE(bolero_defaults), |
| 859 | .max_register = BOLERO_CDC_MAX_REGISTER, |
| 860 | .writeable_reg = bolero_is_writeable_register, |
| 861 | .volatile_reg = bolero_is_volatile_register, |
| 862 | .readable_reg = bolero_is_readable_register, |
| 863 | }; |