Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #ifndef _WCD9XXX_COMMON_V2 |
| 15 | |
| 16 | #define _WCD9XXX_COMMON_V2 |
| 17 | |
| 18 | #define CLSH_REQ_ENABLE true |
| 19 | #define CLSH_REQ_DISABLE false |
| 20 | |
| 21 | #define WCD_CLSH_EVENT_PRE_DAC 0x01 |
| 22 | #define WCD_CLSH_EVENT_POST_PA 0x02 |
| 23 | #define MAX_VBAT_MONITOR_WRITES 17 |
| 24 | /* |
| 25 | * Basic states for Class H state machine. |
| 26 | * represented as a bit mask within a u8 data type |
| 27 | * bit 0: EAR mode |
| 28 | * bit 1: HPH Left mode |
| 29 | * bit 2: HPH Right mode |
| 30 | * bit 3: Lineout mode |
| 31 | */ |
| 32 | #define WCD_CLSH_STATE_IDLE 0x00 |
| 33 | #define WCD_CLSH_STATE_EAR (0x01 << 0) |
| 34 | #define WCD_CLSH_STATE_HPHL (0x01 << 1) |
| 35 | #define WCD_CLSH_STATE_HPHR (0x01 << 2) |
| 36 | #define WCD_CLSH_STATE_LO (0x01 << 3) |
| 37 | |
| 38 | /* |
| 39 | * Though number of CLSH states are 4, max state shoulbe be 5 |
| 40 | * because state array index starts from 1. |
| 41 | */ |
| 42 | #define WCD_CLSH_STATE_MAX 5 |
| 43 | #define NUM_CLSH_STATES_V2 (0x01 << WCD_CLSH_STATE_MAX) |
| 44 | |
| 45 | |
| 46 | /* Derived State: Bits 1 and 2 should be set for Headphone stereo */ |
| 47 | #define WCD_CLSH_STATE_HPH_ST (WCD_CLSH_STATE_HPHL | \ |
| 48 | WCD_CLSH_STATE_HPHR) |
| 49 | |
| 50 | #define WCD_CLSH_STATE_HPHL_LO (WCD_CLSH_STATE_HPHL | \ |
| 51 | WCD_CLSH_STATE_LO) |
| 52 | #define WCD_CLSH_STATE_HPHR_LO (WCD_CLSH_STATE_HPHR | \ |
| 53 | WCD_CLSH_STATE_LO) |
| 54 | #define WCD_CLSH_STATE_HPH_ST_LO (WCD_CLSH_STATE_HPH_ST | \ |
| 55 | WCD_CLSH_STATE_LO) |
| 56 | #define WCD_CLSH_STATE_EAR_LO (WCD_CLSH_STATE_EAR | \ |
| 57 | WCD_CLSH_STATE_LO) |
| 58 | #define WCD_CLSH_STATE_HPHL_EAR (WCD_CLSH_STATE_HPHL | \ |
| 59 | WCD_CLSH_STATE_EAR) |
| 60 | #define WCD_CLSH_STATE_HPHR_EAR (WCD_CLSH_STATE_HPHR | \ |
| 61 | WCD_CLSH_STATE_EAR) |
| 62 | #define WCD_CLSH_STATE_HPH_ST_EAR (WCD_CLSH_STATE_HPH_ST | \ |
| 63 | WCD_CLSH_STATE_EAR) |
| 64 | |
| 65 | enum { |
| 66 | CLS_H_NORMAL = 0, /* Class-H Default */ |
| 67 | CLS_H_HIFI, /* Class-H HiFi */ |
| 68 | CLS_H_LP, /* Class-H Low Power */ |
| 69 | CLS_AB, /* Class-AB Low HIFI*/ |
| 70 | CLS_H_LOHIFI, /* LoHIFI */ |
| 71 | CLS_H_ULP, /* Ultra Low power */ |
| 72 | CLS_AB_HIFI, /* Class-AB */ |
| 73 | CLS_NONE, /* None of the above modes */ |
| 74 | }; |
| 75 | |
| 76 | /* Class H data that the codec driver will maintain */ |
| 77 | struct wcd_clsh_cdc_data { |
| 78 | u8 state; |
| 79 | int flyback_users; |
| 80 | int buck_users; |
| 81 | int clsh_users; |
| 82 | int interpolator_modes[WCD_CLSH_STATE_MAX]; |
| 83 | }; |
| 84 | |
| 85 | struct wcd_mad_audio_header { |
| 86 | u32 reserved[3]; |
| 87 | u32 num_reg_cfg; |
| 88 | }; |
| 89 | |
| 90 | struct wcd_mad_microphone_info { |
| 91 | uint8_t input_microphone; |
| 92 | uint8_t cycle_time; |
| 93 | uint8_t settle_time; |
| 94 | uint8_t padding; |
| 95 | } __packed; |
| 96 | |
| 97 | struct wcd_mad_micbias_info { |
| 98 | uint8_t micbias; |
| 99 | uint8_t k_factor; |
| 100 | uint8_t external_bypass_capacitor; |
| 101 | uint8_t internal_biasing; |
| 102 | uint8_t cfilter; |
| 103 | uint8_t padding[3]; |
| 104 | } __packed; |
| 105 | |
| 106 | struct wcd_mad_rms_audio_beacon_info { |
| 107 | uint8_t rms_omit_samples; |
| 108 | uint8_t rms_comp_time; |
| 109 | uint8_t detection_mechanism; |
| 110 | uint8_t rms_diff_threshold; |
| 111 | uint8_t rms_threshold_lsb; |
| 112 | uint8_t rms_threshold_msb; |
| 113 | uint8_t padding[2]; |
| 114 | uint8_t iir_coefficients[36]; |
| 115 | } __packed; |
| 116 | |
| 117 | struct wcd_mad_rms_ultrasound_info { |
| 118 | uint8_t rms_comp_time; |
| 119 | uint8_t detection_mechanism; |
| 120 | uint8_t rms_diff_threshold; |
| 121 | uint8_t rms_threshold_lsb; |
| 122 | uint8_t rms_threshold_msb; |
| 123 | uint8_t padding[3]; |
| 124 | uint8_t iir_coefficients[36]; |
| 125 | } __packed; |
| 126 | |
| 127 | struct wcd_mad_audio_cal { |
| 128 | uint32_t version; |
| 129 | struct wcd_mad_microphone_info microphone_info; |
| 130 | struct wcd_mad_micbias_info micbias_info; |
| 131 | struct wcd_mad_rms_audio_beacon_info audio_info; |
| 132 | struct wcd_mad_rms_audio_beacon_info beacon_info; |
| 133 | struct wcd_mad_rms_ultrasound_info ultrasound_info; |
| 134 | } __packed; |
| 135 | |
| 136 | struct wcd9xxx_anc_header { |
| 137 | u32 reserved[3]; |
| 138 | u32 num_anc_slots; |
| 139 | }; |
| 140 | |
| 141 | struct vbat_monitor_reg { |
| 142 | u32 size; |
| 143 | u32 writes[MAX_VBAT_MONITOR_WRITES]; |
| 144 | } __packed; |
| 145 | |
| 146 | struct wcd_reg_mask_val { |
| 147 | u16 reg; |
| 148 | u8 mask; |
| 149 | u8 val; |
| 150 | }; |
| 151 | |
| 152 | extern void wcd_clsh_fsm(struct snd_soc_codec *codec, |
| 153 | struct wcd_clsh_cdc_data *cdc_clsh_d, |
| 154 | u8 clsh_event, u8 req_state, |
| 155 | int int_mode); |
| 156 | |
| 157 | extern void wcd_clsh_init(struct wcd_clsh_cdc_data *clsh); |
| 158 | extern int wcd_clsh_get_clsh_state(struct wcd_clsh_cdc_data *clsh); |
| 159 | extern void wcd_clsh_imped_config(struct snd_soc_codec *codec, int imped, |
| 160 | bool reset); |
| 161 | |
| 162 | enum { |
| 163 | RESERVED = 0, |
| 164 | AANC_LPF_FF_FB = 1, |
| 165 | AANC_LPF_COEFF_MSB, |
| 166 | AANC_LPF_COEFF_LSB, |
| 167 | HW_MAD_AUDIO_ENABLE, |
| 168 | HW_MAD_ULTR_ENABLE, |
| 169 | HW_MAD_BEACON_ENABLE, |
| 170 | HW_MAD_AUDIO_SLEEP_TIME, |
| 171 | HW_MAD_ULTR_SLEEP_TIME, |
| 172 | HW_MAD_BEACON_SLEEP_TIME, |
| 173 | HW_MAD_TX_AUDIO_SWITCH_OFF, |
| 174 | HW_MAD_TX_ULTR_SWITCH_OFF, |
| 175 | HW_MAD_TX_BEACON_SWITCH_OFF, |
| 176 | MAD_AUDIO_INT_DEST_SELECT_REG, |
| 177 | MAD_ULT_INT_DEST_SELECT_REG, |
| 178 | MAD_BEACON_INT_DEST_SELECT_REG, |
| 179 | MAD_CLIP_INT_DEST_SELECT_REG, |
| 180 | VBAT_INT_DEST_SELECT_REG, |
| 181 | MAD_AUDIO_INT_MASK_REG, |
| 182 | MAD_ULT_INT_MASK_REG, |
| 183 | MAD_BEACON_INT_MASK_REG, |
| 184 | MAD_CLIP_INT_MASK_REG, |
| 185 | VBAT_INT_MASK_REG, |
| 186 | MAD_AUDIO_INT_STATUS_REG, |
| 187 | MAD_ULT_INT_STATUS_REG, |
| 188 | MAD_BEACON_INT_STATUS_REG, |
| 189 | MAD_CLIP_INT_STATUS_REG, |
| 190 | VBAT_INT_STATUS_REG, |
| 191 | MAD_AUDIO_INT_CLEAR_REG, |
| 192 | MAD_ULT_INT_CLEAR_REG, |
| 193 | MAD_BEACON_INT_CLEAR_REG, |
| 194 | MAD_CLIP_INT_CLEAR_REG, |
| 195 | VBAT_INT_CLEAR_REG, |
| 196 | SB_PGD_PORT_TX_WATERMARK_N, |
| 197 | SB_PGD_PORT_TX_ENABLE_N, |
| 198 | SB_PGD_PORT_RX_WATERMARK_N, |
| 199 | SB_PGD_PORT_RX_ENABLE_N, |
| 200 | SB_PGD_TX_PORTn_MULTI_CHNL_0, |
| 201 | SB_PGD_TX_PORTn_MULTI_CHNL_1, |
| 202 | SB_PGD_RX_PORTn_MULTI_CHNL_0, |
| 203 | SB_PGD_RX_PORTn_MULTI_CHNL_1, |
| 204 | AANC_FF_GAIN_ADAPTIVE, |
| 205 | AANC_FFGAIN_ADAPTIVE_EN, |
| 206 | AANC_GAIN_CONTROL, |
| 207 | SPKR_CLIP_PIPE_BANK_SEL, |
| 208 | SPKR_CLIPDET_VAL0, |
| 209 | SPKR_CLIPDET_VAL1, |
| 210 | SPKR_CLIPDET_VAL2, |
| 211 | SPKR_CLIPDET_VAL3, |
| 212 | SPKR_CLIPDET_VAL4, |
| 213 | SPKR_CLIPDET_VAL5, |
| 214 | SPKR_CLIPDET_VAL6, |
| 215 | SPKR_CLIPDET_VAL7, |
| 216 | VBAT_RELEASE_INT_DEST_SELECT_REG, |
| 217 | VBAT_RELEASE_INT_MASK_REG, |
| 218 | VBAT_RELEASE_INT_STATUS_REG, |
| 219 | VBAT_RELEASE_INT_CLEAR_REG, |
| 220 | MAD2_CLIP_INT_DEST_SELECT_REG, |
| 221 | MAD2_CLIP_INT_MASK_REG, |
| 222 | MAD2_CLIP_INT_STATUS_REG, |
| 223 | MAD2_CLIP_INT_CLEAR_REG, |
| 224 | SPKR2_CLIP_PIPE_BANK_SEL, |
| 225 | SPKR2_CLIPDET_VAL0, |
| 226 | SPKR2_CLIPDET_VAL1, |
| 227 | SPKR2_CLIPDET_VAL2, |
| 228 | SPKR2_CLIPDET_VAL3, |
| 229 | SPKR2_CLIPDET_VAL4, |
| 230 | SPKR2_CLIPDET_VAL5, |
| 231 | SPKR2_CLIPDET_VAL6, |
| 232 | SPKR2_CLIPDET_VAL7, |
| 233 | MAX_CFG_REGISTERS, |
| 234 | }; |
| 235 | |
| 236 | #endif |