| Asish Bhattacharya | 8e2277f | 2017-07-20 18:31:55 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef _SWRM_REGISTERS_H |
| 14 | #define _SWRM_REGISTERS_H |
| 15 | |
| 16 | #define SWRM_BASE_ADDRESS 0x00 |
| 17 | |
| 18 | #define SWRM_COMP_HW_VERSION SWRM_BASE_ADDRESS |
| 19 | #define SWRM_COMP_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000004) |
| 20 | #define SWRM_COMP_CFG_RMSK 0x3 |
| 21 | #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_BMSK 0x2 |
| 22 | #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_SHFT 0x1 |
| 23 | #define SWRM_COMP_CFG_ENABLE_BMSK 0x1 |
| 24 | #define SWRM_COMP_CFG_ENABLE_SHFT 0x0 |
| 25 | |
| 26 | #define SWRM_COMP_SW_RESET (SWRM_BASE_ADDRESS+0x00000008) |
| 27 | |
| 28 | #define SWRM_COMP_PARAMS (SWRM_BASE_ADDRESS+0x100) |
| 29 | #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK 0x0000001F |
| 30 | #define SWRM_COMP_PARAMS_DIN_PORTS_MASK 0x000003E0 |
| 31 | #define SWRM_COMP_PARAMS_WR_FIFO_DEPTH 0x00007C00 |
| 32 | #define SWRM_COMP_PARAMS_RD_FIFO_DEPTH 0x000F8000 |
| 33 | #define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES 0x00F00000 |
| 34 | #define SWRM_COMP_PARAMS_DATA_LANES 0x07000000 |
| 35 | |
| 36 | |
| 37 | #define SWRM_INTERRUPT_STATUS (SWRM_BASE_ADDRESS+0x00000200) |
| 38 | #define SWRM_INTERRUPT_STATUS_RMSK 0x1FFFD |
| 39 | |
| 40 | #define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ 0x1 |
| 41 | #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED 0x2 |
| 42 | #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS 0x4 |
| 43 | #define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET 0x8 |
| 44 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10 |
| 45 | #define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20 |
| 46 | #define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW 0x40 |
| 47 | #define SWRM_INTERRUPT_STATUS_CMD_ERROR 0x80 |
| 48 | #define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION 0x100 |
| 49 | #define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH 0x200 |
| 50 | #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400 |
| 51 | #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED 0x800 |
| 52 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED 0x1000 |
| 53 | #define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL 0x2000 |
| 54 | #define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED 0x4000 |
| 55 | #define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED 0x8000 |
| 56 | #define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST 0x10000 |
| 57 | |
| 58 | #define SWRM_INTERRUPT_MASK_ADDR (SWRM_BASE_ADDRESS+0x00000204) |
| 59 | #define SWRM_INTERRUPT_MASK_RMSK 0x1FFFF |
| 60 | |
| 61 | #define SWRM_INTERRUPT_MASK_SLAVE_PEND_IRQ_BMSK 0x1 |
| 62 | #define SWRM_INTERRUPT_MASK_SLAVE_PEND_IRQ_SHFT 0x0 |
| 63 | |
| 64 | #define SWRM_INTERRUPT_MASK_NEW_SLAVE_ATTACHED_BMSK 0x2 |
| 65 | #define SWRM_INTERRUPT_MASK_NEW_SLAVE_ATTACHED_SHFT 0x1 |
| 66 | |
| 67 | #define SWRM_INTERRUPT_MASK_CHANGE_ENUM_SLAVE_STATUS_BMSK 0x4 |
| 68 | #define SWRM_INTERRUPT_MASK_CHANGE_ENUM_SLAVE_STATUS_SHFT 0x2 |
| 69 | |
| 70 | #define SWRM_INTERRUPT_MASK_MASTER_CLASH_DET_BMSK 0x8 |
| 71 | #define SWRM_INTERRUPT_MASK_MASTER_CLASH_DET_SHFT 0x3 |
| 72 | |
| 73 | #define SWRM_INTERRUPT_MASK_RD_FIFO_OVERFLOW_BMSK 0x10 |
| 74 | #define SWRM_INTERRUPT_MASK_RD_FIFO_OVERFLOW_SHFT 0x4 |
| 75 | |
| 76 | #define SWRM_INTERRUPT_MASK_RD_FIFO_UNDERFLOW_BMSK 0x20 |
| 77 | #define SWRM_INTERRUPT_MASK_RD_FIFO_UNDERFLOW_SHFT 0x5 |
| 78 | |
| 79 | #define SWRM_INTERRUPT_MASK_WR_CMD_FIFO_OVERFLOW_BMSK 0x40 |
| 80 | #define SWRM_INTERRUPT_MASK_WR_CMD_FIFO_OVERFLOW_SHFT 0x6 |
| 81 | |
| 82 | #define SWRM_INTERRUPT_MASK_CMD_ERROR_BMSK 0x80 |
| 83 | #define SWRM_INTERRUPT_MASK_CMD_ERROR_SHFT 0x7 |
| 84 | |
| 85 | #define SWRM_INTERRUPT_MASK_DOUT_PORT_COLLISION_BMSK 0x100 |
| 86 | #define SWRM_INTERRUPT_MASK_DOUT_PORT_COLLISION_SHFT 0x8 |
| 87 | |
| 88 | #define SWRM_INTERRUPT_MASK_READ_EN_RD_VALID_MISMATCH_BMSK 0x200 |
| 89 | #define SWRM_INTERRUPT_MASK_READ_EN_RD_VALID_MISMATCH_SHFT 0x9 |
| 90 | |
| 91 | #define SWRM_INTERRUPT_MASK_SPECIAL_CMD_ID_FINISHED_BMSK 0x400 |
| 92 | #define SWRM_INTERRUPT_MASK_SPECIAL_CMD_ID_FINISHED_SHFT 0xA |
| 93 | |
| 94 | #define SWRM_INTERRUPT_MASK_NEW_SLAVE_AUTO_ENUM_FINISHED_BMSK 0x800 |
| 95 | #define SWRM_INTERRUPT_MASK_NEW_SLAVE_AUTO_ENUM_FINISHED_SHFT 0xB |
| 96 | |
| 97 | #define SWRM_INTERRUPT_MASK_AUTO_ENUM_FAILED_BMSK 0x1000 |
| 98 | #define SWRM_INTERRUPT_MASK_AUTO_ENUM_FAILED_SHFT 0xC |
| 99 | |
| 100 | #define SWRM_INTERRUPT_MASK_AUTO_ENUM_TABLE_IS_FULL_BMSK 0x2000 |
| 101 | #define SWRM_INTERRUPT_MASK_AUTO_ENUM_TABLE_IS_FULL_SHFT 0xD |
| 102 | |
| 103 | #define SWRM_INTERRUPT_MASK_BUS_RESET_FINISHED_BMSK 0x4000 |
| 104 | #define SWRM_INTERRUPT_MASK_BUS_RESET_FINISHED_SHFT 0xE |
| 105 | |
| 106 | #define SWRM_INTERRUPT_MASK_CLK_STOP_FINISHED_BMSK 0x8000 |
| 107 | #define SWRM_INTERRUPT_MASK_CLK_STOP_FINISHED_SHFT 0xF |
| 108 | |
| 109 | #define SWRM_INTERRUPT_MASK_ERROR_PORT_TEST_BMSK 0x10000 |
| 110 | #define SWRM_INTERRUPT_MASK_ERROR_PORT_TEST_SHFT 0x10 |
| 111 | |
| 112 | #define SWRM_INTERRUPT_MAX 0x11 |
| 113 | |
| 114 | #define SWRM_INTERRUPT_CLEAR (SWRM_BASE_ADDRESS+0x00000208) |
| 115 | |
| 116 | #define SWRM_CMD_FIFO_WR_CMD (SWRM_BASE_ADDRESS + 0x00000300) |
| 117 | #define SWRM_CMD_FIFO_WR_CMD_MASK 0xFFFFFFFF |
| 118 | #define SWRM_CMD_FIFO_RD_CMD (SWRM_BASE_ADDRESS + 0x00000304) |
| 119 | #define SWRM_CMD_FIFO_RD_CMD_MASK 0xFFFFFFF |
| 120 | #define SWRM_CMD_FIFO_CMD (SWRM_BASE_ADDRESS + 0x00000308) |
| 121 | #define SWRM_CMD_FIFO_STATUS (SWRM_BASE_ADDRESS + 0x0000030C) |
| 122 | |
| 123 | #define SWRM_CMD_FIFO_STATUS_WR_CMD_FIFO_CNT_MASK 0x1F00 |
| 124 | #define SWRM_CMD_FIFO_STATUS_RD_CMD_FIFO_CNT_MASK 0x7C00000 |
| 125 | |
| 126 | #define SWRM_CMD_FIFO_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000314) |
| 127 | #define SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_BMSK 0x7 |
| 128 | #define SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT 0x0 |
| 129 | |
| 130 | #define SWRM_CMD_FIFO_RD_FIFO_ADDR (SWRM_BASE_ADDRESS + 0x00000318) |
| 131 | |
| 132 | #define SWRM_ENUMERATOR_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000500) |
| 133 | #define SWRM_ENUMERATOR_CFG_AUTO_ENUM_EN_BMSK 0x1 |
| 134 | #define SWRM_ENUMERATOR_CFG_AUTO_ENUM_EN_SHFT 0x0 |
| 135 | |
| 136 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (SWRM_BASE_ADDRESS+0x530+0x8*m) |
| 137 | #define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (SWRM_BASE_ADDRESS+0x534+0x8*m) |
| 138 | |
| 139 | #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (SWRM_BASE_ADDRESS+0x101C+0x40*m) |
| 140 | #define SWRM_MCP_FRAME_CTRL_BANK_RMSK 0x00ff07ff |
| 141 | #define SWRM_MCP_FRAME_CTRL_BANK_SHFT 0 |
| 142 | #define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK 0xff0000 |
| 143 | #define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT 16 |
| 144 | #define SWRM_MCP_FRAME_CTRL_BANK_PHASE_BMSK 0xf800 |
| 145 | #define SWRM_MCP_FRAME_CTRL_BANK_PHASE_SHFT 11 |
| 146 | #define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_BMSK 0x700 |
| 147 | #define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT 8 |
| 148 | #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK 0xF8 |
| 149 | #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3 |
| 150 | #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK 0x7 |
| 151 | #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0 |
| 152 | |
| 153 | #define SWRM_MCP_BUS_CTRL_ADDR (SWRM_BASE_ADDRESS+0x00001044) |
| 154 | #define SWRM_MCP_BUS_CTRL_BUS_RESET_BMSK 0x1 |
| 155 | #define SWRM_MCP_BUS_CTRL_BUS_RESET_SHFT 0x0 |
| 156 | #define SWRM_MCP_BUS_CTRL_CLK_START_BMSK 0x2 |
| 157 | #define SWRM_MCP_BUS_CTRL_CLK_START_SHFT 0x1 |
| 158 | |
| 159 | #define SWRM_MCP_CFG_ADDR (SWRM_BASE_ADDRESS+0x00001048) |
| 160 | #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK 0x3E0000 |
| 161 | #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT 0x11 |
| 162 | #define SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK 0x02 |
| 163 | |
| 164 | #define SWRM_MCP_STATUS (SWRM_BASE_ADDRESS+0x104C) |
| 165 | #define SWRM_MCP_STATUS_BANK_NUM_MASK 0x01 |
| 166 | |
| 167 | #define SWRM_MCP_SLV_STATUS (SWRM_BASE_ADDRESS+0x1090) |
| 168 | #define SWRM_MCP_SLV_STATUS_MASK 0x03 |
| 169 | |
| 170 | #define SWRM_DP_PORT_CTRL_BANK(n, m) (SWRM_BASE_ADDRESS + \ |
| 171 | 0x00001124 + \ |
| 172 | 0x100*(n-1) + \ |
| 173 | 0x40*m) |
| 174 | #define SWRM_DP_PORT_CTRL_BANK_MASK 0xFFFFFFFF |
| 175 | #define SWRM_DP_PORT_CTRL_EN_CHAN_MASK 0xFF000000 |
| 176 | #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18 |
| 177 | #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10 |
| 178 | #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08 |
| 179 | #define SWRM_DP_PORT_CTRL_SAMPLE_INTERVAL 0x00 |
| 180 | |
| 181 | /* Soundwire Slave Register definition */ |
| 182 | |
| 183 | #define SWRS_BASE_ADDRESS 0x00 |
| 184 | |
| 185 | #define SWRS_DP_REG_OFFSET(port, bank) ((0x100*port)+(0x10*bank)) |
| 186 | |
| 187 | #define SWRS_DP_CHANNEL_ENABLE_BANK(n, m) (SWRS_BASE_ADDRESS + 0x120 + \ |
| 188 | SWRS_DP_REG_OFFSET(n, m)) |
| 189 | #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \ |
| 190 | SWRS_DP_REG_OFFSET(n, m)) |
| 191 | #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \ |
| 192 | SWRS_DP_REG_OFFSET(n, m)) |
| 193 | #define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \ |
| 194 | SWRS_DP_REG_OFFSET(n, m)) |
| 195 | #define SWRS_DP_HCONTROL_BANK(n, m) (SWRS_BASE_ADDRESS + 0x126 + \ |
| 196 | SWRS_DP_REG_OFFSET(n, m)) |
| 197 | #define SWRS_DP_BLOCK_CONTROL_3_BANK(n, m) (SWRS_BASE_ADDRESS + 0x127 + \ |
| 198 | SWRS_DP_REG_OFFSET(n, m)) |
| 199 | #define SWRS_SCP_FRAME_CTRL_BANK(m) (SWRS_BASE_ADDRESS + 0x60 + \ |
| 200 | 0x10*m) |
| 201 | #define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (SWRS_BASE_ADDRESS + 0xE0 + \ |
| 202 | 0x10*m) |
| 203 | |
| 204 | #endif /* _SWRM_REGISTERS_H */ |