David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012, 2014, The Linux Foundation. All rights reserved. |
dianlujitao | e0b5c19 | 2018-01-18 22:55:45 +0800 | [diff] [blame] | 2 | * Copyright (C) 2018 The LineageOS Project |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are |
| 6 | * met: |
| 7 | * * Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * * Redistributions in binary form must reproduce the above |
| 10 | * copyright notice, this list of conditions and the following |
| 11 | * disclaimer in the documentation and/or other materials provided |
| 12 | * with the distribution. |
| 13 | * * Neither the name of The Linux Foundation nor the names of its |
| 14 | * contributors may be used to endorse or promote products derived |
| 15 | * from this software without specific prior written permission. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 20 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 24 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 25 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 26 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 27 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | * |
| 29 | */ |
| 30 | |
| 31 | #ifdef __cplusplus |
| 32 | extern "C" { |
| 33 | #endif |
| 34 | |
Michael Bestas | 420f265 | 2019-09-29 23:59:05 +0300 | [diff] [blame] | 35 | #define FAILED -1 |
| 36 | #define SUCCESS 0 |
| 37 | #define INDEFINITE_DURATION 0 |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 38 | |
| 39 | /* Hints sent to perf HAL from power HAL |
| 40 | * These have to be kept in sync with Perf HAL side definitions |
| 41 | */ |
Michael Bestas | 420f265 | 2019-09-29 23:59:05 +0300 | [diff] [blame] | 42 | #define VENDOR_HINT_DISPLAY_OFF 0x00001040 |
| 43 | #define VENDOR_HINT_DISPLAY_ON 0x00001041 |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 44 | |
BeYkeRYkt | ef7a7ed | 2018-12-13 06:42:35 +0900 | [diff] [blame] | 45 | #define VENDOR_HINT_SCROLL_BOOST 0x00001080 |
| 46 | #define VENDOR_HINT_FIRST_LAUNCH_BOOST 0x00001081 |
| 47 | |
| 48 | enum SCROLL_BOOST_TYPE { |
| 49 | SCROLL_VERTICAL = 1, |
| 50 | SCROLL_HORIZONTAL = 2, |
| 51 | SCROLL_PANEL_VIEW = 3, |
| 52 | SCROLL_PREFILING = 4, |
| 53 | }; |
| 54 | |
| 55 | enum LAUNCH_BOOST_TYPE { |
| 56 | LAUNCH_BOOST_V1 = 1, |
| 57 | LAUNCH_BOOST_V2 = 2, |
| 58 | LAUNCH_BOOST_V3 = 3, |
| 59 | }; |
| 60 | |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 61 | enum SCREEN_DISPLAY_TYPE { |
| 62 | DISPLAY_OFF = 0x00FF, |
| 63 | }; |
| 64 | |
| 65 | enum PWR_CLSP_TYPE { |
| 66 | ALL_CPUS_PWR_CLPS_DIS = 0x101, |
| 67 | }; |
| 68 | |
| 69 | /* For CPUx min freq, the leftmost byte |
| 70 | * represents the CPU and the |
| 71 | * rightmost byte represents the frequency |
| 72 | * All intermediate frequencies on the |
| 73 | * device are supported. The hex value |
| 74 | * passed into PerfLock will be multiplied |
| 75 | * by 10^5. This frequency or the next |
| 76 | * highest frequency available will be set |
| 77 | * |
| 78 | * For example, if 1.4 Ghz is required on |
| 79 | * CPU0, use 0x20E |
| 80 | * |
| 81 | * If the highest available frequency |
| 82 | * on the device is required, use |
| 83 | * CPUx_MIN_FREQ_TURBO_MAX |
| 84 | * where x represents the CPU |
| 85 | */ |
| 86 | enum CPU0_MIN_FREQ_LVL { |
| 87 | CPU0_MIN_FREQ_NONTURBO_MAX = 0x20A, |
| 88 | CPU0_MIN_FREQ_TURBO_MAX = 0x2FE, |
| 89 | }; |
| 90 | |
| 91 | enum CPU1_MIN_FREQ_LVL { |
| 92 | CPU1_MIN_FREQ_NONTURBO_MAX = 0x30A, |
| 93 | CPU1_MIN_FREQ_TURBO_MAX = 0x3FE, |
| 94 | }; |
| 95 | |
| 96 | enum CPU2_MIN_FREQ_LVL { |
| 97 | CPU2_MIN_FREQ_NONTURBO_MAX = 0x40A, |
| 98 | CPU2_MIN_FREQ_TURBO_MAX = 0x4FE, |
| 99 | }; |
| 100 | |
| 101 | enum CPU3_MIN_FREQ_LVL { |
| 102 | CPU3_MIN_FREQ_NONTURBO_MAX = 0x50A, |
| 103 | CPU3_MIN_FREQ_TURBO_MAX = 0x5FE, |
| 104 | }; |
| 105 | |
| 106 | enum CPU0_MAX_FREQ_LVL { |
| 107 | CPU0_MAX_FREQ_NONTURBO_MAX = 0x150A, |
| 108 | }; |
| 109 | |
| 110 | enum CPU1_MAX_FREQ_LVL { |
| 111 | CPU1_MAX_FREQ_NONTURBO_MAX = 0x160A, |
| 112 | }; |
| 113 | |
| 114 | enum CPU2_MAX_FREQ_LVL { |
| 115 | CPU2_MAX_FREQ_NONTURBO_MAX = 0x170A, |
| 116 | }; |
| 117 | |
| 118 | enum CPU3_MAX_FREQ_LVL { |
| 119 | CPU3_MAX_FREQ_NONTURBO_MAX = 0x180A, |
| 120 | }; |
| 121 | |
| 122 | enum MIN_CPUS_ONLINE_LVL { |
| 123 | CPUS_ONLINE_MIN_2 = 0x702, |
| 124 | CPUS_ONLINE_MIN_3 = 0x703, |
| 125 | CPUS_ONLINE_MIN_4 = 0x704, |
| 126 | CPUS_ONLINE_MPD_OVERRIDE = 0x777, |
| 127 | CPUS_ONLINE_MAX = 0x7FF, |
| 128 | }; |
| 129 | |
| 130 | enum MAX_CPUS_ONLINE_LVL { |
| 131 | CPUS_ONLINE_MAX_LIMIT_1 = 0x8FE, |
| 132 | CPUS_ONLINE_MAX_LIMIT_2 = 0x8FD, |
| 133 | CPUS_ONLINE_MAX_LIMIT_3 = 0x8FC, |
| 134 | CPUS_ONLINE_MAX_LIMIT_4 = 0x8FB, |
| 135 | CPUS_ONLINE_MAX_LIMIT_MAX = 0x8FB, |
| 136 | }; |
| 137 | |
| 138 | enum SAMPLING_RATE_LVL { |
| 139 | MS_500 = 0xBCD, |
| 140 | MS_50 = 0xBFA, |
| 141 | MS_20 = 0xBFD, |
| 142 | }; |
| 143 | |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 144 | enum INTERACTIVE_TIMER_RATE_LVL { |
| 145 | TR_MS_500 = 0xECD, |
| 146 | TR_MS_100 = 0xEF5, |
| 147 | TR_MS_50 = 0xEFA, |
| 148 | TR_MS_30 = 0xEFC, |
| 149 | TR_MS_20 = 0xEFD, |
| 150 | }; |
| 151 | |
| 152 | /* This timer rate applicable to cpu0 |
| 153 | across 8939 series chipset */ |
| 154 | enum INTERACTIVE_TIMER_RATE_LVL_CPU0_8939 { |
| 155 | TR_MS_CPU0_500 = 0x30CD, |
| 156 | TR_MS_CPU0_100 = 0x30F5, |
| 157 | TR_MS_CPU0_50 = 0x30FA, |
| 158 | TR_MS_CPU0_30 = 0x30FC, |
| 159 | TR_MS_CPU0_20 = 0x30FD, |
| 160 | }; |
| 161 | |
| 162 | /* This timer rate applicable to cpu4 |
| 163 | across 8939 series chipset */ |
| 164 | enum INTERACTIVE_TIMER_RATE_LVL_CPU4_8939 { |
| 165 | TR_MS_CPU4_500 = 0x3BCD, |
| 166 | TR_MS_CPU4_100 = 0x3BF5, |
| 167 | TR_MS_CPU4_50 = 0x3BFA, |
| 168 | TR_MS_CPU4_30 = 0x3BFC, |
| 169 | TR_MS_CPU4_20 = 0x3BFD, |
| 170 | }; |
| 171 | |
| 172 | /* This timer rate applicable to big.little arch */ |
| 173 | enum INTERACTIVE_TIMER_RATE_LVL_BIG_LITTLE { |
| 174 | BIG_LITTLE_TR_MS_100 = 0x64, |
| 175 | BIG_LITTLE_TR_MS_50 = 0x32, |
| 176 | BIG_LITTLE_TR_MS_40 = 0x28, |
| 177 | BIG_LITTLE_TR_MS_30 = 0x1E, |
| 178 | BIG_LITTLE_TR_MS_20 = 0x14, |
| 179 | }; |
| 180 | |
| 181 | /* INTERACTIVE opcodes */ |
| 182 | enum INTERACTIVE_OPCODES { |
| 183 | INT_OP_CLUSTER0_TIMER_RATE = 0x41424000, |
| 184 | INT_OP_CLUSTER1_TIMER_RATE = 0x41424100, |
| 185 | INT_OP_CLUSTER0_USE_SCHED_LOAD = 0x41430000, |
| 186 | INT_OP_CLUSTER1_USE_SCHED_LOAD = 0x41430100, |
| 187 | INT_OP_CLUSTER0_USE_MIGRATION_NOTIF = 0x41434000, |
| 188 | INT_OP_CLUSTER1_USE_MIGRATION_NOTIF = 0x41434100, |
| 189 | INT_OP_NOTIFY_ON_MIGRATE = 0x4241C000 |
| 190 | }; |
| 191 | |
| 192 | enum INTERACTIVE_HISPEED_FREQ_LVL { |
| 193 | HS_FREQ_1026 = 0xF0A, |
Michael Bestas | 420f265 | 2019-09-29 23:59:05 +0300 | [diff] [blame] | 194 | HS_FREQ_800 = 0xF08, |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | enum INTERACTIVE_HISPEED_LOAD_LVL { |
| 198 | HISPEED_LOAD_90 = 0x105A, |
| 199 | }; |
| 200 | |
| 201 | enum SYNC_FREQ_LVL { |
| 202 | SYNC_FREQ_300 = 0x1103, |
| 203 | SYNC_FREQ_600 = 0X1106, |
| 204 | SYNC_FREQ_384 = 0x1103, |
| 205 | SYNC_FREQ_NONTURBO_MAX = 0x110A, |
| 206 | SYNC_FREQ_TURBO = 0x110F, |
| 207 | }; |
| 208 | |
| 209 | enum OPTIMAL_FREQ_LVL { |
| 210 | OPTIMAL_FREQ_300 = 0x1203, |
| 211 | OPTIMAL_FREQ_600 = 0x1206, |
| 212 | OPTIMAL_FREQ_384 = 0x1203, |
| 213 | OPTIMAL_FREQ_NONTURBO_MAX = 0x120A, |
| 214 | OPTIMAL_FREQ_TURBO = 0x120F, |
| 215 | }; |
| 216 | |
| 217 | enum SCREEN_PWR_CLPS_LVL { |
| 218 | PWR_CLPS_DIS = 0x1300, |
| 219 | PWR_CLPS_ENA = 0x1301, |
| 220 | }; |
| 221 | |
| 222 | enum THREAD_MIGRATION_LVL { |
| 223 | THREAD_MIGRATION_SYNC_OFF = 0x1400, |
| 224 | }; |
| 225 | |
| 226 | enum INTERACTIVE_IO_BUSY_LVL { |
| 227 | INTERACTIVE_IO_BUSY_OFF = 0x1B00, |
| 228 | INTERACTIVE_IO_BUSY_ON = 0x1B01, |
| 229 | }; |
| 230 | |
| 231 | enum SCHED_BOOST_LVL { |
| 232 | SCHED_BOOST_ON = 0x1E01, |
| 233 | }; |
| 234 | |
| 235 | enum CPU4_MIN_FREQ_LVL { |
| 236 | CPU4_MIN_FREQ_NONTURBO_MAX = 0x1F0A, |
| 237 | CPU4_MIN_FREQ_TURBO_MAX = 0x1FFE, |
| 238 | }; |
| 239 | |
| 240 | enum CPU5_MIN_FREQ_LVL { |
| 241 | CPU5_MIN_FREQ_NONTURBO_MAX = 0x200A, |
| 242 | CPU5_MIN_FREQ_TURBO_MAX = 0x20FE, |
| 243 | }; |
| 244 | |
| 245 | enum CPU6_MIN_FREQ_LVL { |
| 246 | CPU6_MIN_FREQ_NONTURBO_MAX = 0x210A, |
| 247 | CPU6_MIN_FREQ_TURBO_MAX = 0x21FE, |
| 248 | }; |
| 249 | |
| 250 | enum CPU7_MIN_FREQ_LVL { |
| 251 | CPU7_MIN_FREQ_NONTURBO_MAX = 0x220A, |
| 252 | CPU7_MIN_FREQ_TURBO_MAX = 0x22FE, |
| 253 | }; |
| 254 | |
| 255 | enum CPU4_MAX_FREQ_LVL { |
| 256 | CPU4_MAX_FREQ_NONTURBO_MAX = 0x230A, |
| 257 | }; |
| 258 | |
| 259 | enum CPU5_MAX_FREQ_LVL { |
| 260 | CPU5_MAX_FREQ_NONTURBO_MAX = 0x240A, |
| 261 | }; |
| 262 | |
| 263 | enum CPU6_MAX_FREQ_LVL { |
| 264 | CPU6_MAX_FREQ_NONTURBO_MAX = 0x250A, |
| 265 | }; |
| 266 | |
| 267 | enum CPU7_MAX_FREQ_LVL { |
| 268 | CPU7_MAX_FREQ_NONTURBO_MAX = 0x260A, |
| 269 | }; |
| 270 | |
dianlujitao | e0b5c19 | 2018-01-18 22:55:45 +0800 | [diff] [blame] | 271 | enum SCHED_PREFER_IDLE { |
| 272 | SCHED_PREFER_IDLE_DIS = 0x3E01, |
| 273 | }; |
| 274 | |
| 275 | enum SCHED_MIGRATE_COST_CHNG { |
| 276 | SCHED_MIGRATE_COST_SET = 0x3F01, |
| 277 | }; |
| 278 | |
| 279 | /** |
| 280 | * MPCTL v3 opcodes |
| 281 | */ |
| 282 | /* 0x1 */ |
| 283 | enum POWER_COLLAPSE { |
| 284 | ALL_CPUS_PWR_CLPS_DIS_V3 = 0x40400000, |
| 285 | }; |
| 286 | |
| 287 | /* 0x2 */ |
| 288 | enum CPUFREQ { |
| 289 | MIN_FREQ_BIG_CORE_0 = 0x40800000, |
| 290 | MIN_FREQ_BIG_CORE_0_RESIDX = 0x40802000, |
| 291 | MIN_FREQ_LITTLE_CORE_0 = 0x40800100, |
| 292 | MIN_FREQ_LITTLE_CORE_0_RESIDX = 0x40802100, |
| 293 | MAX_FREQ_BIG_CORE_0 = 0x40804000, |
| 294 | MAX_FREQ_BIG_CORE_0_RESIDX = 0x40806000, |
| 295 | MAX_FREQ_LITTLE_CORE_0 = 0x40804100, |
| 296 | MAX_FREQ_LITTLE_CORE_0_RESIDX = 0x40806100, |
| 297 | }; |
| 298 | |
| 299 | /* 0x3 */ |
| 300 | enum SCHED { |
| 301 | SCHED_BOOST_ON_V3 = 0x40C00000, |
| 302 | SCHED_PREFER_IDLE_DIS_V3 = 0x40C04000, |
| 303 | SCHED_MIGRATE_COST_SET_V3 = 0x40C08000, |
| 304 | SCHED_SMALL_TASK = 0x40C0C000, |
| 305 | SCHED_MOSTLY_IDLE_LOAD = 0x40C10000, |
| 306 | SCHED_MOSTLY_IDLE_NR_RUN = 0x40C14000, |
| 307 | SCHED_GROUP_ON = 0x40C28000, |
| 308 | SCHED_SPILL_NR_RUN = 0x40C2C000, |
| 309 | SCHED_RESTRICT_CLUSTER_SPILL = 0x40C34000, |
| 310 | SCHED_GROUP_UP_MIGRATE = 0x40C54000, |
| 311 | SCHED_GROUP_DOWN_MIGRATE = 0x40C58000, |
| 312 | }; |
| 313 | |
| 314 | /* 0x4 */ |
| 315 | enum CORE_HOTPLUG { |
| 316 | CPUS_ONLINE_MIN_BIG = 0x41000000, |
| 317 | CPUS_ONLINE_MAX_BIG = 0x41004000, |
| 318 | CPUS_ONLINE_MIN_LITTLE = 0x41000100, |
| 319 | CPUS_ONLINE_MAX_LITTLE = 0x41004100, |
| 320 | }; |
| 321 | |
| 322 | /* 0x5 */ |
| 323 | enum INTERACTIVE { |
| 324 | ABOVE_HISPEED_DELAY_BIG = 0x41400000, |
| 325 | ABOVE_HISPEED_DELAY_BIG_RESIDX = 0x41402000, |
| 326 | GO_HISPEED_LOAD_BIG = 0x41410000, |
| 327 | HISPEED_FREQ_BIG = 0x41414000, |
| 328 | TARGET_LOADS_BIG = 0x41420000, |
| 329 | IGNORE_HISPEED_NOTIF_BIG = 0x41438000, |
| 330 | ABOVE_HISPEED_DELAY_LITTLE = 0x41400100, |
| 331 | ABOVE_HISPEED_DELAY_LITTLE_RESIDX = 0x41402100, |
| 332 | GO_HISPEED_LOAD_LITTLE = 0x41410100, |
| 333 | HISPEED_FREQ_LITTLE = 0x41414100, |
| 334 | TARGET_LOADS_LITTLE = 0x41420100, |
| 335 | IGNORE_HISPEED_NOTIF_LITTLE = 0x41438100, |
| 336 | }; |
| 337 | |
| 338 | /* 0x6 */ |
| 339 | enum CPUBW_HWMON { |
| 340 | CPUBW_HWMON_MIN_FREQ = 0x41800000, |
| 341 | CPUBW_HWMON_MIN_FREQ_RESIDX = 0x41802000, |
| 342 | CPUBW_HWMON_HYST_OPT = 0x4180C000, |
| 343 | LOW_POWER_CEIL_MBPS = 0x41810000, |
| 344 | LOW_POWER_IO_PERCENT = 0x41814000, |
| 345 | CPUBW_HWMON_SAMPLE_MS = 0x41820000, |
| 346 | }; |
| 347 | |
| 348 | /* 0xA */ |
| 349 | enum GPU { |
| 350 | GPU_MIN_POWER_LEVEL = 0x42804000, |
| 351 | GPU_MAX_POWER_LEVEL = 0x42808000, |
| 352 | GPU_MIN_FREQ = 0x4280C000, |
| 353 | GPU_MIN_FREQ_RESIDX = 0x4280E000, |
| 354 | GPU_MAX_FREQ = 0x42810000, |
| 355 | GPU_MAX_FREQ_RESIDX = 0x42812000, |
| 356 | GPUBW_MIN_FREQ = 0x42814000, |
| 357 | GPUBW_MAX_FREQ = 0x42818000, |
| 358 | }; |
| 359 | |
David Ng | ee7c4c5 | 2018-03-22 23:49:12 -0700 | [diff] [blame] | 360 | #ifdef __cplusplus |
| 361 | } |
| 362 | #endif |