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| /* |
| * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. |
| * |
| * Permission to use, copy, modify, and/or distribute this software for any |
| * purpose with or without fee is hereby granted, provided that the above |
| * copyright notice and this permission notice appear in all copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| */ |
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| #ifndef _U_SIG_EHT_SU_MU_INFO_H_ |
| #define _U_SIG_EHT_SU_MU_INFO_H_ |
| #if !defined(__ASSEMBLER__) |
| #endif |
| |
| #define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 |
| |
| |
| struct u_sig_eht_su_mu_info { |
| #ifndef WIFI_BIT_ORDER_BIG_ENDIAN |
| uint32_t phy_version : 3, // [2:0] |
| transmit_bw : 3, // [5:3] |
| dl_ul_flag : 1, // [6:6] |
| bss_color_id : 6, // [12:7] |
| txop_duration : 7, // [19:13] |
| disregard_0a : 5, // [24:20] |
| validate_0b : 1, // [25:25] |
| reserved_0c : 6; // [31:26] |
| uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] |
| validate_1a : 1, // [2:2] |
| punctured_channel_information : 5, // [7:3] |
| validate_1b : 1, // [8:8] |
| mcs_of_eht_sig : 2, // [10:9] |
| num_eht_sig_symbols : 5, // [15:11] |
| crc : 4, // [19:16] |
| tail : 6, // [25:20] |
| dot11ax_su_extended : 1, // [26:26] |
| reserved_1d : 3, // [29:27] |
| rx_ndp : 1, // [30:30] |
| rx_integrity_check_passed : 1; // [31:31] |
| #else |
| uint32_t reserved_0c : 6, // [31:26] |
| validate_0b : 1, // [25:25] |
| disregard_0a : 5, // [24:20] |
| txop_duration : 7, // [19:13] |
| bss_color_id : 6, // [12:7] |
| dl_ul_flag : 1, // [6:6] |
| transmit_bw : 3, // [5:3] |
| phy_version : 3; // [2:0] |
| uint32_t rx_integrity_check_passed : 1, // [31:31] |
| rx_ndp : 1, // [30:30] |
| reserved_1d : 3, // [29:27] |
| dot11ax_su_extended : 1, // [26:26] |
| tail : 6, // [25:20] |
| crc : 4, // [19:16] |
| num_eht_sig_symbols : 5, // [15:11] |
| mcs_of_eht_sig : 2, // [10:9] |
| validate_1b : 1, // [8:8] |
| punctured_channel_information : 5, // [7:3] |
| validate_1a : 1, // [2:2] |
| eht_ppdu_sig_cmn_type : 2; // [1:0] |
| #endif |
| }; |
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| #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 |
| #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 |
| #define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 |
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| #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 |
| #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 |
| #define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 |
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| #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 |
| #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 |
| #define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 |
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| #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 |
| #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 |
| #define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 |
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| #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 |
| #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 |
| #define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 |
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| #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 |
| #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 |
| #define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 |
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| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 |
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| #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 |
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| #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 |
| #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 |
| #define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 |
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| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 |
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| #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 |
| #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 |
| #define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 |
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| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 |
| #define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 |
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| #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 |
| #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 |
| #define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 |
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| #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 |
| #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 |
| #define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 |
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| #define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 |
| #define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 |
| #define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 |
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| #define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 |
| #define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 |
| #define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 |
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| #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 |
| #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 |
| #define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 |
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| #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 |
| #define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 |
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| #define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 |
| #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 |
| #define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 |
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| #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 |
| #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 |
| #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 |
| #define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 |
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| #endif |