Merge 5404c814f313ca85455ce93028f8667d00f6cf8c on remote branch
Change-Id: Icd15d162618946ebf6a5a100f37dcfa0563a0680
diff --git a/fw/htt.h b/fw/htt.h
index 77da2f6..28e052e 100644
--- a/fw/htt.h
+++ b/fw/htt.h
@@ -747,6 +747,10 @@
HTT_STATS_DMAC_RESET_STATS_TAG = 155, /* htt_dmac_reset_stats_tlv */
HTT_STATS_RX_PDEV_BE_UL_OFDMA_USER_STATS_TAG = 156, /* htt_rx_pdev_be_ul_ofdma_user_stats_tlv */
HTT_STATS_PHY_TPC_STATS_TAG = 157, /* htt_phy_tpc_stats_tlv */
+ HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, /* htt_pdev_puncture_stats_tlv */
+ HTT_STATS_ML_PEER_DETAILS_TAG = 159, /* htt_ml_peer_details_tlv */
+ HTT_STATS_ML_PEER_EXT_DETAILS_TAG = 160, /* htt_ml_peer_ext_details_tlv */
+ HTT_STATS_ML_LINK_INFO_DETAILS_TAG = 161, /* htt_ml_link_info_tlv */
HTT_STATS_MAX_TAG,
@@ -5179,6 +5183,7 @@
HTT_RX_MON_HOST2MON_BUF_RING, /* Status buffers and Packet buffers are provided by host */
HTT_RX_MON_MON2HOST_DEST_RING, /* Used by monitor to fill status buffers and provide to host */
HTT_LPASS_TO_FW_RXBUF_RING, /* new LPASS to FW refill ring to recycle rx buffers */
+ HTT_HOST3_TO_FW_RXBUF_RING, /* used by host for EasyMesh feature */
/* Add Other SRING which can't be directly configured by host software above this line */
};
diff --git a/fw/htt_stats.h b/fw/htt_stats.h
index 04b37f5..3909f0d 100644
--- a/fw/htt_stats.h
+++ b/fw/htt_stats.h
@@ -442,6 +442,27 @@
*/
HTT_DBG_SOC_ERROR_STATS = 45,
+ /** HTT_DBG_PDEV_PUNCTURE_STATS
+ * PARAMS:
+ * - param 0: enum from htt_tx_pdev_puncture_stats_upload_t, indicating
+ * the stats to upload
+ * RESP MSG:
+ * - one or more htt_pdev_puncture_stats_tlv, depending on param 0
+ */
+ HTT_DBG_PDEV_PUNCTURE_STATS = 46,
+
+ /* HTT_DBG_EXT_STATS_ML_PEERS_INFO
+ * PARAMS:
+ * - param 0:
+ * Bit 0 -> HTT_ML_PEER_DETAILS_TLV always enabled by default
+ * Bit 1 -> HTT_ML_PEER_EXT_DETAILS_TLV will be uploaded when
+ * this bit is set
+ * Bit 2 -> HTT_ML_LINK_INFO_TLV will be uploaded when this bit is set
+ * RESP MSG:
+ * - htt_ml_peer_stats_t
+ */
+ HTT_DBG_EXT_STATS_ML_PEERS_INFO = 47,
+
/* keep this last */
HTT_DBG_NUM_EXT_STATS = 256,
@@ -593,6 +614,21 @@
HTT_UPLOAD_BE_TXBF_OFDMA_STATS,
} htt_tx_pdev_txbf_ofdma_stats_upload_t;
+/* htt_tx_pdev_puncture_stats_upload_t
+ * Enumerations for specifying which stats to upload in response to
+ * HTT_DBG_PDEV_PUNCTURE_STATS.
+ */
+typedef enum {
+ /* upload puncture stats for all supported modes, both TX and RX */
+ HTT_UPLOAD_PUNCTURE_STATS_ALL,
+
+ /* upload puncture stats for all supported TX modes */
+ HTT_UPLOAD_PUNCTURE_STATS_TX,
+
+ /* upload puncture stats for all supported RX modes */
+ HTT_UPLOAD_PUNCTURE_STATS_RX,
+} htt_tx_pdev_puncture_stats_upload_t;
+
#define HTT_STATS_MAX_STRING_SZ32 4
#define HTT_STATS_MACID_INVALID 0xff
#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
@@ -1318,6 +1354,20 @@
* BIT [31 : 16] :- reserved
*/
A_UINT32 sendn_frms_allowed;
+ /*
+ * tid_ext_flags, tid_ext2_flags, and tid_flush_reason are opaque fields
+ * that cannot be interpreted by the host.
+ * They are only for off-line debug.
+ */
+ A_UINT32 tid_ext_flags;
+ A_UINT32 tid_ext2_flags;
+ A_UINT32 tid_flush_reason;
+ A_UINT32 mlo_flush_tqm_status_pending_low;
+ A_UINT32 mlo_flush_tqm_status_pending_high;
+ A_UINT32 mlo_flush_partner_info_low;
+ A_UINT32 mlo_flush_partner_info_high;
+ A_UINT32 mlo_flush_initator_info_low;
+ A_UINT32 mlo_flush_initator_info_high;
} htt_tx_tid_stats_v1_tlv;
#define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff
@@ -1418,6 +1468,24 @@
A_UINT32 remove_mpdus_max_retries;
} htt_peer_stats_cmn_tlv;
+#define HTT_PEER_DETAILS_ML_PEER_OFFSET_BYTES 32
+#define HTT_PEER_DETAILS_ML_PEER_OFFSET_DWORD 8
+#define HTT_PEER_DETAILS_ML_PEER_ID_VALID_M 0x00000001
+#define HTT_PEER_DETAILS_ML_PEER_ID_VALID_S 0
+#define HTT_PEER_DETAILS_ML_PEER_ID_M 0x00001ffe
+#define HTT_PEER_DETAILS_ML_PEER_ID_S 1
+#define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000
+#define HTT_PEER_DETAILS_LINK_IDX_S 13
+
+#define HTT_PEER_DETAILS_SET(word, httsym, val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PEER_DETAILS_ ## httsym, val); \
+ (word) |= ((val) << HTT_PEER_DETAILS_ ## httsym ## _S); \
+ } while(0)
+
+#define HTT_PEER_DETAILS_GET(word, httsym) \
+ (((word) & HTT_PEER_DETAILS_ ## httsym ## _M) >> HTT_PEER_DETAILS_ ## httsym ## _S)
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/** This enum type of HTT_PEER_TYPE */
@@ -1432,6 +1500,11 @@
htt_mac_addr mac_addr;
A_UINT32 peer_flags;
A_UINT32 qpeer_flags;
+ /* Dword 8 */
+ A_UINT32 ml_peer_id_valid : 1, /* [0:0] */
+ ml_peer_id : 12, /* [12:1] */
+ link_idx : 8, /* [20:13] */
+ rsvd : 11; /* [31:21] */
} htt_peer_details_tlv;
typedef struct {
@@ -1452,6 +1525,19 @@
} htt_ast_entry_tlv;
typedef enum {
+ HTT_STATS_DIRECTION_TX,
+ HTT_STATS_DIRECTION_RX,
+} HTT_STATS_DIRECTION;
+
+typedef enum {
+ HTT_STATS_PPDU_TYPE_MODE_SU,
+ HTT_STATS_PPDU_TYPE_DL_MU_MIMO,
+ HTT_STATS_PPDU_TYPE_UL_MU_MIMO,
+ HTT_STATS_PPDU_TYPE_DL_MU_OFDMA,
+ HTT_STATS_PPDU_TYPE_UL_MU_OFDMA,
+} HTT_STATS_PPDU_TYPE;
+
+typedef enum {
HTT_STATS_PREAM_OFDM,
HTT_STATS_PREAM_CCK,
HTT_STATS_PREAM_HT,
@@ -3260,6 +3346,17 @@
HTT_SCHED_TID_FALLBACK_TO_PREV_DECISION, /* Fall back to previous decision */
HTT_SCHED_TID_SKIP_PEER_ALREADY_IN_TXQ, /* skip tid, peer is already available in the txq */
HTT_SCHED_TID_SKIP_DELAY_UL_SCHED, /* skip tid delay UL schedule */
+ HTT_SCHED_TID_SKIP_PWR_SAVE_STATE_OFF, /* Limit UL scheduling to primary link if not in power save state */
+ HTT_SCHED_TID_SKIP_TWT_SUSPEND, /* Skip UL trigger for certain cases ex TWT suspend */
+ HTT_SCHED_TID_SKIP_DISABLE_160MHZ_OFDMA, /* Skip ul tid if peer supports 160MHZ */
+ HTT_SCHED_TID_SKIP_ULMU_DISABLE_FROM_OMI, /* Skip ul tid if sta send omi to indicate to disable UL mu data */
+ HTT_SCHED_TID_SKIP_UL_MAX_SCHED_CMD_EXCEEDED,/* skip ul tid if max sched cmd is exceeded */
+ HTT_SCHED_TID_SKIP_UL_SMALL_QDEPTH, /* Skip ul tid for small qdepth */
+ HTT_SCHED_TID_SKIP_UL_TWT_PAUSED, /* Skip ul tid if twt txq is paused */
+ HTT_SCHED_TID_SKIP_PEER_UL_RX_NOT_ACTIVE, /* Skip ul tid if peer ul rx is not active */
+ HTT_SCHED_TID_SKIP_NO_FORCE_TRIGGER, /* Skip ul tid if there is no force triggers */
+ HTT_SCHED_TID_SKIP_SMART_BASIC_TRIGGER, /* Skip ul tid if smart basic trigger doesnot have enough data */
+
HTT_SCHED_INELIGIBILITY_MAX,
} htt_sched_txq_sched_ineligibility_tlv_enum;
@@ -7426,4 +7523,544 @@
A_UINT32 drain_dest_ring_mask;
} htt_dmac_reset_stats_tlv;
+
+/* Support up to 640 MHz mode for future expansion */
+#define HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT 32
+
+#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_M 0x000000ff
+#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_S 0
+
+#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_GET(_var) \
+ (((_var) & HTT_PDEV_PUNCTURE_STATS_MAC_ID_M) >> \
+ HTT_PDEV_PUNCTURE_STATS_MAC_ID_S)
+
+#define HTT_PDEV_PUNCTURE_STATS_MAC_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PDEV_PUNCTURE_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_PDEV_PUNCTURE_STATS_MAC_ID_S)); \
+ } while (0)
+
+/*
+ * TLV used to provide puncturing related stats for TX/RX and each PPDU type.
+ */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+
+ /**
+ * BIT [ 7 : 0] :- mac_id
+ * BIT [31 : 8] :- reserved
+ */
+ union {
+ struct {
+ A_UINT32 mac_id: 8,
+ reserved: 24;
+ };
+ A_UINT32 mac_id__word;
+ };
+
+ /*
+ * Stats direction (TX/RX). Enum value from HTT_STATS_DIRECTION.
+ */
+ A_UINT32 direction;
+
+ /*
+ * Preamble type. Enum value from HTT_STATS_PREAM_TYPE.
+ *
+ * Note that for although OFDM rates don't technically support
+ * "puncturing", this TLV can be used to indicate the 20 MHz sub-bands
+ * utilized for OFDM legacy duplicate packets, which are also used during
+ * puncturing sequences.
+ */
+ A_UINT32 preamble;
+
+ /*
+ * Stats PPDU type. Enum value from HTT_STATS_PPDU_TYPE.
+ */
+ A_UINT32 ppdu_type;
+
+ /*
+ * Indicates the number of valid elements in the
+ * "num_subbands_used_cnt" array, and must be <=
+ * HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT.
+ *
+ * Also indicates how many bits in the last_used_pattern_mask may be
+ * non-zero.
+ */
+ A_UINT32 subband_count;
+
+ /*
+ * The last used transmit 20 MHz subband mask. Bit 0 represents the lowest
+ * 20 MHz subband mask, bit 1 the second lowest, and so on.
+ *
+ * All 32 bits are valid and will be used for expansion to higher BW modes.
+ */
+ A_UINT32 last_used_pattern_mask;
+
+
+ /*
+ * Number of array elements with valid values is equal to "subband_count".
+ * If subband_count is < HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT, the
+ * remaining elements will be implicitly set to 0x0.
+ *
+ * The array index is the number of 20 MHz subbands utilized during TX/RX,
+ * and the counter value at that index is the number of times that subband
+ * count was used.
+ *
+ * The count is incremented once for each OTA PPDU transmitted / received.
+ */
+ A_UINT32 num_subbands_used_cnt[HTT_PUNCTURE_STATS_MAX_SUBBAND_COUNT];
+} htt_pdev_puncture_stats_tlv;
+
+#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M 0x0000003F
+#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S 0
+#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M 0x00000FC0
+#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S 6
+#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M 0x0FFFF000
+#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S 12
+
+#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_GET(_var) \
+ (((_var) & HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M) >> \
+ HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S)
+
+#define HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD, _val); \
+ ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_PEER_ASSOC_IPC_RECVD_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_GET(_var) \
+ (((_var) & HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M) >> \
+ HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S)
+
+#define HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD, _val); \
+ ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_SCHED_PEER_DELETE_RECVD_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_GET(_var) \
+ (((_var) & HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M) >> \
+ HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)
+
+#define HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX, _val); \
+ ((_var) &= ~(HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_EXT_DETAILS_MLD_AST_INDEX_S)); \
+ } while (0)
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ union {
+ struct {
+ A_UINT32 peer_assoc_ipc_recvd : 6,
+ sched_peer_delete_recvd : 6,
+ mld_ast_index : 16,
+ reserved : 4;
+ };
+ A_UINT32 msg_dword_1;
+ };
+} htt_ml_peer_ext_details_tlv;
+
+#define HTT_ML_LINK_INFO_VALID_M 0x00000001
+#define HTT_ML_LINK_INFO_VALID_S 0
+#define HTT_ML_LINK_INFO_ACTIVE_M 0x00000002
+#define HTT_ML_LINK_INFO_ACTIVE_S 1
+#define HTT_ML_LINK_INFO_PRIMARY_M 0x00000004
+#define HTT_ML_LINK_INFO_PRIMARY_S 2
+#define HTT_ML_LINK_INFO_ASSOC_LINK_M 0x00000008
+#define HTT_ML_LINK_INFO_ASSOC_LINK_S 3
+#define HTT_ML_LINK_INFO_CHIP_ID_M 0x00000070
+#define HTT_ML_LINK_INFO_CHIP_ID_S 4
+#define HTT_ML_LINK_INFO_IEEE_LINK_ID_M 0x00007F80
+#define HTT_ML_LINK_INFO_IEEE_LINK_ID_S 7
+#define HTT_ML_LINK_INFO_HW_LINK_ID_M 0x00038000
+#define HTT_ML_LINK_INFO_HW_LINK_ID_S 15
+#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M 0x000C0000
+#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S 18
+#define HTT_ML_LINK_INFO_MASTER_LINK_M 0x00100000
+#define HTT_ML_LINK_INFO_MASTER_LINK_S 20
+#define HTT_ML_LINK_INFO_ANCHOR_LINK_M 0x00200000
+#define HTT_ML_LINK_INFO_ANCHOR_LINK_S 21
+#define HTT_ML_LINK_INFO_INITIALIZED_M 0x00400000
+#define HTT_ML_LINK_INFO_INITIALIZED_S 22
+
+#define HTT_ML_LINK_INFO_SW_PEER_ID_M 0x0000ffff
+#define HTT_ML_LINK_INFO_SW_PEER_ID_S 0
+#define HTT_ML_LINK_INFO_VDEV_ID_M 0x00ff0000
+#define HTT_ML_LINK_INFO_VDEV_ID_S 16
+
+#define HTT_ML_LINK_INFO_VALID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_VALID_M) >> \
+ HTT_ML_LINK_INFO_VALID_S)
+
+#define HTT_ML_LINK_INFO_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VALID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_VALID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_VALID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_ACTIVE_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_ACTIVE_M) >> \
+ HTT_ML_LINK_INFO_ACTIVE_S)
+
+#define HTT_ML_LINK_INFO_ACTIVE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ACTIVE, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_ACTIVE_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_ACTIVE_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_PRIMARY_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_PRIMARY_M) >> \
+ HTT_ML_LINK_INFO_PRIMARY_S)
+
+#define HTT_ML_LINK_INFO_PRIMARY_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_PRIMARY, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_PRIMARY_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_PRIMARY_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_ASSOC_LINK_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_ASSOC_LINK_M) >> \
+ HTT_ML_LINK_INFO_ASSOC_LINK_S)
+
+#define HTT_ML_LINK_INFO_ASSOC_LINK_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ASSOC_LINK, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_ASSOC_LINK_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_ASSOC_LINK_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_CHIP_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_CHIP_ID_M) >> \
+ HTT_ML_LINK_INFO_CHIP_ID_S)
+
+#define HTT_ML_LINK_INFO_CHIP_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_CHIP_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_CHIP_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_CHIP_ID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_IEEE_LINK_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_IEEE_LINK_ID_M) >> \
+ HTT_ML_LINK_INFO_IEEE_LINK_ID_S)
+
+#define HTT_ML_LINK_INFO_IEEE_LINK_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_IEEE_LINK_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_IEEE_LINK_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_IEEE_LINK_ID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_HW_LINK_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_HW_LINK_ID_M) >> \
+ HTT_ML_LINK_INFO_HW_LINK_ID_S)
+
+#define HTT_ML_LINK_INFO_HW_LINK_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_HW_LINK_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_HW_LINK_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_HW_LINK_ID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M) >> \
+ HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S)
+
+#define HTT_ML_LINK_INFO_LOGICAL_LINK_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_LOGICAL_LINK_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_LOGICAL_LINK_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_LOGICAL_LINK_ID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_MASTER_LINK_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_MASTER_LINK_M) >> \
+ HTT_ML_LINK_INFO_MASTER_LINK_S)
+
+#define HTT_ML_LINK_INFO_MASTER_LINK_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_MASTER_LINK, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_MASTER_LINK_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_MASTER_LINK_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_ANCHOR_LINK_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_ANCHOR_LINK_M) >> \
+ HTT_ML_LINK_INFO_ANCHOR_LINK_S)
+
+#define HTT_ML_LINK_INFO_ANCHOR_LINK_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_ANCHOR_LINK, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_ANCHOR_LINK_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_ANCHOR_LINK_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_INITIALIZED_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_INITIALIZED_M) >> \
+ HTT_ML_LINK_INFO_INITIALIZED_S)
+
+#define HTT_ML_LINK_INFO_INITIALIZED_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_INITIALIZED, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_INITIALIZED_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_INITIALIZED_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_SW_PEER_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_SW_PEER_ID_M) >> \
+ HTT_ML_LINK_INFO_SW_PEER_ID_S)
+
+#define HTT_ML_LINK_INFO_SW_PEER_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_SW_PEER_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_SW_PEER_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_SW_PEER_ID_S)); \
+ } while (0)
+
+#define HTT_ML_LINK_INFO_VDEV_ID_GET(_var) \
+ (((_var) & HTT_ML_LINK_INFO_VDEV_ID_M) >> \
+ HTT_ML_LINK_INFO_VDEV_ID_S)
+
+#define HTT_ML_LINK_INFO_VDEV_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_LINK_INFO_VDEV_ID, _val); \
+ ((_var) &= ~(HTT_ML_LINK_INFO_VDEV_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_LINK_INFO_VDEV_ID_S)); \
+ } while (0)
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ union {
+ struct {
+ A_UINT32 valid : 1,
+ active : 1,
+ primary : 1,
+ assoc_link : 1,
+ chip_id : 3,
+ ieee_link_id : 8,
+ hw_link_id : 3,
+ logical_link_id : 2,
+ master_link : 1,
+ anchor_link : 1,
+ initialized : 1,
+ reserved : 9;
+ };
+ A_UINT32 msg_dword_1;
+ };
+
+ union {
+ struct {
+ A_UINT32 sw_peer_id : 16,
+ vdev_id : 8,
+ reserved1 : 8;
+ };
+ A_UINT32 msg_dword_2;
+ };
+
+ A_UINT32 primary_tid_mask;
+} htt_ml_link_info_tlv;
+
+#define HTT_ML_PEER_DETAILS_NUM_LINKS_M 0x00000003
+#define HTT_ML_PEER_DETAILS_NUM_LINKS_S 0
+#define HTT_ML_PEER_DETAILS_ML_PEER_ID_M 0x00003FFC
+#define HTT_ML_PEER_DETAILS_ML_PEER_ID_S 2
+#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M 0x0001C000
+#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S 14
+#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M 0x00060000
+#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S 17
+#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M 0x00380000
+#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S 19
+#define HTT_ML_PEER_DETAILS_NON_STR_M 0x00400000
+#define HTT_ML_PEER_DETAILS_NON_STR_S 22
+#define HTT_ML_PEER_DETAILS_EMLSR_M 0x00800000
+#define HTT_ML_PEER_DETAILS_EMLSR_S 23
+#define HTT_ML_PEER_DETAILS_IS_STA_KO_M 0x01000000
+#define HTT_ML_PEER_DETAILS_IS_STA_KO_S 24
+#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M 0x06000000
+#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S 25
+#define HTT_ML_PEER_DETAILS_ALLOCATED_M 0x08000000
+#define HTT_ML_PEER_DETAILS_ALLOCATED_S 27
+
+#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M 0x000000ff
+#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S 0
+
+#define HTT_ML_PEER_DETAILS_NUM_LINKS_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_NUM_LINKS_M) >> \
+ HTT_ML_PEER_DETAILS_NUM_LINKS_S)
+
+#define HTT_ML_PEER_DETAILS_NUM_LINKS_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LINKS, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LINKS_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LINKS_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_ML_PEER_ID_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_ML_PEER_ID_M) >> \
+ HTT_ML_PEER_DETAILS_ML_PEER_ID_S)
+
+#define HTT_ML_PEER_DETAILS_ML_PEER_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ML_PEER_ID, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_ML_PEER_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ML_PEER_ID_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M) >> \
+ HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S)
+
+#define HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_LINK_IDX_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M) >> \
+ HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S)
+
+#define HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PRIMARY_CHIP_ID_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M) >> \
+ HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S)
+
+#define HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_LINK_INIT_COUNT_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_NON_STR_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_NON_STR_M) >> \
+ HTT_ML_PEER_DETAILS_NON_STR_S)
+
+#define HTT_ML_PEER_DETAILS_NON_STR_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NON_STR, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_NON_STR_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NON_STR_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_EMLSR_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_EMLSR_M) >> \
+ HTT_ML_PEER_DETAILS_EMLSR_S)
+
+#define HTT_ML_PEER_DETAILS_EMLSR_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_EMLSR, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_EMLSR_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_EMLSR_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_IS_STA_KO_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_IS_STA_KO_M) >> \
+ HTT_ML_PEER_DETAILS_IS_STA_KO_S)
+
+#define HTT_ML_PEER_DETAILS_IS_STA_KO_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_IS_STA_KO, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_IS_STA_KO_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_IS_STA_KO_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M) >> \
+ HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S)
+
+#define HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_NUM_LOCAL_LINKS_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_ALLOCATED_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_ALLOCATED_M) >> \
+ HTT_ML_PEER_DETAILS_ALLOCATED_S)
+
+#define HTT_ML_PEER_DETAILS_ALLOCATED_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_ALLOCATED, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_ALLOCATED_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_ALLOCATED_S)); \
+ } while (0)
+
+#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_GET(_var) \
+ (((_var) & HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M) >> \
+ HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)
+
+#define HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP, _val); \
+ ((_var) &= ~(HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_M)); \
+ ((_var) |= ((_val) << HTT_ML_PEER_DETAILS_PARTICIPATING_CHIPS_BITMAP_S)); \
+ } while (0)
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ htt_mac_addr remote_mld_mac_addr;
+ union {
+ struct {
+ A_UINT32 num_links : 2,
+ ml_peer_id : 12,
+ primary_link_idx : 3,
+ primary_chip_id : 2,
+ link_init_count : 3,
+ non_str : 1,
+ emlsr : 1,
+ is_sta_ko : 1,
+ num_local_links : 2,
+ allocated : 1,
+ reserved : 4;
+ };
+ A_UINT32 msg_dword_1;
+ };
+
+ union {
+ struct {
+ A_UINT32 participating_chips_bitmap : 8,
+ reserved1 : 24;
+ };
+ A_UINT32 msg_dword_2;
+ };
+ /*
+ * ml_peer_flags is an opaque field that cannot be interpreted by
+ * the host; it is only for off-line debug.
+ */
+ A_UINT32 ml_peer_flags;
+} htt_ml_peer_details_tlv;
+
+/* STATS_TYPE : HTT_DBG_EXT_STATS_ML_PEERS_INFO
+ * TLV_TAGS:
+ * - HTT_STATS_ML_PEER_DETAILS_TAG
+ * - HTT_STATS_ML_LINK_INFO_DETAILS_TAG
+ * - HTT_STATS_ML_PEER_EXT_DETAILS_TAG (multiple)
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct _htt_ml_peer_stats {
+ htt_ml_peer_details_tlv ml_peer_details;
+ htt_ml_peer_ext_details_tlv ml_peer_ext_details;
+ htt_ml_link_info_tlv ml_link_info[];
+} htt_ml_peer_stats_t;
+
+
#endif /* __HTT_STATS_H__ */
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index 918e292..2b8c15c 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -592,6 +592,7 @@
WMI_SERVICE_LINKSPEED_ROAM_TRIGGER_SUPPORT = 339, /* FW supports linkspeed trigger roam */
WMI_SERVICE_UMAC_HANG_RECOVERY_SUPPORT = 340, /* FW supports recovering system from UMAC hang condition */
WMI_SERVICE_COAP_OFFLOAD_SUPPORT = 341, /* FW supports CoAP (the Constrained Application Protocol) offload */
+ WMI_SERVICE_TDLS_WIDEBAND_SUPPORT = 342, /* FW supports Wideband TDLS */
WMI_MAX_EXT2_SERVICE
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index 4930c95..1acec0d 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -1282,6 +1282,12 @@
WMITLV_TAG_STRUC_WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param,
WMITLV_TAG_STRUC_WMI_WOW_COAP_BUF_INFO_EVENT_fixed_param,
WMITLV_TAG_STRUC_wmi_coap_tuple,
+ WMITLV_TAG_STRUC_wmi_iface_powersave_stats,
+ WMITLV_TAG_STRUC_wmi_roam_bss_info_param,
+ WMITLV_TAG_STRUC_wmi_vendor_control_param,
+ WMITLV_TAG_STRUC_wmi_coex_dbam_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_is_my_mgmt_frame,
} WMITLV_TAG_ID;
/*
@@ -1785,6 +1791,7 @@
OP(WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID) \
OP(WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMDID) \
OP(WMI_WOW_COAP_GET_BUF_INFO_CMDID) \
+ OP(WMI_COEX_DBAM_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -2074,6 +2081,7 @@
OP(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID) \
OP(WMI_HALPHY_CTRL_PATH_STATS_EVENTID) \
OP(WMI_WOW_COAP_BUF_INFO_EVENTID) \
+ OP(WMI_COEX_DBAM_COMPLETE_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -5106,6 +5114,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param, WMI_WOW_COAP_GET_BUF_INFO_CMD_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_GET_BUF_INFO_CMDID);
+/* coex dbam cmd */
+#define WMITLV_TABLE_WMI_COEX_DBAM_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_cmd_fixed_param, wmi_coex_dbam_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_CMDID);
+
/************************** TLV definitions of WMI events *******************************/
@@ -5372,7 +5385,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_rx_params_ext, mgmt_rx_params_ext, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_frame_pn_params, pn_params, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_ml_info, ml_info, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID);
/* Management Rx FW Consumed Event */
@@ -5421,7 +5435,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_bss_info_param, bss_info_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
/* Roam Synch Event */
@@ -5459,7 +5474,8 @@
/* Get Roam Vendor Control Param Event */
#define WMITLV_TABLE_WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID(id,op,buf,len) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_event_fixed_param, wmi_roam_get_vendor_control_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_event_fixed_param, wmi_roam_get_vendor_control_param_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_vendor_control_param, vendor_control_param, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID);
/* WOW Wakeup Host Event */
@@ -5712,7 +5728,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param, wmi_iface_link_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_link_stats, iface_link_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_wmm_ac_stats, ac, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_offload_stats, iface_offload_stats, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_iface_powersave_stats, iface_powersave_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_LINK_STATS_EVENTID);
@@ -6912,6 +6929,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, payloads, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_COAP_BUF_INFO_EVENTID);
+/* coex dbam cmd complete event */
+#define WMITLV_TABLE_WMI_COEX_DBAM_COMPLETE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param, wmi_coex_dbam_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_COEX_DBAM_COMPLETE_EVENTID);
+
#ifdef __cplusplus
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index c56f0cd..8d5687a 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -851,7 +851,7 @@
WMI_ROAM_SET_PARAM_CMDID,
/** Enable or Disable roam vendor control */
WMI_ROAM_ENABLE_VENDOR_CONTROL_CMDID,
- /** Get roam vendor control params */
+ /** Get firmware ini value */
WMI_ROAM_GET_VENDOR_CONTROL_PARAM_CMDID,
/** offload scan specific commands */
@@ -1305,6 +1305,8 @@
WMI_COEX_GET_ANTENNA_ISOLATION_CMDID,
WMI_SAR_LIMITS_CMDID,
WMI_SAR_GET_LIMITS_CMDID,
+ /** Dedicated BT Antenna Mode (DBAM) command */
+ WMI_COEX_DBAM_CMDID,
/**
* OBSS scan offload enable/disable commands
@@ -1888,7 +1890,7 @@
WMI_ROAM_CAPABILITY_REPORT_EVENTID,
/** Send AP frame content like beacon/probe resp etc.. */
WMI_ROAM_FRAME_EVENTID,
- /** GET Roam Vendor Control Param event */
+ /** Send firmware ini value corresponding to param_id */
WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID,
/** P2P disc found */
@@ -2171,6 +2173,8 @@
/* Coex Event */
WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX),
WMI_SAR_GET_LIMITS_EVENTID,
+ /** Dedicated BT Antenna Mode (DBAM) complete event */
+ WMI_COEX_DBAM_COMPLETE_EVENTID,
/* LPI Event */
WMI_LPI_RESULT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_LPI),
@@ -5838,6 +5842,12 @@
} wmi_frame_pn_params;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag (WMITLV_TAG_STRUC_wmi_is_my_frame) */
+ A_UINT32 mgmt_frm_sub_type; /* to indicate which sub-type of MGMT frame */
+ A_UINT32 is_my_frame; /* to indicate frame is sent to this BSSID */
+} wmi_is_my_mgmt_frame;
+
+typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_ml_info */
/**
* CU vdev map to initmate about the on-going Critical update
@@ -10048,6 +10058,14 @@
A_UINT32 fwd_count;
} wmi_iface_offload_stats;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_powersave_stats */
+ /** Total TIM beacon event that wlan ps received **/
+ A_UINT32 tot_tim_bcn;
+ /** Total error TIM beacon found by wlan ps including no rx in TIM wakeup and TIM event in active state **/
+ A_UINT32 tot_err_tim_bcn;
+} wmi_iface_powersave_stats;
+
/** Interface statistics (once started) reset and start afresh after each connection */
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_iface_link_stats_event_fixed_param */
@@ -10062,6 +10080,7 @@
* wmi_iface_link_stats iface_link_stats;
* num_ac * size of(struct wmi_wmm_ac_stats)
* wmi_iface_offload_stats iface_offload_stats[num_offload_stats]
+ * wmi_iface_powersave_stats iface_powersave_stats[]
*/
} wmi_iface_link_stats_event_fixed_param;
@@ -12073,6 +12092,10 @@
#define WMI_MLO_FLAGS_SET_PEER_ID_VALID(mlo_flags, value) WMI_SET_BITS(mlo_flags, 4, 1, value)
#define WMI_MLO_FLAGS_GET_MCAST_VDEV(mlo_flags) WMI_GET_BITS(mlo_flags, 5, 1)
#define WMI_MLO_FLAGS_SET_MCAST_VDEV(mlo_flags, value) WMI_SET_BITS(mlo_flags, 5, 1, value)
+#define WMI_MLO_FLAGS_GET_EMLSR_SUPPORT(mlo_flags) WMI_GET_BITS(mlo_flags, 6, 1)
+#define WMI_MLO_FLAGS_SET_EMLSR_SUPPORT(mlo_flags, value) WMI_SET_BITS(mlo_flags, 6, 1, value)
+#define WMI_MLO_FLAGS_GET_FORCE_LINK_INACTIVE(mlo_flags) WMI_GET_BITS(mlo_flags, 7, 1)
+#define WMI_MLO_FLAGS_SET_FORCE_LINK_INACTIVE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 7, 1, value)
/* this structure used for pass mlo flags*/
typedef struct {
@@ -14110,6 +14133,11 @@
*/
WMI_VDEV_PARAM_VDEV_TRAFFIC_CONFIG, /* 0xB6 */
+ /* Final bmiss time for Non WOW mode in sec */
+ WMI_VDEV_PARAM_FINAL_BMISS_TIME_SEC, /* 0xB7 */
+ /* Final bmiss time for WOW mode in sec */
+ WMI_VDEV_PARAM_FINAL_BMISS_TIME_WOW_SEC, /* 0xB8 */
+
/*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
* The below vdev param types are used for prototyping, and are
@@ -16348,6 +16376,10 @@
A_UINT32 ieee_link_id;
/** eMLSR transition timeout in microseconds */
A_UINT32 emlsr_trans_timeout_us;
+ /** eMLSR transition delay in microseconds */
+ A_UINT32 emlsr_trans_delay_us;
+ /** eMLSR padding delay in microseconds */
+ A_UINT32 emlsr_padding_delay_us;
} wmi_peer_assoc_mlo_params;
typedef struct {
@@ -18072,6 +18104,23 @@
A_UINT32 notif_params1;
} wmi_roam_event_fixed_param;
+#define WMI_ROAM_BSS_INFO_FLAG_IS_MLD 0
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_bss_info_param */
+ /*
+ * bit0: WMI_ROAM_BSS_INFO_FLAG_IS_MLD
+ */
+ A_UINT32 flags;
+ /*
+ * mld score if WMI_ROAM_BSS_INFO_FLAG_IS_MLD set, otherwise link score
+ */
+ A_UINT32 score;
+ /*
+ * mld address if WMI_ROAM_BSS_INFO_FLAG_IS_MLD set, otherwise link address
+ */
+ wmi_mac_addr mac_addr;
+} wmi_roam_bss_info_param;
/* roam_reason: bits 0-3 */
#define WMI_ROAM_REASON_INVALID 0x0 /** invalid reason. Do not interpret reason field */
@@ -18965,6 +19014,8 @@
WOW_REASON_DELAYED_WAKEUP_HOST_CFG_TIMER_ELAPSED,
/* Data store list is full, so Host wakeup should be triggered */
WOW_REASON_DELAYED_WAKEUP_DATA_STORE_LIST_FULL,
+ /* Sched PM FW initiated termination event */
+ WOW_REASON_SCHED_PM_TERMINATED,
/* add new WOW_REASON_ defs before this line */
WOW_REASON_MAX,
@@ -24219,6 +24270,9 @@
A_UINT32 vdev_id;
/* Exact frame length without considering 4 byte alignement */
A_UINT32 frame_length;
+ A_INT32 rssi; /* Units in dBm */
+ /* The frequency on which to transmit. */
+ A_UINT32 primary_channel_freq; /* MHz units */
/**
* TLV (tag length value) parameters follows roam_frame_event
* The TLV's are:
@@ -29514,6 +29568,18 @@
A_UINT32 config_arg6;
} WMI_COEX_CONFIG_CMD_fixed_param;
+typedef enum wmi_coex_dbam_mode_type {
+ WMI_COEX_DBAM_DISABLE = 0,
+ WMI_COEX_DBAM_ENABLE = 1,
+ WMI_COEX_DBAM_FORCED = 2,
+} WMI_COEX_DBAM_MODE_TYPE;
+
+typedef struct {
+ A_UINT32 tlv_header;
+ A_UINT32 vdev_id;
+ A_UINT32 dbam_mode; /* wmi_coex_dbam_mode_type enum */
+} wmi_coex_dbam_cmd_fixed_param;
+
/**
* This command is sent from WLAN host driver to firmware to
* request firmware to enable/disable channel avoidance report
@@ -30099,6 +30165,45 @@
#define WMI_NSS_RATIO_INFO_GET(dword) \
WMI_GET_BITS(dword, WMI_NSS_RATIO_INFO_BITPOS, 4)
+/*
+ * 11BE EML Capability Set and Get macros
+ */
+#define WMI_SUPPORT_EMLSR_GET(eml_capability) WMI_GET_BITS(eml_capability, 0, 1)
+#define WMI_SUPPORT_EMLSR_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 0, 1, value)
+
+#define WMI_EMLSR_PADDING_DELAY_GET(eml_capability) WMI_GET_BITS(eml_capability, 1, 3)
+#define WMI_EMLSR_PADDING_DELAY_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 1, 3, value)
+
+#define WMI_EMLSR_TRANSITION_DELAY_GET(eml_capability) WMI_GET_BITS(eml_capability, 4, 3)
+#define WMI_EMLSR_TRANSITION_DELAY_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 4, 3, value)
+
+#define WMI_SUPPORT_EMLMR_GET(eml_capability) WMI_GET_BITS(eml_capability, 7, 1)
+#define WMI_SUPPORT_EMLMR_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 7, 1, value)
+
+#define WMI_EMLMR_DELAY_GET(eml_capability) WMI_GET_BITS(eml_capability, 8, 3)
+#define WMI_EMLMR_DELAY_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 8, 3, value)
+
+#define WMI_TRANSITION_TIMEOUT_GET(eml_capability) WMI_GET_BITS(eml_capability, 11, 4)
+#define WMI_TRANSITION_TIMEOUT_SET(eml_capability, value) WMI_SET_BITS(eml_capability, 11, 4, value)
+
+/*
+ * 11BE MLD Capability Set and Get macros
+ */
+#define WMI_MAX_NUM_SIMULTANEOUS_LINKS_GET(mld_capability) WMI_GET_BITS(mld_capability, 0, 4)
+#define WMI_MAX_NUM_SIMULTANEOUS_LINKS_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 0, 4, value)
+
+#define WMI_SUPPORT_SRS_GET(mld_capability) WMI_GET_BITS(mld_capability, 4, 1)
+#define WMI_SUPPORT_SRS_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 4, 1, value)
+
+#define WMI_TID_TO_LINK_NEGOTIATION_GET(mld_capability) WMI_GET_BITS(mld_capability, 5, 2)
+#define WMI_TID_TO_LINK_NEGOTIATION_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 5, 2, value)
+
+#define WMI_FREQ_SEPERATION_STR_GET(mld_capability) WMI_GET_BITS(mld_capability, 7, 5)
+#define WMI_FREQ_SEPERATION_STR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 7, 5, value)
+
+#define WMI_SUPPORT_AAR_GET(mld_capability) WMI_GET_BITS(mld_capability, 12, 1)
+#define WMI_SUPPORT_AAR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 12, 1, value)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */
/* hw_mode_id - identify a particular set of HW characteristics, as specified
@@ -30348,11 +30453,32 @@
*/
A_UINT32 eht_supp_mcs_ext_2G[WMI_MAX_EHT_SUPP_MCS_2G_SIZE];
A_UINT32 eht_supp_mcs_ext_5G[WMI_MAX_EHT_SUPP_MCS_5G_SIZE];
- /**************************************************************************
- * Currently pls do not add any new param after EHT
- * as still under development.
- * We can add new param before it.
- **************************************************************************/
+ union {
+ struct {
+ A_UINT32 emlsr_support:1,
+ emlsr_padding_delay:3,
+ emlsr_transition_delay:3,
+ emlmr_support:1,
+ emlmr_delay:3,
+ transition_timeout:4,
+ reserved: 17;
+ };
+ A_UINT32 eml_capability;
+ };
+ union {
+ struct {
+ A_UINT32 max_num_simultaneous_links:4,
+ srs_support:1,
+ tid_to_link_negotiation_support:2, /* Set to 0 if TID-to-link mapping is not supported by the MLD.
+ * Set to 1 if MLD supports the mapping of each TID to the same or different link set.
+ * Set to 2 if MLD only supports the mapping of all TIDs to the same link set.
+ * Value 3 is reserved */
+ freq_separation_str:5,
+ aar_support:1,
+ reserved2: 19;
+ };
+ A_UINT32 mld_capability;
+ };
} WMI_MAC_PHY_CAPABILITIES_EXT;
typedef struct {
@@ -31624,6 +31750,7 @@
WMI_RETURN_STRING(WMI_WOW_COAP_ADD_KEEPALIVE_PATTERN_CMDID);
WMI_RETURN_STRING(WMI_WOW_COAP_DEL_KEEPALIVE_PATTERN_CMDID);
WMI_RETURN_STRING(WMI_WOW_COAP_GET_BUF_INFO_CMDID);
+ WMI_RETURN_STRING(WMI_COEX_DBAM_CMDID);
}
return (A_UINT8 *) "Invalid WMI cmd";
@@ -32280,6 +32407,23 @@
} wmi_coex_report_isolation_event_fixed_param;
typedef enum {
+ WMI_COEX_DBAM_COMP_SUCCESS = 0, /* success, mode is applied */
+ WMI_COEX_DBAM_COMP_ONGOING = 1, /* success, mode is applied */
+ WMI_COEX_DBAM_COMP_DELAYED = 2, /* DBAM is delayed and TDD is selected temporarily */
+ WMI_COEX_DBAM_COMP_NOT_SUPPORT = 3, /* DBAM is not supported */
+ WMI_COEX_DBAM_COMP_TEST_MODE = 4, /* ignore due to test mode */
+ WMI_COEX_DBAM_COMP_INVALID_PARAM = 5, /* invalid parameter is received */
+ WMI_COEX_DBAM_COMP_FAIL = 6, /* command failed */
+} wmi_coex_dbam_comp_status;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_coex_dbam_complete_event_fixed_param */
+ A_UINT32 tlv_header;
+ A_UINT32 comp_status; /* wmi_coex_dbam_comp_status */
+} wmi_coex_dbam_complete_event_fixed_param;
+
+typedef enum {
WMI_RCPI_MEASUREMENT_TYPE_AVG_MGMT = 1,
WMI_RCPI_MEASUREMENT_TYPE_AVG_DATA = 2,
WMI_RCPI_MEASUREMENT_TYPE_LAST_MGMT = 3,
@@ -32478,6 +32622,7 @@
WMI_PDEV_ROUTING_TYPE_IPV4,
WMI_PDEV_ROUTING_TYPE_IPV6,
WMI_PDEV_ROUTING_TYPE_EAP,
+ WMI_PDEV_ROUTING_TYPE_VLAN,
} wmi_pdev_pkt_routing_type;
typedef enum {
@@ -34512,6 +34657,8 @@
ROAM_VENDOR_CONTROL_PARAM_PASSIVE_CH_DWELLTIME,
ROAM_VENDOR_CONTROL_PARAM_HOME_CH_TIME,
ROAM_VENDOR_CONTROL_PARAM_AWAY_TIME,
+ /* Sending query for all roam_vendor_control_param */
+ ROAM_VENDOR_CONTROL_PARAM_ALL = 0xFFFFFFFF,
} WMI_ROAM_GET_VENDOR_CONTROL_PARAM_ID;
typedef struct {
@@ -34528,12 +34675,25 @@
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_get_vendor_control_param_event_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
A_UINT32 vdev_id;
- /** Vendor Control Param ID from enum WMI_ROAM_GET_VENDOR_CONTROL_PARAM_ID */
+ /**
+ * Vendor Control Param ID from enum WMI_ROAM_GET_VENDOR_CONTROL_PARAM_ID
+ * If param_id is ROAM_VENDOR_CONTROL_PARAM_ALL, send all vendor control
+ * param value defined in enum WMI_ROAM_GET_VENDOR_CONTROL_PARAM_ID
+ * using wmi_vendor_control_param tlv
+ */
A_UINT32 param_id;
/** Vendor control param value */
A_UINT32 param_value;
} wmi_roam_get_vendor_control_param_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vendor_control_param */
+ /** Vendor Control Param ID from enum WMI_ROAM_GET_VENDOR_CONTROL_PARAM_ID */
+ A_UINT32 param_id;
+ /** Vendor control param value */
+ A_UINT32 param_value;
+} wmi_vendor_control_param;
+
/** the definition of different ROAM parameters */
typedef enum {
/* roam param to configure below roam events
@@ -36414,7 +36574,15 @@
#define WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 8, 1)
#define WMI_EHTCAP_MAC_MAXAMPDULEN_EXP_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 8, 1, value)
-/* Bit 9-15: reserved */
+/* Bit 9: EHT TRS support */
+#define WMI_EHTCAP_MAC_TRS_SUPPORT_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 9, 1)
+#define WMI_EHTCAP_MAC_TRS_SUPPORT_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 9, 1, value)
+
+/* Bit 10: TXOP return support in txop sharing mode 2 */
+#define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 10, 1)
+#define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 10, 1, value)
+
+/* Bit 11-15: reserved */
/****** End of 11BE EHT MAC Capabilities Information field ******/
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index da2989a..cfeaed8 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -37,7 +37,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
-#define __WMI_REVISION_ 1161
+#define __WMI_REVISION_ 1172
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
diff --git a/hw/qca8074/v2/phyrx_other_receive_info_su_evm_details.h b/hw/qca8074/v2/phyrx_other_receive_info_su_evm_details.h
new file mode 100644
index 0000000..b6ae2b3
--- /dev/null
+++ b/hw/qca8074/v2/phyrx_other_receive_info_su_evm_details.h
@@ -0,0 +1,900 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT! This file is automatically generated
+// These definitions are tied to a particular hardware layout
+
+
+#ifndef _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
+#define _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 number_of_symbols[15:0], nss_count[23:16], pilot_count[31:24]
+// 1 pilot_0_evm[31:0]
+// 2 pilot_1_evm[31:0]
+// 3 pilot_2_evm[31:0]
+// 4 pilot_3_evm[31:0]
+// 5 pilot_4_evm[31:0]
+// 6 pilot_5_evm[31:0]
+// 7 pilot_6_evm[31:0]
+// 8 pilot_7_evm[31:0]
+// 9 pilot_8_evm[31:0]
+// 10 pilot_9_evm[31:0]
+// 11 pilot_10_evm[31:0]
+// 12 pilot_11_evm[31:0]
+// 13 pilot_12_evm[31:0]
+// 14 pilot_13_evm[31:0]
+// 15 pilot_14_evm[31:0]
+// 16 pilot_15_evm[31:0]
+// 17 pilot_16_evm[31:0]
+// 18 pilot_17_evm[31:0]
+// 19 pilot_18_evm[31:0]
+// 20 pilot_19_evm[31:0]
+// 21 pilot_20_evm[31:0]
+// 22 pilot_21_evm[31:0]
+// 23 pilot_22_evm[31:0]
+// 24 pilot_23_evm[31:0]
+// 25 pilot_24_evm[31:0]
+// 26 pilot_25_evm[31:0]
+// 27 pilot_26_evm[31:0]
+// 28 pilot_27_evm[31:0]
+// 29 pilot_28_evm[31:0]
+// 30 pilot_29_evm[31:0]
+// 31 pilot_30_evm[31:0]
+// 32 pilot_31_evm[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS 33
+
+struct phyrx_other_receive_info_su_evm_details {
+ uint32_t number_of_symbols : 16, //[15:0]
+ nss_count : 8, //[23:16]
+ pilot_count : 8; //[31:24]
+ uint32_t pilot_0_evm : 32; //[31:0]
+ uint32_t pilot_1_evm : 32; //[31:0]
+ uint32_t pilot_2_evm : 32; //[31:0]
+ uint32_t pilot_3_evm : 32; //[31:0]
+ uint32_t pilot_4_evm : 32; //[31:0]
+ uint32_t pilot_5_evm : 32; //[31:0]
+ uint32_t pilot_6_evm : 32; //[31:0]
+ uint32_t pilot_7_evm : 32; //[31:0]
+ uint32_t pilot_8_evm : 32; //[31:0]
+ uint32_t pilot_9_evm : 32; //[31:0]
+ uint32_t pilot_10_evm : 32; //[31:0]
+ uint32_t pilot_11_evm : 32; //[31:0]
+ uint32_t pilot_12_evm : 32; //[31:0]
+ uint32_t pilot_13_evm : 32; //[31:0]
+ uint32_t pilot_14_evm : 32; //[31:0]
+ uint32_t pilot_15_evm : 32; //[31:0]
+ uint32_t pilot_16_evm : 32; //[31:0]
+ uint32_t pilot_17_evm : 32; //[31:0]
+ uint32_t pilot_18_evm : 32; //[31:0]
+ uint32_t pilot_19_evm : 32; //[31:0]
+ uint32_t pilot_20_evm : 32; //[31:0]
+ uint32_t pilot_21_evm : 32; //[31:0]
+ uint32_t pilot_22_evm : 32; //[31:0]
+ uint32_t pilot_23_evm : 32; //[31:0]
+ uint32_t pilot_24_evm : 32; //[31:0]
+ uint32_t pilot_25_evm : 32; //[31:0]
+ uint32_t pilot_26_evm : 32; //[31:0]
+ uint32_t pilot_27_evm : 32; //[31:0]
+ uint32_t pilot_28_evm : 32; //[31:0]
+ uint32_t pilot_29_evm : 32; //[31:0]
+ uint32_t pilot_30_evm : 32; //[31:0]
+ uint32_t pilot_31_evm : 32; //[31:0]
+};
+
+/*
+
+number_of_symbols
+
+ The number of symbols over which this EVM measurement
+ was done
+
+ <legal all>
+
+nss_count
+
+ The number of Spatial Streams in this SU reception.
+
+ <legal 1-8>
+
+pilot_count
+
+ The number of pilots captured per Spatial Stream in this
+ log
+
+ <legal 1-32>
+
+pilot_0_evm
+
+
+
+
+ Example mapping of Nss and pilots to the evm fields:
+
+ With NSS_count = 2, Pilot_count = 3
+
+ Pilot_0_evm => NSS 0, Pilot 0
+
+ Pilot_1_evm => NSS 1, Pilot 0
+
+ Pilot_2_evm => NSS 0, Pilot 1
+
+ Pilot_3_evm => NSS 1, Pilot 1
+
+ Pilot_4_evm => NSS 0, Pilot 2
+
+ Pilot_5_evm => NSS 1, Pilot 2
+
+
+
+ <legal all>
+
+pilot_1_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_2_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_3_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_4_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_5_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_6_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_7_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_8_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_9_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_10_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_11_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_12_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_13_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_14_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_15_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_16_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_17_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_18_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_19_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_20_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_21_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_22_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_23_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_24_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_25_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_26_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_27_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_28_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_29_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_30_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+
+pilot_31_evm
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS
+
+ The number of symbols over which this EVM measurement
+ was done
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS_MASK 0x0000ffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT
+
+ The number of Spatial Streams in this SU reception.
+
+ <legal 1-8>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_LSB 16
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_NSS_COUNT_MASK 0x00ff0000
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT
+
+ The number of pilots captured per Spatial Stream in this
+ log
+
+ <legal 1-32>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_OFFSET 0x00000000
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_LSB 24
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_0_PILOT_COUNT_MASK 0xff000000
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM
+
+
+
+
+ Example mapping of Nss and pilots to the evm fields:
+
+ With NSS_count = 2, Pilot_count = 3
+
+ Pilot_0_evm => NSS 0, Pilot 0
+
+ Pilot_1_evm => NSS 1, Pilot 0
+
+ Pilot_2_evm => NSS 0, Pilot 1
+
+ Pilot_3_evm => NSS 1, Pilot 1
+
+ Pilot_4_evm => NSS 0, Pilot 2
+
+ Pilot_5_evm => NSS 1, Pilot 2
+
+
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_OFFSET 0x00000004
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_1_PILOT_0_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_OFFSET 0x00000008
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_2_PILOT_1_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_OFFSET 0x0000000c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_3_PILOT_2_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_OFFSET 0x00000010
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_4_PILOT_3_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_OFFSET 0x00000014
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_5_PILOT_4_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_OFFSET 0x00000018
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_6_PILOT_5_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_OFFSET 0x0000001c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_7_PILOT_6_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_OFFSET 0x00000020
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_8_PILOT_7_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_OFFSET 0x00000024
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_9_PILOT_8_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_OFFSET 0x00000028
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_10_PILOT_9_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_OFFSET 0x0000002c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_11_PILOT_10_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_OFFSET 0x00000030
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_12_PILOT_11_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_OFFSET 0x00000034
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_13_PILOT_12_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_OFFSET 0x00000038
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_14_PILOT_13_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_OFFSET 0x0000003c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_15_PILOT_14_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_OFFSET 0x00000040
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_16_PILOT_15_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_OFFSET 0x00000044
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_17_PILOT_16_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_OFFSET 0x00000048
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_18_PILOT_17_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_OFFSET 0x0000004c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_19_PILOT_18_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_OFFSET 0x00000050
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_20_PILOT_19_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_OFFSET 0x00000054
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_21_PILOT_20_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_OFFSET 0x00000058
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_22_PILOT_21_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_OFFSET 0x0000005c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_23_PILOT_22_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_OFFSET 0x00000060
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_24_PILOT_23_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_OFFSET 0x00000064
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_25_PILOT_24_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_OFFSET 0x00000068
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_26_PILOT_25_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_OFFSET 0x0000006c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_27_PILOT_26_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_OFFSET 0x00000070
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_28_PILOT_27_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_OFFSET 0x00000074
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_29_PILOT_28_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_OFFSET 0x00000078
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_30_PILOT_29_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_OFFSET 0x0000007c
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_31_PILOT_30_EVM_MASK 0xffffffff
+
+/* Description PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM
+
+
+
+
+ See Pilot_0_evm descriptions details for mapping info
+
+ <legal all>
+*/
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_OFFSET 0x00000080
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_LSB 0
+#define PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_32_PILOT_31_EVM_MASK 0xffffffff
+
+
+#endif // _PHYRX_OTHER_RECEIVE_INFO_SU_EVM_DETAILS_H_
diff --git a/hw/qca8074/v2/phyrx_pkt_end_info.h b/hw/qca8074/v2/phyrx_pkt_end_info.h
new file mode 100644
index 0000000..84e06c0
--- /dev/null
+++ b/hw/qca8074/v2/phyrx_pkt_end_info.h
@@ -0,0 +1,1901 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT! This file is automatically generated
+// These definitions are tied to a particular hardware layout
+
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_location_info.h"
+#include "rx_timing_offset_info.h"
+#include "receive_rssi_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27]
+// 1 phy_timestamp_1_lower_32[31:0]
+// 2 phy_timestamp_1_upper_32[31:0]
+// 3 phy_timestamp_2_lower_32[31:0]
+// 4 phy_timestamp_2_upper_32[31:0]
+// 5-13 struct rx_location_info rx_location_info_details;
+// 14 struct rx_timing_offset_info rx_timing_offset_info_details;
+// 15-30 struct receive_rssi_info post_rssi_info_details;
+// 31 phy_sw_status_31_0[31:0]
+// 32 phy_sw_status_63_32[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
+
+struct phyrx_pkt_end_info {
+ uint32_t phy_internal_nap : 1, //[0]
+ location_info_valid : 1, //[1]
+ timing_info_valid : 1, //[2]
+ rssi_info_valid : 1, //[3]
+ rx_frame_correction_needed : 1, //[4]
+ frameless_frame_received : 1, //[5]
+ reserved_0a : 6, //[11:6]
+ dl_ofdma_info_valid : 1, //[12]
+ dl_ofdma_ru_start_index : 7, //[19:13]
+ dl_ofdma_ru_width : 7, //[26:20]
+ reserved_0b : 5; //[31:27]
+ uint32_t phy_timestamp_1_lower_32 : 32; //[31:0]
+ uint32_t phy_timestamp_1_upper_32 : 32; //[31:0]
+ uint32_t phy_timestamp_2_lower_32 : 32; //[31:0]
+ uint32_t phy_timestamp_2_upper_32 : 32; //[31:0]
+ struct rx_location_info rx_location_info_details;
+ struct rx_timing_offset_info rx_timing_offset_info_details;
+ struct receive_rssi_info post_rssi_info_details;
+ uint32_t phy_sw_status_31_0 : 32; //[31:0]
+ uint32_t phy_sw_status_63_32 : 32; //[31:0]
+};
+
+/*
+
+phy_internal_nap
+
+ When set, PHY RX entered an internal NAP state, as PHY
+ determined that this reception was not destined to this
+ device
+
+location_info_valid
+
+ Indicates that the RX_LOCATION_INFO structure later on
+ in the TLV contains valid info
+
+timing_info_valid
+
+ Indicates that the RX_TIMING_OFFSET_INFO structure later
+ on in the TLV contains valid info
+
+rssi_info_valid
+
+ Indicates that the RECEIVE_RSSI_INFO structure later on
+ in the TLV contains valid info
+
+rx_frame_correction_needed
+
+ When clear, no action is needed in the MAC.
+
+
+
+ When set, the falling edge of the rx_frame happened 4us
+ too late. MAC will need to compensate for this delay in
+ order to maintain proper SIFS timing and/or not to get
+ de-slotted.
+
+
+
+ PHY uses this for very short 11a frames.
+
+
+
+ When set, PHY will have passed this TLV to the MAC up to
+ 8 us into the 'real SIFS' time, and thus within 4us from the
+ falling edge of the rx_frame.
+
+
+
+ <legal all>
+
+frameless_frame_received
+
+ When set, PHY has received the 'frameless frame' . Can
+ be used in the 'MU-RTS -CTS exchange where CTS reception can
+ be problematic.
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+
+dl_ofdma_info_valid
+
+ When set, the following DL_ofdma_... fields are valid.
+
+ It provides the MAC insight into which RU was allocated
+ to this device.
+
+ <legal all>
+
+dl_ofdma_ru_start_index
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0 and
+ in increasing frequency order and not primary-secondary
+ order
+
+ <legal 0-73>
+
+dl_ofdma_ru_width
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+
+reserved_0b
+
+ <legal 0>
+
+phy_timestamp_1_lower_32
+
+ TODO PHY: cleanup descriptionThe PHY timestamp in the
+ AMPI of the first rising edge of rx_clear_pri after
+ TX_PHY_DESC. . This field should set to 0 by the PHY and
+ should be updated by the AMPI before being forwarded to the
+ rest of the MAC. This field indicates the lower 32 bits of
+ the timestamp
+
+phy_timestamp_1_upper_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the first rising edge
+ of rx_clear_pri after TX_PHY_DESC. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+
+phy_timestamp_2_lower_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ lower 32 bits of the timestamp
+
+phy_timestamp_2_upper_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+
+struct rx_location_info rx_location_info_details
+
+ Overview of location related info
+
+struct rx_timing_offset_info rx_timing_offset_info_details
+
+ Overview of timing offset related info
+
+struct receive_rssi_info post_rssi_info_details
+
+ Overview of the post-RSSI values.
+
+phy_sw_status_31_0
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+
+phy_sw_status_63_32
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+
+
+/* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP
+
+ When set, PHY RX entered an internal NAP state, as PHY
+ determined that this reception was not destined to this
+ device
+*/
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID
+
+ Indicates that the RX_LOCATION_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID
+
+ Indicates that the RX_TIMING_OFFSET_INFO structure later
+ on in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID
+
+ Indicates that the RECEIVE_RSSI_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED
+
+ When clear, no action is needed in the MAC.
+
+
+
+ When set, the falling edge of the rx_frame happened 4us
+ too late. MAC will need to compensate for this delay in
+ order to maintain proper SIFS timing and/or not to get
+ de-slotted.
+
+
+
+ PHY uses this for very short 11a frames.
+
+
+
+ When set, PHY will have passed this TLV to the MAC up to
+ 8 us into the 'real SIFS' time, and thus within 4us from the
+ falling edge of the rx_frame.
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+/* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED
+
+ When set, PHY has received the 'frameless frame' . Can
+ be used in the 'MU-RTS -CTS exchange where CTS reception can
+ be problematic.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+/* Description PHYRX_PKT_END_INFO_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID
+
+ When set, the following DL_ofdma_... fields are valid.
+
+ It provides the MAC insight into which RU was allocated
+ to this device.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0 and
+ in increasing frequency order and not primary-secondary
+ order
+
+ <legal 0-73>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000
+
+/* Description PHYRX_PKT_END_INFO_0_RESERVED_0B
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000
+
+/* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32
+
+ TODO PHY: cleanup descriptionThe PHY timestamp in the
+ AMPI of the first rising edge of rx_clear_pri after
+ TX_PHY_DESC. . This field should set to 0 by the PHY and
+ should be updated by the AMPI before being forwarded to the
+ rest of the MAC. This field indicates the lower 32 bits of
+ the timestamp
+*/
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the first rising edge
+ of rx_clear_pri after TX_PHY_DESC. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ lower 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the first selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the second selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the first
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the second
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS
+
+ Status of rtt_fac_legacy
+
+
+
+ <enum 0 location_fac_legacy_status_not_valid>
+
+ <enum 1 location_fac_legacy_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS
+
+ Status of rtt_fac_legacy_ext80
+
+
+
+ <enum 0 location_fac_legacy_ext80_status_not_valid>
+
+ <enum 1 location_fac_legacy_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS
+
+ Status of rtt_fac_vht
+
+
+
+ <enum 0 location_fac_vht_status_not_valid>
+
+ <enum 1 location_fac_vht_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS
+
+ Status of rtt_fac_vht_ext80
+
+
+
+ <enum 0 location_fac_vht_ext80_status_not_valid>
+
+ <enum 1 location_fac_vht_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS
+
+ To support fine SIFS adjustment, need to provide FAC
+ value @ integer number of 320 MHz clock cycles to MAC. It
+ is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+ if it is a (V)HT/HE packet
+
+
+
+ 12 bits, signed, no fractional part
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS
+
+ Status of rtt_fac_sifs
+
+ 0: not valid
+
+ 1: valid and from L-LTF
+
+ 2: valid and from (V)HT/HE-LTF
+
+ 3: reserved
+
+ <legal 0-2>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS
+
+ Status of channel frequency response dump
+
+
+
+ <enum 0 location_CFR_dump_not_valid>
+
+ <enum 1 location_CFR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS
+
+ Status of channel impulse response dump
+
+
+
+ <enum 0 location_CIR_dump_not_valid>
+
+ <enum 1 location_CIR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE
+
+ Channel dump size. It shows how many tones in CFR in
+ one chain, for example, it will show 52 for Legacy20 and 484
+ for VHT160
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE
+
+ Indicator showing if HW IFFT mode or SW IFFT mode
+
+
+
+ <enum 0 location_sw_ifft_mode>
+
+ <enum 1 location_hw_ifft_mode>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS
+
+ Indicate if BTCF is used to capture the timestamps
+
+
+
+ <enum 0 location_not_BTCF_based_ts>
+
+ <enum 1 location_BTCF_based_ts>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE
+
+ Indicate preamble type
+
+
+
+ <enum 0 location_preamble_type_legacy>
+
+ <enum 1 location_preamble_type_ht>
+
+ <enum 2 location_preamble_type_vht>
+
+ <enum 3 location_preamble_type_he_su_4xltf>
+
+ <enum 4 location_preamble_type_he_su_2xltf>
+
+ <enum 5 location_preamble_type_he_su_1xltf>
+
+ <enum 6
+ location_preamble_type_he_trigger_based_ul_4xltf>
+
+ <enum 7
+ location_preamble_type_he_trigger_based_ul_2xltf>
+
+ <enum 8
+ location_preamble_type_he_trigger_based_ul_1xltf>
+
+ <enum 9 location_preamble_type_he_mu_4xltf>
+
+ <enum 10 location_preamble_type_he_mu_2xltf>
+
+ <enum 11 location_preamble_type_he_mu_1xltf>
+
+ <enum 12
+ location_preamble_type_he_extended_range_su_4xltf>
+
+ <enum 13
+ location_preamble_type_he_extended_range_su_2xltf>
+
+ <enum 14
+ location_preamble_type_he_extended_range_su_1xltf>
+
+ <legal 0-14>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG
+
+ Indicate the bandwidth of L-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT
+
+ Indicate the bandwidth of (V)HT/HE-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE
+
+ Indicate GI (guard interval) type
+
+
+
+ <enum 0 gi_0_8_us > HE related GI. Can also be used
+ for HE
+
+ <enum 1 gi_0_4_us > HE related GI. Can also be used
+ for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE
+
+ Bits 0~4 indicate MCS rate, if Legacy,
+
+ 0: 48 Mbps,
+
+ 1: 24 Mbps,
+
+ 2: 12 Mbps,
+
+ 3: 6 Mbps,
+
+ 4: 54 Mbps,
+
+ 5: 36 Mbps,
+
+ 6: 18 Mbps,
+
+ 7: 9 Mbps,
+
+
+
+ if HT, 0-7: MCS0-MCS7,
+
+ if VHT, 0-9: MCS0-MCS9,
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN
+
+ For 20/40/80, this field shows the first selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected pri80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80
+
+ For 20/40/80, this field shows the second selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected ext80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK
+
+ Rx chain mask, each bit is a Rx chain
+
+ 0: the Rx chain is not used
+
+ 1: the Rx chain is used
+
+ Support up to 8 Rx chains
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS
+
+ RX packet start timestamp
+
+
+
+ It reports the time the first L-STF ADC sample arrived
+ at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS
+
+ RX packet end timestamp
+
+
+
+ It reports the time the last symbol's last ADC sample
+ arrived at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START
+
+ The phase of the SFO of the first symbol's first FFT
+ input sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END
+
+ The phase of the SFO of the last symbol's last FFT input
+ sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8
+
+ The high 8 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 8 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32
+
+ The low 32 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 32 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT
+
+ CFO measurement. Needed for passive locationing
+
+
+
+ 14 bits, signed 1.13. 13 bits fraction to provide a
+ resolution of 153 Hz
+
+
+
+ In units of cycles/800 ns
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD
+
+ Channel delay spread measurement. Needed for selecting
+ GI length
+
+
+
+ 8 bits, unsigned. At 25 ns step. Can represent up to
+ 6375 ns
+
+
+
+ In units of cycles @ 40 MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL
+
+ Indicate which timing backoff value is used
+
+
+
+ <enum 0 timing_backoff_low_rssi>
+
+ <enum 1 timing_backoff_mid_rssi>
+
+ <enum 2 timing_backoff_high_rssi>
+
+ <enum 3 reserved>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID
+
+ <enum 0 rx_location_info_is_not_valid>
+
+ <enum 1 rx_location_info_is_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET
+
+ Cumulative reference frequency error at end of RX
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+
+#endif // _PHYRX_PKT_END_INFO_H_
diff --git a/hw/qca8074/v2/reo_entrance_ring.h b/hw/qca8074/v2/reo_entrance_ring.h
new file mode 100644
index 0000000..e7662a5
--- /dev/null
+++ b/hw/qca8074/v2/reo_entrance_ring.h
@@ -0,0 +1,1181 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT! This file is automatically generated
+// These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info;
+// 4 rx_reo_queue_desc_addr_31_0[31:0]
+// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
+// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], reserved_6a[31:11]
+// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+ struct rx_mpdu_details reo_level_mpdu_frame_info;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ rounded_mpdu_byte_count : 14, //[21:8]
+ reo_destination_indication : 5, //[26:22]
+ frameless_bar : 1, //[27]
+ reserved_5a : 4; //[31:28]
+ uint32_t rxdma_push_reason : 2, //[1:0]
+ rxdma_error_code : 5, //[6:2]
+ mpdu_fragment_number : 4, //[10:7]
+ reserved_6a : 21; //[31:11]
+ uint32_t reserved_7a : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct rx_mpdu_details reo_level_mpdu_frame_info
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Details related to the MPDU being pushed into the REO
+
+rx_reo_queue_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+
+rounded_mpdu_byte_count
+
+ An approximation of the number of bytes received in this
+ MPDU.
+
+ Used to keeps stats on the amount of data flowing
+ through a queue.
+
+ <legal all>
+
+reo_destination_indication
+
+ RXDMA copy the MPDU's first MSDU's destination
+ indication field here. This is used for REO to be able to
+ re-route the packet to a different SW destination ring if
+ the packet is detected as error in REO.
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_7> REO remaps this
+
+ <enum 8 reo_destination_8> REO remaps this <enum 9
+ reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+frameless_bar
+
+ When set, this REO entrance ring struct contains BAR
+ info from a multi TID BAR frame. The original multi TID BAR
+ frame itself contained all the REO info for the first TID,
+ but all the subsequent TID info and their linkage to the REO
+ descriptors is passed down as 'frameless' BAR info.
+
+
+
+ The only fields valid in this descriptor when this bit
+ is set are:
+
+ Rx_reo_queue_desc_addr_31_0
+
+ RX_reo_queue_desc_addr_39_32
+
+
+
+ And within the
+
+ Reo_level_mpdu_frame_info:
+
+ Within Rx_mpdu_desc_info_details:
+
+ Mpdu_Sequence_number
+
+ BAR_frame
+
+ Peer_meta_data
+
+ All other fields shall be set to 0
+
+
+
+ <legal all>
+
+reserved_5a
+
+ <legal 0>
+
+rxdma_push_reason
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+
+rxdma_error_code
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 Rxdma_flush_request>RXDMA received a flush
+ request
+
+mpdu_fragment_number
+
+ Field only valid when Reo_level_mpdu_frame_info.
+
+ Rx_mpdu_desc_info_details.
+
+ Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in field:
+ Reo_level_mpdu_frame_info.
+
+ Rx_mpdu_desc_info_details.
+
+ Mpdu_Sequence_number
+
+
+
+ <legal all>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+ring_id
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+
+looping_count
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
+
+
+/* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 3
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
+
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
+
+ An approximation of the number of bytes received in this
+ MPDU.
+
+ Used to keeps stats on the amount of data flowing
+ through a queue.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
+
+/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
+
+ RXDMA copy the MPDU's first MSDU's destination
+ indication field here. This is used for REO to be able to
+ re-route the packet to a different SW destination ring if
+ the packet is detected as error in REO.
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_7> REO remaps this
+
+ <enum 8 reo_destination_8> REO remaps this <enum 9
+ reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
+
+/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR
+
+ When set, this REO entrance ring struct contains BAR
+ info from a multi TID BAR frame. The original multi TID BAR
+ frame itself contained all the REO info for the first TID,
+ but all the subsequent TID info and their linkage to the REO
+ descriptors is passed down as 'frameless' BAR info.
+
+
+
+ The only fields valid in this descriptor when this bit
+ is set are:
+
+ Rx_reo_queue_desc_addr_31_0
+
+ RX_reo_queue_desc_addr_39_32
+
+
+
+ And within the
+
+ Reo_level_mpdu_frame_info:
+
+ Within Rx_mpdu_desc_info_details:
+
+ Mpdu_Sequence_number
+
+ BAR_frame
+
+ Peer_meta_data
+
+ All other fields shall be set to 0
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
+
+/* Description REO_ENTRANCE_RING_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
+
+/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
+
+/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 Rxdma_flush_request>RXDMA received a flush
+ request
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
+
+/* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER
+
+ Field only valid when Reo_level_mpdu_frame_info.
+
+ Rx_mpdu_desc_info_details.
+
+ Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in field:
+ Reo_level_mpdu_frame_info.
+
+ Rx_mpdu_desc_info_details.
+
+ Mpdu_Sequence_number
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
+
+/* Description REO_ENTRANCE_RING_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 11
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfffff800
+
+/* Description REO_ENTRANCE_RING_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 0
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000fffff
+
+/* Description REO_ENTRANCE_RING_7_RING_ID
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+*/
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB 20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
+
+/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_ENTRANCE_RING_H_
diff --git a/hw/qca8074/v2/wcss_version.h b/hw/qca8074/v2/wcss_version.h
new file mode 100644
index 0000000..ac51424
--- /dev/null
+++ b/hw/qca8074/v2/wcss_version.h
@@ -0,0 +1,16 @@
+/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 1057