Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 1 | /* |
Gopichand Nakkala | 92f07d8 | 2013-01-08 21:16:34 -0800 | [diff] [blame] | 2 | * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | /* |
Jeff Johnson | 32d95a3 | 2012-09-10 13:15:23 -0700 | [diff] [blame] | 22 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 23 | * |
| 24 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 25 | * |
| 26 | * |
| 27 | * Permission to use, copy, modify, and/or distribute this software for |
| 28 | * any purpose with or without fee is hereby granted, provided that the |
| 29 | * above copyright notice and this permission notice appear in all |
| 30 | * copies. |
| 31 | * |
| 32 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 33 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 34 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 35 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 36 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 37 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 38 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 39 | * PERFORMANCE OF THIS SOFTWARE. |
| 40 | */ |
| 41 | |
| 42 | #ifndef WLAN_PHY_H |
| 43 | #define WLAN_PHY_H |
| 44 | /*============================================================================ |
| 45 | @file wlan_phy.h |
| 46 | |
| 47 | Contains definitions of all PHY related structures that aree needed by FTM/PTT |
| 48 | |
Anand Kumar | 012623a | 2013-01-11 17:00:00 -0800 | [diff] [blame] | 49 | Copyright (c) 2007 Qualcomm Technologies, Inc. All Rights Reserved. |
| 50 | Qualcomm Technologies Proprietary and Confidential |
| 51 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 52 | ============================================================================*/ |
| 53 | #include <wlan_nv.h> |
| 54 | |
| 55 | /* Currently this structure holds the information about the current calibration mode. |
| 56 | In future, if anymore info is needed, that can be added here */ |
| 57 | typedef PACKED_PRE struct PACKED_POST |
| 58 | { |
| 59 | tANI_U8 currentCalibration; |
| 60 | } sCalibrationInfo; |
| 61 | |
| 62 | typedef PACKED_PRE struct PACKED_POST { |
| 63 | tANI_S16 I; //ADC sample of PHY_I_RAIL |
| 64 | tANI_S16 Q; //ADC sample of PHY_Q_RAIL |
| 65 | }tIQSamples; |
| 66 | |
| 67 | typedef tIQSamples tIQAdc; |
| 68 | typedef tIQSamples tIQDac; |
| 69 | |
| 70 | typedef PACKED_PRE struct PACKED_POST |
| 71 | { |
| 72 | tANI_U8 maxGainIndex; |
| 73 | tANI_U8 topGainDb; |
| 74 | tANI_U8 bottomGainDb; |
| 75 | tANI_U8 unused[1]; |
| 76 | }tAsicAgc; |
| 77 | |
| 78 | #define TXFIR_MEM QWLAN_TXFIR_TXCAL_MEM0_MREG |
| 79 | #define TXFIR_MEM_GAIN_MULT (16) //bytes per gain |
| 80 | #define TXFIR_MEM_PER_CHAIN (16 * TXFIR_MEM_GAIN_MULT) //# of gains per chain * bytes per gain |
| 81 | |
| 82 | typedef tIQAdc tTxCarrierError; |
| 83 | |
| 84 | #define ONE_MICROSECOND (160) |
| 85 | #define DEFAULT_INTERFRAME_SPACE (ONE_MICROSECOND * 10) //10 microseconds |
| 86 | |
| 87 | typedef enum { |
| 88 | PHYDBG_TX_IDLE = 0, |
| 89 | PHYDBG_TX_START = 1, |
| 90 | PHYDBG_TX_WARMUP = 2, |
| 91 | PHYDBG_TX_INFD = 3, |
| 92 | PHYDBG_TX_CMD = 4, |
| 93 | PHYDBG_TX_SVC = 5, |
| 94 | PHYDBG_TX_PYLDF = 6, |
| 95 | PHYDBG_TX_PYLDR = 7, |
| 96 | PHYDBG_TX_CRC = 8, |
| 97 | PHYDBG_TX_FLUSH = 9, |
| 98 | PHYDBG_TX_TXDONEWAIT = 10, |
| 99 | PHYDBG_TX_TIFWAIT = 11 |
| 100 | } ePhyDbgTxStatus; |
| 101 | |
| 102 | typedef enum { |
| 103 | PHYDBG_PREAMBLE_OFDM, |
| 104 | PHYDBG_PREAMBLE_GREENFIELD, |
| 105 | PHYDBG_PREAMBLE_MIXED, |
| 106 | PHYDBG_PREAMBLE_SHORTB, |
Gopichand Nakkala | 90bcf7a | 2013-01-04 11:45:31 -0800 | [diff] [blame] | 107 | PHYDBG_PREAMBLE_LONGB, |
| 108 | |
| 109 | PHYDBG_LDPC_PREAMBLE_OFDM = 0x10, |
| 110 | PHYDBG_LDPC_PREAMBLE_GREENFIELD = 0x11, |
| 111 | PHYDBG_LDPC_PREAMBLE_MIXED = 0x12 |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 112 | } ePhyDbgPreamble; |
| 113 | |
| 114 | |
| 115 | //grab ram |
| 116 | #ifdef VERIFY_HALPHY_SIMV_MODEL |
| 117 | #define GRAB_RAM_DBLOCK_SIZE (256) //number of samples in full capture |
| 118 | #else |
| 119 | #define GRAB_RAM_DBLOCK_SIZE (1024) //number of samples in full capture |
| 120 | #endif |
| 121 | |
| 122 | #define MAX_REQUESTED_GRAB_RAM_SAMPLES 256 //only allow 256 samples at a time |
| 123 | #define GRAB_RAM_BUFFER_DEPTH (4*1024) //maximum grab ram size in full capture |
| 124 | #define LAST_GRAB_RAM_SAMPLE_INDEX (GRAB_RAM_BUFFER_DEPTH - 1) |
| 125 | |
| 126 | |
| 127 | typedef PACKED_PRE struct PACKED_POST { |
| 128 | tIQAdc rx0; |
| 129 | } tGrabRamSample; |
| 130 | |
| 131 | |
| 132 | enum { |
| 133 | GRABRAM_RAWADC = 0, |
| 134 | GRABRAM_POSTIQ |
| 135 | }; |
| 136 | typedef tANI_U32 eGrabRamSampleType; |
| 137 | |
| 138 | typedef tANI_S8 tANI_S6; |
| 139 | typedef tANI_S16 tANI_S9; |
| 140 | typedef tANI_S16 tANI_S10; |
| 141 | typedef tANI_S16 tANI_S12; |
| 142 | typedef tANI_U16 tANI_U10; |
| 143 | |
| 144 | |
| 145 | |
| 146 | //convert float to a format that preserves enough accuracy to be used by driver |
| 147 | typedef tANI_S16 t2Decimal; |
| 148 | #define CONVERT_TO_2DECIMAL_PLACES(x) (x * 100) |
| 149 | #define CONVERT_FROM_2DECIMAL_PLACES(x) (x / 100) |
| 150 | |
| 151 | #ifndef PTT_FLOAT |
| 152 | #define PTT_FLOAT tANI_U32 // driver code can't include float, |
| 153 | //so this reserves space in our structures to allow floating point measurements |
| 154 | #endif |
| 155 | |
| 156 | typedef enum |
| 157 | { |
| 158 | PHY_RX_CHAIN_0 = 0, |
| 159 | |
| 160 | PHY_MAX_RX_CHAINS = 1, |
| 161 | PHY_ALL_RX_CHAINS, |
| 162 | PHY_NO_RX_CHAINS |
| 163 | }ePhyRxChains; |
| 164 | |
| 165 | typedef enum |
| 166 | { |
| 167 | PHY_I_RAIL = 0, |
| 168 | PHY_Q_RAIL = 1, |
| 169 | PHY_NUM_IQ_RAILS |
| 170 | }ePhyIQ; |
| 171 | |
| 172 | //[RY] extend total gain steps to 24 |
| 173 | |
| 174 | enum |
| 175 | { |
| 176 | TX_GAIN_STEP_0, |
| 177 | TX_GAIN_STEP_1, |
| 178 | TX_GAIN_STEP_2, |
| 179 | TX_GAIN_STEP_3, |
| 180 | TX_GAIN_STEP_4, |
| 181 | TX_GAIN_STEP_5, |
| 182 | TX_GAIN_STEP_6, |
| 183 | TX_GAIN_STEP_7, |
| 184 | TX_GAIN_STEP_8, |
| 185 | TX_GAIN_STEP_9, |
| 186 | TX_GAIN_STEP_10, |
| 187 | TX_GAIN_STEP_11, |
| 188 | TX_GAIN_STEP_12, |
| 189 | TX_GAIN_STEP_13, |
| 190 | TX_GAIN_STEP_14, |
| 191 | TX_GAIN_STEP_15, |
| 192 | TX_GAIN_STEP_16, |
| 193 | TX_GAIN_STEP_17, |
| 194 | TX_GAIN_STEP_18, |
| 195 | TX_GAIN_STEP_19, |
| 196 | TX_GAIN_STEP_20, |
| 197 | TX_GAIN_STEP_21, |
| 198 | TX_GAIN_STEP_22, |
| 199 | TX_GAIN_STEP_23, |
| 200 | TX_GAIN_STEP_24, |
| 201 | TX_GAIN_STEP_25, |
| 202 | TX_GAIN_STEP_26, |
| 203 | TX_GAIN_STEP_27, |
| 204 | TX_GAIN_STEP_28, |
| 205 | TX_GAIN_STEP_29, |
| 206 | TX_GAIN_STEP_30, |
| 207 | TX_GAIN_STEP_31, |
| 208 | |
| 209 | RX_GAIN_STEP_0 = 0, |
| 210 | RX_GAIN_STEP_1, |
| 211 | RX_GAIN_STEP_2, |
| 212 | RX_GAIN_STEP_3, |
| 213 | RX_GAIN_STEP_4, |
| 214 | RX_GAIN_STEP_5, |
| 215 | RX_GAIN_STEP_6, |
| 216 | RX_GAIN_STEP_7, |
| 217 | RX_GAIN_STEP_8, |
| 218 | RX_GAIN_STEP_9, |
| 219 | RX_GAIN_STEP_10, |
| 220 | RX_GAIN_STEP_11, |
| 221 | RX_GAIN_STEP_12, |
| 222 | RX_GAIN_STEP_13, |
| 223 | RX_GAIN_STEP_14, |
| 224 | RX_GAIN_STEP_15, |
| 225 | |
| 226 | NUM_TX_GAIN_STEPS = 32, |
| 227 | MAX_TX_GAIN_STEP = TX_GAIN_STEP_31, |
| 228 | |
| 229 | NUM_RX_GAIN_STEPS = 16, |
| 230 | MAX_RX_GAIN_STEP = RX_GAIN_STEP_15, |
| 231 | }; |
| 232 | typedef tANI_U32 eGainSteps; |
| 233 | |
| 234 | |
| 235 | //[RY] new for PRIMA |
| 236 | #define DPD_RESPONSE_SIZE 128 |
| 237 | typedef PACKED_PRE struct PACKED_POST { |
Sanoop K | 05588fc | 2012-12-12 13:51:22 -0800 | [diff] [blame] | 238 | tANI_U8 dpdCalFailCnt; //Count for number of times DPD cal failed. |
| 239 | tANI_U8 dpdCalSuccessCnt; //Count for number of times DPD cal passed. |
Shailender Karmuchi | 07f514b | 2013-06-25 01:14:09 -0700 | [diff] [blame] | 240 | tANI_U8 dpdColdBootRepeatCalStatus; |
| 241 | tANI_U8 dpdLastIteration; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 242 | tANI_S16 dpd_threshold[DPD_RESPONSE_SIZE]; |
| 243 | tANI_S16 dpd_aoffset[DPD_RESPONSE_SIZE]; |
| 244 | tANI_S16 dpd_again[DPD_RESPONSE_SIZE]; |
| 245 | tANI_S16 dpd_poffset[DPD_RESPONSE_SIZE]; |
| 246 | tANI_S16 dpd_pgain[DPD_RESPONSE_SIZE]; |
Shailender Karmuchi | 07f514b | 2013-06-25 01:14:09 -0700 | [diff] [blame] | 247 | tANI_S32 dpd_sample[20]; |
| 248 | tANI_U8 dpd_try; |
| 249 | tANI_U8 band; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 250 | }sDPDcorrectionCalValues; |
| 251 | |
| 252 | typedef PACKED_PRE struct PACKED_POST { |
| 253 | sDPDcorrectionCalValues dpd[PHY_MAX_TX_CHAINS]; |
| 254 | }sTxChainsDPDCalValues; |
| 255 | |
| 256 | |
| 257 | //[RY] RX IQ correction coefficients Memory |
| 258 | typedef PACKED_PRE struct PACKED_POST { |
| 259 | tANI_S9 coeff_i[5]; |
| 260 | tANI_S9 coeff_q[5]; |
| 261 | }sIQCalValues; |
| 262 | |
| 263 | //[RY], added for RIVA |
| 264 | typedef PACKED_PRE struct PACKED_POST { |
| 265 | tANI_S9 iq_ampimb_coeff; |
| 266 | tANI_S16 txloleakage_i; // raw data is 6-bit 2's compliment |
| 267 | tANI_S16 txloleakage_q; // raw data is 6-bit 2's compliment |
| 268 | }sTXIQCalValues; |
| 269 | |
| 270 | //[RY], added for RIVA |
| 271 | typedef PACKED_PRE struct PACKED_POST { |
| 272 | tANI_S9 iqphaseimb_coeff_i[5]; |
| 273 | tANI_S9 iqphaseimb_coeff_q[5]; |
| 274 | }sTXIQPhaseImbCalValues; |
| 275 | |
| 276 | typedef PACKED_PRE struct PACKED_POST { |
| 277 | sIQCalValues iq[PHY_MAX_RX_CHAINS]; |
| 278 | }sRxChainsIQCalValues; |
| 279 | |
| 280 | //[RY] change for PRIMA |
| 281 | typedef PACKED_PRE struct PACKED_POST { |
| 282 | sTXIQCalValues iq[PHY_MAX_TX_CHAINS]; |
| 283 | sTXIQPhaseImbCalValues iqImb[PHY_MAX_TX_CHAINS]; |
| 284 | }sTxChainsIQCalValues; |
| 285 | |
| 286 | typedef PACKED_PRE struct PACKED_POST { |
| 287 | tANI_S9 co_i[3]; |
| 288 | tANI_S9 co_q[3]; |
| 289 | }sHKIQCalValues; |
| 290 | |
| 291 | typedef PACKED_PRE struct PACKED_POST { |
| 292 | sHKIQCalValues co[PHY_MAX_TX_CHAINS]; |
| 293 | }sTxChainsHKIQCalValues; |
| 294 | |
| 295 | typedef PACKED_PRE struct PACKED_POST { |
| 296 | tANI_U8 lna_code; //wlan_lna_5g_control1,wl_5g_lna_load_ctune |
| 297 | tANI_U8 gm_code; //wlan_rxgm_5g_control4,wlgm_ctune |
| 298 | }sLnaBandCalValues; |
| 299 | |
| 300 | typedef PACKED_PRE struct PACKED_POST { |
| 301 | sLnaBandCalValues lnaCode[PHY_MAX_RX_CHAINS]; |
| 302 | }sTxChainsLnaBandCalValues; |
| 303 | |
| 304 | typedef tANI_U16 t_mW; //milliWatts |
| 305 | typedef tANI_U8 tPwrTemplateIndex; //5-bit number used as the index into the tx gain tables |
| 306 | |
| 307 | typedef PACKED_PRE struct PACKED_POST { |
| 308 | tANI_U8 txPowerAdc[PHY_MAX_TX_CHAINS]; |
| 309 | }sTxChainsPowerAdcReadings; |
| 310 | |
| 311 | typedef PACKED_PRE struct PACKED_POST |
| 312 | { |
| 313 | tANI_U8 agcGain; |
| 314 | }tRxGain; |
| 315 | |
| 316 | typedef PACKED_PRE struct PACKED_POST { |
| 317 | tANI_U8 rx[PHY_MAX_RX_CHAINS]; |
| 318 | }sRxChainsData; |
| 319 | |
| 320 | typedef sRxChainsData sRxChainsRssi; |
| 321 | typedef sRxChainsData sRxChainsAgcDisable; |
| 322 | |
| 323 | typedef PACKED_PRE struct PACKED_POST { |
| 324 | tANI_BOOLEAN rx[PHY_MAX_RX_CHAINS]; |
| 325 | }sRxChainsBoolean; |
| 326 | |
| 327 | typedef sRxChainsBoolean sRxChainsAgcEnable; |
| 328 | |
| 329 | #define NUM_AGC_GAINS 64 |
| 330 | typedef tRxGain sAgcGainLut[NUM_AGC_GAINS]; |
| 331 | |
| 332 | |
| 333 | typedef PACKED_PRE struct PACKED_POST |
| 334 | { |
| 335 | tANI_S6 iLo; |
| 336 | tANI_S6 qLo; |
| 337 | }sTxFirLoCorrect; |
| 338 | |
| 339 | typedef tIQAdc sTxLoCorrectBB[PHY_MAX_TX_CHAINS][NUM_TX_GAIN_STEPS]; |
| 340 | |
| 341 | typedef PACKED_PRE struct PACKED_POST |
| 342 | { |
| 343 | tANI_U32 txIqLoCache[PHY_MAX_TX_CHAINS][NUM_TX_GAIN_STEPS][4]; |
| 344 | tANI_U32 spatialRotation; |
| 345 | }tAsicTxFir; |
| 346 | |
| 347 | //Tx Power Config |
| 348 | //A collection of selected calibrated power points at selected frequencies. |
| 349 | //The algorithm does not need to know any particulars about which frequencies or cal points, |
| 350 | // just the linearized adjustments at the selected calibration points |
| 351 | #define MAX_TPC_CHANNELS (NUM_RF_CHANNELS) |
| 352 | #define START_TPC_CHANNEL (2412) |
| 353 | #define END_TPC_CHANNEL (2484) |
| 354 | |
| 355 | #define MAX_PWR_LUT_DBM (24) |
| 356 | #define MIN_PWR_LUT_DBM (8) |
| 357 | |
| 358 | |
| 359 | /* The reason that MAX_PWR_LUT_DBM_2DEC_PLACES is not simply (MAX_PWR_LUT_DBM * 100) is due to the fact |
| 360 | that we are interpolating the 5-bit power template index from this range compared to a LUT range of 0 to 127. |
| 361 | There is an expectation that this power range is evenly divided in 0.5dBm steps. |
| 362 | We expect that a commanded 13dBm would yield a power template index of 10, where a power template index of 0 would represent 8dBm. |
| 363 | If we used an even 2400 to represent the max power, then the calculation for 13dBm actually returns 9: |
| 364 | (127 - 0)*((1300 - 800)/(2400 - 800))+0 = 39.6875 = 39. When shifted to 5 bits, =9. Not what we wanted. |
| 365 | What we need to do is find the 2-decimal place power that corresponds as closely as possible to the 127 in the 0 to 127 range. |
| 366 | For the 800 to 2400 range, that comes out to 2386.5, so 2386. So again for a commanded power of 13dBm: |
| 367 | (127 - 0)*((1300 - 800)/(2386 - 800))+0 = 40.0378 = 40. When shifted to 5-bits, = 10, which is what we wanted. |
| 368 | |
| 369 | */ |
| 370 | |
| 371 | #define MIN_PWR_LUT_DBM_2DEC_PLACES (MIN_PWR_LUT_DBM * 100) |
| 372 | #define MAX_PWR_LUT_DBM_2DEC_PLACES ((MAX_PWR_LUT_DBM * 100) - (1 + (100 * (MAX_PWR_LUT_DBM - MIN_PWR_LUT_DBM))/TPC_MEM_POWER_LUT_DEPTH)) |
| 373 | |
| 374 | //macro provides a quick conversion of dbm value between MIN_PWR_LUT_DBM and MAX_PWR_LUT_DBM to a power template index(0 to 31) |
| 375 | //based on convention, which may not hold true in the future. |
| 376 | #define CONVERT_DBM_GINDEX(dbm) (((dbm - MIN_PWR_LUT_DBM) * 32) / (MAX_PWR_LUT_DBM - MIN_PWR_LUT_DBM)) |
| 377 | |
| 378 | typedef tANI_U8 tTxGainCombo; //7-bit gain value used to get the power measurement |
| 379 | |
| 380 | typedef PACKED_PRE struct PACKED_POST |
| 381 | { |
| 382 | tPowerDetect min; |
| 383 | tPowerDetect max; |
| 384 | }tPwrTemplateRange; |
| 385 | |
| 386 | |
| 387 | |
| 388 | /* |
| 389 | The following union affords backward compatibility with txGain usage with band-specific tTpcConfig tables. |
| 390 | Due to my finding that 7-bits is not enough precision, we need to reuse the txGain space as extra precision bits |
| 391 | for the adjustedPwrDet. My spreadsheet shows that we need at least 4 bits more precision. |
| 392 | To know which usage, the MSB of adjustedPwrDet can be set to signify the extra precision in place of the txGain, which isn't used anyway. |
| 393 | We just need to be careful not to interpret a pre-existing table's txGain as extra precision. |
| 394 | */ |
| 395 | |
| 396 | typedef union |
| 397 | { |
| 398 | tTxGainCombo txGain; //7-bit gain used to measure the pwrDetAdc value |
| 399 | tANI_U8 hi8_adjustedPwrDet; //if the MSB is set in adjustedPwrDet, then these are extra bits of precision |
| 400 | }uExtraLutBits; |
| 401 | |
| 402 | |
| 403 | typedef PACKED_PRE struct PACKED_POST |
| 404 | { |
| 405 | t2Decimal min; //sometimes used for comparing chain powers |
| 406 | t2Decimal max; //sometimes used for comparing chain powers |
| 407 | }tPowerdBmRange; //absolute power measurement precision maintained to two decimal places |
| 408 | |
| 409 | |
| 410 | typedef tANI_U16 tRfADCVal; |
| 411 | typedef tRfADCVal tTempADCVal; |
| 412 | |
| 413 | typedef PACKED_PRE struct PACKED_POST |
| 414 | { |
| 415 | tRfADCVal pdadc_offset; |
| 416 | tANI_U8 reserved[2]; |
| 417 | }tTpcParams; |
| 418 | |
| 419 | |
| 420 | //these definitions used as indexing to power per channel per rate table stored in NV |
| 421 | #define CB_RATE_POWER_OFFSET 0 |
| 422 | #define CB_RATE_POWER_OFFSET_LAST_INDEX 60 //last index where we would apply the CB_RATE_POWER_OFFSET |
| 423 | |
| 424 | /* TX Power Calibration & Report Types */ |
| 425 | |
| 426 | |
| 427 | typedef PACKED_PRE struct PACKED_POST |
| 428 | { |
| 429 | tANI_U8 temperatureAdc; //= 5 bit temperature measured at time sample was taken |
| 430 | tANI_U8 txGain; //= 7 bit gain value used to get the power measurement |
| 431 | tANI_U8 pwrDetAdc; //= 8 bit ADC power detect value |
| 432 | tANI_U8 reserved; |
| 433 | uAbsPwrPrecision absPowerMeasured; //= dBm measurement, will be truncated to two decimal places |
| 434 | }tTpcCalPoint; |
| 435 | |
| 436 | |
| 437 | typedef PACKED_PRE struct PACKED_POST |
| 438 | { |
| 439 | tANI_U16 numTpcCalPoints; |
| 440 | tANI_U16 reserved; |
| 441 | tTpcCalPoint chain[MAX_TPC_CAL_POINTS]; |
| 442 | }tTpcChainData; |
| 443 | |
| 444 | |
| 445 | typedef PACKED_PRE struct PACKED_POST |
| 446 | { |
| 447 | tANI_U16 freq; //frequency in MHz |
| 448 | tANI_U16 reserved; |
| 449 | tTpcChainData empirical[PHY_MAX_TX_CHAINS]; //TPC samples passed in |
| 450 | }tTpcFreqData; |
| 451 | |
| 452 | typedef PACKED_PRE struct PACKED_POST |
| 453 | { |
| 454 | tANI_U8 numChannels; |
| 455 | tANI_U8 reserved[3]; |
| 456 | tTpcFreqData calValues[MAX_TPC_CHANNELS]; |
| 457 | }sTpcFreqCalTable; |
| 458 | |
| 459 | |
| 460 | typedef PACKED_PRE struct PACKED_POST { |
| 461 | tPowerDetect lut; //7-bit value in the power Lookup Table |
| 462 | tANI_U8 reserved[3]; |
| 463 | |
| 464 | uAbsPwrPrecision abs; //LUT value conversion to absolute dBm |
| 465 | }tTxPowerLutOutput; |
| 466 | |
| 467 | typedef PACKED_PRE struct PACKED_POST { |
| 468 | tANI_U8 gain; //8-bit coarse(bits 4-7) & fine(bits 0-3) gain commanded for the current index |
| 469 | tPowerDetect adc; //8-bit power ADC sampled during the packet preamble |
| 470 | tANI_U16 rawAdc; //11-bit power raw ADC sampled |
| 471 | |
| 472 | tTxPowerLutOutput indexMinMatch; //minimum LUT matching power that satisfies the power template index setting |
| 473 | tTxPowerLutOutput indexMaxMatch; //maximum LUT matching power that satisfies the power template index setting |
| 474 | tTxPowerLutOutput output; //output power values corresponding to power ADC index |
| 475 | }tTxChainPower; |
| 476 | |
| 477 | extern const tRfChannelProps rfChannels[NUM_RF_CHANNELS]; |
| 478 | |
| 479 | typedef enum |
| 480 | { |
| 481 | RF_CAL_TONE_28NEG, |
| 482 | RF_CAL_TONE_24NEG, |
| 483 | RF_CAL_TONE_20NEG, |
| 484 | RF_CAL_TONE_16NEG, |
| 485 | RF_CAL_TONE_12NEG, |
| 486 | RF_CAL_TONE_8NEG, |
| 487 | RF_CAL_TONE_4NEG, |
| 488 | RF_CAL_TONE_4POS, |
| 489 | RF_CAL_TONE_8POS, |
| 490 | RF_CAL_TONE_12POS, |
| 491 | RF_CAL_TONE_16POS, |
| 492 | RF_CAL_TONE_20POS, |
| 493 | RF_CAL_TONE_24POS, |
| 494 | RF_CAL_TONE_28POS, |
| 495 | |
| 496 | NUM_RF_TONES, |
| 497 | |
| 498 | MIN_RF_TONE = RF_CAL_TONE_28NEG, |
| 499 | MAX_RF_TONE = RF_CAL_TONE_28POS |
| 500 | }eRfTones; |
| 501 | |
| 502 | typedef tANI_U8 tDcoCorrect; |
| 503 | typedef tANI_S8 tIm2Correct; |
| 504 | |
| 505 | typedef PACKED_PRE struct PACKED_POST { |
| 506 | tDcoCorrect IDcoCorrect; |
| 507 | tDcoCorrect QDcoCorrect; |
| 508 | tANI_U8 dcRange; |
| 509 | }tRxDcoCorrect; |
| 510 | |
| 511 | typedef PACKED_PRE struct PACKED_POST { |
| 512 | tRxDcoCorrect dco[PHY_MAX_RX_CHAINS]; |
| 513 | }tRxChainsDcoCorrections; |
| 514 | |
| 515 | typedef PACKED_PRE struct PACKED_POST { |
| 516 | tIm2Correct ICorrect; |
| 517 | tIm2Correct QCorrect; |
| 518 | }tRxIm2Correct; |
| 519 | |
| 520 | typedef PACKED_PRE struct PACKED_POST { |
| 521 | tRxIm2Correct dco[PHY_MAX_RX_CHAINS]; |
| 522 | }tRxChainsIm2Corrections; |
| 523 | |
| 524 | typedef PACKED_PRE struct PACKED_POST { |
| 525 | tDcoCorrect IDcoCorrect; |
| 526 | tDcoCorrect QDcoCorrect; |
| 527 | }tTxLoCorrect; |
| 528 | |
| 529 | typedef PACKED_PRE struct PACKED_POST { |
| 530 | tTxLoCorrect txLo[PHY_MAX_TX_CHAINS]; |
| 531 | }sTxChainsLoCorrections; |
| 532 | |
| 533 | |
| 534 | //tDcoCorrect is needed to define rf specific structures |
| 535 | |
| 536 | #define NUM_RF_RX_GAIN_STEPS (128) |
| 537 | #define MAX_RF_RX_GAIN_STEP (NUM_RF_RX_GAIN_STEPS - 1) |
| 538 | |
| 539 | #define NUM_RF_TX_GAIN_STEPS (16) |
| 540 | #define MAX_RF_TX_GAIN_STEP (NUM_RF_TX_GAIN_STEPS - 1) |
| 541 | |
| 542 | #define RF_AGC_GAIN_LUT_DEPTH (128) |
| 543 | #define NUM_RF_DCO_VALUES (128) //There are only 32 DCO values, but our algorithm it makes more sense for us to access these by AGC gain index |
| 544 | #define MAX_RF_DCO_VALUE (NUM_RF_DCO_VALUES - 1) |
| 545 | |
| 546 | |
| 547 | typedef PACKED_PRE struct PACKED_POST |
| 548 | { |
| 549 | tANI_U16 gainReg1; //GEMINI_REG_RX_GC_0 (lna + mix + tia + bq1 + bq2 + pga) |
| 550 | }tRfRxGain; |
| 551 | |
| 552 | |
| 553 | typedef PACKED_PRE struct PACKED_POST |
| 554 | { |
| 555 | tANI_U16 bbf_gain_cnt; |
| 556 | tANI_U16 bbf_lin_adj; |
| 557 | tANI_U16 lo_mix_da_gain_cntl; |
| 558 | tANI_U16 pa_gain_cntl; |
| 559 | tANI_U16 da_pa_bias_1_cnt; |
| 560 | tANI_U16 da_pa_bias_2_cntl; |
| 561 | }tRfTxGain; |
| 562 | |
| 563 | typedef PACKED_PRE struct PACKED_POST |
| 564 | { |
| 565 | //TODO:define this struct for Gemini |
| 566 | tANI_U8 rxIf; |
| 567 | tANI_U8 txIf; |
| 568 | tANI_U8 txRf; |
| 569 | tANI_U8 reserved; |
| 570 | }sRfSpecificFilterSettings; |
| 571 | |
| 572 | typedef sRfSpecificFilterSettings sRfChannelFilterSettings[NUM_RF_CHANNELS]; |
| 573 | |
| 574 | |
| 575 | typedef PACKED_PRE struct PACKED_POST |
| 576 | { |
| 577 | tANI_U8 hdet_ctl_ext_atten; |
| 578 | tANI_U8 hdet_dcoc_code; |
| 579 | tANI_U8 hdet_dcoc_ib_rcal_en; |
| 580 | tANI_U8 hdet_dcoc_ib_scal_en; |
| 581 | }sRfNvCalValues; //stored in QFUSE |
| 582 | |
| 583 | |
| 584 | |
| 585 | typedef enum |
| 586 | { |
| 587 | SYNTH_UNLOCKED, |
| 588 | SYNTH_LOCK |
| 589 | }eRfSynthLock; |
| 590 | |
| 591 | typedef enum |
| 592 | { |
| 593 | TEMP_SENSOR_PA, |
| 594 | TEMP_SENSOR_RX |
| 595 | }eRfTempSensor; |
| 596 | |
| 597 | typedef enum |
| 598 | { |
| 599 | TEMPERATURE_BIN_0, //-30 to 5 C |
| 600 | TEMPERATURE_BIN_1, //5 to 45 C |
| 601 | TEMPERATURE_BIN_2, //45 to 85 C |
| 602 | TEMPERATURE_BIN_3, //85 to 125 C |
| 603 | NUM_TEMPERATURE_BINS |
| 604 | }eTemperatureBins; |
| 605 | |
| 606 | typedef PACKED_PRE struct PACKED_POST { |
| 607 | tANI_U16 hdetDcocCode; |
| 608 | tANI_U16 hdetDcoOffset; |
| 609 | }sRfHdetCalValues; |
| 610 | |
| 611 | #define TPC_TXPWR_ENABLE_MASK QWLAN_TPC_TXPWR_ENABLE_EN_MASK |
| 612 | |
| 613 | |
| 614 | #define TPC_MEM_TX0_PWR_LUT_OFFSET QWLAN_TPC_POWERDET0_RAM_MREG |
| 615 | #define TPC_MEM_TX1_PWR_LUT_OFFSET QWLAN_TPC_POWERDET1_RAM_MREG |
| 616 | #define TPC_MEM_TX2_PWR_LUT_OFFSET QWLAN_TPC_POWERDET2_RAM_MREG |
| 617 | #define TPC_MEM_TX3_PWR_LUT_OFFSET QWLAN_TPC_POWERDET3_RAM_MREG |
| 618 | #define TPC_MEM_TX0_GAIN_LUT_OFFSET QWLAN_TPC_GAIN_LUT0_MREG |
| 619 | #define TPC_MEM_TX1_GAIN_LUT_OFFSET QWLAN_TPC_GAIN_LUT1_MREG |
| 620 | #define TPC_MEM_TX2_GAIN_LUT_OFFSET QWLAN_TPC_GAIN_LUT2_MREG |
| 621 | #define TPC_MEM_TX3_GAIN_LUT_OFFSET QWLAN_TPC_GAIN_LUT3_MREG |
| 622 | |
| 623 | //these masks are the same for both chains |
| 624 | #define TPC_POWERDET_MASK QWLAN_TPC_POWERDET0_RAM_POWER_MASK |
| 625 | #define TPC_GAIN_RF_MASK QWLAN_TPC_GAIN_LUT0_RF_GAIN_MASK |
| 626 | #define TPC_GAIN_RF_OFFSET QWLAN_TPC_GAIN_LUT0_RF_GAIN_OFFSET |
| 627 | #define TPC_GAIN_DIG_MASK QWLAN_TPC_GAIN_LUT0_DIG_GAIN_MASK |
| 628 | |
| 629 | |
| 630 | #define TPC_MEM_GAIN_LUT_DEPTH 32 |
| 631 | |
| 632 | |
| 633 | #define TPC_ADC_CTRL_REG QWLAN_TPC_ADC_CTRL_GET_ADC_REG |
| 634 | #define TPC_ADC_GET_MASK QWLAN_TPC_ADC_CTRL_GET_ADC_GET_ADC_MASK |
| 635 | |
| 636 | #define TPC_ADC_FAILED_MASK QWLAN_TPC_ADC_STATUS_FAILED_MASK |
| 637 | #define TPC_ADC_BUSY_P_MASK QWLAN_TPC_ADC_STATUS_BUSY_P_MASK |
| 638 | #define TPC_ADC_BUSY_T_MASK QWLAN_TPC_ADC_STATUS_BUSY_T_MASK |
| 639 | |
| 640 | |
| 641 | #define MSK_1 0x1 |
| 642 | #define MSK_2 0x3 |
| 643 | #define MSK_3 0x7 |
| 644 | #define MSK_4 0xF |
| 645 | #define MSK_5 0x1F |
| 646 | #define MSK_6 0x3F |
| 647 | #define MSK_7 0x7F |
| 648 | #define MSK_8 0xFF |
| 649 | #define MSK_9 0x1FF |
| 650 | #define MSK_10 0x3FF |
| 651 | #define MSK_11 0x7FF |
| 652 | #define MSK_12 0xFFF |
| 653 | #define MSK_13 0x1FFF |
| 654 | #define MSK_14 0x3FFF |
| 655 | #define MSK_15 0x7FFF |
| 656 | #define MSK_16 0xFFFF |
| 657 | #define MSK_17 0x1FFFF |
| 658 | #define MSK_18 0x3FFFF |
| 659 | #define MSK_19 0x7FFFF |
| 660 | #define MSK_20 0xFFFFF |
| 661 | #define MSK_21 0x1FFFFF |
| 662 | #define MSK_22 0x3FFFFF |
| 663 | #define MSK_23 0x7FFFFF |
| 664 | #define MSK_24 0xFFFFFF |
| 665 | #define MSK_25 0x1FFFFFF |
| 666 | #define MSK_26 0x3FFFFFF |
| 667 | #define MSK_27 0x7FFFFFF |
| 668 | #define MSK_28 0xFFFFFFF |
| 669 | #define MSK_29 0x1FFFFFFF |
| 670 | #define MSK_30 0x3FFFFFFF |
| 671 | #define MSK_31 0x7FFFFFFF |
| 672 | #define MSK_32 0xFFFFFFFF |
| 673 | |
| 674 | |
| 675 | #define COARSE_GAIN_MASK MSK_4 |
| 676 | #define COARSE_GAIN_OFFSET 4 |
| 677 | #define FINE_GAIN_MASK MSK_4 //the upper most bit overlaps the coarse gain and should not be used for TPC LUT data |
| 678 | #define FINE_GAIN_OFFSET 0 |
| 679 | |
| 680 | typedef enum |
| 681 | { |
| 682 | TPC_COARSE_TXPWR_0, |
| 683 | TPC_COARSE_TXPWR_1, |
| 684 | TPC_COARSE_TXPWR_2, |
| 685 | TPC_COARSE_TXPWR_3, |
| 686 | TPC_COARSE_TXPWR_4, |
| 687 | TPC_COARSE_TXPWR_5, |
| 688 | TPC_COARSE_TXPWR_6, |
| 689 | TPC_COARSE_TXPWR_7, |
| 690 | TPC_COARSE_TXPWR_8, |
| 691 | TPC_COARSE_TXPWR_9, |
| 692 | TPC_COARSE_TXPWR_10, |
| 693 | TPC_COARSE_TXPWR_11, |
| 694 | TPC_COARSE_TXPWR_12, |
| 695 | TPC_COARSE_TXPWR_13, |
| 696 | TPC_COARSE_TXPWR_14, |
| 697 | TPC_COARSE_TXPWR_15, |
| 698 | TPC_COARSE_TXPWR_16, |
| 699 | TPC_COARSE_TXPWR_17, |
| 700 | TPC_COARSE_TXPWR_18, |
| 701 | TPC_COARSE_TXPWR_19, |
| 702 | TPC_COARSE_TXPWR_20, |
| 703 | TPC_COARSE_TXPWR_21, |
| 704 | TPC_COARSE_TXPWR_22, |
| 705 | TPC_COARSE_TXPWR_23, |
| 706 | TPC_COARSE_TXPWR_24, |
| 707 | TPC_COARSE_TXPWR_25, |
| 708 | TPC_COARSE_TXPWR_26, |
| 709 | TPC_COARSE_TXPWR_27, |
| 710 | TPC_COARSE_TXPWR_28, |
| 711 | TPC_COARSE_TXPWR_29, |
| 712 | TPC_COARSE_TXPWR_30, |
| 713 | TPC_COARSE_TXPWR_31, |
| 714 | NUM_TPC_COARSE_STEPS = TPC_COARSE_TXPWR_31 - TPC_COARSE_TXPWR_0 + 1, |
| 715 | MIN_TPC_COARSE_TXPWR = TPC_COARSE_TXPWR_0, |
| 716 | MAX_TPC_COARSE_TXPWR = TPC_COARSE_TXPWR_31 |
| 717 | }eTxCoarseGain; //refers to the external RF power adjustment |
| 718 | |
| 719 | typedef enum |
| 720 | { |
| 721 | TPC_FINE_TXPWR_0, |
| 722 | TPC_FINE_TXPWR_1, |
| 723 | TPC_FINE_TXPWR_2, |
| 724 | TPC_FINE_TXPWR_3, |
| 725 | TPC_FINE_TXPWR_4, |
| 726 | TPC_FINE_TXPWR_5, |
| 727 | TPC_FINE_TXPWR_6, |
| 728 | TPC_FINE_TXPWR_7, |
| 729 | TPC_FINE_TXPWR_8, |
| 730 | TPC_FINE_TXPWR_9, |
| 731 | TPC_FINE_TXPWR_10, |
| 732 | TPC_FINE_TXPWR_11, |
| 733 | TPC_FINE_TXPWR_12, |
| 734 | TPC_FINE_TXPWR_13, |
| 735 | TPC_FINE_TXPWR_14, |
| 736 | TPC_FINE_TXPWR_15, |
| 737 | MIN_TPC_FINE_TXPWR = TPC_FINE_TXPWR_0, |
| 738 | MAX_TPC_FINE_TXPWR = TPC_FINE_TXPWR_15 |
| 739 | }eTxFineGain; //refers to the internal TxFIR power adjustment |
| 740 | |
| 741 | typedef PACKED_PRE struct PACKED_POST { |
| 742 | eTxCoarseGain coarsePwr; |
| 743 | eTxFineGain finePwr; |
| 744 | }tTxGain; |
| 745 | |
| 746 | //for 30second periodic interrupt, do this every 5 minutes |
| 747 | #define HAL_PHY_PERIODIC_CAL_ITER_LIMIT 10 |
| 748 | |
| 749 | typedef enum |
| 750 | { |
| 751 | //these show which rx and tx chains are enabled, other chains are disable accordingly |
| 752 | //Production modes |
| 753 | PHY_CHAIN_SEL_R0_T0_ON, |
| 754 | |
| 755 | PHY_CHAIN_SEL_BT_R0_T0_ON, //simultaneous bluetooth receive enabled |
| 756 | |
| 757 | |
| 758 | //test modes |
| 759 | PHY_CHAIN_SEL_R0_ON, |
| 760 | PHY_CHAIN_SEL_T0_ON, |
| 761 | PHY_CHAIN_SEL_NO_RX_TX, |
| 762 | |
| 763 | MAX_PHY_CHAIN_SEL, |
| 764 | INVALID_PHY_CHAIN_SEL, |
| 765 | PHY_MAX_CHAIN_SELECT = 0x7FFFFFFF /* define as 4 bytes data */ |
| 766 | }ePhyChainSelect; |
| 767 | |
| 768 | typedef enum |
| 769 | { |
| 770 | #ifdef CHANNEL_BONDED_CAPABLE |
| 771 | |
| 772 | PHY_CCA_40MHZ_SOURCE = 0, |
| 773 | #endif |
| 774 | |
| 775 | PHY_CCA_20MHZ_SOURCE = 1 |
| 776 | }ePhyCCASource; |
| 777 | |
| 778 | typedef enum |
| 779 | { |
| 780 | PHY_CCA_FORCED_ON = 0, |
| 781 | PHY_CCA_ED = 1, |
| 782 | PHY_CCA_CD = 2, |
| 783 | PHY_CCA_CD_AND_CS = 3, |
| 784 | PHY_CCA_ED_AND_CD = 4, |
| 785 | PHY_CCA_ED_OR_CD = 5, |
| 786 | PHY_CCA_ED_AND_CD_AND_CS = 6, |
| 787 | PHY_CCA_ED_OR_CD_AND_CS = 7, |
| 788 | PHY_CCA_SEC_ED40_AND_NOR_PKTDET40_PKTDET20 = 8, |
| 789 | PHY_CCA_SEC_BUSY = 9 |
| 790 | }ePhyCCAMode; |
| 791 | |
| 792 | typedef enum |
| 793 | { |
| 794 | PHY_RX_DISABLE_NONE = 0, |
| 795 | PHY_RX_DISABLE_11AG = 0x00000001, |
| 796 | PHY_RX_DISABLE_11B = 0x00000002, |
| 797 | PHY_RX_DISABLE_11N40 = 0x00000004, |
| 798 | PHY_RX_DISABLE_11AC80 = 0x00000008, |
| 799 | |
| 800 | PHY_RX_DISABLE_11ABG = (PHY_RX_DISABLE_11AG | PHY_RX_DISABLE_11B), |
| 801 | PHY_RX_DISABLE_ALL_TYPES = (PHY_RX_DISABLE_11B | PHY_RX_DISABLE_11AG | |
| 802 | PHY_RX_DISABLE_11N40 | PHY_RX_DISABLE_11AC80), |
| 803 | }ePhyRxDisabledPktTypes; |
| 804 | |
| 805 | |
| 806 | // Enum for network density setting. |
| 807 | typedef enum |
| 808 | { |
| 809 | PHY_NW_DENSITY_LOW = 0, |
| 810 | PHY_NW_DENSITY_MED, |
| 811 | PHY_NW_DENSITY_HIGH, |
| 812 | PHY_NW_DENSITY_ADAPTIVE |
| 813 | } ePhyNwDensity; |
| 814 | |
| 815 | |
| 816 | typedef enum |
| 817 | { |
| 818 | ALL_CALS, //RxDco 1st, TxLO 2nd |
| 819 | RX_DCO_CAL_ONLY, |
| 820 | RX_IM2_CAL_ONLY, |
| 821 | RX_DCO_IM2_CAL, |
| 822 | TX_LO_CAL_ONLY, |
| 823 | RX_IQ_CAL_ONLY, |
| 824 | TX_IQ_CAL_ONLY, |
| 825 | HKDAC_TX_IQ_CAL_ONLY, |
| 826 | NO_CALS = 0xFF |
| 827 | }eCalSelection; |
| 828 | |
| 829 | |
| 830 | //supports testing of closed-loop power control |
| 831 | typedef enum |
| 832 | { |
| 833 | FORCE_CLOSED_LOOP_GAIN = 0, //phyDbg pkt gen only uses gain index 0 when we are taking measurements with the closed-loop gain |
| 834 | FORCE_POWER_TEMPLATE_INDEX = 1, //only use forced power template index |
| 835 | FIXED_POWER_DBM = 2, //only use to specify fixed power, ignoring rate/channel/reg limits |
| 836 | REGULATORY_POWER_LIMITS = 3, //use production power Lut settings limited by power limit table per channel |
| 837 | RATE_POWER_NON_LIMITED = 4, //use power specified per rate and channel group, but don't limit power by channel |
| 838 | POWER_INDX_SRC_MAX_VAL = 0x7FFFFFFF, //dummy val to set enum to 4 bytes |
| 839 | }ePowerTempIndexSource; |
| 840 | |
| 841 | #define BIT_0 0x00000001 |
| 842 | #define BIT_1 0x00000002 |
| 843 | #define BIT_2 0x00000004 |
| 844 | #define BIT_3 0x00000008 |
| 845 | #define BIT_4 0x00000010 |
| 846 | #define BIT_5 0x00000020 |
| 847 | #define BIT_6 0x00000040 |
| 848 | #define BIT_7 0x00000080 |
| 849 | #define BIT_8 0x00000100 |
| 850 | #define BIT_9 0x00000200 |
| 851 | #define BIT_10 0x00000400 |
| 852 | #define BIT_11 0x00000800 |
| 853 | #define BIT_12 0x00001000 |
| 854 | #define BIT_13 0x00002000 |
| 855 | #define BIT_14 0x00004000 |
| 856 | #define BIT_15 0x00008000 |
| 857 | #define BIT_16 0x00010000 |
| 858 | #define BIT_17 0x00020000 |
| 859 | #define BIT_18 0x00040000 |
| 860 | #define BIT_19 0x00080000 |
| 861 | #define BIT_20 0x00100000 |
| 862 | #define BIT_21 0x00200000 |
| 863 | #define BIT_22 0x00400000 |
| 864 | #define BIT_23 0x00800000 |
| 865 | #define BIT_24 0x01000000 |
| 866 | #define BIT_25 0x02000000 |
| 867 | #define BIT_26 0x04000000 |
| 868 | #define BIT_27 0x08000000 |
| 869 | #define BIT_28 0x10000000 |
| 870 | #define BIT_29 0x20000000 |
| 871 | #define BIT_30 0x40000000 |
| 872 | #define BIT_31 0x80000000 |
| 873 | |
| 874 | #define WFM_CLK_80 BIT_3 |
| 875 | #define WFM_START BIT_0 |
| 876 | #define WFM_STOP BIT_1 |
| 877 | |
| 878 | #define WFM_MEM_I_DATA_MASK (0x7FF) |
| 879 | #define WFM_MEM_Q_DATA_OFFSET (0xB) |
| 880 | #define WFM_MEM_Q_DATA_MASK (0x3FF800) |
| 881 | |
| 882 | typedef enum |
| 883 | { |
| 884 | WAVE_SINGLE_SHOT = 0, |
| 885 | WAVE_CONTINUOUS = BIT_2 |
| 886 | }eWaveMode; |
| 887 | |
| 888 | typedef enum |
| 889 | { |
| 890 | RATE_240 = 0, |
| 891 | RATE_160 = 1, |
| 892 | RATE_120 = 2, |
| 893 | RATE_80 = 3, |
| 894 | RATE_40 = 4, |
| 895 | RATE_20 = 5, |
| 896 | }eWaveRate; |
| 897 | |
| 898 | #define MAX_TONE_AMPLITUDE (2^11) // peak to peak |
| 899 | |
| 900 | #define MAX_TEST_WAVEFORM_SAMPLES 500 |
| 901 | |
| 902 | #define NUM_RX_IMB_CAL_TONES 4 |
| 903 | |
| 904 | #define CAL_WFM_TX_TONE_8_START_IDX 0 |
| 905 | #define CAL_WFM_TX_TONE_8_STOP_IDX 255 |
| 906 | #define CAL_WFM_TX_TONE_MINUS_8_START_IDX 256 |
| 907 | #define CAL_WFM_TX_TONE_MINUS_8_STOP_IDX 511 |
| 908 | #define CAL_WFM_RX_TONE_START_IDX 512 |
| 909 | #define CAL_WFM_RX_TONE_STOP_IDX 767 |
| 910 | |
| 911 | #define B_RATE_CAL_ADJUSTMENT -150 |
| 912 | #define GN_RATE_BANDEDGE_ADJUSTMENT -100 |
| 913 | |
| 914 | #define TPC_INDEX_WIFI_DIRECT 0 |
| 915 | #define TPC_INDEX_LOW_POWER 1 |
| 916 | #define MIN_TPC_GAIN_INDEX 0 //Index 0 used for Wifi Direct |
| 917 | #define TPC_GAIN_LUT_PWR_SLOPE 2 |
| 918 | #define MAX_TPC_GAIN_LUT_DBM (22) |
| 919 | #define MIN_TPC_GAIN_LUT_DBM (6) |
| 920 | |
| 921 | #define MAX_TPC_GAIN_LUT_DBM_2DEC_PLACES (MAX_TPC_GAIN_LUT_DBM * 100) |
| 922 | #define MIN_TPC_GAIN_LUT_DBM_2DEC_PLACES (MIN_TPC_GAIN_LUT_DBM * 100) |
| 923 | |
Anand Kumar | 012623a | 2013-01-11 17:00:00 -0800 | [diff] [blame] | 924 | typedef enum |
| 925 | { |
| 926 | RF_BANDWIDTH_20MHZ = 20, |
| 927 | RF_BANDWIDTH_40MHZ = 40, |
| 928 | RF_BANDWIDTH_80MHZ = 80, |
| 929 | RF_MIN_BANDWIDTH = RF_BANDWIDTH_20MHZ, |
| 930 | RF_MAX_BANDWIDTH = RF_BANDWIDTH_80MHZ, |
| 931 | RF_BANDWIDTH_INVALID = 0x7FFFFFFF |
| 932 | }eRfBandwidth; |
| 933 | |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 934 | #endif /* WLAN_PHY_H */ |