Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 1 | /* |
Jeff Johnson | 32d95a3 | 2012-09-10 13:15:23 -0700 | [diff] [blame] | 2 | * Copyright (c) 2012, The Linux Foundation. All rights reserved. |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | #ifndef WLAN_QCT_DXE_I_H |
| 23 | #define WLAN_QCT_DXE_I_H |
| 24 | |
| 25 | /**========================================================================= |
| 26 | |
| 27 | @file wlan_qct_dxe_i.h |
| 28 | |
| 29 | @brief |
| 30 | |
| 31 | This file contains the external API exposed by the wlan data transfer abstraction layer module. |
| 32 | Copyright (c) 2011 QUALCOMM Incorporated. |
| 33 | All Rights Reserved. |
| 34 | Qualcomm Confidential and Proprietary |
| 35 | ========================================================================*/ |
| 36 | |
| 37 | /*=========================================================================== |
| 38 | |
| 39 | EDIT HISTORY FOR FILE |
| 40 | |
| 41 | |
| 42 | This section contains comments describing changes made to the module. |
| 43 | Notice that changes are listed in reverse chronological order. |
| 44 | |
| 45 | |
| 46 | $Header:$ $DateTime: $ $Author: $ |
| 47 | |
| 48 | |
| 49 | when who what, where, why |
| 50 | -------- --- ---------------------------------------------------------- |
| 51 | 08/03/10 schang Created module. |
| 52 | |
| 53 | ===========================================================================*/ |
| 54 | |
| 55 | /*=========================================================================== |
| 56 | |
| 57 | INCLUDE FILES FOR MODULE |
| 58 | |
| 59 | ===========================================================================*/ |
| 60 | |
| 61 | /*---------------------------------------------------------------------------- |
| 62 | * Include Files |
| 63 | * -------------------------------------------------------------------------*/ |
| 64 | #include "wlan_qct_dxe.h" |
| 65 | #include "wlan_qct_pal_trace.h" |
Madan Mohan Koyyalamudi | ea77701 | 2012-10-31 14:22:34 -0700 | [diff] [blame^] | 66 | #include "wlan_qct_pal_timer.h" |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 67 | #include "vos_trace.h" |
| 68 | /*---------------------------------------------------------------------------- |
| 69 | * Preprocessor Definitions and Constants |
| 70 | * -------------------------------------------------------------------------*/ |
| 71 | #define WLANDXE_CTXT_COOKIE 0xC00CC111 |
| 72 | |
| 73 | |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 74 | /* From here WCNSS DXE register information |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 75 | * This is temporary definition location to make compile and unit test |
| 76 | * If official msmreg.h integrated, this part will be eliminated */ |
| 77 | /* Start with base address */ |
Madan Mohan Koyyalamudi | 8cb5398 | 2012-09-28 14:34:47 -0700 | [diff] [blame] | 78 | |
| 79 | #define WLANDXE_BMU_AVAILABLE_BD_PDU 0x03080084 |
| 80 | |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 81 | #ifdef WCN_PRONTO |
| 82 | #define WLANDXE_CCU_DXE_INT_SELECT 0xfb2050dc |
| 83 | #define WLANDXE_CCU_DXE_INT_SELECT_STAT 0xfb2050e0 |
| 84 | #define WLANDXE_CCU_ASIC_INT_ENABLE 0xfb2050e4 |
| 85 | #else |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 86 | #define WLANDXE_CCU_DXE_INT_SELECT 0x03200b10 |
| 87 | #define WLANDXE_CCU_DXE_INT_SELECT_STAT 0x03200b14 |
| 88 | #define WLANDXE_CCU_ASIC_INT_ENABLE 0x03200b18 |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 89 | #endif |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 90 | |
| 91 | #ifdef PAL_OS_TYPE_BMP |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 92 | #define WLANDXE_WCNSS_BASE_ADDRESS 0xCDD00000 |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 93 | #else |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 94 | #ifdef WCN_PRONTO |
| 95 | #define WLANDXE_WCNSS_BASE_ADDRESS 0xfb000000 |
| 96 | #else |
| 97 | #define WLANDXE_WCNSS_BASE_ADDRESS 0x03000000 |
| 98 | #endif |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 99 | #endif /* PAL_OS_TYPE_BMP */ |
| 100 | |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 101 | #define WLANDXE_REGISTER_BASE_ADDRESS WLANDXE_WCNSS_BASE_ADDRESS + 0x202000 |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 102 | |
| 103 | /* Common over the channels register addresses */ |
| 104 | #define WALNDEX_DMA_CSR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x00 |
| 105 | #define WALNDEX_DMA_ENCH_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x04 |
| 106 | #define WALNDEX_DMA_CH_EN_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x08 |
| 107 | #define WALNDEX_DMA_CH_DONE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x0C |
| 108 | #define WALNDEX_DMA_CH_ERR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x10 |
| 109 | #define WALNDEX_DMA_CH_STOP_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x14 |
| 110 | |
| 111 | /* Interrupt Control register address */ |
| 112 | #define WLANDXE_INT_MASK_REG_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x18 |
| 113 | #define WLANDXE_INT_SRC_MSKD_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x1C |
| 114 | #define WLANDXE_INT_SRC_RAW_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x20 |
| 115 | #define WLANDXE_INT_ED_SRC_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x24 |
| 116 | #define WLANDXE_INT_DONE_SRC_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x28 |
| 117 | #define WLANDXE_INT_ERR_SRC_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x2C |
| 118 | #define WLANDXE_INT_CLR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x30 |
| 119 | #define WLANDXE_INT_ED_CLR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x34 |
| 120 | #define WLANDXE_INT_DONE_CLR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x38 |
| 121 | #define WLANDXE_INT_ERR_CLR_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x3C |
| 122 | |
| 123 | #define WLANDXE_DMA_CH_PRES_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x40 |
| 124 | #define WLANDXE_ARB_CH_MSK_CLR_ADDRRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x74 |
| 125 | |
| 126 | /* Channel Counter register */ |
| 127 | #define WLANDXE_DMA_COUNTER_0 WLANDXE_REGISTER_BASE_ADDRESS + 0x200 |
| 128 | #define WLANDXE_DMA_COUNTER_1 WLANDXE_REGISTER_BASE_ADDRESS + 0x204 |
| 129 | #define WLANDXE_DMA_COUNTER_2 WLANDXE_REGISTER_BASE_ADDRESS + 0x208 |
| 130 | #define WLANDXE_DMA_COUNTER_3 WLANDXE_REGISTER_BASE_ADDRESS + 0x20C |
| 131 | #define WLANDXE_DMA_COUNTER_4 WLANDXE_REGISTER_BASE_ADDRESS + 0x210 |
| 132 | #define WLANDXE_DMA_COUNTER_5 WLANDXE_REGISTER_BASE_ADDRESS + 0x214 |
| 133 | #define WLANDXE_DMA_COUNTER_6 WLANDXE_REGISTER_BASE_ADDRESS + 0x218 |
| 134 | |
| 135 | #define WLANDXE_ENGINE_STAT_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x64 |
| 136 | #define WLANDXE_BMU_SB_QDAT_AV_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x5c |
| 137 | |
| 138 | /* Channel Base address */ |
| 139 | #define WLANDXE_DMA_CHAN0_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x400 |
| 140 | #define WLANDXE_DMA_CHAN1_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x440 |
| 141 | #define WLANDXE_DMA_CHAN2_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x480 |
| 142 | #define WLANDXE_DMA_CHAN3_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x4C0 |
| 143 | #define WLANDXE_DMA_CHAN4_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x500 |
| 144 | #define WLANDXE_DMA_CHAN5_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x540 |
| 145 | #define WLANDXE_DMA_CHAN6_BASE_ADDRESS WLANDXE_REGISTER_BASE_ADDRESS + 0x580 |
| 146 | |
| 147 | /* Channel specific register offset */ |
| 148 | #define WLANDXE_DMA_CH_CTRL_REG 0x0000 |
| 149 | #define WLANDXE_DMA_CH_STATUS_REG 0x0004 |
| 150 | #define WLANDXE_DMA_CH_SZ_REG 0x0008 |
| 151 | #define WLANDXE_DMA_CH_SADRL_REG 0x000C |
| 152 | #define WLANDXE_DMA_CH_SADRH_REG 0x0010 |
| 153 | #define WLANDXE_DMA_CH_DADRL_REG 0x0014 |
| 154 | #define WLANDXE_DMA_CH_DADRH_REG 0x0018 |
| 155 | #define WLANDXE_DMA_CH_DESCL_REG 0x001C |
| 156 | #define WLANDXE_DMA_CH_DESCH_REG 0x0020 |
| 157 | #define WLANDXE_DMA_CH_LST_DESCL_REG 0x0024 |
| 158 | #define WLANDXE_DMA_CH_LST_DESCH_REG 0x0028 |
| 159 | #define WLANDXE_DMA_CH_BD_REG 0x002C |
| 160 | #define WLANDXE_DMA_CH_HEAD_REG 0x0030 |
| 161 | #define WLANDXE_DMA_CH_TAIL_REG 0x0034 |
| 162 | #define WLANDXE_DMA_CH_PDU_REG 0x0038 |
| 163 | #define WLANDXE_DMA_CH_TSTMP_REG 0x003C |
| 164 | |
| 165 | /* Common CSR Register Contorol mask and offset */ |
| 166 | #define WLANDXE_DMA_CSR_RESERVED_MASK 0xFFFE0000 |
| 167 | #define WLANDXE_DMA_CSR_RESERVED_OFFSET 0x11 |
| 168 | #define WLANDXE_DMA_CSR_RESERVED_DEFAULT 0x0 |
| 169 | |
| 170 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_MASK 0x10000 |
| 171 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_OFFSET 0x10 |
| 172 | #define WLANDXE_DMA_CSR_H2H_SYNC_EN_DEFAULT 0x0 |
| 173 | |
| 174 | #define WLANDXE_DMA_CSR_PAUSED_MASK 0x8000 |
| 175 | #define WLANDXE_DMA_CSR_PAUSED_OFFSET 0xF |
| 176 | #define WLANDXE_DMA_CSR_PAUSED_DEFAULT 0x0 |
| 177 | |
| 178 | #define WLANDXE_DMA_CSR_ECTR_EN_MASK 0x4000 |
| 179 | #define WLANDXE_DMA_CSR_ECTR_EN_OFFSET 0xE |
| 180 | #define WLANDXE_DMA_CSR_ECTR_EN_DEFAULT 0x4000 |
| 181 | |
| 182 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_MASK 0x3E00 |
| 183 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_OFFSET 0x9 |
| 184 | #define WLANDXE_DMA_CSR_B2H_TSTMP_OFF_DEFAULT 0xE00 |
| 185 | |
| 186 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_MASK 0x1F0 |
| 187 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_OFFSET 0x4 |
| 188 | #define WLANDXE_DMA_CSR_H2B_TSTMP_OFF_DEFAULT 0x50 |
| 189 | |
| 190 | #define WLANDXE_DMA_CSR_TSTMP_EN_MASK 0x8 |
| 191 | #define WLANDXE_DMA_CSR_TSTMP_EN_OFFSET 0x3 |
| 192 | #define WLANDXE_DMA_CSR_TSTMP_EN_DEFAULT 0x0 |
| 193 | |
| 194 | #define WLANDXE_DMA_CSR_RESET_MASK 0x4 |
| 195 | #define WLANDXE_DMA_CSR_RESET_OFFSET 0x2 |
| 196 | #define WLANDXE_DMA_CSR_RESET_DEFAULT 0x0 |
| 197 | |
| 198 | #define WLANDXE_DMA_CSR_PAUSE_MASK 0x2 |
| 199 | #define WLANDXE_DMA_CSR_PAUSE_OFFSET 0x1 |
| 200 | #define WLANDXE_DMA_CSR_PAUSE_DEFAULT 0x0 |
| 201 | |
| 202 | #define WLANDXE_DMA_CSR_EN_MASK 0x1 |
| 203 | #define WLANDXE_DMA_CSR_EN_OFFSET 0x0 |
| 204 | #define WLANDXE_DMA_CSR_EN_DEFAULT 0x0 |
| 205 | #define WLANDXE_DMA_CSR_DEFAULT 0x4E50 |
| 206 | |
| 207 | /* Channel CTRL Register Control mask and offset */ |
| 208 | #define WLANDXE_CH_CTRL_RSVD_MASK 0x80000000 |
| 209 | #define WLANDXE_CH_CTRL_RSVD_OFFSET 0x1F |
| 210 | #define WLANDXE_CH_CTRL_RSVD_DEFAULT 0x0 |
| 211 | |
| 212 | #define WLANDXE_CH_CTRL_SWAP_MASK 0x80000000 |
| 213 | |
| 214 | #define WLANDXE_CH_CTRL_BDT_IDX_MASK 0x60000000 |
| 215 | #define WLANDXE_CH_CTRL_BDT_IDX_OFFSET 0x1D |
| 216 | #define WLANDXE_CH_CTRL_BDT_IDX_DEFAULT 0x0 |
| 217 | |
| 218 | #define WLANDXE_CH_CTRL_DFMT_MASK 0x10000000 |
| 219 | #define WLANDXE_CH_CTRL_DFMT_OFFSET 0x1C |
| 220 | #define WLANDXE_CH_CTRL_DFMT_DEFAULT 0x10000000 |
| 221 | #define WLANDXE_CH_CTRL_DFMT_ESHORT 0x0 |
| 222 | #define WLANDXE_CH_CTRL_DFMT_ELONG 0x1 |
| 223 | |
| 224 | #define WLANDXE_CH_CTRL_ABORT_MASK 0x8000000 |
| 225 | #define WLANDXE_CH_CTRL_ABORT_OFFSET 0x1B |
| 226 | #define WLANDXE_CH_CTRL_ABORT_DEFAULT 0x0 |
| 227 | |
| 228 | #define WLANDXE_CH_CTRL_ENDIAN_MASK 0x4000000 |
| 229 | |
| 230 | #define WLANDXE_CH_CTRL_CTR_SEL_MASK 0x3C00000 |
| 231 | #define WLANDXE_CH_CTRL_CTR_SEL_OFFSET 0x16 |
| 232 | #define WLANDXE_CH_CTRL_CTR_SEL_DEFAULT 0x0 |
| 233 | |
| 234 | #define WLANDXE_CH_CTRL_EDVEN_MASK 0x200000 |
| 235 | #define WLANDXE_CH_CTRL_EDVEN_OFFSET 0x15 |
| 236 | #define WLANDXE_CH_CTRL_EDVEN_DEFAULT 0x0 |
| 237 | |
| 238 | #define WLANDXE_CH_CTRL_EDEN_MASK 0x100000 |
| 239 | #define WLANDXE_CH_CTRL_EDEN_OFFSET 0x14 |
| 240 | #define WLANDXE_CH_CTRL_EDEN_DEFAULT 0x0 |
| 241 | |
| 242 | #define WLANDXE_CH_CTRL_INE_DONE_MASK 0x80000 |
| 243 | #define WLANDXE_CH_CTRL_INE_DONE_OFFSET 0x13 |
| 244 | #define WLANDXE_CH_CTRL_INE_DONE_DEFAULT 0x0 |
| 245 | |
| 246 | #define WLANDXE_CH_CTRL_INE_ERR_MASK 0x40000 |
| 247 | #define WLANDXE_CH_CTRL_INE_ERR_OFFSET 0x12 |
| 248 | #define WLANDXE_CH_CTRL_INE_ERR_DEFAULT 0x0 |
| 249 | |
| 250 | #define WLANDXE_CH_CTRL_INE_ED_MASK 0x20000 |
| 251 | #define WLANDXE_CH_CTRL_INE_ED_OFFSET 0x11 |
| 252 | #define WLANDXE_CH_CTRL_INE_ED_DEFAULT 0x0 |
| 253 | |
| 254 | #define WLANDXE_CH_CTRL_STOP_MASK 0x10000 |
| 255 | #define WLANDXE_CH_CTRL_STOP_OFFSET 0x10 |
| 256 | #define WLANDXE_CH_CTRL_STOP_DEFAULT 0x0 |
| 257 | |
| 258 | #define WLANDXE_CH_CTRL_PRIO_MASK 0xE000 |
| 259 | #define WLANDXE_CH_CTRL_PRIO_OFFSET 0xD |
| 260 | #define WLANDXE_CH_CTRL_PRIO_DEFAULT 0x0 |
| 261 | |
| 262 | #define WLANDXE_CH_CTRL_BTHLD_SEL_MASK 0x1E00 |
| 263 | #define WLANDXE_CH_CTRL_BTHLD_SEL_OFFSET 0x9 |
| 264 | #define WLANDXE_CH_CTRL_BTHLD_SEL_DEFAULT 0x600 |
| 265 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD0 0x0 |
| 266 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD1 0x1 |
| 267 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD2 0x2 |
| 268 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD3 0x3 |
| 269 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD4 0x4 |
| 270 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD5 0x5 |
| 271 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD6 0x6 |
| 272 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD7 0x7 |
| 273 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD8 0x8 |
| 274 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD9 0x9 |
| 275 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ETHLD10 0xA |
| 276 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD11 0xB |
| 277 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD12 0xC |
| 278 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD13 0xD |
| 279 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD14 0xE |
| 280 | #define WLANDXE_CH_CTRL_BTHLD_SEL_ERSVD15 0xF |
| 281 | |
| 282 | #define WLANDXE_CH_CTRL_PDU_REL_MASK 0x100 |
| 283 | #define WLANDXE_CH_CTRL_PDU_REL_OFFSET 0x8 |
| 284 | #define WLANDXE_CH_CTRL_PDU_REL_DEFAULT 0x100 |
| 285 | #define WLANDXE_CH_CTRL_PDU_REL_EKEEP 0x0 |
| 286 | #define WLANDXE_CH_CTRL_PDU_REL_ERELEASE 0x1 |
| 287 | |
| 288 | #define WLANDXE_CH_CTRL_PIQ_MASK 0x80 |
| 289 | #define WLANDXE_CH_CTRL_PIQ_OFFSET 0x7 |
| 290 | #define WLANDXE_CH_CTRL_PIQ_DEFAULT 0x0 |
| 291 | #define WLANDXE_CH_CTRL_PIQ_EFLAT 0x0 |
| 292 | #define WLANDXE_CH_CTRL_PIQ_EQUEUE 0x1 |
| 293 | |
| 294 | #define WLANDXE_CH_CTRL_DIQ_MASK 0x40 |
| 295 | #define WLANDXE_CH_CTRL_DIQ_OFFSET 0x6 |
| 296 | #define WLANDXE_CH_CTRL_DIQ_DEFAULT 0x0 |
| 297 | #define WLANDXE_CH_CTRL_DIQ_EFLAT 0x0 |
| 298 | #define WLANDXE_CH_CTRL_DIQ_EQUEUE 0x1 |
| 299 | |
| 300 | #define WLANDXE_CH_CTRL_SIQ_MASK 0x20 |
| 301 | #define WLANDXE_CH_CTRL_SIQ_OFFSET 0x5 |
| 302 | #define WLANDXE_CH_CTRL_SIQ_DEFAULT 0x0 |
| 303 | #define WLANDXE_CH_CTRL_SIQ_EFLAT 0x0 |
| 304 | #define WLANDXE_CH_CTRL_SIQ_EQUEUE 0x1 |
| 305 | |
| 306 | #define WLANDXE_CH_CTRL_BDH_MASK 0x10 |
| 307 | #define WLANDXE_CH_CTRL_BDH_OFFSET 0x4 |
| 308 | #define WLANDXE_CH_CTRL_BDH_DEFAULT 0x0 |
| 309 | |
| 310 | #define WLANDXE_CH_CTRL_EOP_MASK 0x8 |
| 311 | #define WLANDXE_CH_CTRL_EOP_OFFSET 0x3 |
| 312 | #define WLANDXE_CH_CTRL_EOP_DEFAULT 0x8 |
| 313 | |
| 314 | #define WLANDXE_CH_CTRL_XTYPE_MASK 0x6 |
| 315 | #define WLANDXE_CH_CTRL_XTYPE_OFFSET 0x1 |
| 316 | #define WLANDXE_CH_CTRL_XTYPE_DEFAULT 0x0 |
| 317 | #define WLANDXE_CH_CTRL_XTYPE_EH2H 0x0 |
| 318 | #define WLANDXE_CH_CTRL_XTYPE_EB2B 0x1 |
| 319 | #define WLANDXE_CH_CTRL_XTYPE_EH2B 0x2 |
| 320 | #define WLANDXE_CH_CTRL_XTYPE_EB2H 0x3 |
| 321 | |
| 322 | #define WLANDXE_CH_CTRL_DONE_MASK 0x4 |
| 323 | |
| 324 | #define WLANDXE_CH_CTRL_ERR_MASK 0x20 |
| 325 | |
| 326 | #define WLANDXE_CH_CTRL_MASKED_MASK 0x8 |
| 327 | |
| 328 | #define WLANDXE_CH_CTRL_EN_MASK 0x1 |
| 329 | #define WLANDXE_CH_CTRL_EN_OFFSET 0x0 |
| 330 | #define WLANDXE_CH_CTRL_EN_DEFAULT 0x0 |
| 331 | #define WLANDXE_CH_CTRL_DEFAULT 0x10000708 |
| 332 | |
| 333 | |
| 334 | #define WLANDXE_DESC_CTRL_VALID 0x00000001 |
| 335 | #define WLANDXE_DESC_CTRL_XTYPE_MASK 0x00000006 |
| 336 | #define WLANDXE_DESC_CTRL_XTYPE_H2H 0x00000000 |
| 337 | #define WLANDXE_DESC_CTRL_XTYPE_B2B 0x00000002 |
| 338 | #define WLANDXE_DESC_CTRL_XTYPE_H2B 0x00000004 |
| 339 | #define WLANDXE_DESC_CTRL_XTYPE_B2H 0x00000006 |
| 340 | #define WLANDXE_DESC_CTRL_EOP 0x00000008 |
| 341 | #define WLANDXE_DESC_CTRL_BDH 0x00000010 |
| 342 | #define WLANDXE_DESC_CTRL_SIQ 0x00000020 |
| 343 | #define WLANDXE_DESC_CTRL_DIQ 0x00000040 |
| 344 | #define WLANDXE_DESC_CTRL_PIQ 0x00000080 |
| 345 | #define WLANDXE_DESC_CTRL_PDU_REL 0x00000100 |
| 346 | #define WLANDXE_DESC_CTRL_BTHLD_SEL 0x00001E00 |
| 347 | #define WLANDXE_DESC_CTRL_PRIO 0x0000E000 |
| 348 | #define WLANDXE_DESC_CTRL_STOP 0x00010000 |
| 349 | #define WLANDXE_DESC_CTRL_INT 0x00020000 |
| 350 | #define WLANDXE_DESC_CTRL_BDT_SWAP 0x00100000 |
| 351 | #define WLANDXE_DESC_CTRL_ENDIANNESS 0x00200000 |
| 352 | #define WLANDXE_DESC_CTRL_DFMT 0x10000000 |
| 353 | #define WLANDXE_DESC_CTRL_RSVD 0xfffc0000 |
| 354 | /* CSR Register Control mask and offset */ |
| 355 | |
| 356 | #define WLANDXE_CH_STAT_INT_DONE_MASK 0x00008000 |
| 357 | #define WLANDXE_CH_STAT_INT_ERR_MASK 0x00004000 |
| 358 | #define WLANDXE_CH_STAT_INT_ED_MASK 0x00002000 |
| 359 | |
| 360 | #define WLANDXE_CH_STAT_MASKED_MASK 0x00000008 |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 361 | /* Till here WCNSS DXE register information |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 362 | * This is temporary definition location to make compile and unit test |
| 363 | * If official msmreg.h integrated, this part will be eliminated */ |
| 364 | |
| 365 | /* Interrupt control channel mask */ |
| 366 | #define WLANDXE_INT_MASK_CHAN_0 0x00000001 |
| 367 | #define WLANDXE_INT_MASK_CHAN_1 0x00000002 |
| 368 | #define WLANDXE_INT_MASK_CHAN_2 0x00000004 |
| 369 | #define WLANDXE_INT_MASK_CHAN_3 0x00000008 |
| 370 | #define WLANDXE_INT_MASK_CHAN_4 0x00000010 |
| 371 | #define WLANDXE_INT_MASK_CHAN_5 0x00000020 |
| 372 | #define WLANDXE_INT_MASK_CHAN_6 0x00000040 |
| 373 | |
| 374 | #define WLANDXE_TX_LOW_RES_THRESHOLD (5) |
| 375 | |
| 376 | /* DXE Descriptor Endian swap macro */ |
| 377 | #ifdef WLANDXE_ENDIAN_SWAP_ENABLE |
| 378 | #define WLANDXE_U32_SWAP_ENDIAN(a) (((a & 0x000000FF) << 24) | \ |
| 379 | ((a & 0x0000FF00) << 8) | \ |
| 380 | ((a & 0x00FF0000) >> 8) | \ |
| 381 | ((a & 0xFF000000) >> 24)) |
| 382 | #else |
| 383 | /* If DXE HW does not need endian swap, DO NOTHING */ |
| 384 | #define WLANDXE_U32_SWAP_ENDIAN(a) (a) |
| 385 | #endif /* WLANDXE_ENDIAN_SWAP_ENABLE */ |
| 386 | |
| 387 | /* Log Definition will be mappped with PAL MSG */ |
| 388 | #define HDXE_MSG WPAL_TRACE |
| 389 | #define HDXE_ASSERT(a) VOS_ASSERT(a) |
| 390 | |
| 391 | /*---------------------------------------------------------------------------- |
| 392 | * Type Declarations |
| 393 | * -------------------------------------------------------------------------*/ |
| 394 | /* DMA Channel Q handle Method type |
| 395 | * Linear handle or circular */ |
| 396 | typedef enum |
| 397 | { |
| 398 | WLANDXE_CHANNEL_HANDLE_LINEAR, |
| 399 | WLANDXE_CHANNEL_HANDLE_CIRCULA |
| 400 | }WLANDXE_ChannelHandleType; |
| 401 | |
| 402 | typedef enum |
| 403 | { |
| 404 | WLANDXE_TX_COMP_INT_LR_THRESHOLD, |
| 405 | WLANDXE_TX_COMP_INT_PER_K_FRAMES, |
| 406 | WLANDXE_TX_COMP_INT_TIMER |
| 407 | } WLANDXE_TXCompIntEnableType; |
| 408 | |
| 409 | typedef enum |
| 410 | { |
| 411 | WLANDXE_SHORT_DESCRIPTOR, |
| 412 | WLANDXE_LONG_DESCRIPTOR |
| 413 | } WLANDXE_DescriptorType; |
| 414 | |
| 415 | typedef enum |
| 416 | { |
| 417 | WLANDXE_DMA_CHANNEL_0, |
| 418 | WLANDXE_DMA_CHANNEL_1, |
| 419 | WLANDXE_DMA_CHANNEL_2, |
| 420 | WLANDXE_DMA_CHANNEL_3, |
| 421 | WLANDXE_DMA_CHANNEL_4, |
| 422 | WLANDXE_DMA_CHANNEL_5, |
| 423 | WLANDXE_DMA_CHANNEL_6, |
| 424 | WLANDXE_DMA_CHANNEL_MAX |
| 425 | } WLANDXE_DMAChannelType; |
| 426 | |
| 427 | /** DXE HW Long Descriptor format */ |
| 428 | typedef struct |
| 429 | { |
| 430 | wpt_uint32 srcMemAddrL; |
| 431 | wpt_uint32 srcMemAddrH; |
| 432 | wpt_uint32 dstMemAddrL; |
| 433 | wpt_uint32 dstMemAddrH; |
| 434 | wpt_uint32 phyNextL; |
| 435 | wpt_uint32 phyNextH; |
| 436 | } WLANDXE_LongDesc; |
| 437 | |
| 438 | |
| 439 | /** DXE HW Short Descriptor format */ |
| 440 | typedef struct tDXEShortDesc |
| 441 | { |
| 442 | wpt_uint32 srcMemAddrL; |
| 443 | wpt_uint32 dstMemAddrL; |
| 444 | wpt_uint32 phyNextL; |
| 445 | } WLANDXE_ShortDesc; |
| 446 | |
| 447 | |
| 448 | /* DXE Descriptor Data Type |
| 449 | * Pick up from GEN5 */ |
| 450 | typedef struct |
| 451 | { |
| 452 | union |
| 453 | { |
| 454 | wpt_uint32 ctrl; |
| 455 | wpt_uint32 valid :1; //0 = DMA stop, 1 = DMA continue with this descriptor |
| 456 | wpt_uint32 transferType :2; //0 = Host to Host space |
| 457 | wpt_uint32 eop :1; //End of Packet |
| 458 | wpt_uint32 bdHandling :1; //if transferType = Host to BMU, then 0 means first 128 bytes contain BD, and 1 means create new empty BD |
| 459 | wpt_uint32 siq :1; // SIQ |
| 460 | wpt_uint32 diq :1; // DIQ |
| 461 | wpt_uint32 pduRel :1; //0 = don't release BD and PDUs when done, 1 = release them |
| 462 | wpt_uint32 bthldSel :4; //BMU Threshold Select |
| 463 | wpt_uint32 prio :3; //Specifies the priority level to use for the transfer |
| 464 | wpt_uint32 stopChannel :1; //1 = DMA stops processing further, channel requires re-enabling after this |
| 465 | wpt_uint32 intr :1; //Interrupt on Descriptor Done |
| 466 | wpt_uint32 rsvd :1; //reserved |
| 467 | wpt_uint32 transferSize :14; //14 bits used - ignored for BMU transfers, only used for host to host transfers? |
| 468 | } descCtrl; |
| 469 | wpt_uint32 xfrSize; |
| 470 | union |
| 471 | { |
| 472 | WLANDXE_LongDesc dxe_long_desc; |
| 473 | WLANDXE_ShortDesc dxe_short_desc; |
| 474 | }dxedesc; |
| 475 | } WLANDXE_DescType; |
| 476 | |
| 477 | typedef struct |
| 478 | { |
| 479 | void *nextCtrlBlk; |
| 480 | wpt_packet *xfrFrame; |
| 481 | WLANDXE_DescType *linkedDesc; |
| 482 | unsigned int linkedDescPhyAddr; |
| 483 | wpt_uint32 ctrlBlkOrder; |
| 484 | #ifdef FEATURE_R33D |
| 485 | wpt_uint32 shadowBufferVa; |
| 486 | #endif /* FEATURE_R33D */ |
| 487 | } WLANDXE_DescCtrlBlkType; |
| 488 | |
| 489 | typedef struct |
| 490 | { |
| 491 | /* Q handle method, linear or ring */ |
| 492 | WLANDXE_ChannelHandleType queueMethod; |
| 493 | |
| 494 | /* Number of descriptors for DXE that can be queued for transfer at one time */ |
| 495 | wpt_uint32 nDescs; |
| 496 | |
| 497 | /* Maximum number of receive buffers of shared memory to use for this pipe */ |
| 498 | wpt_uint32 nRxBuffers; |
| 499 | |
| 500 | /* Reference WQ - for H2B and B2H only */ |
| 501 | wpt_uint32 refWQ; |
| 502 | |
| 503 | /* for usb only, endpoint info for CH_SADR or CH_DADR */ |
| 504 | wpt_uint32 refEP; |
| 505 | |
| 506 | /* H2B(Tx), B2H(Rx), H2H(SRAM<->HostMem R/W) */ |
| 507 | wpt_uint32 xfrType; |
| 508 | |
| 509 | /* Channel Priority 7(Highest) - 0(Lowest) */ |
| 510 | wpt_uint32 chPriority; |
| 511 | |
| 512 | /* 1 = BD attached to frames for this pipe */ |
| 513 | wpt_boolean bdPresent; |
| 514 | |
| 515 | wpt_uint32 chk_size; |
| 516 | |
| 517 | wpt_uint32 bmuThdSel; |
| 518 | |
| 519 | /* Added in Gen5 for Prefetch */ |
| 520 | wpt_boolean useLower4G; |
| 521 | |
| 522 | wpt_boolean useShortDescFmt; |
| 523 | /* Till here inharited from GEN5 code */ |
| 524 | /* From now on, added for PRIMA */ |
| 525 | } WLANDXE_ChannelConfigType; |
| 526 | |
| 527 | typedef struct |
| 528 | { |
| 529 | wpt_uint32 chDXEBaseAddr; |
| 530 | wpt_uint32 chDXEStatusRegAddr; |
| 531 | wpt_uint32 chDXEDesclRegAddr; |
| 532 | wpt_uint32 chDXEDeschRegAddr; |
| 533 | wpt_uint32 chDXELstDesclRegAddr; |
| 534 | wpt_uint32 chDXECtrlRegAddr; |
| 535 | wpt_uint32 chDXESzRegAddr; |
| 536 | wpt_uint32 chDXEDadrlRegAddr; |
| 537 | wpt_uint32 chDXEDadrhRegAddr; |
| 538 | wpt_uint32 chDXESadrlRegAddr; |
| 539 | wpt_uint32 chDXESadrhRegAddr; |
| 540 | } WLANDXE_ChannelRegisterType; |
| 541 | |
| 542 | typedef struct |
| 543 | { |
| 544 | wpt_uint32 refWQ_swapped; |
| 545 | wpt_boolean chEnabled; |
| 546 | wpt_boolean chConfigured; |
| 547 | wpt_uint32 channel; |
| 548 | wpt_uint32 chk_size_mask; |
| 549 | wpt_uint32 bmuThdSel_mask; |
| 550 | wpt_uint32 cw_ctrl_read; |
| 551 | wpt_uint32 cw_ctrl_write; |
| 552 | wpt_uint32 cw_ctrl_write_valid; |
| 553 | wpt_uint32 cw_ctrl_write_eop; |
| 554 | wpt_uint32 cw_ctrl_write_eop_int; |
| 555 | wpt_uint32 chan_mask; |
| 556 | wpt_uint32 chan_mask_read_disable; |
| 557 | wpt_uint32 intMask; |
| 558 | } WLANDXE_ChannelExConfigType; |
| 559 | |
| 560 | typedef struct |
| 561 | { |
| 562 | WDTS_ChannelType channelType; |
| 563 | WLANDXE_DescCtrlBlkType *headCtrlBlk; |
| 564 | WLANDXE_DescCtrlBlkType *tailCtrlBlk; |
| 565 | #if !(defined(FEATURE_R33D) || defined(WLANDXE_TEST_CHANNEL_ENABLE)) |
| 566 | WLANDXE_DescType *descriptorAllocation; |
| 567 | #endif |
| 568 | WLANDXE_DescType *DescBottomLoc; |
| 569 | unsigned int descBottomLocPhyAddr; |
| 570 | wpt_uint32 numDesc; |
| 571 | wpt_uint32 numFreeDesc; |
| 572 | wpt_uint32 numRsvdDesc; |
| 573 | wpt_uint32 maxFrameSize; |
| 574 | wpt_uint32 numFragmentCurrentChain; |
| 575 | wpt_uint32 numFrameBeforeInt; |
| 576 | wpt_uint32 numTotalFrame; |
| 577 | wpt_mutex dxeChannelLock; |
| 578 | wpt_boolean hitLowResource; |
| 579 | WLANDXE_ChannelConfigType channelConfig; |
| 580 | WLANDXE_ChannelRegisterType channelRegister; |
| 581 | WLANDXE_ChannelExConfigType extraConfig; |
| 582 | WLANDXE_DMAChannelType assignedDMAChannel; |
| 583 | wpt_uint64 rxDoneHistogram; |
Madan Mohan Koyyalamudi | ea77701 | 2012-10-31 14:22:34 -0700 | [diff] [blame^] | 584 | wpt_timer healthMonitorTimer; |
| 585 | wpt_msg *healthMonitorMsg; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 586 | } WLANDXE_ChannelCBType; |
| 587 | |
| 588 | typedef struct |
| 589 | { |
| 590 | WLANDXE_TXCompIntEnableType txIntEnable; |
| 591 | unsigned int txLowResourceThreshold_LoPriCh; |
| 592 | unsigned int txLowResourceThreshold_HiPriCh; |
| 593 | unsigned int rxLowResourceThreshold; |
| 594 | unsigned int txInterruptEnableFrameCount; |
| 595 | unsigned int txInterruptEnablePeriod; |
| 596 | } WLANDXE_TxCompIntConfigType; |
| 597 | |
| 598 | typedef struct |
| 599 | { |
| 600 | WLANDXE_ChannelCBType dxeChannel[WDTS_CHANNEL_MAX]; |
| 601 | WLANDXE_RxFrameReadyCbType rxReadyCB; |
| 602 | WLANDXE_TxCompleteCbType txCompCB; |
| 603 | WLANDXE_LowResourceCbType lowResourceCB; |
| 604 | WLANDXE_TxCompIntConfigType txCompInt; |
| 605 | void *clientCtxt; |
| 606 | wpt_uint32 interruptPath; |
| 607 | wpt_msg *rxIsrMsg; |
| 608 | wpt_msg *txIsrMsg; |
| 609 | wpt_msg *rxPktAvailMsg; |
| 610 | volatile WLANDXE_PowerStateType hostPowerState; |
| 611 | wpt_boolean rxIntDisabledByIMPS; |
| 612 | wpt_boolean txIntDisabledByIMPS; |
| 613 | WLANDXE_SetPowerStateCbType setPowerStateCb; |
| 614 | volatile WLANDXE_RivaPowerStateType rivaPowerState; |
| 615 | wpt_boolean ringNotEmpty; |
| 616 | wpt_boolean txIntEnable; |
| 617 | wpt_uint32 txCompletedFrames; |
| 618 | wpt_uint8 ucTxMsgCnt; |
| 619 | wpt_uint16 lastKickOffDxe; |
| 620 | wpt_uint32 dxeCookie; |
| 621 | wpt_packet *freeRXPacket; |
| 622 | wpt_boolean rxPalPacketUnavailable; |
Jeff Johnson | e724574 | 2012-09-05 17:12:55 -0700 | [diff] [blame] | 623 | wpt_boolean driverReloadInProcessing; |
Jeff Johnson | 295189b | 2012-06-20 16:38:30 -0700 | [diff] [blame] | 624 | } WLANDXE_CtrlBlkType; |
| 625 | |
| 626 | /*========================================================================== |
| 627 | @ Function Name |
| 628 | dxeCommonDefaultConfig |
| 629 | |
| 630 | @ Description |
| 631 | |
| 632 | @ Parameters |
| 633 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 634 | DXE host driver main control block |
| 635 | |
| 636 | @ Return |
| 637 | wpt_status |
| 638 | |
| 639 | ===========================================================================*/ |
| 640 | extern wpt_status dxeCommonDefaultConfig |
| 641 | ( |
| 642 | WLANDXE_CtrlBlkType *dxeCtrlBlk |
| 643 | ); |
| 644 | |
| 645 | /*========================================================================== |
| 646 | @ Function Name |
| 647 | dxeChannelDefaultConfig |
| 648 | |
| 649 | @ Description |
| 650 | Get defualt configuration values from pre defined structure |
| 651 | All the channels must have it's own configurations |
| 652 | |
| 653 | @ Parameters |
| 654 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 655 | DXE host driver main control block |
| 656 | WLANDXE_ChannelCBType *channelEntry |
| 657 | Channel specific control block |
| 658 | |
| 659 | @ Return |
| 660 | wpt_status |
| 661 | |
| 662 | ===========================================================================*/ |
| 663 | extern wpt_status dxeChannelDefaultConfig |
| 664 | ( |
| 665 | WLANDXE_CtrlBlkType *dxeCtrlBlk, |
| 666 | WLANDXE_ChannelCBType *channelEntry |
| 667 | ); |
| 668 | |
| 669 | #endif /* WLAN_QCT_DXE_I_H */ |