| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1 | /* |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 2 | * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef _AR6320V2DEF_H_ |
| 29 | #define _AR6320V2DEF_H_ |
| 30 | |
| 31 | /* Base Addresses */ |
| 32 | #define AR6320V2_RTC_SOC_BASE_ADDRESS 0x00000800 |
| 33 | #define AR6320V2_RTC_WMAC_BASE_ADDRESS 0x00001000 |
| 34 | #define AR6320V2_MAC_COEX_BASE_ADDRESS 0x0000f000 |
| 35 | #define AR6320V2_BT_COEX_BASE_ADDRESS 0x00002000 |
| 36 | #define AR6320V2_SOC_PCIE_BASE_ADDRESS 0x00038000 |
| 37 | #define AR6320V2_SOC_CORE_BASE_ADDRESS 0x0003a000 |
| 38 | #define AR6320V2_WLAN_UART_BASE_ADDRESS 0x0000c000 |
| 39 | #define AR6320V2_WLAN_SI_BASE_ADDRESS 0x00010000 |
| 40 | #define AR6320V2_WLAN_GPIO_BASE_ADDRESS 0x00005000 |
| 41 | #define AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00006000 |
| 42 | #define AR6320V2_WLAN_MAC_BASE_ADDRESS 0x00010000 |
| 43 | #define AR6320V2_EFUSE_BASE_ADDRESS 0x00024000 |
| 44 | #define AR6320V2_FPGA_REG_BASE_ADDRESS 0x00039000 |
| 45 | #define AR6320V2_WLAN_UART2_BASE_ADDRESS 0x00054c00 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 46 | #define AR6320V2_DBI_BASE_ADDRESS 0x0003c000 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 47 | |
| 48 | #define AR6320V2_SCRATCH_3_ADDRESS 0x0028 |
| 49 | #define AR6320V2_TARG_DRAM_START 0x00400000 |
| 50 | #define AR6320V2_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 |
| 51 | #define AR6320V2_SOC_RESET_CONTROL_OFFSET 0x00000000 |
| 52 | #define AR6320V2_SOC_CLOCK_CONTROL_OFFSET 0x00000028 |
| 53 | #define AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| 54 | #define AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000000 |
| 55 | #define AR6320V2_WLAN_GPIO_PIN0_ADDRESS 0x00000068 |
| 56 | #define AR6320V2_WLAN_GPIO_PIN1_ADDRESS 0x0000006c |
| 57 | #define AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 |
| 58 | #define AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 |
| 59 | #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 |
| 60 | #define AR6320V2_SOC_LPO_CAL_OFFSET 0x000000e0 |
| 61 | #define AR6320V2_WLAN_GPIO_PIN10_ADDRESS 0x00000090 |
| 62 | #define AR6320V2_WLAN_GPIO_PIN11_ADDRESS 0x00000094 |
| 63 | #define AR6320V2_WLAN_GPIO_PIN12_ADDRESS 0x00000098 |
| 64 | #define AR6320V2_WLAN_GPIO_PIN13_ADDRESS 0x0000009c |
| 65 | #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 |
| 66 | #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 67 | #define AR6320V2_SOC_LPO_CAL_ENABLE_LSB 20 |
| 68 | #define AR6320V2_SOC_LPO_CAL_ENABLE_MASK 0x00100000 |
| 69 | |
| 70 | #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 |
| 71 | #define AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| 72 | #define AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
| 73 | #define AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 |
| 74 | #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB 18 |
| 75 | #define AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 |
| 76 | #define AR6320V2_SI_CONFIG_I2C_LSB 16 |
| 77 | #define AR6320V2_SI_CONFIG_I2C_MASK 0x00010000 |
| 78 | #define AR6320V2_SI_CONFIG_POS_SAMPLE_LSB 7 |
| 79 | #define AR6320V2_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 |
| 80 | #define AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB 4 |
| 81 | #define AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 |
| 82 | #define AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB 5 |
| 83 | #define AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 |
| 84 | #define AR6320V2_SI_CONFIG_DIVIDER_LSB 0 |
| 85 | #define AR6320V2_SI_CONFIG_DIVIDER_MASK 0x0000000f |
| 86 | #define AR6320V2_SI_CONFIG_OFFSET 0x00000000 |
| 87 | #define AR6320V2_SI_TX_DATA0_OFFSET 0x00000008 |
| 88 | #define AR6320V2_SI_TX_DATA1_OFFSET 0x0000000c |
| 89 | #define AR6320V2_SI_RX_DATA0_OFFSET 0x00000010 |
| 90 | #define AR6320V2_SI_RX_DATA1_OFFSET 0x00000014 |
| 91 | #define AR6320V2_SI_CS_OFFSET 0x00000004 |
| 92 | #define AR6320V2_SI_CS_DONE_ERR_MASK 0x00000400 |
| 93 | #define AR6320V2_SI_CS_DONE_INT_MASK 0x00000200 |
| 94 | #define AR6320V2_SI_CS_START_LSB 8 |
| 95 | #define AR6320V2_SI_CS_START_MASK 0x00000100 |
| 96 | #define AR6320V2_SI_CS_RX_CNT_LSB 4 |
| 97 | #define AR6320V2_SI_CS_RX_CNT_MASK 0x000000f0 |
| 98 | #define AR6320V2_SI_CS_TX_CNT_LSB 0 |
| 99 | #define AR6320V2_SI_CS_TX_CNT_MASK 0x0000000f |
| 100 | #define AR6320V2_CE_COUNT 8 |
| 101 | #define AR6320V2_SR_WR_INDEX_ADDRESS 0x003c |
| 102 | #define AR6320V2_DST_WATERMARK_ADDRESS 0x0050 |
| 103 | #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB 14 |
| 104 | #define AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 |
| 105 | #define AR6320V2_RX_MPDU_START_0_RETRY_LSB 14 |
| 106 | #define AR6320V2_RX_MPDU_START_0_RETRY_MASK 0x00004000 |
| 107 | #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB 16 |
| 108 | #define AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 |
| 109 | #define AR6320V2_RX_MPDU_START_2_PN_47_32_LSB 0 |
| 110 | #define AR6320V2_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff |
| 111 | #define AR6320V2_RX_MPDU_START_2_TID_LSB 28 |
| 112 | #define AR6320V2_RX_MPDU_START_2_TID_MASK 0xf0000000 |
| 113 | #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 |
| 114 | #define AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 |
| 115 | #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB 15 |
| 116 | #define AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 |
| 117 | #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB 2 |
| 118 | #define AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 |
| 119 | #define AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB 13 |
| 120 | #define AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 |
| 121 | #define AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 |
| 122 | #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 |
| 123 | #define AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 |
| 124 | #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 |
| 125 | #define AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff |
| 126 | |
| 127 | #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 |
| 128 | #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 |
| 129 | #define AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 |
| 130 | #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB 13 |
| 131 | #define AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 |
| 132 | #define AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 |
| 133 | #define AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 |
| 134 | #define AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 |
| 135 | #define AR6320V2_DST_WR_INDEX_ADDRESS 0x0040 |
| 136 | #define AR6320V2_SRC_WATERMARK_ADDRESS 0x004c |
| 137 | #define AR6320V2_SRC_WATERMARK_LOW_MASK 0xffff0000 |
| 138 | #define AR6320V2_SRC_WATERMARK_HIGH_MASK 0x0000ffff |
| 139 | #define AR6320V2_DST_WATERMARK_LOW_MASK 0xffff0000 |
| 140 | #define AR6320V2_DST_WATERMARK_HIGH_MASK 0x0000ffff |
| 141 | #define AR6320V2_CURRENT_SRRI_ADDRESS 0x0044 |
| 142 | #define AR6320V2_CURRENT_DRRI_ADDRESS 0x0048 |
| 143 | #define AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 |
| 144 | #define AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004 |
| 145 | #define AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008 |
| 146 | #define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010 |
| 147 | #define AR6320V2_HOST_IS_ADDRESS 0x0030 |
| 148 | #define AR6320V2_HOST_IS_COPY_COMPLETE_MASK 0x00000001 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 149 | #define AR6320V2_HOST_IE_ADDRESS 0x002c |
| 150 | #define AR6320V2_HOST_IE_COPY_COMPLETE_MASK 0x00000001 |
| 151 | #define AR6320V2_SR_BA_ADDRESS 0x0000 |
| 152 | #define AR6320V2_SR_SIZE_ADDRESS 0x0004 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 153 | #define AR6320V2_DR_BA_ADDRESS 0x0008 |
| 154 | #define AR6320V2_DR_SIZE_ADDRESS 0x000c |
| 155 | #define AR6320V2_MISC_IE_ADDRESS 0x0034 |
| 156 | #define AR6320V2_MISC_IS_AXI_ERR_MASK 0x00000400 |
| 157 | #define AR6320V2_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 |
| 158 | #define AR6320V2_MISC_IS_SRC_LEN_ERR_MASK 0x00000100 |
| 159 | #define AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080 |
| 160 | #define AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040 |
| 161 | #define AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020 |
| 162 | #define AR6320V2_SRC_WATERMARK_LOW_LSB 16 |
| 163 | #define AR6320V2_SRC_WATERMARK_HIGH_LSB 0 |
| 164 | #define AR6320V2_DST_WATERMARK_LOW_LSB 16 |
| 165 | #define AR6320V2_DST_WATERMARK_HIGH_LSB 0 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 166 | #define AR6320V2_SOC_GLOBAL_RESET_ADDRESS 0x0008 |
| 167 | #define AR6320V2_RTC_STATE_ADDRESS 0x0000 |
| 168 | #define AR6320V2_RTC_STATE_COLD_RESET_MASK 0x00002000 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 169 | #define AR6320V2_RTC_STATE_V_MASK 0x00000007 |
| 170 | #define AR6320V2_RTC_STATE_V_LSB 0 |
| 171 | #define AR6320V2_RTC_STATE_V_ON 3 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 172 | #define AR6320V2_FW_IND_EVENT_PENDING 1 |
| 173 | #define AR6320V2_FW_IND_INITIALIZED 2 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 174 | #define AR6320V2_CPU_INTR_ADDRESS 0x0010 |
| 175 | #define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
| 176 | #define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 |
| 177 | #define AR6320V2_SOC_RESET_CONTROL_ADDRESS 0x00000000 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 178 | #define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
| 179 | #define AR6320V2_CORE_CTRL_ADDRESS 0x0000 |
| 180 | #define AR6320V2_CORE_CTRL_CPU_INTR_MASK 0x00002000 |
| 181 | #define AR6320V2_LOCAL_SCRATCH_OFFSET 0x000000c0 |
| 182 | #define AR6320V2_CLOCK_GPIO_OFFSET 0xffffffff |
| 183 | #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 |
| 184 | #define AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 |
| 185 | #define AR6320V2_SOC_CHIP_ID_ADDRESS 0x000000f0 |
| 186 | #define AR6320V2_SOC_CHIP_ID_VERSION_MASK 0xfffc0000 |
| 187 | #define AR6320V2_SOC_CHIP_ID_VERSION_LSB 18 |
| 188 | #define AR6320V2_SOC_CHIP_ID_REVISION_MASK 0x00000f00 |
| 189 | #define AR6320V2_SOC_CHIP_ID_REVISION_LSB 8 |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 190 | #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) |
| 191 | #define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000 |
| 192 | #define AR6320V2_CE0_BASE_ADDRESS 0x00034400 |
| 193 | #define AR6320V2_CE1_BASE_ADDRESS 0x00034800 |
| 194 | #define AR6320V2_CE2_BASE_ADDRESS 0x00034c00 |
| 195 | #define AR6320V2_CE3_BASE_ADDRESS 0x00035000 |
| 196 | #define AR6320V2_CE4_BASE_ADDRESS 0x00035400 |
| 197 | #define AR6320V2_CE5_BASE_ADDRESS 0x00035800 |
| 198 | #define AR6320V2_CE6_BASE_ADDRESS 0x00035c00 |
| 199 | #define AR6320V2_CE7_BASE_ADDRESS 0x00036000 |
| 200 | #define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800 |
| 201 | #define AR6320V2_CE_CTRL1_ADDRESS 0x0010 |
| 202 | #define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff |
| 203 | #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000 |
| 204 | #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00 |
| 205 | #define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8 |
| 206 | #define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0 |
| 207 | #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000 |
| 208 | #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000 |
| 209 | #define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16 |
| 210 | #define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17 |
| 211 | #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020 |
| 212 | #define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5 |
| 213 | #define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000 |
| 214 | #define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004 |
| 215 | #define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001 |
| 216 | #define AR6320V2_MUX_ID_MASK 0x0000 |
| 217 | #define AR6320V2_TRANSACTION_ID_MASK 0x3fff |
| 218 | #define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000 |
| 219 | #define AR6320V2_FW_IND_HELPER 4 |
| 220 | #define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008 |
| 221 | #define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014 |
| 222 | #define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400 |
| 223 | #define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800 |
| 224 | #define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800 |
| 225 | #define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c |
| 226 | #define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 227 | #define AR6320V2_SOC_POWER_REG_OFFSET 0x0000010c |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 228 | /* Copy Engine Debug */ |
| 229 | #define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c |
| 230 | #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 |
| 231 | #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 |
| 232 | #define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f |
| 233 | #define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET 0x00000108 |
| 234 | #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB 0 |
| 235 | #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB 0 |
| 236 | #define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 |
| 237 | #define AR6320V2_WLAN_DEBUG_OUT_OFFSET 0x00000110 |
| 238 | #define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB 19 |
| 239 | #define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB 0 |
| 240 | #define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff |
| 241 | #define AR6320V2_AMBA_DEBUG_BUS_OFFSET 0x0000011c |
| 242 | #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13 |
| 243 | #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8 |
| 244 | #define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00 |
| 245 | #define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB 4 |
| 246 | #define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB 0 |
| 247 | #define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f |
| 248 | #define AR6320V2_CE_WRAPPER_DEBUG_OFFSET 0x0008 |
| 249 | #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB 5 |
| 250 | #define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB 0 |
| 251 | #define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK 0x0000003f |
| 252 | #define AR6320V2_CE_DEBUG_OFFSET 0x0054 |
| 253 | #define AR6320V2_CE_DEBUG_SEL_MSB 5 |
| 254 | #define AR6320V2_CE_DEBUG_SEL_LSB 0 |
| 255 | #define AR6320V2_CE_DEBUG_SEL_MASK 0x0000003f |
| 256 | /* End */ |
| 257 | |
| 258 | /* PLL start */ |
| 259 | #define AR6320V2_EFUSE_OFFSET 0x0000032c |
| 260 | #define AR6320V2_EFUSE_XTAL_SEL_MSB 10 |
| 261 | #define AR6320V2_EFUSE_XTAL_SEL_LSB 8 |
| 262 | #define AR6320V2_EFUSE_XTAL_SEL_MASK 0x00000700 |
| 263 | #define AR6320V2_BB_PLL_CONFIG_OFFSET 0x000002f4 |
| 264 | #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB 20 |
| 265 | #define AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB 18 |
| 266 | #define AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 |
| 267 | #define AR6320V2_BB_PLL_CONFIG_FRAC_MSB 17 |
| 268 | #define AR6320V2_BB_PLL_CONFIG_FRAC_LSB 0 |
| 269 | #define AR6320V2_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff |
| 270 | #define AR6320V2_WLAN_PLL_SETTLE_TIME_MSB 10 |
| 271 | #define AR6320V2_WLAN_PLL_SETTLE_TIME_LSB 0 |
| 272 | #define AR6320V2_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff |
| 273 | #define AR6320V2_WLAN_PLL_SETTLE_OFFSET 0x0018 |
| 274 | #define AR6320V2_WLAN_PLL_SETTLE_SW_MASK 0x000007ff |
| 275 | #define AR6320V2_WLAN_PLL_SETTLE_RSTMASK 0xffffffff |
| 276 | #define AR6320V2_WLAN_PLL_SETTLE_RESET 0x00000400 |
| 277 | #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB 18 |
| 278 | #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB 18 |
| 279 | #define AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 |
| 280 | #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB 16 |
| 281 | #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB 16 |
| 282 | #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 |
| 283 | #define AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET 0x1 |
| 284 | #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB 15 |
| 285 | #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB 14 |
| 286 | #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000 |
| 287 | #define AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0 |
| 288 | #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB 13 |
| 289 | #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB 10 |
| 290 | #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 |
| 291 | #define AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET 0x0 |
| 292 | #define AR6320V2_WLAN_PLL_CONTROL_DIV_MSB 9 |
| 293 | #define AR6320V2_WLAN_PLL_CONTROL_DIV_LSB 0 |
| 294 | #define AR6320V2_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff |
| 295 | #define AR6320V2_WLAN_PLL_CONTROL_DIV_RESET 0x11 |
| 296 | #define AR6320V2_WLAN_PLL_CONTROL_OFFSET 0x0014 |
| 297 | #define AR6320V2_WLAN_PLL_CONTROL_SW_MASK 0x001fffff |
| 298 | #define AR6320V2_WLAN_PLL_CONTROL_RSTMASK 0xffffffff |
| 299 | #define AR6320V2_WLAN_PLL_CONTROL_RESET 0x00010011 |
| 300 | #define AR6320V2_SOC_CORE_CLK_CTRL_OFFSET 0x00000114 |
| 301 | #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB 2 |
| 302 | #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB 0 |
| 303 | #define AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 |
| 304 | #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5 |
| 305 | #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 |
| 306 | #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 |
| 307 | #define AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0 |
| 308 | #define AR6320V2_RTC_SYNC_STATUS_OFFSET 0x0244 |
| 309 | #define AR6320V2_SOC_CPU_CLOCK_OFFSET 0x00000020 |
| 310 | #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB 1 |
| 311 | #define AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB 0 |
| 312 | #define AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| 313 | /* PLL end */ |
| 314 | |
| 315 | #define AR6320V2_PCIE_INTR_CE_MASK(n) \ |
| 316 | (AR6320V2_PCIE_INTR_CE0_MASK << (n)) |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 317 | #endif |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 318 | #define AR6320V2_DRAM_BASE_ADDRESS AR6320V2_TARG_DRAM_START |
| 319 | #define AR6320V2_FW_INDICATOR_ADDRESS \ |
| 320 | (AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS) |
| 321 | #define AR6320V2_SYSTEM_SLEEP_OFFSET AR6320V2_SOC_SYSTEM_SLEEP_OFFSET |
| 322 | #define AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET 0x002c |
| 323 | #define AR6320V2_WLAN_RESET_CONTROL_OFFSET AR6320V2_SOC_RESET_CONTROL_OFFSET |
| 324 | #define AR6320V2_CLOCK_CONTROL_OFFSET AR6320V2_SOC_CLOCK_CONTROL_OFFSET |
| 325 | #define AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK \ |
| 326 | AR6320V2_SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| 327 | #define AR6320V2_RESET_CONTROL_MBOX_RST_MASK 0x00000004 |
| 328 | #define AR6320V2_RESET_CONTROL_SI0_RST_MASK \ |
| 329 | AR6320V2_SOC_RESET_CONTROL_SI0_RST_MASK |
| 330 | #define AR6320V2_GPIO_BASE_ADDRESS AR6320V2_WLAN_GPIO_BASE_ADDRESS |
| 331 | #define AR6320V2_GPIO_PIN0_OFFSET AR6320V2_WLAN_GPIO_PIN0_ADDRESS |
| 332 | #define AR6320V2_GPIO_PIN1_OFFSET AR6320V2_WLAN_GPIO_PIN1_ADDRESS |
| 333 | #define AR6320V2_GPIO_PIN0_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN0_CONFIG_MASK |
| 334 | #define AR6320V2_GPIO_PIN1_CONFIG_MASK AR6320V2_WLAN_GPIO_PIN1_CONFIG_MASK |
| 335 | #define AR6320V2_SI_BASE_ADDRESS 0x00050000 |
| 336 | #define AR6320V2_CPU_CLOCK_OFFSET AR6320V2_SOC_CPU_CLOCK_OFFSET |
| 337 | #define AR6320V2_LPO_CAL_OFFSET AR6320V2_SOC_LPO_CAL_OFFSET |
| 338 | #define AR6320V2_GPIO_PIN10_OFFSET AR6320V2_WLAN_GPIO_PIN10_ADDRESS |
| 339 | #define AR6320V2_GPIO_PIN11_OFFSET AR6320V2_WLAN_GPIO_PIN11_ADDRESS |
| 340 | #define AR6320V2_GPIO_PIN12_OFFSET AR6320V2_WLAN_GPIO_PIN12_ADDRESS |
| 341 | #define AR6320V2_GPIO_PIN13_OFFSET AR6320V2_WLAN_GPIO_PIN13_ADDRESS |
| 342 | #define AR6320V2_CPU_CLOCK_STANDARD_LSB AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB |
| 343 | #define AR6320V2_CPU_CLOCK_STANDARD_MASK AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK |
| 344 | #define AR6320V2_LPO_CAL_ENABLE_LSB AR6320V2_SOC_LPO_CAL_ENABLE_LSB |
| 345 | #define AR6320V2_LPO_CAL_ENABLE_MASK AR6320V2_SOC_LPO_CAL_ENABLE_MASK |
| 346 | #define AR6320V2_ANALOG_INTF_BASE_ADDRESS \ |
| 347 | AR6320V2_WLAN_ANALOG_INTF_BASE_ADDRESS |
| 348 | #define AR6320V2_MBOX_BASE_ADDRESS 0x00008000 |
| 349 | #define AR6320V2_INT_STATUS_ENABLE_ERROR_LSB 7 |
| 350 | #define AR6320V2_INT_STATUS_ENABLE_ERROR_MASK 0x00000080 |
| 351 | #define AR6320V2_INT_STATUS_ENABLE_CPU_LSB 6 |
| 352 | #define AR6320V2_INT_STATUS_ENABLE_CPU_MASK 0x00000040 |
| 353 | #define AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB 4 |
| 354 | #define AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010 |
| 355 | #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB 0 |
| 356 | #define AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f |
| 357 | #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 17 |
| 358 | #define AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00020000 |
| 359 | #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 16 |
| 360 | #define AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00010000 |
| 361 | #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB 24 |
| 362 | #define AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0xff000000 |
| 363 | #define AR6320V2_INT_STATUS_ENABLE_ADDRESS 0x0828 |
| 364 | #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB 8 |
| 365 | #define AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK 0x0000ff00 |
| 366 | #define AR6320V2_HOST_INT_STATUS_ADDRESS 0x0800 |
| 367 | #define AR6320V2_CPU_INT_STATUS_ADDRESS 0x0801 |
| 368 | #define AR6320V2_ERROR_INT_STATUS_ADDRESS 0x0802 |
| 369 | #define AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK 0x00040000 |
| 370 | #define AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB 18 |
| 371 | #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00020000 |
| 372 | #define AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB 17 |
| 373 | #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00010000 |
| 374 | #define AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB 16 |
| 375 | #define AR6320V2_COUNT_DEC_ADDRESS 0x0840 |
| 376 | #define AR6320V2_HOST_INT_STATUS_CPU_MASK 0x00000040 |
| 377 | #define AR6320V2_HOST_INT_STATUS_CPU_LSB 6 |
| 378 | #define AR6320V2_HOST_INT_STATUS_ERROR_MASK 0x00000080 |
| 379 | #define AR6320V2_HOST_INT_STATUS_ERROR_LSB 7 |
| 380 | #define AR6320V2_HOST_INT_STATUS_COUNTER_MASK 0x00000010 |
| 381 | #define AR6320V2_HOST_INT_STATUS_COUNTER_LSB 4 |
| 382 | #define AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS 0x0805 |
| 383 | #define AR6320V2_WINDOW_DATA_ADDRESS 0x0874 |
| 384 | #define AR6320V2_WINDOW_READ_ADDR_ADDRESS 0x087c |
| 385 | #define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS 0x0878 |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 386 | #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f |
| 387 | #define AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB 0 |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 388 | |
| 389 | struct targetdef_s ar6320v2_targetdef = { |
| 390 | .d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS, |
| 391 | .d_RTC_WMAC_BASE_ADDRESS = AR6320V2_RTC_WMAC_BASE_ADDRESS, |
| 392 | .d_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, |
| 393 | .d_WLAN_SYSTEM_SLEEP_OFFSET = AR6320V2_WLAN_SYSTEM_SLEEP_OFFSET, |
| 394 | .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = |
| 395 | AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_LSB, |
| 396 | .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = |
| 397 | AR6320V2_WLAN_SYSTEM_SLEEP_DISABLE_MASK, |
| 398 | .d_CLOCK_CONTROL_OFFSET = AR6320V2_CLOCK_CONTROL_OFFSET, |
| 399 | .d_CLOCK_CONTROL_SI0_CLK_MASK = AR6320V2_CLOCK_CONTROL_SI0_CLK_MASK, |
| 400 | .d_RESET_CONTROL_OFFSET = AR6320V2_SOC_RESET_CONTROL_OFFSET, |
| 401 | .d_RESET_CONTROL_MBOX_RST_MASK = AR6320V2_RESET_CONTROL_MBOX_RST_MASK, |
| 402 | .d_RESET_CONTROL_SI0_RST_MASK = AR6320V2_RESET_CONTROL_SI0_RST_MASK, |
| 403 | .d_WLAN_RESET_CONTROL_OFFSET = AR6320V2_WLAN_RESET_CONTROL_OFFSET, |
| 404 | .d_WLAN_RESET_CONTROL_COLD_RST_MASK = |
| 405 | AR6320V2_WLAN_RESET_CONTROL_COLD_RST_MASK, |
| 406 | .d_WLAN_RESET_CONTROL_WARM_RST_MASK = |
| 407 | AR6320V2_WLAN_RESET_CONTROL_WARM_RST_MASK, |
| 408 | .d_GPIO_BASE_ADDRESS = AR6320V2_GPIO_BASE_ADDRESS, |
| 409 | .d_GPIO_PIN0_OFFSET = AR6320V2_GPIO_PIN0_OFFSET, |
| 410 | .d_GPIO_PIN1_OFFSET = AR6320V2_GPIO_PIN1_OFFSET, |
| 411 | .d_GPIO_PIN0_CONFIG_MASK = AR6320V2_GPIO_PIN0_CONFIG_MASK, |
| 412 | .d_GPIO_PIN1_CONFIG_MASK = AR6320V2_GPIO_PIN1_CONFIG_MASK, |
| 413 | .d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR6320V2_SI_CONFIG_BIDIR_OD_DATA_LSB, |
| 414 | .d_SI_CONFIG_BIDIR_OD_DATA_MASK = |
| 415 | AR6320V2_SI_CONFIG_BIDIR_OD_DATA_MASK, |
| 416 | .d_SI_CONFIG_I2C_LSB = AR6320V2_SI_CONFIG_I2C_LSB, |
| 417 | .d_SI_CONFIG_I2C_MASK = AR6320V2_SI_CONFIG_I2C_MASK, |
| 418 | .d_SI_CONFIG_POS_SAMPLE_LSB = AR6320V2_SI_CONFIG_POS_SAMPLE_LSB, |
| 419 | .d_SI_CONFIG_POS_SAMPLE_MASK = AR6320V2_SI_CONFIG_POS_SAMPLE_MASK, |
| 420 | .d_SI_CONFIG_INACTIVE_CLK_LSB = AR6320V2_SI_CONFIG_INACTIVE_CLK_LSB, |
| 421 | .d_SI_CONFIG_INACTIVE_CLK_MASK = AR6320V2_SI_CONFIG_INACTIVE_CLK_MASK, |
| 422 | .d_SI_CONFIG_INACTIVE_DATA_LSB = AR6320V2_SI_CONFIG_INACTIVE_DATA_LSB, |
| 423 | .d_SI_CONFIG_INACTIVE_DATA_MASK = |
| 424 | AR6320V2_SI_CONFIG_INACTIVE_DATA_MASK, |
| 425 | .d_SI_CONFIG_DIVIDER_LSB = AR6320V2_SI_CONFIG_DIVIDER_LSB, |
| 426 | .d_SI_CONFIG_DIVIDER_MASK = AR6320V2_SI_CONFIG_DIVIDER_MASK, |
| 427 | .d_SI_BASE_ADDRESS = AR6320V2_SI_BASE_ADDRESS, |
| 428 | .d_SI_CONFIG_OFFSET = AR6320V2_SI_CONFIG_OFFSET, |
| 429 | .d_SI_TX_DATA0_OFFSET = AR6320V2_SI_TX_DATA0_OFFSET, |
| 430 | .d_SI_TX_DATA1_OFFSET = AR6320V2_SI_TX_DATA1_OFFSET, |
| 431 | .d_SI_RX_DATA0_OFFSET = AR6320V2_SI_RX_DATA0_OFFSET, |
| 432 | .d_SI_RX_DATA1_OFFSET = AR6320V2_SI_RX_DATA1_OFFSET, |
| 433 | .d_SI_CS_OFFSET = AR6320V2_SI_CS_OFFSET, |
| 434 | .d_SI_CS_DONE_ERR_MASK = AR6320V2_SI_CS_DONE_ERR_MASK, |
| 435 | .d_SI_CS_DONE_INT_MASK = AR6320V2_SI_CS_DONE_INT_MASK, |
| 436 | .d_SI_CS_START_LSB = AR6320V2_SI_CS_START_LSB, |
| 437 | .d_SI_CS_START_MASK = AR6320V2_SI_CS_START_MASK, |
| 438 | .d_SI_CS_RX_CNT_LSB = AR6320V2_SI_CS_RX_CNT_LSB, |
| 439 | .d_SI_CS_RX_CNT_MASK = AR6320V2_SI_CS_RX_CNT_MASK, |
| 440 | .d_SI_CS_TX_CNT_LSB = AR6320V2_SI_CS_TX_CNT_LSB, |
| 441 | .d_SI_CS_TX_CNT_MASK = AR6320V2_SI_CS_TX_CNT_MASK, |
| 442 | .d_BOARD_DATA_SZ = AR6320_BOARD_DATA_SZ, |
| 443 | .d_BOARD_EXT_DATA_SZ = AR6320_BOARD_EXT_DATA_SZ, |
| 444 | .d_MBOX_BASE_ADDRESS = AR6320V2_MBOX_BASE_ADDRESS, |
| 445 | .d_LOCAL_SCRATCH_OFFSET = AR6320V2_LOCAL_SCRATCH_OFFSET, |
| 446 | .d_CPU_CLOCK_OFFSET = AR6320V2_CPU_CLOCK_OFFSET, |
| 447 | .d_LPO_CAL_OFFSET = AR6320V2_LPO_CAL_OFFSET, |
| 448 | .d_GPIO_PIN10_OFFSET = AR6320V2_GPIO_PIN10_OFFSET, |
| 449 | .d_GPIO_PIN11_OFFSET = AR6320V2_GPIO_PIN11_OFFSET, |
| 450 | .d_GPIO_PIN12_OFFSET = AR6320V2_GPIO_PIN12_OFFSET, |
| 451 | .d_GPIO_PIN13_OFFSET = AR6320V2_GPIO_PIN13_OFFSET, |
| 452 | .d_CLOCK_GPIO_OFFSET = AR6320V2_CLOCK_GPIO_OFFSET, |
| 453 | .d_CPU_CLOCK_STANDARD_LSB = AR6320V2_CPU_CLOCK_STANDARD_LSB, |
| 454 | .d_CPU_CLOCK_STANDARD_MASK = AR6320V2_CPU_CLOCK_STANDARD_MASK, |
| 455 | .d_LPO_CAL_ENABLE_LSB = AR6320V2_LPO_CAL_ENABLE_LSB, |
| 456 | .d_LPO_CAL_ENABLE_MASK = AR6320V2_LPO_CAL_ENABLE_MASK, |
| 457 | .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = |
| 458 | AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, |
| 459 | .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = |
| 460 | AR6320V2_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, |
| 461 | .d_ANALOG_INTF_BASE_ADDRESS = AR6320V2_ANALOG_INTF_BASE_ADDRESS, |
| 462 | .d_WLAN_MAC_BASE_ADDRESS = AR6320V2_WLAN_MAC_BASE_ADDRESS, |
| 463 | .d_FW_INDICATOR_ADDRESS = AR6320V2_FW_INDICATOR_ADDRESS, |
| 464 | .d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS, |
| 465 | .d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS, |
| 466 | .d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS, |
| Mohit Khanna | 440c529 | 2016-05-12 11:05:06 -0700 | [diff] [blame] | 467 | #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 468 | .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, |
| 469 | .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, |
| Mohit Khanna | 440c529 | 2016-05-12 11:05:06 -0700 | [diff] [blame] | 470 | #endif |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 471 | .d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK, |
| 472 | .d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS, |
| 473 | .d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS, |
| 474 | /* htt_rx.c */ |
| 475 | .d_RX_MSDU_END_4_FIRST_MSDU_MASK = |
| 476 | AR6320V2_RX_MSDU_END_4_FIRST_MSDU_MASK, |
| 477 | .d_RX_MSDU_END_4_FIRST_MSDU_LSB = |
| 478 | AR6320V2_RX_MSDU_END_4_FIRST_MSDU_LSB, |
| 479 | .d_RX_MPDU_START_0_RETRY_MASK = |
| 480 | AR6320V2_RX_MPDU_START_0_RETRY_MASK, |
| 481 | .d_RX_MPDU_START_0_SEQ_NUM_MASK = |
| 482 | AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, |
| 483 | .d_RX_MPDU_START_0_SEQ_NUM_MASK = |
| 484 | AR6320V2_RX_MPDU_START_0_SEQ_NUM_MASK, |
| 485 | .d_RX_MPDU_START_0_SEQ_NUM_LSB = AR6320V2_RX_MPDU_START_0_SEQ_NUM_LSB, |
| 486 | .d_RX_MPDU_START_2_PN_47_32_LSB = |
| 487 | AR6320V2_RX_MPDU_START_2_PN_47_32_LSB, |
| 488 | .d_RX_MPDU_START_2_PN_47_32_MASK = |
| 489 | AR6320V2_RX_MPDU_START_2_PN_47_32_MASK, |
| 490 | .d_RX_MPDU_START_2_TID_LSB = |
| 491 | AR6320V2_RX_MPDU_START_2_TID_LSB, |
| 492 | .d_RX_MPDU_START_2_TID_MASK = |
| 493 | AR6320V2_RX_MPDU_START_2_TID_MASK, |
| 494 | .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = |
| 495 | AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, |
| 496 | .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = |
| 497 | AR6320V2_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, |
| 498 | .d_RX_MSDU_END_4_LAST_MSDU_MASK = |
| 499 | AR6320V2_RX_MSDU_END_4_LAST_MSDU_MASK, |
| 500 | .d_RX_MSDU_END_4_LAST_MSDU_LSB = AR6320V2_RX_MSDU_END_4_LAST_MSDU_LSB, |
| 501 | .d_RX_ATTENTION_0_MCAST_BCAST_MASK = |
| 502 | AR6320V2_RX_ATTENTION_0_MCAST_BCAST_MASK, |
| 503 | .d_RX_ATTENTION_0_MCAST_BCAST_LSB = |
| 504 | AR6320V2_RX_ATTENTION_0_MCAST_BCAST_LSB, |
| 505 | .d_RX_ATTENTION_0_FRAGMENT_MASK = |
| 506 | AR6320V2_RX_ATTENTION_0_FRAGMENT_MASK, |
| 507 | .d_RX_ATTENTION_0_FRAGMENT_LSB = AR6320V2_RX_ATTENTION_0_FRAGMENT_LSB, |
| 508 | .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = |
| 509 | AR6320V2_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, |
| 510 | .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = |
| 511 | AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, |
| 512 | .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = |
| 513 | AR6320V2_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, |
| 514 | .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = |
| 515 | AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_MASK, |
| 516 | .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = |
| 517 | AR6320V2_RX_MSDU_START_0_MSDU_LENGTH_LSB, |
| 518 | .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = |
| 519 | AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, |
| 520 | .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = |
| 521 | AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_MASK, |
| 522 | .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = |
| 523 | AR6320V2_RX_MSDU_START_2_DECAP_FORMAT_LSB, |
| 524 | .d_RX_MPDU_START_0_ENCRYPTED_MASK = |
| 525 | AR6320V2_RX_MPDU_START_0_ENCRYPTED_MASK, |
| 526 | .d_RX_MPDU_START_0_ENCRYPTED_LSB = |
| 527 | AR6320V2_RX_MPDU_START_0_ENCRYPTED_LSB, |
| 528 | .d_RX_ATTENTION_0_MORE_DATA_MASK = |
| 529 | AR6320V2_RX_ATTENTION_0_MORE_DATA_MASK, |
| 530 | .d_RX_ATTENTION_0_MSDU_DONE_MASK = |
| 531 | AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK, |
| 532 | .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = |
| 533 | AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 534 | #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) |
| 535 | .d_CE_COUNT = AR6320V2_CE_COUNT, |
| 536 | .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, |
| 537 | .d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS, |
| 538 | .d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS, |
| 539 | .d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK, |
| 540 | .d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 541 | /* PLL start */ |
| 542 | .d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET, |
| 543 | .d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB, |
| 544 | .d_EFUSE_XTAL_SEL_LSB = AR6320V2_EFUSE_XTAL_SEL_LSB, |
| 545 | .d_EFUSE_XTAL_SEL_MASK = AR6320V2_EFUSE_XTAL_SEL_MASK, |
| 546 | .d_BB_PLL_CONFIG_OFFSET = AR6320V2_BB_PLL_CONFIG_OFFSET, |
| 547 | .d_BB_PLL_CONFIG_OUTDIV_MSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_MSB, |
| 548 | .d_BB_PLL_CONFIG_OUTDIV_LSB = AR6320V2_BB_PLL_CONFIG_OUTDIV_LSB, |
| 549 | .d_BB_PLL_CONFIG_OUTDIV_MASK = AR6320V2_BB_PLL_CONFIG_OUTDIV_MASK, |
| 550 | .d_BB_PLL_CONFIG_FRAC_MSB = AR6320V2_BB_PLL_CONFIG_FRAC_MSB, |
| 551 | .d_BB_PLL_CONFIG_FRAC_LSB = AR6320V2_BB_PLL_CONFIG_FRAC_LSB, |
| 552 | .d_BB_PLL_CONFIG_FRAC_MASK = AR6320V2_BB_PLL_CONFIG_FRAC_MASK, |
| 553 | .d_WLAN_PLL_SETTLE_TIME_MSB = AR6320V2_WLAN_PLL_SETTLE_TIME_MSB, |
| 554 | .d_WLAN_PLL_SETTLE_TIME_LSB = AR6320V2_WLAN_PLL_SETTLE_TIME_LSB, |
| 555 | .d_WLAN_PLL_SETTLE_TIME_MASK = AR6320V2_WLAN_PLL_SETTLE_TIME_MASK, |
| 556 | .d_WLAN_PLL_SETTLE_OFFSET = AR6320V2_WLAN_PLL_SETTLE_OFFSET, |
| 557 | .d_WLAN_PLL_SETTLE_SW_MASK = AR6320V2_WLAN_PLL_SETTLE_SW_MASK, |
| 558 | .d_WLAN_PLL_SETTLE_RSTMASK = AR6320V2_WLAN_PLL_SETTLE_RSTMASK, |
| 559 | .d_WLAN_PLL_SETTLE_RESET = AR6320V2_WLAN_PLL_SETTLE_RESET, |
| 560 | .d_WLAN_PLL_CONTROL_NOPWD_MSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MSB, |
| 561 | .d_WLAN_PLL_CONTROL_NOPWD_LSB = AR6320V2_WLAN_PLL_CONTROL_NOPWD_LSB, |
| 562 | .d_WLAN_PLL_CONTROL_NOPWD_MASK = AR6320V2_WLAN_PLL_CONTROL_NOPWD_MASK, |
| 563 | .d_WLAN_PLL_CONTROL_BYPASS_MSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_MSB, |
| 564 | .d_WLAN_PLL_CONTROL_BYPASS_LSB = AR6320V2_WLAN_PLL_CONTROL_BYPASS_LSB, |
| 565 | .d_WLAN_PLL_CONTROL_BYPASS_MASK = |
| 566 | AR6320V2_WLAN_PLL_CONTROL_BYPASS_MASK, |
| 567 | .d_WLAN_PLL_CONTROL_BYPASS_RESET = |
| 568 | AR6320V2_WLAN_PLL_CONTROL_BYPASS_RESET, |
| 569 | .d_WLAN_PLL_CONTROL_CLK_SEL_MSB = |
| 570 | AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MSB, |
| 571 | .d_WLAN_PLL_CONTROL_CLK_SEL_LSB = |
| 572 | AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_LSB, |
| 573 | .d_WLAN_PLL_CONTROL_CLK_SEL_MASK = |
| 574 | AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_MASK, |
| 575 | .d_WLAN_PLL_CONTROL_CLK_SEL_RESET = |
| 576 | AR6320V2_WLAN_PLL_CONTROL_CLK_SEL_RESET, |
| 577 | .d_WLAN_PLL_CONTROL_REFDIV_MSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_MSB, |
| 578 | .d_WLAN_PLL_CONTROL_REFDIV_LSB = AR6320V2_WLAN_PLL_CONTROL_REFDIV_LSB, |
| 579 | .d_WLAN_PLL_CONTROL_REFDIV_MASK = |
| 580 | AR6320V2_WLAN_PLL_CONTROL_REFDIV_MASK, |
| 581 | .d_WLAN_PLL_CONTROL_REFDIV_RESET = |
| 582 | AR6320V2_WLAN_PLL_CONTROL_REFDIV_RESET, |
| 583 | .d_WLAN_PLL_CONTROL_DIV_MSB = AR6320V2_WLAN_PLL_CONTROL_DIV_MSB, |
| 584 | .d_WLAN_PLL_CONTROL_DIV_LSB = AR6320V2_WLAN_PLL_CONTROL_DIV_LSB, |
| 585 | .d_WLAN_PLL_CONTROL_DIV_MASK = AR6320V2_WLAN_PLL_CONTROL_DIV_MASK, |
| 586 | .d_WLAN_PLL_CONTROL_DIV_RESET = AR6320V2_WLAN_PLL_CONTROL_DIV_RESET, |
| 587 | .d_WLAN_PLL_CONTROL_OFFSET = AR6320V2_WLAN_PLL_CONTROL_OFFSET, |
| 588 | .d_WLAN_PLL_CONTROL_SW_MASK = AR6320V2_WLAN_PLL_CONTROL_SW_MASK, |
| 589 | .d_WLAN_PLL_CONTROL_RSTMASK = AR6320V2_WLAN_PLL_CONTROL_RSTMASK, |
| 590 | .d_WLAN_PLL_CONTROL_RESET = AR6320V2_WLAN_PLL_CONTROL_RESET, |
| 591 | .d_SOC_CORE_CLK_CTRL_OFFSET = AR6320V2_SOC_CORE_CLK_CTRL_OFFSET, |
| 592 | .d_SOC_CORE_CLK_CTRL_DIV_MSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MSB, |
| 593 | .d_SOC_CORE_CLK_CTRL_DIV_LSB = AR6320V2_SOC_CORE_CLK_CTRL_DIV_LSB, |
| 594 | .d_SOC_CORE_CLK_CTRL_DIV_MASK = AR6320V2_SOC_CORE_CLK_CTRL_DIV_MASK, |
| 595 | .d_RTC_SYNC_STATUS_PLL_CHANGING_MSB = |
| 596 | AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MSB, |
| 597 | .d_RTC_SYNC_STATUS_PLL_CHANGING_LSB = |
| 598 | AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_LSB, |
| 599 | .d_RTC_SYNC_STATUS_PLL_CHANGING_MASK = |
| 600 | AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_MASK, |
| 601 | .d_RTC_SYNC_STATUS_PLL_CHANGING_RESET = |
| 602 | AR6320V2_RTC_SYNC_STATUS_PLL_CHANGING_RESET, |
| 603 | .d_RTC_SYNC_STATUS_OFFSET = AR6320V2_RTC_SYNC_STATUS_OFFSET, |
| 604 | .d_SOC_CPU_CLOCK_OFFSET = AR6320V2_SOC_CPU_CLOCK_OFFSET, |
| 605 | .d_SOC_CPU_CLOCK_STANDARD_MSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_MSB, |
| 606 | .d_SOC_CPU_CLOCK_STANDARD_LSB = AR6320V2_SOC_CPU_CLOCK_STANDARD_LSB, |
| 607 | .d_SOC_CPU_CLOCK_STANDARD_MASK = AR6320V2_SOC_CPU_CLOCK_STANDARD_MASK, |
| 608 | /* PLL end */ |
| 609 | .d_SOC_POWER_REG_OFFSET = AR6320V2_SOC_POWER_REG_OFFSET, |
| 610 | .d_PCIE_INTR_CAUSE_ADDRESS = AR6320V2_PCIE_INTR_CAUSE_ADDRESS, |
| 611 | .d_SOC_RESET_CONTROL_ADDRESS = AR6320V2_SOC_RESET_CONTROL_ADDRESS, |
| 612 | .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = |
| 613 | AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, |
| 614 | .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = |
| 615 | AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, |
| 616 | .d_SOC_RESET_CONTROL_CE_RST_MASK = |
| 617 | AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 618 | .d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET, |
| 619 | .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = |
| 620 | AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB, |
| 621 | .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = |
| 622 | AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB, |
| 623 | .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK = |
| 624 | AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK, |
| 625 | .d_WLAN_DEBUG_CONTROL_OFFSET = AR6320V2_WLAN_DEBUG_CONTROL_OFFSET, |
| 626 | .d_WLAN_DEBUG_CONTROL_ENABLE_MSB = |
| 627 | AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB, |
| 628 | .d_WLAN_DEBUG_CONTROL_ENABLE_LSB = |
| 629 | AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB, |
| 630 | .d_WLAN_DEBUG_CONTROL_ENABLE_MASK = |
| 631 | AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK, |
| 632 | .d_WLAN_DEBUG_OUT_OFFSET = AR6320V2_WLAN_DEBUG_OUT_OFFSET, |
| 633 | .d_WLAN_DEBUG_OUT_DATA_MSB = AR6320V2_WLAN_DEBUG_OUT_DATA_MSB, |
| 634 | .d_WLAN_DEBUG_OUT_DATA_LSB = AR6320V2_WLAN_DEBUG_OUT_DATA_LSB, |
| 635 | .d_WLAN_DEBUG_OUT_DATA_MASK = AR6320V2_WLAN_DEBUG_OUT_DATA_MASK, |
| 636 | .d_AMBA_DEBUG_BUS_OFFSET = AR6320V2_AMBA_DEBUG_BUS_OFFSET, |
| 637 | .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB = |
| 638 | AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB, |
| 639 | .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB = |
| 640 | AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB, |
| 641 | .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK = |
| 642 | AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK, |
| 643 | .d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB, |
| 644 | .d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB, |
| 645 | .d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK, |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 646 | #endif |
| 647 | .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = |
| 648 | AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, |
| 649 | .d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS, |
| 650 | .d_SOC_LF_TIMER_CONTROL0_ADDRESS = |
| 651 | AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS, |
| 652 | .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = |
| 653 | AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, |
| 654 | /* chip id start */ |
| 655 | .d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS, |
| 656 | .d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK, |
| 657 | .d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB, |
| 658 | .d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK, |
| 659 | .d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB, |
| 660 | /* chip id end */ |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 661 | }; |
| 662 | |
| 663 | struct hostdef_s ar6320v2_hostdef = { |
| 664 | .d_INT_STATUS_ENABLE_ERROR_LSB = AR6320V2_INT_STATUS_ENABLE_ERROR_LSB, |
| 665 | .d_INT_STATUS_ENABLE_ERROR_MASK = |
| 666 | AR6320V2_INT_STATUS_ENABLE_ERROR_MASK, |
| 667 | .d_INT_STATUS_ENABLE_CPU_LSB = AR6320V2_INT_STATUS_ENABLE_CPU_LSB, |
| 668 | .d_INT_STATUS_ENABLE_CPU_MASK = AR6320V2_INT_STATUS_ENABLE_CPU_MASK, |
| 669 | .d_INT_STATUS_ENABLE_COUNTER_LSB = |
| 670 | AR6320V2_INT_STATUS_ENABLE_COUNTER_LSB, |
| 671 | .d_INT_STATUS_ENABLE_COUNTER_MASK = |
| 672 | AR6320V2_INT_STATUS_ENABLE_COUNTER_MASK, |
| 673 | .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = |
| 674 | AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_LSB, |
| 675 | .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = |
| 676 | AR6320V2_INT_STATUS_ENABLE_MBOX_DATA_MASK, |
| 677 | .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = |
| 678 | AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, |
| 679 | .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = |
| 680 | AR6320V2_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, |
| 681 | .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = |
| 682 | AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, |
| 683 | .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = |
| 684 | AR6320V2_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, |
| 685 | .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = |
| 686 | AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_LSB, |
| 687 | .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = |
| 688 | AR6320V2_COUNTER_INT_STATUS_ENABLE_BIT_MASK, |
| 689 | .d_INT_STATUS_ENABLE_ADDRESS = AR6320V2_INT_STATUS_ENABLE_ADDRESS, |
| 690 | .d_CPU_INT_STATUS_ENABLE_BIT_LSB = |
| 691 | AR6320V2_CPU_INT_STATUS_ENABLE_BIT_LSB, |
| 692 | .d_CPU_INT_STATUS_ENABLE_BIT_MASK = |
| 693 | AR6320V2_CPU_INT_STATUS_ENABLE_BIT_MASK, |
| 694 | .d_HOST_INT_STATUS_ADDRESS = AR6320V2_HOST_INT_STATUS_ADDRESS, |
| 695 | .d_CPU_INT_STATUS_ADDRESS = AR6320V2_CPU_INT_STATUS_ADDRESS, |
| 696 | .d_ERROR_INT_STATUS_ADDRESS = AR6320V2_ERROR_INT_STATUS_ADDRESS, |
| 697 | .d_ERROR_INT_STATUS_WAKEUP_MASK = |
| 698 | AR6320V2_ERROR_INT_STATUS_WAKEUP_MASK, |
| 699 | .d_ERROR_INT_STATUS_WAKEUP_LSB = AR6320V2_ERROR_INT_STATUS_WAKEUP_LSB, |
| 700 | .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = |
| 701 | AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, |
| 702 | .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = |
| 703 | AR6320V2_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, |
| 704 | .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = |
| 705 | AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_MASK, |
| 706 | .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = |
| 707 | AR6320V2_ERROR_INT_STATUS_TX_OVERFLOW_LSB, |
| 708 | .d_COUNT_DEC_ADDRESS = AR6320V2_COUNT_DEC_ADDRESS, |
| 709 | .d_HOST_INT_STATUS_CPU_MASK = AR6320V2_HOST_INT_STATUS_CPU_MASK, |
| 710 | .d_HOST_INT_STATUS_CPU_LSB = AR6320V2_HOST_INT_STATUS_CPU_LSB, |
| 711 | .d_HOST_INT_STATUS_ERROR_MASK = AR6320V2_HOST_INT_STATUS_ERROR_MASK, |
| 712 | .d_HOST_INT_STATUS_ERROR_LSB = AR6320V2_HOST_INT_STATUS_ERROR_LSB, |
| 713 | .d_HOST_INT_STATUS_COUNTER_MASK = |
| 714 | AR6320V2_HOST_INT_STATUS_COUNTER_MASK, |
| 715 | .d_HOST_INT_STATUS_COUNTER_LSB = AR6320V2_HOST_INT_STATUS_COUNTER_LSB, |
| 716 | .d_RX_LOOKAHEAD_VALID_ADDRESS = AR6320V2_RX_LOOKAHEAD_VALID_ADDRESS, |
| 717 | .d_WINDOW_DATA_ADDRESS = AR6320V2_WINDOW_DATA_ADDRESS, |
| 718 | .d_WINDOW_READ_ADDR_ADDRESS = AR6320V2_WINDOW_READ_ADDR_ADDRESS, |
| 719 | .d_WINDOW_WRITE_ADDR_ADDRESS = AR6320V2_WINDOW_WRITE_ADDR_ADDRESS, |
| 720 | .d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS, |
| 721 | .d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS, |
| 722 | .d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 723 | .d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK, |
| 724 | .d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB, |
| 725 | .d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING, |
| 726 | .d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 727 | .d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 728 | #if defined(SDIO_3_0) |
| 729 | .d_HOST_INT_STATUS_MBOX_DATA_MASK = |
| 730 | AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK, |
| 731 | .d_HOST_INT_STATUS_MBOX_DATA_LSB = |
| 732 | AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB, |
| 733 | #endif |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 734 | #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) |
| 735 | .d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER, |
| 736 | .d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK, |
| 737 | .d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK, |
| 738 | .d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS, |
| 739 | .d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET, |
| 740 | .d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS, |
| 741 | .d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK, |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 742 | .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, |
| 743 | .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, |
| 744 | .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, |
| 745 | .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, |
| 746 | .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, |
| 747 | .d_HOST_CE_COUNT = 8, |
| 748 | .d_ENABLE_MSI = 0, |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 749 | #endif |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 750 | }; |
| 751 | |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 752 | #if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB) |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 753 | struct ce_reg_def ar6320v2_ce_targetdef = { |
| 754 | /* copy_engine.c */ |
| 755 | .d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS, |
| 756 | .d_SRC_WATERMARK_ADDRESS = AR6320V2_SRC_WATERMARK_ADDRESS, |
| 757 | .d_SRC_WATERMARK_LOW_MASK = AR6320V2_SRC_WATERMARK_LOW_MASK, |
| 758 | .d_SRC_WATERMARK_HIGH_MASK = AR6320V2_SRC_WATERMARK_HIGH_MASK, |
| 759 | .d_DST_WATERMARK_LOW_MASK = AR6320V2_DST_WATERMARK_LOW_MASK, |
| 760 | .d_DST_WATERMARK_HIGH_MASK = AR6320V2_DST_WATERMARK_HIGH_MASK, |
| 761 | .d_CURRENT_SRRI_ADDRESS = AR6320V2_CURRENT_SRRI_ADDRESS, |
| 762 | .d_CURRENT_DRRI_ADDRESS = AR6320V2_CURRENT_DRRI_ADDRESS, |
| 763 | .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = |
| 764 | AR6320V2_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, |
| 765 | .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = |
| 766 | AR6320V2_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, |
| 767 | .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = |
| 768 | AR6320V2_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, |
| 769 | .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = |
| 770 | AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK, |
| 771 | .d_HOST_IS_ADDRESS = AR6320V2_HOST_IS_ADDRESS, |
| 772 | .d_HOST_IS_COPY_COMPLETE_MASK = AR6320V2_HOST_IS_COPY_COMPLETE_MASK, |
| 773 | .d_CE_WRAPPER_BASE_ADDRESS = AR6320V2_CE_WRAPPER_BASE_ADDRESS, |
| 774 | .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = |
| 775 | AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS, |
| 776 | .d_HOST_IE_ADDRESS = AR6320V2_HOST_IE_ADDRESS, |
| 777 | .d_HOST_IE_COPY_COMPLETE_MASK = AR6320V2_HOST_IE_COPY_COMPLETE_MASK, |
| 778 | .d_SR_BA_ADDRESS = AR6320V2_SR_BA_ADDRESS, |
| 779 | .d_SR_SIZE_ADDRESS = AR6320V2_SR_SIZE_ADDRESS, |
| 780 | .d_CE_CTRL1_ADDRESS = AR6320V2_CE_CTRL1_ADDRESS, |
| 781 | .d_CE_CTRL1_DMAX_LENGTH_MASK = AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK, |
| 782 | .d_DR_BA_ADDRESS = AR6320V2_DR_BA_ADDRESS, |
| 783 | .d_DR_SIZE_ADDRESS = AR6320V2_DR_SIZE_ADDRESS, |
| 784 | .d_MISC_IE_ADDRESS = AR6320V2_MISC_IE_ADDRESS, |
| 785 | .d_MISC_IS_AXI_ERR_MASK = AR6320V2_MISC_IS_AXI_ERR_MASK, |
| 786 | .d_MISC_IS_DST_ADDR_ERR_MASK = AR6320V2_MISC_IS_DST_ADDR_ERR_MASK, |
| 787 | .d_MISC_IS_SRC_LEN_ERR_MASK = AR6320V2_MISC_IS_SRC_LEN_ERR_MASK, |
| 788 | .d_MISC_IS_DST_MAX_LEN_VIO_MASK = |
| 789 | AR6320V2_MISC_IS_DST_MAX_LEN_VIO_MASK, |
| 790 | .d_MISC_IS_DST_RING_OVERFLOW_MASK = |
| 791 | AR6320V2_MISC_IS_DST_RING_OVERFLOW_MASK, |
| 792 | .d_MISC_IS_SRC_RING_OVERFLOW_MASK = |
| 793 | AR6320V2_MISC_IS_SRC_RING_OVERFLOW_MASK, |
| 794 | .d_SRC_WATERMARK_LOW_LSB = AR6320V2_SRC_WATERMARK_LOW_LSB, |
| 795 | .d_SRC_WATERMARK_HIGH_LSB = AR6320V2_SRC_WATERMARK_HIGH_LSB, |
| 796 | .d_DST_WATERMARK_LOW_LSB = AR6320V2_DST_WATERMARK_LOW_LSB, |
| 797 | .d_DST_WATERMARK_HIGH_LSB = AR6320V2_DST_WATERMARK_HIGH_LSB, |
| 798 | .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = |
| 799 | AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, |
| 800 | .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = |
| 801 | AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, |
| 802 | .d_CE_CTRL1_DMAX_LENGTH_LSB = AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB, |
| 803 | .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = |
| 804 | AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, |
| 805 | .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = |
| 806 | AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, |
| 807 | .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = |
| 808 | AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, |
| 809 | .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = |
| 810 | AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, |
| 811 | .d_CE_WRAPPER_DEBUG_OFFSET = AR6320V2_CE_WRAPPER_DEBUG_OFFSET, |
| 812 | .d_CE_WRAPPER_DEBUG_SEL_MSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB, |
| 813 | .d_CE_WRAPPER_DEBUG_SEL_LSB = AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB, |
| 814 | .d_CE_WRAPPER_DEBUG_SEL_MASK = AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK, |
| 815 | .d_CE_DEBUG_OFFSET = AR6320V2_CE_DEBUG_OFFSET, |
| 816 | .d_CE_DEBUG_SEL_MSB = AR6320V2_CE_DEBUG_SEL_MSB, |
| 817 | .d_CE_DEBUG_SEL_LSB = AR6320V2_CE_DEBUG_SEL_LSB, |
| 818 | .d_CE_DEBUG_SEL_MASK = AR6320V2_CE_DEBUG_SEL_MASK, |
| 819 | .d_CE0_BASE_ADDRESS = AR6320V2_CE0_BASE_ADDRESS, |
| 820 | .d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS, |
| 821 | |
| 822 | }; |
| Govind Singh | 4cc8213 | 2016-05-12 20:02:01 +0530 | [diff] [blame] | 823 | #endif |
| Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 824 | #endif |