Houston Hoffman | c3c6bc1 | 2016-05-06 17:08:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010,2016 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | |
| 19 | #if defined(AR900B_HEADERS_DEF) |
| 20 | #define AR900B 1 |
| 21 | |
| 22 | #define WLAN_HEADERS 1 |
| 23 | #include "common_drv.h" |
| 24 | #include "AR900B/soc_addrs.h" |
| 25 | #include "AR900B/extra/hw/apb_map.h" |
| 26 | #include "AR900B/hw/gpio_athr_wlan_reg.h" |
| 27 | #ifdef WLAN_HEADERS |
| 28 | #include "AR900B/extra/hw/wifi_top_reg_map.h" |
| 29 | #include "AR900B/hw/rtc_soc_reg.h" |
| 30 | #endif |
| 31 | #include "AR900B/hw/si_reg.h" |
| 32 | #include "AR900B/extra/hw/pcie_local_reg.h" |
| 33 | #include "AR900B/hw/ce_wrapper_reg_csr.h" |
| 34 | #if 0 |
| 35 | #include "hw/soc_core_reg.h" |
| 36 | #include "hw/soc_pcie_reg.h" |
| 37 | #include "hw/ce_reg_csr.h" |
| 38 | #endif |
| 39 | |
| 40 | #include "AR900B/extra/hw/soc_core_reg.h" |
| 41 | #include "AR900B/hw/soc_pcie_reg.h" |
| 42 | #include "AR900B/extra/hw/ce_reg_csr.h" |
| 43 | #include <AR900B/hw/interface/rx_location_info.h> |
| 44 | #include <AR900B/hw/interface/rx_pkt_end.h> |
| 45 | #include <AR900B/hw/interface/rx_phy_ppdu_end.h> |
| 46 | #include <AR900B/hw/interface/rx_timing_offset.h> |
| 47 | #include <AR900B/hw/interface/rx_location_info.h> |
| 48 | #include <AR900B/hw/tlv/rx_ppdu_start.h> |
| 49 | #include <AR900B/hw/tlv/rx_ppdu_end.h> |
| 50 | #include <AR900B/hw/tlv/rx_mpdu_start.h> |
| 51 | #include <AR900B/hw/tlv/rx_mpdu_end.h> |
| 52 | #include <AR900B/hw/tlv/rx_msdu_start.h> |
| 53 | #include <AR900B/hw/tlv/rx_msdu_end.h> |
| 54 | #include <AR900B/hw/tlv/rx_attention.h> |
| 55 | #include <AR900B/hw/tlv/rx_frag_info.h> |
| 56 | #include <AR900B/hw/datastruct/msdu_link_ext.h> |
| 57 | #include <AR900B/hw/emu_phy_reg.h> |
| 58 | |
| 59 | /* Base address is defined in pcie_local_reg.h. Macros which access the |
| 60 | * registers include the base address in their definition. |
| 61 | */ |
| 62 | #define PCIE_LOCAL_BASE_ADDRESS 0 |
| 63 | |
| 64 | #define FW_EVENT_PENDING_ADDRESS (WIFICMN_SCRATCH_3_ADDRESS) |
| 65 | #define DRAM_BASE_ADDRESS TARG_DRAM_START |
| 66 | |
| 67 | /* Backwards compatibility -- TBDXXX */ |
| 68 | |
| 69 | #define MISSING 0 |
| 70 | |
| 71 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB WIFI_SYSTEM_SLEEP_DISABLE_LSB |
| 72 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK WIFI_SYSTEM_SLEEP_DISABLE_MASK |
| 73 | #define WLAN_RESET_CONTROL_COLD_RST_MASK WIFI_RESET_CONTROL_MAC_COLD_RST_MASK |
| 74 | #define WLAN_RESET_CONTROL_WARM_RST_MASK WIFI_RESET_CONTROL_MAC_WARM_RST_MASK |
| 75 | #define SOC_CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_ADDRESS |
| 76 | #define SOC_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_ADDRESS |
| 77 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_ADDRESS |
| 78 | #define SOC_LPO_CAL_OFFSET SOC_LPO_CAL_ADDRESS |
| 79 | #define SOC_RESET_CONTROL_CE_RST_MASK WIFI_RESET_CONTROL_CE_RESET_MASK |
| 80 | #define WLAN_SYSTEM_SLEEP_OFFSET WIFI_SYSTEM_SLEEP_ADDRESS |
| 81 | #define WLAN_RESET_CONTROL_OFFSET WIFI_RESET_CONTROL_ADDRESS |
| 82 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET |
| 83 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| 84 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK |
| 85 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS |
| 86 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS |
| 87 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS |
| 88 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK |
| 89 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK |
| 90 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS |
| 91 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS |
| 92 | #define LOCAL_SCRATCH_OFFSET 0x18 |
| 93 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS |
| 94 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS |
| 95 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS |
| 96 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS |
| 97 | #define SI_CONFIG_OFFSET SI_CONFIG_ADDRESS |
| 98 | #define SI_TX_DATA0_OFFSET SI_TX_DATA0_ADDRESS |
| 99 | #define SI_TX_DATA1_OFFSET SI_TX_DATA1_ADDRESS |
| 100 | #define SI_RX_DATA0_OFFSET SI_RX_DATA0_ADDRESS |
| 101 | #define SI_RX_DATA1_OFFSET SI_RX_DATA1_ADDRESS |
| 102 | #define SI_CS_OFFSET SI_CS_ADDRESS |
| 103 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB |
| 104 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK |
| 105 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB |
| 106 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK |
| 107 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS |
| 108 | #define MBOX_BASE_ADDRESS MISSING |
| 109 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING |
| 110 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING |
| 111 | #define INT_STATUS_ENABLE_CPU_LSB MISSING |
| 112 | #define INT_STATUS_ENABLE_CPU_MASK MISSING |
| 113 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| 114 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| 115 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| 116 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| 117 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| 118 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| 119 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| 120 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| 121 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 122 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 123 | #define INT_STATUS_ENABLE_ADDRESS MISSING |
| 124 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 125 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 126 | #define HOST_INT_STATUS_ADDRESS MISSING |
| 127 | #define CPU_INT_STATUS_ADDRESS MISSING |
| 128 | #define ERROR_INT_STATUS_ADDRESS MISSING |
| 129 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| 130 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| 131 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| 132 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| 133 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| 134 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| 135 | #define COUNT_DEC_ADDRESS MISSING |
| 136 | #define HOST_INT_STATUS_CPU_MASK MISSING |
| 137 | #define HOST_INT_STATUS_CPU_LSB MISSING |
| 138 | #define HOST_INT_STATUS_ERROR_MASK MISSING |
| 139 | #define HOST_INT_STATUS_ERROR_LSB MISSING |
| 140 | #define HOST_INT_STATUS_COUNTER_MASK MISSING |
| 141 | #define HOST_INT_STATUS_COUNTER_LSB MISSING |
| 142 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| 143 | #define WINDOW_DATA_ADDRESS MISSING |
| 144 | #define WINDOW_READ_ADDR_ADDRESS MISSING |
| 145 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING |
| 146 | /* MAC Descriptor */ |
| 147 | #define RX_PPDU_END_ANTENNA_OFFSET_DWORD (RX_PPDU_END_25_RX_ANTENNA_OFFSET >> 2) |
| 148 | /* GPIO Register */ |
| 149 | #define GPIO_ENABLE_W1TS_LOW_ADDRESS WLAN_GPIO_ENABLE_W1TS_LOW_ADDRESS |
| 150 | #define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB |
| 151 | #define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB |
| 152 | #define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK |
| 153 | /* CE descriptor */ |
| 154 | #define CE_SRC_DESC_SIZE_DWORD 2 |
| 155 | #define CE_DEST_DESC_SIZE_DWORD 2 |
| 156 | #define CE_SRC_DESC_SRC_PTR_OFFSET_DWORD 0 |
| 157 | #define CE_SRC_DESC_INFO_OFFSET_DWORD 1 |
| 158 | #define CE_DEST_DESC_DEST_PTR_OFFSET_DWORD 0 |
| 159 | #define CE_DEST_DESC_INFO_OFFSET_DWORD 1 |
| 160 | #if _BYTE_ORDER == _BIG_ENDIAN |
| 161 | #define CE_SRC_DESC_INFO_NBYTES_MASK 0xFFFF0000 |
| 162 | #define CE_SRC_DESC_INFO_NBYTES_SHIFT 16 |
| 163 | #define CE_SRC_DESC_INFO_GATHER_MASK 0x00008000 |
| 164 | #define CE_SRC_DESC_INFO_GATHER_SHIFT 15 |
| 165 | #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00004000 |
| 166 | #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 14 |
| 167 | #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 |
| 168 | #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 |
| 169 | #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 |
| 170 | #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 |
| 171 | #define CE_SRC_DESC_INFO_META_DATA_MASK 0x00000FFF |
| 172 | #define CE_SRC_DESC_INFO_META_DATA_SHIFT 0 |
| 173 | #else |
| 174 | #define CE_SRC_DESC_INFO_NBYTES_MASK 0x0000FFFF |
| 175 | #define CE_SRC_DESC_INFO_NBYTES_SHIFT 0 |
| 176 | #define CE_SRC_DESC_INFO_GATHER_MASK 0x00010000 |
| 177 | #define CE_SRC_DESC_INFO_GATHER_SHIFT 16 |
| 178 | #define CE_SRC_DESC_INFO_BYTE_SWAP_MASK 0x00020000 |
| 179 | #define CE_SRC_DESC_INFO_BYTE_SWAP_SHIFT 17 |
| 180 | #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 |
| 181 | #define CE_SRC_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 |
| 182 | #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 |
| 183 | #define CE_SRC_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 |
| 184 | #define CE_SRC_DESC_INFO_META_DATA_MASK 0xFFF00000 |
| 185 | #define CE_SRC_DESC_INFO_META_DATA_SHIFT 20 |
| 186 | #endif |
| 187 | #if _BYTE_ORDER == _BIG_ENDIAN |
| 188 | #define CE_DEST_DESC_INFO_NBYTES_MASK 0xFFFF0000 |
| 189 | #define CE_DEST_DESC_INFO_NBYTES_SHIFT 16 |
| 190 | #define CE_DEST_DESC_INFO_GATHER_MASK 0x00008000 |
| 191 | #define CE_DEST_DESC_INFO_GATHER_SHIFT 15 |
| 192 | #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00004000 |
| 193 | #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 14 |
| 194 | #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00002000 |
| 195 | #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 13 |
| 196 | #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00001000 |
| 197 | #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 12 |
| 198 | #define CE_DEST_DESC_INFO_META_DATA_MASK 0x00000FFF |
| 199 | #define CE_DEST_DESC_INFO_META_DATA_SHIFT 0 |
| 200 | #else |
| 201 | #define CE_DEST_DESC_INFO_NBYTES_MASK 0x0000FFFF |
| 202 | #define CE_DEST_DESC_INFO_NBYTES_SHIFT 0 |
| 203 | #define CE_DEST_DESC_INFO_GATHER_MASK 0x00010000 |
| 204 | #define CE_DEST_DESC_INFO_GATHER_SHIFT 16 |
| 205 | #define CE_DEST_DESC_INFO_BYTE_SWAP_MASK 0x00020000 |
| 206 | #define CE_DEST_DESC_INFO_BYTE_SWAP_SHIFT 17 |
| 207 | #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_MASK 0x00040000 |
| 208 | #define CE_DEST_DESC_INFO_HOST_INT_DISABLE_SHIFT 18 |
| 209 | #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_MASK 0x00080000 |
| 210 | #define CE_DEST_DESC_INFO_TARGET_INT_DISABLE_SHIFT 19 |
| 211 | #define CE_DEST_DESC_INFO_META_DATA_MASK 0xFFF00000 |
| 212 | #define CE_DEST_DESC_INFO_META_DATA_SHIFT 20 |
| 213 | #endif |
| 214 | |
| 215 | #define MY_TARGET_DEF AR900B_TARGETdef |
| 216 | #define MY_HOST_DEF AR900B_HOSTdef |
| 217 | #define MY_CEREG_DEF AR900B_CE_TARGETdef |
| 218 | #define MY_TARGET_BOARD_DATA_SZ AR900B_BOARD_DATA_SZ |
| 219 | #define MY_TARGET_BOARD_EXT_DATA_SZ AR900B_BOARD_EXT_DATA_SZ |
| 220 | #include "targetdef.h" |
| 221 | #include "hostdef.h" |
| 222 | #else |
| 223 | #include "common_drv.h" |
| 224 | #include "targetdef.h" |
| 225 | #include "hostdef.h" |
| 226 | struct targetdef_s *AR900B_TARGETdef; |
| 227 | struct hostdef_s *AR900B_HOSTdef; |
| 228 | #endif /*AR900B_HEADERS_DEF */ |