| Venkateswara Swamy Bandaru | 2aa2c69 | 2016-09-20 20:25:39 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | |
| 19 | #if defined(QCA8074_HEADERS_DEF) |
| 20 | |
| 21 | #undef UMAC |
| 22 | #define WLAN_HEADERS 1 |
| 23 | |
| Leo Chang | 5ea93a4 | 2016-11-03 12:39:49 -0700 | [diff] [blame] | 24 | #include <lithium_top_reg.h> |
| Venkateswara Swamy Bandaru | 2aa2c69 | 2016-09-20 20:25:39 +0530 | [diff] [blame] | 25 | |
| 26 | #define MISSING 0 |
| 27 | |
| 28 | #define SOC_RESET_CONTROL_OFFSET MISSING |
| 29 | #define GPIO_PIN0_OFFSET MISSING |
| 30 | #define GPIO_PIN1_OFFSET MISSING |
| 31 | #define GPIO_PIN0_CONFIG_MASK MISSING |
| 32 | #define GPIO_PIN1_CONFIG_MASK MISSING |
| 33 | #define LOCAL_SCRATCH_OFFSET 0x18 |
| 34 | #define GPIO_PIN10_OFFSET MISSING |
| 35 | #define GPIO_PIN11_OFFSET MISSING |
| 36 | #define GPIO_PIN12_OFFSET MISSING |
| 37 | #define GPIO_PIN13_OFFSET MISSING |
| 38 | #define MBOX_BASE_ADDRESS MISSING |
| 39 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING |
| 40 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING |
| 41 | #define INT_STATUS_ENABLE_CPU_LSB MISSING |
| 42 | #define INT_STATUS_ENABLE_CPU_MASK MISSING |
| 43 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| 44 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| 45 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| 46 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| 47 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| 48 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| 49 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| 50 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| 51 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 52 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 53 | #define INT_STATUS_ENABLE_ADDRESS MISSING |
| 54 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| 55 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| 56 | #define HOST_INT_STATUS_ADDRESS MISSING |
| 57 | #define CPU_INT_STATUS_ADDRESS MISSING |
| 58 | #define ERROR_INT_STATUS_ADDRESS MISSING |
| 59 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| 60 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| 61 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| 62 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| 63 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| 64 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| 65 | #define COUNT_DEC_ADDRESS MISSING |
| 66 | #define HOST_INT_STATUS_CPU_MASK MISSING |
| 67 | #define HOST_INT_STATUS_CPU_LSB MISSING |
| 68 | #define HOST_INT_STATUS_ERROR_MASK MISSING |
| 69 | #define HOST_INT_STATUS_ERROR_LSB MISSING |
| 70 | #define HOST_INT_STATUS_COUNTER_MASK MISSING |
| 71 | #define HOST_INT_STATUS_COUNTER_LSB MISSING |
| 72 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| 73 | #define WINDOW_DATA_ADDRESS MISSING |
| 74 | #define WINDOW_READ_ADDR_ADDRESS MISSING |
| 75 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING |
| 76 | /* GPIO Register */ |
| 77 | #define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING |
| 78 | #define GPIO_PIN0_CONFIG_LSB MISSING |
| 79 | #define GPIO_PIN0_PAD_PULL_LSB MISSING |
| 80 | #define GPIO_PIN0_PAD_PULL_MASK MISSING |
| 81 | /* SI reg */ |
| 82 | #define SI_CONFIG_ERR_INT_MASK MISSING |
| 83 | #define SI_CONFIG_ERR_INT_LSB MISSING |
| 84 | |
| 85 | #define RTC_SOC_BASE_ADDRESS MISSING |
| 86 | #define RTC_WMAC_BASE_ADDRESS MISSING |
| 87 | #define SOC_CORE_BASE_ADDRESS MISSING |
| 88 | #define WLAN_MAC_BASE_ADDRESS MISSING |
| 89 | #define GPIO_BASE_ADDRESS MISSING |
| 90 | #define ANALOG_INTF_BASE_ADDRESS MISSING |
| 91 | #define CE0_BASE_ADDRESS MISSING |
| 92 | #define CE1_BASE_ADDRESS MISSING |
| 93 | #define CE_COUNT 12 |
| 94 | #define CE_WRAPPER_BASE_ADDRESS MISSING |
| 95 | #define SI_BASE_ADDRESS MISSING |
| 96 | #define DRAM_BASE_ADDRESS MISSING |
| 97 | |
| 98 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING |
| 99 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING |
| 100 | #define CLOCK_CONTROL_OFFSET MISSING |
| 101 | #define CLOCK_CONTROL_SI0_CLK_MASK MISSING |
| 102 | #define RESET_CONTROL_SI0_RST_MASK MISSING |
| 103 | #define WLAN_RESET_CONTROL_OFFSET MISSING |
| 104 | #define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING |
| 105 | #define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING |
| 106 | #define CPU_CLOCK_OFFSET MISSING |
| 107 | |
| 108 | #define CPU_CLOCK_STANDARD_LSB MISSING |
| 109 | #define CPU_CLOCK_STANDARD_MASK MISSING |
| 110 | #define LPO_CAL_ENABLE_LSB MISSING |
| 111 | #define LPO_CAL_ENABLE_MASK MISSING |
| 112 | #define WLAN_SYSTEM_SLEEP_OFFSET MISSING |
| 113 | |
| 114 | #define SOC_CHIP_ID_ADDRESS MISSING |
| 115 | #define SOC_CHIP_ID_REVISION_MASK MISSING |
| 116 | #define SOC_CHIP_ID_REVISION_LSB MISSING |
| 117 | #define SOC_CHIP_ID_REVISION_MSB MISSING |
| 118 | |
| 119 | #define FW_IND_EVENT_PENDING MISSING |
| 120 | #define FW_IND_INITIALIZED MISSING |
| 121 | |
| 122 | #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING |
| 123 | #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING |
| 124 | #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING |
| 125 | #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING |
| 126 | #define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING |
| 127 | #define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING |
| 128 | #define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING |
| 129 | #define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING |
| 130 | |
| 131 | #define SR_WR_INDEX_ADDRESS MISSING |
| 132 | #define DST_WATERMARK_ADDRESS MISSING |
| 133 | |
| 134 | #define DST_WR_INDEX_ADDRESS MISSING |
| 135 | #define SRC_WATERMARK_ADDRESS MISSING |
| 136 | #define SRC_WATERMARK_LOW_MASK MISSING |
| 137 | #define SRC_WATERMARK_HIGH_MASK MISSING |
| 138 | #define DST_WATERMARK_LOW_MASK MISSING |
| 139 | #define DST_WATERMARK_HIGH_MASK MISSING |
| 140 | #define CURRENT_SRRI_ADDRESS MISSING |
| 141 | #define CURRENT_DRRI_ADDRESS MISSING |
| 142 | #define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING |
| 143 | #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING |
| 144 | #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING |
| 145 | #define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING |
| 146 | #define HOST_IS_ADDRESS MISSING |
| 147 | #define MISC_IS_ADDRESS MISSING |
| 148 | #define HOST_IS_COPY_COMPLETE_MASK MISSING |
| 149 | #define CE_WRAPPER_BASE_ADDRESS MISSING |
| 150 | #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING |
| 151 | #define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING |
| 152 | #define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING |
| 153 | #define HOST_IE_ADDRESS UMAC_CE_COMMON_CE_HOST_IE_0 |
| 154 | #define HOST_IE_ADDRESS_2 UMAC_CE_COMMON_CE_HOST_IE_1 |
| 155 | #define HOST_IE_COPY_COMPLETE_MASK MISSING |
| 156 | #define SR_BA_ADDRESS MISSING |
| 157 | #define SR_BA_ADDRESS_HIGH MISSING |
| 158 | #define SR_SIZE_ADDRESS MISSING |
| 159 | #define CE_CTRL1_ADDRESS MISSING |
| 160 | #define CE_CTRL1_DMAX_LENGTH_MASK MISSING |
| 161 | #define DR_BA_ADDRESS MISSING |
| 162 | #define DR_BA_ADDRESS_HIGH MISSING |
| 163 | #define DR_SIZE_ADDRESS MISSING |
| 164 | #define CE_CMD_REGISTER MISSING |
| 165 | #define CE_MSI_ADDRESS MISSING |
| 166 | #define CE_MSI_ADDRESS_HIGH MISSING |
| 167 | #define CE_MSI_DATA MISSING |
| 168 | #define CE_MSI_ENABLE_BIT MISSING |
| 169 | #define MISC_IE_ADDRESS MISSING |
| 170 | #define MISC_IS_AXI_ERR_MASK MISSING |
| 171 | #define MISC_IS_DST_ADDR_ERR_MASK MISSING |
| 172 | #define MISC_IS_SRC_LEN_ERR_MASK MISSING |
| 173 | #define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING |
| 174 | #define MISC_IS_DST_RING_OVERFLOW_MASK MISSING |
| 175 | #define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING |
| 176 | #define SRC_WATERMARK_LOW_LSB MISSING |
| 177 | #define SRC_WATERMARK_HIGH_LSB MISSING |
| 178 | #define DST_WATERMARK_LOW_LSB MISSING |
| 179 | #define DST_WATERMARK_HIGH_LSB MISSING |
| 180 | #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING |
| 181 | #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING |
| 182 | #define CE_CTRL1_DMAX_LENGTH_LSB MISSING |
| 183 | #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING |
| 184 | #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING |
| 185 | #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING |
| 186 | #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING |
| 187 | #define CE_CTRL1_IDX_UPD_EN_MASK MISSING |
| 188 | #define CE_WRAPPER_DEBUG_OFFSET MISSING |
| 189 | #define CE_WRAPPER_DEBUG_SEL_MSB MISSING |
| 190 | #define CE_WRAPPER_DEBUG_SEL_LSB MISSING |
| 191 | #define CE_WRAPPER_DEBUG_SEL_MASK MISSING |
| 192 | #define CE_DEBUG_OFFSET MISSING |
| 193 | #define CE_DEBUG_SEL_MSB MISSING |
| 194 | #define CE_DEBUG_SEL_LSB MISSING |
| 195 | #define CE_DEBUG_SEL_MASK MISSING |
| 196 | #define CE0_BASE_ADDRESS MISSING |
| 197 | #define CE1_BASE_ADDRESS MISSING |
| 198 | #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING |
| 199 | #define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING |
| 200 | |
| 201 | #define QCA8074_BOARD_DATA_SZ MISSING |
| 202 | #define QCA8074_BOARD_EXT_DATA_SZ MISSING |
| 203 | |
| 204 | #define MY_TARGET_DEF QCA8074_TARGETdef |
| 205 | #define MY_HOST_DEF QCA8074_HOSTdef |
| 206 | #define MY_CEREG_DEF QCA8074_CE_TARGETdef |
| 207 | #define MY_TARGET_BOARD_DATA_SZ QCA8074_BOARD_DATA_SZ |
| 208 | #define MY_TARGET_BOARD_EXT_DATA_SZ QCA8074_BOARD_EXT_DATA_SZ |
| 209 | #include "targetdef.h" |
| 210 | #include "hostdef.h" |
| 211 | #else |
| 212 | #include "common_drv.h" |
| 213 | #include "targetdef.h" |
| 214 | #include "hostdef.h" |
| 215 | struct targetdef_s *QCA8074_TARGETdef; |
| 216 | struct hostdef_s *QCA8074_HOSTdef; |
| 217 | #endif /*QCA8074_HEADERS_DEF */ |