Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 1 | /* |
Akshay Kosigi | 8eda31c | 2019-07-10 14:42:42 +0530 | [diff] [blame] | 2 | * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | #include "hal_hw_headers.h" |
| 19 | #include "hal_internal.h" |
| 20 | #include "cdp_txrx_mon_struct.h" |
| 21 | #include "qdf_trace.h" |
| 22 | #include "hal_rx.h" |
| 23 | #include "hal_tx.h" |
| 24 | #include "dp_types.h" |
| 25 | #include "hal_api_mon.h" |
| 26 | |
| 27 | /** |
| 28 | * hal_tx_desc_set_dscp_tid_table_id_8074v2() - Sets DSCP to TID conversion |
| 29 | * table ID |
| 30 | * @desc: Handle to Tx Descriptor |
| 31 | * @id: DSCP to tid conversion table to be used for this frame |
| 32 | * |
| 33 | * Return: void |
| 34 | */ |
| 35 | |
| 36 | static void hal_tx_desc_set_dscp_tid_table_id_8074v2(void *desc, uint8_t id) |
| 37 | { |
| 38 | HAL_SET_FLD(desc, TCL_DATA_CMD_5, |
| 39 | DSCP_TID_TABLE_NUM) |= |
| 40 | HAL_TX_SM(TCL_DATA_CMD_5, |
| 41 | DSCP_TID_TABLE_NUM, id); |
| 42 | } |
| 43 | |
| 44 | |
| 45 | #define DSCP_TID_TABLE_SIZE 24 |
| 46 | #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 47 | #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 48 | /** |
| 49 | * hal_tx_set_dscp_tid_map_8074v2() - Configure default DSCP to TID map table |
| 50 | * @soc: HAL SoC context |
| 51 | * @map: DSCP-TID mapping table |
| 52 | * @id: mapping table ID - 0,1 |
| 53 | * |
| 54 | * DSCP are mapped to 8 TID values using TID values programmed |
| 55 | * in two set of mapping registers DSCP_TID1_MAP_<0 to 6> (id = 0) |
| 56 | * and DSCP_TID2_MAP_<0 to 6> (id = 1) |
| 57 | * Each mapping register has TID mapping for 10 DSCP values |
| 58 | * |
| 59 | * Return: none |
| 60 | */ |
| 61 | |
Akshay Kosigi | 8eda31c | 2019-07-10 14:42:42 +0530 | [diff] [blame] | 62 | static void hal_tx_set_dscp_tid_map_8074v2(struct hal_soc *soc, |
| 63 | uint8_t *map, |
| 64 | uint8_t id) |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 65 | { |
| 66 | int i; |
| 67 | uint32_t addr, cmn_reg_addr; |
| 68 | uint32_t value = 0, regval; |
| 69 | uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; |
| 70 | |
Ruchi, Agrawal | fea1a84 | 2018-08-29 12:14:41 +0530 | [diff] [blame] | 71 | if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 72 | return; |
| 73 | |
| 74 | cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( |
| 75 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); |
| 76 | |
| 77 | addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( |
| 78 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, |
| 79 | id * NUM_WORDS_PER_DSCP_TID_TABLE); |
| 80 | |
| 81 | /* Enable read/write access */ |
| 82 | regval = HAL_REG_READ(soc, cmn_reg_addr); |
| 83 | regval |= |
| 84 | (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); |
| 85 | |
| 86 | HAL_REG_WRITE(soc, cmn_reg_addr, regval); |
| 87 | |
| 88 | /* Write 8 (24 bits) DSCP-TID mappings in each interation */ |
| 89 | for (i = 0; i < 64; i += 8) { |
| 90 | value = (map[i] | |
| 91 | (map[i + 1] << 0x3) | |
| 92 | (map[i + 2] << 0x6) | |
| 93 | (map[i + 3] << 0x9) | |
| 94 | (map[i + 4] << 0xc) | |
| 95 | (map[i + 5] << 0xf) | |
| 96 | (map[i + 6] << 0x12) | |
| 97 | (map[i + 7] << 0x15)); |
| 98 | |
Akshay Kosigi | 8eda31c | 2019-07-10 14:42:42 +0530 | [diff] [blame] | 99 | qdf_mem_copy(&val[cnt], &value, 3); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 100 | cnt += 3; |
| 101 | } |
| 102 | |
| 103 | for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { |
| 104 | regval = *(uint32_t *)(val + i); |
| 105 | HAL_REG_WRITE(soc, addr, |
| 106 | (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); |
| 107 | addr += 4; |
| 108 | } |
| 109 | |
| 110 | /* Diasble read/write access */ |
| 111 | regval = HAL_REG_READ(soc, cmn_reg_addr); |
| 112 | regval &= |
| 113 | ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); |
| 114 | |
| 115 | HAL_REG_WRITE(soc, cmn_reg_addr, regval); |
| 116 | } |
| 117 | |
| 118 | /** |
| 119 | * hal_tx_update_dscp_tid_8074v2() - Update the dscp tid map table as |
| 120 | updated by user |
| 121 | * @soc: HAL SoC context |
| 122 | * @map: DSCP-TID mapping table |
| 123 | * @id : MAP ID |
| 124 | * @dscp: DSCP_TID map index |
| 125 | * |
| 126 | * Return: void |
| 127 | */ |
Akshay Kosigi | 8eda31c | 2019-07-10 14:42:42 +0530 | [diff] [blame] | 128 | static void hal_tx_update_dscp_tid_8074v2(struct hal_soc *soc, uint8_t tid, |
| 129 | uint8_t id, uint8_t dscp) |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 130 | { |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 131 | uint32_t addr, addr1, cmn_reg_addr; |
| 132 | uint32_t start_value = 0, end_value = 0; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 133 | uint32_t regval; |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 134 | uint8_t end_bits = 0; |
| 135 | uint8_t start_bits = 0; |
| 136 | uint32_t start_index, end_index; |
| 137 | |
| 138 | cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( |
| 139 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 140 | |
| 141 | addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 142 | SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, |
| 143 | id * NUM_WORDS_PER_DSCP_TID_TABLE); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 144 | |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 145 | start_index = dscp * HAL_TX_BITS_PER_TID; |
| 146 | end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) |
| 147 | % HAL_TX_NUM_DSCP_REGISTER_SIZE; |
| 148 | start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; |
| 149 | addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / |
| 150 | HAL_TX_NUM_DSCP_REGISTER_SIZE)); |
| 151 | |
| 152 | if (end_index < start_index) { |
| 153 | end_bits = end_index + 1; |
| 154 | start_bits = HAL_TX_BITS_PER_TID - end_bits; |
| 155 | start_value = tid << start_index; |
| 156 | end_value = tid >> start_bits; |
| 157 | addr1 = addr + 4; |
| 158 | } else { |
| 159 | start_bits = HAL_TX_BITS_PER_TID - end_bits; |
| 160 | start_value = tid << start_index; |
| 161 | addr1 = 0; |
| 162 | } |
| 163 | |
| 164 | /* Enable read/write access */ |
| 165 | regval = HAL_REG_READ(soc, cmn_reg_addr); |
| 166 | regval |= |
| 167 | (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); |
| 168 | |
| 169 | HAL_REG_WRITE(soc, cmn_reg_addr, regval); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 170 | |
| 171 | regval = HAL_REG_READ(soc, addr); |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 172 | |
| 173 | if (end_index < start_index) |
| 174 | regval &= (~0) >> start_bits; |
| 175 | else |
| 176 | regval &= ~(7 << start_index); |
| 177 | |
| 178 | regval |= start_value; |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 179 | |
| 180 | HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 181 | |
| 182 | if (addr1) { |
| 183 | regval = HAL_REG_READ(soc, addr1); |
| 184 | regval &= (~0) << end_bits; |
| 185 | regval |= end_value; |
| 186 | |
| 187 | HAL_REG_WRITE(soc, addr1, (regval & |
| 188 | HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); |
| 189 | } |
| 190 | |
| 191 | /* Diasble read/write access */ |
| 192 | regval = HAL_REG_READ(soc, cmn_reg_addr); |
| 193 | regval &= |
| 194 | ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); |
| 195 | HAL_REG_WRITE(soc, cmn_reg_addr, regval); |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 196 | } |
Ruchi, Agrawal | 9d28e75 | 2018-09-22 01:32:41 +0530 | [diff] [blame] | 197 | |
Balamurugan Mahalingam | 5d80641 | 2018-07-30 18:04:15 +0530 | [diff] [blame] | 198 | /** |
| 199 | * hal_tx_desc_set_lmac_id - Set the lmac_id value |
| 200 | * @desc: Handle to Tx Descriptor |
| 201 | * @lmac_id: mac Id to ast matching |
| 202 | * b00 – mac 0 |
| 203 | * b01 – mac 1 |
| 204 | * b10 – mac 2 |
| 205 | * b11 – all macs (legacy HK way) |
| 206 | * |
| 207 | * Return: void |
| 208 | */ |
| 209 | static void hal_tx_desc_set_lmac_id_8074v2(void *desc, uint8_t lmac_id) |
| 210 | { |
| 211 | HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= |
| 212 | HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); |
| 213 | } |
| 214 | |