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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / 7090c5fd8d2bc46a463549bf26505e67a32d1d0e / . / core / hif / src / ce / ce_reg.h
blob: cb7439421dbb5b1ec4a09b042801a3dd21433bdf [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame^]1/*
2 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef __CE_REG_H__
29#define __CE_REG_H__
30
31#define DST_WR_INDEX_ADDRESS (scn->target_ce_def->d_DST_WR_INDEX_ADDRESS)
32#define SRC_WATERMARK_ADDRESS (scn->target_ce_def->d_SRC_WATERMARK_ADDRESS)
33#define SRC_WATERMARK_LOW_MASK (scn->target_ce_def->d_SRC_WATERMARK_LOW_MASK)
34#define SRC_WATERMARK_HIGH_MASK (scn->target_ce_def->d_SRC_WATERMARK_HIGH_MASK)
35#define DST_WATERMARK_LOW_MASK (scn->target_ce_def->d_DST_WATERMARK_LOW_MASK)
36#define DST_WATERMARK_HIGH_MASK (scn->target_ce_def->d_DST_WATERMARK_HIGH_MASK)
37#define CURRENT_SRRI_ADDRESS (scn->target_ce_def->d_CURRENT_SRRI_ADDRESS)
38#define CURRENT_DRRI_ADDRESS (scn->target_ce_def->d_CURRENT_DRRI_ADDRESS)
39
40#define SHADOW_VALUE0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_0)
41#define SHADOW_VALUE1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_1)
42#define SHADOW_VALUE2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_2)
43#define SHADOW_VALUE3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_3)
44#define SHADOW_VALUE4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_4)
45#define SHADOW_VALUE5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_5)
46#define SHADOW_VALUE6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_6)
47#define SHADOW_VALUE7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_7)
48#define SHADOW_VALUE8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_8)
49#define SHADOW_VALUE9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_9)
50#define SHADOW_VALUE10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_10)
51#define SHADOW_VALUE11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_11)
52#define SHADOW_VALUE12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_12)
53#define SHADOW_VALUE13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_13)
54#define SHADOW_VALUE14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_14)
55#define SHADOW_VALUE15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_15)
56#define SHADOW_VALUE16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_16)
57#define SHADOW_VALUE17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_17)
58#define SHADOW_VALUE18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_18)
59#define SHADOW_VALUE19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_19)
60#define SHADOW_VALUE20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_20)
61#define SHADOW_VALUE21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_21)
62#define SHADOW_VALUE22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_22)
63#define SHADOW_VALUE23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_VALUE_23)
64#define SHADOW_ADDRESS0 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_0)
65#define SHADOW_ADDRESS1 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_1)
66#define SHADOW_ADDRESS2 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_2)
67#define SHADOW_ADDRESS3 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_3)
68#define SHADOW_ADDRESS4 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_4)
69#define SHADOW_ADDRESS5 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_5)
70#define SHADOW_ADDRESS6 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_6)
71#define SHADOW_ADDRESS7 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_7)
72#define SHADOW_ADDRESS8 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_8)
73#define SHADOW_ADDRESS9 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_9)
74#define SHADOW_ADDRESS10 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_10)
75#define SHADOW_ADDRESS11 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_11)
76#define SHADOW_ADDRESS12 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_12)
77#define SHADOW_ADDRESS13 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_13)
78#define SHADOW_ADDRESS14 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_14)
79#define SHADOW_ADDRESS15 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_15)
80#define SHADOW_ADDRESS16 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_16)
81#define SHADOW_ADDRESS17 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_17)
82#define SHADOW_ADDRESS18 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_18)
83#define SHADOW_ADDRESS19 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_19)
84#define SHADOW_ADDRESS20 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_20)
85#define SHADOW_ADDRESS21 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_21)
86#define SHADOW_ADDRESS22 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_22)
87#define SHADOW_ADDRESS23 (scn->host_shadow_regs->d_A_LOCAL_SHADOW_REG_ADDRESS_23)
88
89#define SHADOW_ADDRESS(i) (SHADOW_ADDRESS0 + i*(SHADOW_ADDRESS1-SHADOW_ADDRESS0))
90
91#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
92 (scn->target_ce_def->d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK)
93#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
94 (scn->target_ce_def->d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK)
95#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
96 (scn->target_ce_def->d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
97#define HOST_IS_DST_RING_LOW_WATERMARK_MASK \
98 (scn->target_ce_def->d_HOST_IS_DST_RING_LOW_WATERMARK_MASK)
99#define MISC_IS_ADDRESS (scn->target_ce_def->d_MISC_IS_ADDRESS)
100#define HOST_IS_COPY_COMPLETE_MASK \
101 (scn->target_ce_def->d_HOST_IS_COPY_COMPLETE_MASK)
102#define CE_WRAPPER_BASE_ADDRESS (scn->target_ce_def->d_CE_WRAPPER_BASE_ADDRESS)
103#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS \
104 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS)
105#define CE_WRAPPER_INDEX_BASE_LOW \
106 (scn->target_ce_def->d_CE_WRAPPER_INDEX_BASE_LOW)
107#define CE_WRAPPER_INDEX_BASE_HIGH \
108 (scn->target_ce_def->d_CE_WRAPPER_INDEX_BASE_HIGH)
109#define HOST_IE_COPY_COMPLETE_MASK \
110 (scn->target_ce_def->d_HOST_IE_COPY_COMPLETE_MASK)
111#define SR_BA_ADDRESS (scn->target_ce_def->d_SR_BA_ADDRESS)
112#define SR_BA_ADDRESS_HIGH (scn->target_ce_def->d_SR_BA_ADDRESS_HIGH)
113#define SR_SIZE_ADDRESS (scn->target_ce_def->d_SR_SIZE_ADDRESS)
114#define CE_CTRL1_ADDRESS (scn->target_ce_def->d_CE_CTRL1_ADDRESS)
115#define CE_CTRL1_DMAX_LENGTH_MASK \
116 (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_MASK)
117#define DR_BA_ADDRESS (scn->target_ce_def->d_DR_BA_ADDRESS)
118#define DR_BA_ADDRESS_HIGH (scn->target_ce_def->d_DR_BA_ADDRESS_HIGH)
119#define DR_SIZE_ADDRESS (scn->target_ce_def->d_DR_SIZE_ADDRESS)
120#define CE_CMD_REGISTER (scn->target_ce_def->d_CE_CMD_REGISTER)
121#define CE_MSI_ADDRESS (scn->target_ce_def->d_CE_MSI_ADDRESS)
122#define CE_MSI_ADDRESS_HIGH (scn->target_ce_def->d_CE_MSI_ADDRESS_HIGH)
123#define CE_MSI_DATA (scn->target_ce_def->d_CE_MSI_DATA)
124#define CE_MSI_ENABLE_BIT (scn->target_ce_def->d_CE_MSI_ENABLE_BIT)
125#define MISC_IE_ADDRESS (scn->target_ce_def->d_MISC_IE_ADDRESS)
126#define MISC_IS_AXI_ERR_MASK (scn->target_ce_def->d_MISC_IS_AXI_ERR_MASK)
127#define MISC_IS_DST_ADDR_ERR_MASK \
128 (scn->target_ce_def->d_MISC_IS_DST_ADDR_ERR_MASK)
129#define MISC_IS_SRC_LEN_ERR_MASK \
130 (scn->target_ce_def->d_MISC_IS_SRC_LEN_ERR_MASK)
131#define MISC_IS_DST_MAX_LEN_VIO_MASK \
132 (scn->target_ce_def->d_MISC_IS_DST_MAX_LEN_VIO_MASK)
133#define MISC_IS_DST_RING_OVERFLOW_MASK \
134 (scn->target_ce_def->d_MISC_IS_DST_RING_OVERFLOW_MASK)
135#define MISC_IS_SRC_RING_OVERFLOW_MASK \
136 (scn->target_ce_def->d_MISC_IS_SRC_RING_OVERFLOW_MASK)
137#define SRC_WATERMARK_LOW_LSB (scn->target_ce_def->d_SRC_WATERMARK_LOW_LSB)
138#define SRC_WATERMARK_HIGH_LSB (scn->target_ce_def->d_SRC_WATERMARK_HIGH_LSB)
139#define DST_WATERMARK_LOW_LSB (scn->target_ce_def->d_DST_WATERMARK_LOW_LSB)
140#define DST_WATERMARK_HIGH_LSB (scn->target_ce_def->d_DST_WATERMARK_HIGH_LSB)
141#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
142 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK)
143#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
144 (scn->target_ce_def->d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
145#define CE_CTRL1_DMAX_LENGTH_LSB (scn->target_ce_def->d_CE_CTRL1_DMAX_LENGTH_LSB)
146#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
147 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
148#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
149 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
150#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
151 (scn->target_ce_def->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
152#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
153 (scn->target_ce_def->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
154#define WLAN_DEBUG_INPUT_SEL_OFFSET \
155 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
156#define WLAN_DEBUG_INPUT_SEL_SRC_MSB \
157 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
158#define WLAN_DEBUG_INPUT_SEL_SRC_LSB \
159 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
160#define WLAN_DEBUG_INPUT_SEL_SRC_MASK \
161 (scn->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
162#define WLAN_DEBUG_CONTROL_OFFSET (scn->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
163#define WLAN_DEBUG_CONTROL_ENABLE_MSB \
164 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
165#define WLAN_DEBUG_CONTROL_ENABLE_LSB \
166 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
167#define WLAN_DEBUG_CONTROL_ENABLE_MASK \
168 (scn->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
169#define WLAN_DEBUG_OUT_OFFSET (scn->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
170#define WLAN_DEBUG_OUT_DATA_MSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
171#define WLAN_DEBUG_OUT_DATA_LSB (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
172#define WLAN_DEBUG_OUT_DATA_MASK (scn->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
173#define AMBA_DEBUG_BUS_OFFSET (scn->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
174#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB \
175 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
176#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB \
177 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
178#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK \
179 (scn->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
180#define AMBA_DEBUG_BUS_SEL_MSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
181#define AMBA_DEBUG_BUS_SEL_LSB (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
182#define AMBA_DEBUG_BUS_SEL_MASK (scn->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
183#define CE_WRAPPER_DEBUG_OFFSET (scn->target_ce_def->d_CE_WRAPPER_DEBUG_OFFSET)
184#define CE_WRAPPER_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MSB)
185#define CE_WRAPPER_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_LSB)
186#define CE_WRAPPER_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_WRAPPER_DEBUG_SEL_MASK)
187#define CE_DEBUG_OFFSET (scn->target_ce_def->d_CE_DEBUG_OFFSET)
188#define CE_DEBUG_SEL_MSB (scn->target_ce_def->d_CE_DEBUG_SEL_MSB)
189#define CE_DEBUG_SEL_LSB (scn->target_ce_def->d_CE_DEBUG_SEL_LSB)
190#define CE_DEBUG_SEL_MASK (scn->target_ce_def->d_CE_DEBUG_SEL_MASK)
191#define HOST_IE_ADDRESS (scn->target_ce_def->d_HOST_IE_ADDRESS)
192#define HOST_IS_ADDRESS (scn->target_ce_def->d_HOST_IS_ADDRESS)
193
194#define SRC_WATERMARK_LOW_SET(x) \
195 (((x) << SRC_WATERMARK_LOW_LSB) & SRC_WATERMARK_LOW_MASK)
196#define SRC_WATERMARK_HIGH_SET(x) \
197 (((x) << SRC_WATERMARK_HIGH_LSB) & SRC_WATERMARK_HIGH_MASK)
198#define DST_WATERMARK_LOW_SET(x) \
199 (((x) << DST_WATERMARK_LOW_LSB) & DST_WATERMARK_LOW_MASK)
200#define DST_WATERMARK_HIGH_SET(x) \
201 (((x) << DST_WATERMARK_HIGH_LSB) & DST_WATERMARK_HIGH_MASK)
202#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
203 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
204 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
205#define CE_CTRL1_DMAX_LENGTH_SET(x) \
206 (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
207#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x) \
208 (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & \
209 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
210#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x) \
211 (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & \
212 CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
213#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) \
214 (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> \
215 WLAN_DEBUG_INPUT_SEL_SRC_LSB)
216#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) \
217 (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & \
218 WLAN_DEBUG_INPUT_SEL_SRC_MASK)
219#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) \
220 (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> \
221 WLAN_DEBUG_CONTROL_ENABLE_LSB)
222#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) \
223 (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & \
224 WLAN_DEBUG_CONTROL_ENABLE_MASK)
225#define WLAN_DEBUG_OUT_DATA_GET(x) \
226 (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
227#define WLAN_DEBUG_OUT_DATA_SET(x) \
228 (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
229#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x) \
230 (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> \
231 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
232#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x) \
233 (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & \
234 AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
235#define AMBA_DEBUG_BUS_SEL_GET(x) \
236 (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
237#define AMBA_DEBUG_BUS_SEL_SET(x) \
238 (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
239#define CE_WRAPPER_DEBUG_SEL_GET(x) \
240 (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
241#define CE_WRAPPER_DEBUG_SEL_SET(x) \
242 (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
243#define CE_DEBUG_SEL_GET(x) (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
244#define CE_DEBUG_SEL_SET(x) (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
245
246#define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
247 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
248
249#define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
250 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS, (addr))
251
252#define CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
253 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH, (addr))
254
255#define CE_SRC_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
256 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_BA_ADDRESS_HIGH)
257
258#define CE_SRC_RING_SZ_SET(scn, CE_ctrl_addr, n) \
259 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_SIZE_ADDRESS, (n))
260
261#define CE_SRC_RING_DMAX_SET(scn, CE_ctrl_addr, n) \
262 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
263 (A_TARGET_READ(scn, (CE_ctrl_addr) + \
264 CE_CTRL1_ADDRESS) & ~CE_CTRL1_DMAX_LENGTH_MASK) | \
265 CE_CTRL1_DMAX_LENGTH_SET(n))
266
267#define CE_CMD_REGISTER_GET(scn, CE_ctrl_addr) \
268 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CMD_REGISTER)
269
270#define CE_CMD_REGISTER_SET(scn, CE_ctrl_addr, n) \
271 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CMD_REGISTER, n)
272
273#define CE_MSI_ADDR_LOW_SET(scn, CE_ctrl_addr, addr) \
274 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS, (addr))
275
276#define CE_MSI_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
277 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_ADDRESS_HIGH, (addr))
278
279#define CE_MSI_DATA_SET(scn, CE_ctrl_addr, data) \
280 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_MSI_DATA, (data))
281
282#define CE_CTRL_REGISTER1_SET(scn, CE_ctrl_addr, val) \
283 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, val)
284
285#define CE_CTRL_REGISTER1_GET(scn, CE_ctrl_addr) \
286 A_TARGET_READ(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS)
287
288#define CE_SRC_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
289 A_TARGET_WRITE(scn, (CE_ctrl_addr) + CE_CTRL1_ADDRESS, \
290 (A_TARGET_READ((targid), \
291 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
292 & ~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
293 CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
294
295#define CE_DEST_RING_BYTE_SWAP_SET(scn, CE_ctrl_addr, n) \
296 A_TARGET_WRITE(scn, (CE_ctrl_addr)+CE_CTRL1_ADDRESS, \
297 (A_TARGET_READ((targid), \
298 (CE_ctrl_addr) + CE_CTRL1_ADDRESS) \
299 & ~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
300 CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
301
302#define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr) \
303 A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
304
305#define CE_DEST_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \
306 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS, (addr))
307
308#define CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, CE_ctrl_addr, addr) \
309 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH, (addr))
310
311#define CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, CE_ctrl_addr) \
312 A_TARGET_READ(scn, (CE_ctrl_addr) + DR_BA_ADDRESS_HIGH)
313
314#define CE_DEST_RING_SZ_SET(scn, CE_ctrl_addr, n) \
315 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DR_SIZE_ADDRESS, (n))
316
317#define CE_SRC_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
318 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
319 (A_TARGET_READ(scn, \
320 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
321 & ~SRC_WATERMARK_HIGH_MASK) | \
322 SRC_WATERMARK_HIGH_SET(n))
323
324#define CE_SRC_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
325 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
326 (A_TARGET_READ(scn, \
327 (CE_ctrl_addr) + SRC_WATERMARK_ADDRESS) \
328 & ~SRC_WATERMARK_LOW_MASK) | \
329 SRC_WATERMARK_LOW_SET(n))
330
331#define CE_DEST_RING_HIGHMARK_SET(scn, CE_ctrl_addr, n) \
332 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
333 (A_TARGET_READ(scn, \
334 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
335 & ~DST_WATERMARK_HIGH_MASK) | \
336 DST_WATERMARK_HIGH_SET(n))
337
338#define CE_DEST_RING_LOWMARK_SET(scn, CE_ctrl_addr, n) \
339 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WATERMARK_ADDRESS, \
340 (A_TARGET_READ(scn, \
341 (CE_ctrl_addr) + DST_WATERMARK_ADDRESS) \
342 & ~DST_WATERMARK_LOW_MASK) | \
343 DST_WATERMARK_LOW_SET(n))
344
345#define CE_COPY_COMPLETE_INTR_ENABLE(scn, CE_ctrl_addr) \
346 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
347 A_TARGET_READ(scn, \
348 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
349 HOST_IE_COPY_COMPLETE_MASK)
350
351#define CE_COPY_COMPLETE_INTR_DISABLE(scn, CE_ctrl_addr) \
352 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
353 A_TARGET_READ(scn, \
354 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
355 & ~HOST_IE_COPY_COMPLETE_MASK)
356
357#define CE_BASE_ADDRESS(CE_id) \
358 CE0_BASE_ADDRESS + ((CE1_BASE_ADDRESS - \
359 CE0_BASE_ADDRESS)*(CE_id))
360
361#define CE_WATERMARK_INTR_ENABLE(scn, CE_ctrl_addr) \
362 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
363 A_TARGET_READ(scn, \
364 (CE_ctrl_addr) + HOST_IE_ADDRESS) | \
365 CE_WATERMARK_MASK)
366
367#define CE_WATERMARK_INTR_DISABLE(scn, CE_ctrl_addr) \
368 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IE_ADDRESS, \
369 A_TARGET_READ(scn, \
370 (CE_ctrl_addr) + HOST_IE_ADDRESS) \
371 & ~CE_WATERMARK_MASK)
372
373#define CE_ERROR_INTR_ENABLE(scn, CE_ctrl_addr) \
374 A_TARGET_WRITE(scn, (CE_ctrl_addr) + MISC_IE_ADDRESS, \
375 A_TARGET_READ(scn, \
376 (CE_ctrl_addr) + MISC_IE_ADDRESS) | CE_ERROR_MASK)
377
378#define CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr) \
379 A_TARGET_READ(scn, (CE_ctrl_addr) + MISC_IS_ADDRESS)
380
381#define CE_ENGINE_INT_STATUS_GET(scn, CE_ctrl_addr) \
382 A_TARGET_READ(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS)
383
384#define CE_ENGINE_INT_STATUS_CLEAR(scn, CE_ctrl_addr, mask) \
385 A_TARGET_WRITE(scn, (CE_ctrl_addr) + HOST_IS_ADDRESS, (mask))
386
387#define CE_WRAPPER_INDEX_BASE_LOW_SET(scn, n) \
388 A_TARGET_WRITE(scn, \
389 CE_WRAPPER_INDEX_BASE_LOW + CE_WRAPPER_BASE_ADDRESS, n)
390
391#define CE_WRAPPER_INDEX_BASE_HIGH_SET(scn, n) \
392 A_TARGET_WRITE(scn, \
393 CE_WRAPPER_INDEX_BASE_HIGH + CE_WRAPPER_BASE_ADDRESS, n)
394
395#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
396 HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
397 HOST_IS_DST_RING_LOW_WATERMARK_MASK | \
398 HOST_IS_DST_RING_HIGH_WATERMARK_MASK)
399
400#define CE_ERROR_MASK (MISC_IS_AXI_ERR_MASK | \
401 MISC_IS_DST_ADDR_ERR_MASK | \
402 MISC_IS_SRC_LEN_ERR_MASK | \
403 MISC_IS_DST_MAX_LEN_VIO_MASK | \
404 MISC_IS_DST_RING_OVERFLOW_MASK | \
405 MISC_IS_SRC_RING_OVERFLOW_MASK)
406
407#define CE_SRC_RING_TO_DESC(baddr, idx) \
408 (&(((struct CE_src_desc *)baddr)[idx]))
409#define CE_DEST_RING_TO_DESC(baddr, idx) \
410 (&(((struct CE_dest_desc *)baddr)[idx]))
411
412/* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
413#define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
414 (((int)(toidx)-(int)(fromidx)) & (nentries_mask))
415
416#define CE_RING_IDX_INCR(nentries_mask, idx) \
417 (((idx) + 1) & (nentries_mask))
418
419#define CE_RING_IDX_ADD(nentries_mask, idx, num) \
420 (((idx) + (num)) & (nentries_mask))
421
422#define CE_INTERRUPT_SUMMARY(scn) \
423 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
424 A_TARGET_READ(scn, CE_WRAPPER_BASE_ADDRESS + \
425 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
426
427/*Macro to increment CE packet errors*/
428#define OL_ATH_CE_PKT_ERROR_COUNT_INCR(_scn, _ce_ecode) \
429 do { if (_ce_ecode == CE_RING_DELTA_FAIL) \
430 (_scn->pkt_stats.ce_ring_delta_fail_count) \
431 += 1; } while (0)
432
433/* Given a Copy Engine's ID, determine the interrupt number for that
434 * copy engine's interrupts.
435 */
436#define CE_ID_TO_INUM(id) (A_INUM_CE0_COPY_COMP_BASE + (id))
437#define CE_INUM_TO_ID(inum) ((inum) - A_INUM_CE0_COPY_COMP_BASE)
438#define CE0_BASE_ADDRESS (scn->target_ce_def->d_CE0_BASE_ADDRESS)
439#define CE1_BASE_ADDRESS (scn->target_ce_def->d_CE1_BASE_ADDRESS)
440
441#ifdef ADRASTEA_SHADOW_REGISTERS
442
443#define NUM_SHADOW_REGISTERS 24
444
445#define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) ((COPY_ENGINE_BASE_ADDRESS \
446 - CE0_BASE_ADDRESS)/(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
447
448u32 shadow_sr_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
449u32 shadow_dst_wr_ind_addr(struct ol_softc *scn, u32 ctrl_addr);
450#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
451 A_TARGET_WRITE(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr), n)
452
453#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
454 A_TARGET_READ(scn, shadow_sr_wr_ind_addr(scn, CE_ctrl_addr))
455
456#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
457 A_TARGET_WRITE(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr), n)
458
459#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
460 A_TARGET_READ(scn, shadow_dst_wr_ind_addr(scn, CE_ctrl_addr))
461
462#else
463
464#define CE_SRC_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
465 A_TARGET_WRITE(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
466
467#define CE_SRC_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
468 A_TARGET_READ(scn, (CE_ctrl_addr) + SR_WR_INDEX_ADDRESS)
469
470#define CE_DEST_RING_WRITE_IDX_SET(scn, CE_ctrl_addr, n) \
471 A_TARGET_WRITE(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
472
473#define CE_DEST_RING_WRITE_IDX_GET(scn, CE_ctrl_addr) \
474 A_TARGET_READ(scn, (CE_ctrl_addr) + DST_WR_INDEX_ADDRESS)
475
476#endif
477
478#endif /* __CE_REG_H__ */