Gitiles
Code Review Sign In
gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qca-wifi-host-cmn / 7508012ea960d984365f2723813d6d910e74e4e1 / . / hif / inc / regtable_pcie.h
blob: 7c22c706bf18d7e97e16abf763ab510e59cba3bf [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]1/*
Komal Seelam75080122016-03-02 15:18:25 +0530[diff] [blame^]2 * Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef _REGTABLE_PCIE_H_
29#define _REGTABLE_PCIE_H_
30
31#define MISSING 0
32
33struct targetdef_s {
34 uint32_t d_RTC_SOC_BASE_ADDRESS;
35 uint32_t d_RTC_WMAC_BASE_ADDRESS;
36 uint32_t d_SYSTEM_SLEEP_OFFSET;
37 uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
38 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
39 uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
40 uint32_t d_CLOCK_CONTROL_OFFSET;
41 uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
42 uint32_t d_RESET_CONTROL_OFFSET;
43 uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
44 uint32_t d_RESET_CONTROL_SI0_RST_MASK;
45 uint32_t d_WLAN_RESET_CONTROL_OFFSET;
46 uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
47 uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
48 uint32_t d_GPIO_BASE_ADDRESS;
49 uint32_t d_GPIO_PIN0_OFFSET;
50 uint32_t d_GPIO_PIN1_OFFSET;
51 uint32_t d_GPIO_PIN0_CONFIG_MASK;
52 uint32_t d_GPIO_PIN1_CONFIG_MASK;
53 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
54 uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
55 uint32_t d_SI_CONFIG_I2C_LSB;
56 uint32_t d_SI_CONFIG_I2C_MASK;
57 uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
58 uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
59 uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
60 uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
61 uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
62 uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
63 uint32_t d_SI_CONFIG_DIVIDER_LSB;
64 uint32_t d_SI_CONFIG_DIVIDER_MASK;
65 uint32_t d_SI_BASE_ADDRESS;
66 uint32_t d_SI_CONFIG_OFFSET;
67 uint32_t d_SI_TX_DATA0_OFFSET;
68 uint32_t d_SI_TX_DATA1_OFFSET;
69 uint32_t d_SI_RX_DATA0_OFFSET;
70 uint32_t d_SI_RX_DATA1_OFFSET;
71 uint32_t d_SI_CS_OFFSET;
72 uint32_t d_SI_CS_DONE_ERR_MASK;
73 uint32_t d_SI_CS_DONE_INT_MASK;
74 uint32_t d_SI_CS_START_LSB;
75 uint32_t d_SI_CS_START_MASK;
76 uint32_t d_SI_CS_RX_CNT_LSB;
77 uint32_t d_SI_CS_RX_CNT_MASK;
78 uint32_t d_SI_CS_TX_CNT_LSB;
79 uint32_t d_SI_CS_TX_CNT_MASK;
80 uint32_t d_BOARD_DATA_SZ;
81 uint32_t d_BOARD_EXT_DATA_SZ;
82 uint32_t d_MBOX_BASE_ADDRESS;
83 uint32_t d_LOCAL_SCRATCH_OFFSET;
84 uint32_t d_CPU_CLOCK_OFFSET;
85 uint32_t d_LPO_CAL_OFFSET;
86 uint32_t d_GPIO_PIN10_OFFSET;
87 uint32_t d_GPIO_PIN11_OFFSET;
88 uint32_t d_GPIO_PIN12_OFFSET;
89 uint32_t d_GPIO_PIN13_OFFSET;
90 uint32_t d_CLOCK_GPIO_OFFSET;
91 uint32_t d_CPU_CLOCK_STANDARD_LSB;
92 uint32_t d_CPU_CLOCK_STANDARD_MASK;
93 uint32_t d_LPO_CAL_ENABLE_LSB;
94 uint32_t d_LPO_CAL_ENABLE_MASK;
95 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
96 uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
97 uint32_t d_ANALOG_INTF_BASE_ADDRESS;
98 uint32_t d_WLAN_MAC_BASE_ADDRESS;
99 uint32_t d_FW_INDICATOR_ADDRESS;
100 uint32_t d_DRAM_BASE_ADDRESS;
101 uint32_t d_SOC_CORE_BASE_ADDRESS;
102 uint32_t d_CORE_CTRL_ADDRESS;
103 uint32_t d_CE_COUNT;
104 uint32_t d_MSI_NUM_REQUEST;
105 uint32_t d_MSI_ASSIGN_FW;
106 uint32_t d_MSI_ASSIGN_CE_INITIAL;
107 uint32_t d_PCIE_INTR_ENABLE_ADDRESS;
108 uint32_t d_PCIE_INTR_CLR_ADDRESS;
109 uint32_t d_PCIE_INTR_FIRMWARE_MASK;
110 uint32_t d_PCIE_INTR_CE_MASK_ALL;
111 uint32_t d_CORE_CTRL_CPU_INTR_MASK;
112 uint32_t d_SR_WR_INDEX_ADDRESS;
113 uint32_t d_DST_WATERMARK_ADDRESS;
114
115 /* htt_rx.c */
116 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
117 uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
118 uint32_t d_RX_MPDU_START_0_RETRY_LSB;
119 uint32_t d_RX_MPDU_START_0_RETRY_MASK;
120 uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
121 uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
122 uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
123 uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
124 uint32_t d_RX_MPDU_START_2_TID_LSB;
125 uint32_t d_RX_MPDU_START_2_TID_MASK;
126 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
127 uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
128 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
129 uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
130 uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
131 uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
132 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
133 uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
134 uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
135 uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
136 uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
137 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
138 uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
139 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
140 uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
141 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
142 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
143 uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
144 uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
145 uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
146 uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
147 uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
148 uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
149 /* end */
150
151 /* PLL start */
152 uint32_t d_EFUSE_OFFSET;
153 uint32_t d_EFUSE_XTAL_SEL_MSB;
154 uint32_t d_EFUSE_XTAL_SEL_LSB;
155 uint32_t d_EFUSE_XTAL_SEL_MASK;
156 uint32_t d_BB_PLL_CONFIG_OFFSET;
157 uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
158 uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
159 uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
160 uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
161 uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
162 uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
163 uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
164 uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
165 uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
166 uint32_t d_WLAN_PLL_SETTLE_OFFSET;
167 uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
168 uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
169 uint32_t d_WLAN_PLL_SETTLE_RESET;
170 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
171 uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
172 uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
173 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
174 uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
175 uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
176 uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
177 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
178 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
179 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
180 uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
181 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
182 uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
183 uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
184 uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
185 uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
186 uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
187 uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
188 uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
189 uint32_t d_WLAN_PLL_CONTROL_OFFSET;
190 uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
191 uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
192 uint32_t d_WLAN_PLL_CONTROL_RESET;
193 uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
194 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
195 uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
196 uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
197 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
198 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
199 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
200 uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
201 uint32_t d_RTC_SYNC_STATUS_OFFSET;
202 uint32_t d_SOC_CPU_CLOCK_OFFSET;
203 uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
204 uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
205 uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
206 /* PLL end */
207
208 uint32_t d_SOC_POWER_REG_OFFSET;
209 uint32_t d_PCIE_INTR_CAUSE_ADDRESS;
210 uint32_t d_SOC_RESET_CONTROL_ADDRESS;
211 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
212 uint32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB;
213 uint32_t d_SOC_RESET_CONTROL_CE_RST_MASK;
214 uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
215 uint32_t d_CPU_INTR_ADDRESS;
216 uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
217 uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
218
219 /* chip id start */
220 uint32_t d_SOC_CHIP_ID_ADDRESS;
221 uint32_t d_SOC_CHIP_ID_VERSION_MASK;
222 uint32_t d_SOC_CHIP_ID_VERSION_LSB;
223 uint32_t d_SOC_CHIP_ID_REVISION_MASK;
224 uint32_t d_SOC_CHIP_ID_REVISION_LSB;
225 /* chip id end */
226
227 uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
228 uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
229 uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
230 uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
231 uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
232 uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
233 uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
234 uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
235 uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
236 uint32_t d_PCIE_INTR_FIRMWARE_ROUTE_MASK;
237 uint32_t d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1;
238 uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
239 uint32_t d_A_SOC_CORE_PCIE_INTR_CLR_GRP1;
240 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1;
241 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_0;
242 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_1;
243 uint32_t d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA;
244 uint32_t d_A_SOC_PCIE_PCIE_SCRATCH_2;
245 uint32_t d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK;
246
247 uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
248 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
249 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
250 uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
251 uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
252 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
253 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
254 uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
255 uint32_t d_WLAN_DEBUG_OUT_OFFSET;
256 uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
257 uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
258 uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
259 uint32_t d_AMBA_DEBUG_BUS_OFFSET;
260 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
261 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
262 uint32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
263 uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
264 uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
265 uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
266
267#ifdef QCA_WIFI_3_0_ADRASTEA
268 uint32_t d_Q6_ENABLE_REGISTER_0;
269 uint32_t d_Q6_ENABLE_REGISTER_1;
270 uint32_t d_Q6_CAUSE_REGISTER_0;
271 uint32_t d_Q6_CAUSE_REGISTER_1;
272 uint32_t d_Q6_CLEAR_REGISTER_0;
273 uint32_t d_Q6_CLEAR_REGISTER_1;
274#endif
275};
276
277#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK \
278 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
279#define A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 \
280 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1)
281#define A_SOC_CORE_SPARE_1_REGISTER \
282 (scn->targetdef->d_A_SOC_CORE_SPARE_1_REGISTER)
283#define A_SOC_CORE_PCIE_INTR_CLR_GRP1 \
284 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_CLR_GRP1)
285#define A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 \
286 (scn->targetdef->d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1)
287#define A_SOC_PCIE_PCIE_SCRATCH_0 \
288 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_0)
289#define A_SOC_PCIE_PCIE_SCRATCH_1 \
290 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_1)
291#define A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA \
292 (scn->targetdef->d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA)
293#define A_SOC_PCIE_PCIE_SCRATCH_2 \
294 (scn->targetdef->d_A_SOC_PCIE_PCIE_SCRATCH_2)
295/* end Q6 iHelium emu registers */
296
297#define PCIE_INTR_FIRMWARE_ROUTE_MASK \
298 (scn->targetdef->d_PCIE_INTR_FIRMWARE_ROUTE_MASK)
299#define A_SOC_CORE_SPARE_0_REGISTER \
300 (scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
301#define A_SOC_CORE_SCRATCH_0_ADDRESS \
302 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
303#define A_SOC_CORE_SCRATCH_1_ADDRESS \
304 (scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
305#define A_SOC_CORE_SCRATCH_2_ADDRESS \
306 (scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
307#define A_SOC_CORE_SCRATCH_3_ADDRESS \
308 (scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
309#define A_SOC_CORE_SCRATCH_4_ADDRESS \
310 (scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
311#define A_SOC_CORE_SCRATCH_5_ADDRESS \
312 (scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
313#define A_SOC_CORE_SCRATCH_6_ADDRESS \
314 (scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
315#define A_SOC_CORE_SCRATCH_7_ADDRESS \
316 (scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
317#define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
318#define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
319#define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
320#define WLAN_SYSTEM_SLEEP_OFFSET \
321 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
322#define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
323 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
324#define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
325 (scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
326#define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
327#define CLOCK_CONTROL_SI0_CLK_MASK \
328 (scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
329#define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET)
330#define RESET_CONTROL_MBOX_RST_MASK \
331 (scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
332#define RESET_CONTROL_SI0_RST_MASK \
333 (scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
334#define WLAN_RESET_CONTROL_OFFSET \
335 (scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
336#define WLAN_RESET_CONTROL_COLD_RST_MASK \
337 (scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
338#define WLAN_RESET_CONTROL_WARM_RST_MASK \
339 (scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
340#define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS)
341#define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET)
342#define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET)
343#define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
344#define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
345#define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
346#define SI_CONFIG_BIDIR_OD_DATA_LSB \
347 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
348#define SI_CONFIG_BIDIR_OD_DATA_MASK \
349 (scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
350#define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB)
351#define SI_CONFIG_I2C_MASK \
352 (scn->targetdef->d_SI_CONFIG_I2C_MASK)
353#define SI_CONFIG_POS_SAMPLE_LSB \
354 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
355#define SI_CONFIG_POS_SAMPLE_MASK \
356 (scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
357#define SI_CONFIG_INACTIVE_CLK_LSB \
358 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
359#define SI_CONFIG_INACTIVE_CLK_MASK \
360 (scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
361#define SI_CONFIG_INACTIVE_DATA_LSB \
362 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
363#define SI_CONFIG_INACTIVE_DATA_MASK \
364 (scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
365#define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
366#define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
367#define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS)
368#define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET)
369#define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET)
370#define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET)
371#define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET)
372#define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET)
373#define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET)
374#define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
375#define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK)
376#define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB)
377#define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK)
378#define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB)
379#define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK)
380#define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB)
381#define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK)
382#define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ)
383#define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ)
384#define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS)
385#define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
386#define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET)
387#define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET)
388#define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET)
389#define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET)
390#define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET)
391#define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET)
392#define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET)
393#define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
394#define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
395#define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
396#define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
397#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
398 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
399#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
400 (scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
401#define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
402#define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
403#define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS)
404#define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS)
405#define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
406#define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS)
407#define CE_COUNT (scn->targetdef->d_CE_COUNT)
408#define PCIE_INTR_ENABLE_ADDRESS (scn->targetdef->d_PCIE_INTR_ENABLE_ADDRESS)
409#define PCIE_INTR_CLR_ADDRESS (scn->targetdef->d_PCIE_INTR_CLR_ADDRESS)
410#define PCIE_INTR_FIRMWARE_MASK (scn->targetdef->d_PCIE_INTR_FIRMWARE_MASK)
411#define PCIE_INTR_CE_MASK_ALL (scn->targetdef->d_PCIE_INTR_CE_MASK_ALL)
412#define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
413#define PCIE_INTR_CAUSE_ADDRESS (scn->targetdef->d_PCIE_INTR_CAUSE_ADDRESS)
414#define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
415#define HOST_GROUP0_MASK (PCIE_INTR_FIRMWARE_MASK | PCIE_INTR_CE_MASK_ALL | \
416 A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK)
417#define SOC_RESET_CONTROL_CE_RST_MASK \
418 (scn->targetdef->d_SOC_RESET_CONTROL_CE_RST_MASK)
419#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
420 (scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
421#define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS)
422#define SOC_LF_TIMER_CONTROL0_ADDRESS \
423 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
424#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
425 (scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
426#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB \
427 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
428#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK \
429 (scn->targetdef->d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
430
431#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) \
432 (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> \
433 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
434#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) \
435 (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & \
436 SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
437
438/* hif_pci.c */
439#define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
440#define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
441#define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
442#define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
443#define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
444#define CHIP_ID_REVISION_GET(x) \
445 (((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
446#define CHIP_ID_VERSION_GET(x) \
447 (((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
448/* hif_pci.c end */
449
450/* misc */
451#define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
452#define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS)
453#define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET)
454/* end */
455
456/* htt_rx.c */
457#define RX_MSDU_END_4_FIRST_MSDU_MASK \
458 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK)
459#define RX_MSDU_END_4_FIRST_MSDU_LSB \
460 (pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB)
461#define RX_MPDU_START_0_RETRY_LSB \
462 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB)
463#define RX_MPDU_START_0_RETRY_MASK \
464 (pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK)
465#define RX_MPDU_START_0_SEQ_NUM_MASK \
466 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK)
467#define RX_MPDU_START_0_SEQ_NUM_LSB \
468 (pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB)
469#define RX_MPDU_START_2_PN_47_32_LSB \
470 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB)
471#define RX_MPDU_START_2_PN_47_32_MASK \
472 (pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK)
473#define RX_MPDU_START_2_TID_LSB \
474 (pdev->targetdef->d_RX_MPDU_START_2_TID_LSB)
475#define RX_MPDU_START_2_TID_MASK \
476 (pdev->targetdef->d_RX_MPDU_START_2_TID_MASK)
477#define RX_MSDU_END_1_KEY_ID_OCT_MASK \
478 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK)
479#define RX_MSDU_END_1_KEY_ID_OCT_LSB \
480 (pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB)
481#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \
482 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK)
483#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \
484 (pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB)
485#define RX_MSDU_END_4_LAST_MSDU_MASK \
486 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK)
487#define RX_MSDU_END_4_LAST_MSDU_LSB \
488 (pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB)
489#define RX_ATTENTION_0_MCAST_BCAST_MASK \
490 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK)
491#define RX_ATTENTION_0_MCAST_BCAST_LSB \
492 (pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB)
493#define RX_ATTENTION_0_FRAGMENT_MASK \
494 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK)
495#define RX_ATTENTION_0_FRAGMENT_LSB \
496 (pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB)
497#define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \
498 (pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK)
499#define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \
500 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK)
501#define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \
502 (pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB)
503#define RX_MSDU_START_0_MSDU_LENGTH_MASK \
504 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK)
505#define RX_MSDU_START_0_MSDU_LENGTH_LSB \
506 (pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB)
507#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \
508 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET)
509#define RX_MSDU_START_2_DECAP_FORMAT_MASK \
510 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK)
511#define RX_MSDU_START_2_DECAP_FORMAT_LSB \
512 (pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB)
513#define RX_MPDU_START_0_ENCRYPTED_MASK \
514 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK)
515#define RX_MPDU_START_0_ENCRYPTED_LSB \
516 (pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB)
517#define RX_ATTENTION_0_MORE_DATA_MASK \
518 (pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK)
519#define RX_ATTENTION_0_MSDU_DONE_MASK \
520 (pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK)
521#define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \
522 (pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK)
523/* end */
524
525/* copy_engine.c */
526/* end */
527/* PLL start */
528#define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET)
529#define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
530#define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
531#define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
532#define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
533#define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
534#define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
535#define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
536#define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
537#define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
538#define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
539#define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
540#define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
541#define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
542#define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
543#define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
544#define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
545#define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
546#define WLAN_PLL_CONTROL_NOPWD_MSB \
547 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
548#define WLAN_PLL_CONTROL_NOPWD_LSB \
549 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
550#define WLAN_PLL_CONTROL_NOPWD_MASK \
551 (scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
552#define WLAN_PLL_CONTROL_BYPASS_MSB \
553 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
554#define WLAN_PLL_CONTROL_BYPASS_LSB \
555 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
556#define WLAN_PLL_CONTROL_BYPASS_MASK \
557 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
558#define WLAN_PLL_CONTROL_BYPASS_RESET \
559 (scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
560#define WLAN_PLL_CONTROL_CLK_SEL_MSB \
561 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
562#define WLAN_PLL_CONTROL_CLK_SEL_LSB \
563 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
564#define WLAN_PLL_CONTROL_CLK_SEL_MASK \
565 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
566#define WLAN_PLL_CONTROL_CLK_SEL_RESET \
567 (scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
568#define WLAN_PLL_CONTROL_REFDIV_MSB \
569 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
570#define WLAN_PLL_CONTROL_REFDIV_LSB \
571 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
572#define WLAN_PLL_CONTROL_REFDIV_MASK \
573 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
574#define WLAN_PLL_CONTROL_REFDIV_RESET \
575 (scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
576#define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
577#define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
578#define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
579#define WLAN_PLL_CONTROL_DIV_RESET \
580 (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
581#define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
582#define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
583#define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
584#define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
585#define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
586#define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
587#define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
588#define SOC_CORE_CLK_CTRL_DIV_MASK \
589 (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
590#define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
591 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
592#define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
593 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
594#define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
595 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
596#define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
597 (scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
598#define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
599#define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
600#define SOC_CPU_CLOCK_STANDARD_MSB \
601 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
602#define SOC_CPU_CLOCK_STANDARD_LSB \
603 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
604#define SOC_CPU_CLOCK_STANDARD_MASK \
605 (scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
606/* PLL end */
607
608/* SET macros */
609#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
610 (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
611 WLAN_SYSTEM_SLEEP_DISABLE_MASK)
612#define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
613 (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
614#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
615#define SI_CONFIG_POS_SAMPLE_SET(x) \
616 (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
617#define SI_CONFIG_INACTIVE_CLK_SET(x) \
618 (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
619#define SI_CONFIG_INACTIVE_DATA_SET(x) \
620 (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
621#define SI_CONFIG_DIVIDER_SET(x) \
622 (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
623#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
624#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
625#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
626#define LPO_CAL_ENABLE_SET(x) \
627 (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
628#define CPU_CLOCK_STANDARD_SET(x) \
629 (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
630#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
631 (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
632/* copy_engine.c */
633/* end */
634/* PLL start */
635#define EFUSE_XTAL_SEL_GET(x) \
636 (((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
637#define EFUSE_XTAL_SEL_SET(x) \
638 (((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
639#define BB_PLL_CONFIG_OUTDIV_GET(x) \
640 (((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
641#define BB_PLL_CONFIG_OUTDIV_SET(x) \
642 (((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
643#define BB_PLL_CONFIG_FRAC_GET(x) \
644 (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
645#define BB_PLL_CONFIG_FRAC_SET(x) \
646 (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
647#define WLAN_PLL_SETTLE_TIME_GET(x) \
648 (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
649#define WLAN_PLL_SETTLE_TIME_SET(x) \
650 (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
651#define WLAN_PLL_CONTROL_NOPWD_GET(x) \
652 (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
653#define WLAN_PLL_CONTROL_NOPWD_SET(x) \
654 (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
655#define WLAN_PLL_CONTROL_BYPASS_GET(x) \
656 (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
657#define WLAN_PLL_CONTROL_BYPASS_SET(x) \
658 (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
659#define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
660 (((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
661#define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
662 (((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
663#define WLAN_PLL_CONTROL_REFDIV_GET(x) \
664 (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
665#define WLAN_PLL_CONTROL_REFDIV_SET(x) \
666 (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
667#define WLAN_PLL_CONTROL_DIV_GET(x) \
668 (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
669#define WLAN_PLL_CONTROL_DIV_SET(x) \
670 (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
671#define SOC_CORE_CLK_CTRL_DIV_GET(x) \
672 (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
673#define SOC_CORE_CLK_CTRL_DIV_SET(x) \
674 (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
675#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
676 (((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
677 RTC_SYNC_STATUS_PLL_CHANGING_LSB)
678#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
679 (((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
680 RTC_SYNC_STATUS_PLL_CHANGING_MASK)
681#define SOC_CPU_CLOCK_STANDARD_GET(x) \
682 (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
683#define SOC_CPU_CLOCK_STANDARD_SET(x) \
684 (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
685/* PLL end */
686
687#ifdef QCA_WIFI_3_0_ADRASTEA
688#define Q6_ENABLE_REGISTER_0 \
689 (scn->targetdef->d_Q6_ENABLE_REGISTER_0)
690#define Q6_ENABLE_REGISTER_1 \
691 (scn->targetdef->d_Q6_ENABLE_REGISTER_1)
692#define Q6_CAUSE_REGISTER_0 \
693 (scn->targetdef->d_Q6_CAUSE_REGISTER_0)
694#define Q6_CAUSE_REGISTER_1 \
695 (scn->targetdef->d_Q6_CAUSE_REGISTER_1)
696#define Q6_CLEAR_REGISTER_0 \
697 (scn->targetdef->d_Q6_CLEAR_REGISTER_0)
698#define Q6_CLEAR_REGISTER_1 \
699 (scn->targetdef->d_Q6_CLEAR_REGISTER_1)
700#endif
701
702struct hostdef_s {
Komal Seelam75080122016-03-02 15:18:25 +0530[diff] [blame^]703 uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
704 uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
705 uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
706 uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
707 uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
708 uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
709 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
710 uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
711 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
712 uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
713 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
714 uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
715 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
716 uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
717 uint32_t d_INT_STATUS_ENABLE_ADDRESS;
718 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
719 uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
720 uint32_t d_HOST_INT_STATUS_ADDRESS;
721 uint32_t d_CPU_INT_STATUS_ADDRESS;
722 uint32_t d_ERROR_INT_STATUS_ADDRESS;
723 uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
724 uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
725 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
726 uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
727 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
728 uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
729 uint32_t d_COUNT_DEC_ADDRESS;
730 uint32_t d_HOST_INT_STATUS_CPU_MASK;
731 uint32_t d_HOST_INT_STATUS_CPU_LSB;
732 uint32_t d_HOST_INT_STATUS_ERROR_MASK;
733 uint32_t d_HOST_INT_STATUS_ERROR_LSB;
734 uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
735 uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
736 uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
737 uint32_t d_WINDOW_DATA_ADDRESS;
738 uint32_t d_WINDOW_READ_ADDR_ADDRESS;
739 uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
740 uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
741 uint32_t d_RTC_STATE_ADDRESS;
742 uint32_t d_RTC_STATE_COLD_RESET_MASK;
743 uint32_t d_PCIE_LOCAL_BASE_ADDRESS;
744 uint32_t d_PCIE_SOC_WAKE_RESET;
745 uint32_t d_PCIE_SOC_WAKE_ADDRESS;
746 uint32_t d_PCIE_SOC_WAKE_V_MASK;
747 uint32_t d_RTC_STATE_V_MASK;
748 uint32_t d_RTC_STATE_V_LSB;
749 uint32_t d_FW_IND_EVENT_PENDING;
750 uint32_t d_FW_IND_INITIALIZED;
751 uint32_t d_FW_IND_HELPER;
752 uint32_t d_RTC_STATE_V_ON;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]753#if defined(SDIO_3_0)
Komal Seelam75080122016-03-02 15:18:25 +0530[diff] [blame^]754 uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
755 uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]756#endif
Komal Seelam75080122016-03-02 15:18:25 +0530[diff] [blame^]757 uint32_t d_PCIE_SOC_RDY_STATUS_ADDRESS;
758 uint32_t d_PCIE_SOC_RDY_STATUS_BAR_MASK;
759 uint32_t d_SOC_PCIE_BASE_ADDRESS;
760 uint32_t d_MSI_MAGIC_ADR_ADDRESS;
761 uint32_t d_MSI_MAGIC_ADDRESS;
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]762 uint32_t d_HOST_CE_COUNT;
763 uint32_t d_ENABLE_MSI;
764 uint32_t d_MUX_ID_MASK;
765 uint32_t d_TRANSACTION_ID_MASK;
766 uint32_t d_DESC_DATA_FLAG_MASK;
767 uint32_t d_A_SOC_PCIE_PCIE_BAR0_START;
768};
769#define A_SOC_PCIE_PCIE_BAR0_START (scn->hostdef->d_A_SOC_PCIE_PCIE_BAR0_START)
770#define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)
771#define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)
772#define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)
773#define HOST_CE_COUNT (scn->hostdef->d_HOST_CE_COUNT)
774#define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)
775#define INT_STATUS_ENABLE_ERROR_LSB \
776 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
777#define INT_STATUS_ENABLE_ERROR_MASK \
778 (scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
779#define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
780#define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
781#define INT_STATUS_ENABLE_COUNTER_LSB \
782 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
783#define INT_STATUS_ENABLE_COUNTER_MASK \
784 (scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
785#define INT_STATUS_ENABLE_MBOX_DATA_LSB \
786 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
787#define INT_STATUS_ENABLE_MBOX_DATA_MASK \
788 (scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
789#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
790 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
791#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
792 (scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
793#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
794 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
795#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
796 (scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
797#define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
798 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
799#define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
800 (scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
801#define INT_STATUS_ENABLE_ADDRESS \
802 (scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
803#define CPU_INT_STATUS_ENABLE_BIT_LSB \
804 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
805#define CPU_INT_STATUS_ENABLE_BIT_MASK \
806 (scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
807#define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
808#define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
809#define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
810#define ERROR_INT_STATUS_WAKEUP_MASK \
811 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
812#define ERROR_INT_STATUS_WAKEUP_LSB \
813 (scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
814#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
815 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
816#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
817 (scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
818#define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
819 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
820#define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
821 (scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
822#define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS)
823#define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
824#define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
825#define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
826#define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
827#define HOST_INT_STATUS_COUNTER_MASK \
828 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
829#define HOST_INT_STATUS_COUNTER_LSB \
830 (scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
831#define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
832#define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS)
833#define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
834#define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
835#define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
836#define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS)
837#define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
838#define PCIE_LOCAL_BASE_ADDRESS (scn->hostdef->d_PCIE_LOCAL_BASE_ADDRESS)
839#define PCIE_SOC_WAKE_RESET (scn->hostdef->d_PCIE_SOC_WAKE_RESET)
840#define PCIE_SOC_WAKE_ADDRESS (scn->hostdef->d_PCIE_SOC_WAKE_ADDRESS)
841#define PCIE_SOC_WAKE_V_MASK (scn->hostdef->d_PCIE_SOC_WAKE_V_MASK)
842#define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK)
843#define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB)
844#define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING)
845#define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED)
846#define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER)
847#define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON)
848#if defined(SDIO_3_0)
849#define HOST_INT_STATUS_MBOX_DATA_MASK \
850 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
851#define HOST_INT_STATUS_MBOX_DATA_LSB \
852 (scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
853#endif
854
855#if !defined(SOC_PCIE_BASE_ADDRESS)
856#define SOC_PCIE_BASE_ADDRESS 0
857#endif
858
859#if !defined(PCIE_SOC_RDY_STATUS_ADDRESS)
860#define PCIE_SOC_RDY_STATUS_ADDRESS 0
861#define PCIE_SOC_RDY_STATUS_BAR_MASK 0
862#endif
863
864#if !defined(MSI_MAGIC_ADR_ADDRESS)
865#define MSI_MAGIC_ADR_ADDRESS 0
866#define MSI_MAGIC_ADDRESS 0
867#endif
868
869/* SET/GET macros */
870#define INT_STATUS_ENABLE_ERROR_SET(x) \
871 (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
872#define INT_STATUS_ENABLE_CPU_SET(x) \
873 (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
874#define INT_STATUS_ENABLE_COUNTER_SET(x) \
875 (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
876 INT_STATUS_ENABLE_COUNTER_MASK)
877#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
878 (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
879 INT_STATUS_ENABLE_MBOX_DATA_MASK)
880#define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
881 (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
882 CPU_INT_STATUS_ENABLE_BIT_MASK)
883#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
884 (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
885 ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
886#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
887 (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
888 ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
889#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
890 (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
891 COUNTER_INT_STATUS_ENABLE_BIT_MASK)
892#define ERROR_INT_STATUS_WAKEUP_GET(x) \
893 (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
894 ERROR_INT_STATUS_WAKEUP_LSB)
895#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
896 (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
897 ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
898#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
899 (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
900 ERROR_INT_STATUS_TX_OVERFLOW_LSB)
901#define HOST_INT_STATUS_CPU_GET(x) \
902 (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
903#define HOST_INT_STATUS_ERROR_GET(x) \
904 (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
905#define HOST_INT_STATUS_COUNTER_GET(x) \
906 (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
907#define RTC_STATE_V_GET(x) \
908 (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
909#if defined(SDIO_3_0)
910#define HOST_INT_STATUS_MBOX_DATA_GET(x) \
911 (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
912 HOST_INT_STATUS_MBOX_DATA_LSB)
913#endif
914
915#define INVALID_REG_LOC_DUMMY_DATA 0xAA
916
917#define AR6320_CORE_CLK_DIV_ADDR 0x403fa8
918#define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0
919#define AR6320_CPU_SPEED_ADDR 0x403fa4
920#define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8
921#define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
922#define AR6320V2_CPU_SPEED_ADDR 0x403fd4
923#define AR6320V3_CORE_CLK_DIV_ADDR 0x404028
924#define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
925#define AR6320V3_CPU_SPEED_ADDR 0x404024
926
927typedef enum {
928 SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
929 SOC_REFCLK_48_MHZ = 0,
930 SOC_REFCLK_19_2_MHZ = 1,
931 SOC_REFCLK_24_MHZ = 2,
932 SOC_REFCLK_26_MHZ = 3,
933 SOC_REFCLK_37_4_MHZ = 4,
934 SOC_REFCLK_38_4_MHZ = 5,
935 SOC_REFCLK_40_MHZ = 6,
936 SOC_REFCLK_52_MHZ = 7,
937} A_refclk_speed_t;
938
939#define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN
940#define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ
941#define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ
942#define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ
943#define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ
944#define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ
945#define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ
946#define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ
947#define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ
948
949#define TARGET_CPU_FREQ 176000000
950
951struct wlan_pll_s {
952 uint32_t refdiv;
953 uint32_t div;
954 uint32_t rnfrac;
955 uint32_t outdiv;
956};
957
958struct cmnos_clock_s {
959 A_refclk_speed_t refclk_speed;
960 uint32_t refclk_hz;
961 uint32_t pll_settling_time; /* 50us */
962 struct wlan_pll_s wlan_pll;
963};
964
965typedef struct TGT_REG_SECTION {
966 uint32_t start_addr;
967 uint32_t end_addr;
968} tgt_reg_section;
969
970typedef struct TGT_REG_TABLE {
971 tgt_reg_section *section;
972 uint32_t section_size;
973} tgt_reg_table;
974
Komal Seelam644263d2016-02-22 20:45:49 +0530[diff] [blame]975struct hif_softc;
976void target_register_tbl_attach(struct hif_softc *scn, u32 target_type);
977void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type);
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame]978
979struct host_shadow_regs_s {
980 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_0;
981 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_1;
982 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_2;
983 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_3;
984 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_4;
985 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_5;
986 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_6;
987 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_7;
988 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_8;
989 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_9;
990 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_10;
991 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_11;
992 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_12;
993 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_13;
994 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_14;
995 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_15;
996 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_16;
997 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_17;
998 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_18;
999 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_19;
1000 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_20;
1001 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_21;
1002 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_22;
1003 uint32_t d_A_LOCAL_SHADOW_REG_VALUE_23;
1004 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_0;
1005 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_1;
1006 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_2;
1007 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_3;
1008 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_4;
1009 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_5;
1010 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_6;
1011 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_7;
1012 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_8;
1013 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_9;
1014 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_10;
1015 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_11;
1016 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_12;
1017 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_13;
1018 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_14;
1019 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_15;
1020 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_16;
1021 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_17;
1022 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_18;
1023 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_19;
1024 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_20;
1025 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_21;
1026 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_22;
1027 uint32_t d_A_LOCAL_SHADOW_REG_ADDRESS_23;
1028};
1029
1030#endif /* _REGTABLE_PCIE_H_ */