blob: 0adc66dafbad47adf8622788abae544ab28a0f7e [file] [log] [blame]
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -08001/*
2 * Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef _HIF_H_
29#define _HIF_H_
30
31#ifdef __cplusplus
32extern "C" {
33#endif /* __cplusplus */
34
35/* Header files */
36#include "athdefs.h"
37#include "a_types.h"
38#include "osapi_linux.h"
39#include "cdf_status.h"
40#include "cdf_nbuf.h"
41#include "ol_if_athvar.h"
42#include <linux/platform_device.h>
43#ifdef HIF_PCI
44#include <linux/pci.h>
45#endif /* HIF_PCI */
46
47#define ENABLE_MBOX_DUMMY_SPACE_FEATURE 1
48
49typedef struct htc_callbacks HTC_CALLBACKS;
50typedef void __iomem *A_target_id_t;
51
52#define HIF_TYPE_AR6002 2
53#define HIF_TYPE_AR6003 3
54#define HIF_TYPE_AR6004 5
55#define HIF_TYPE_AR9888 6
56#define HIF_TYPE_AR6320 7
57#define HIF_TYPE_AR6320V2 8
58/* For attaching Peregrine 2.0 board host_reg_tbl only */
59#define HIF_TYPE_AR9888V2 8
60#define HIF_TYPE_QCA6180 9
61#define HIF_TYPE_ADRASTEA 10
62
63#define TARGET_TYPE_UNKNOWN 0
64#define TARGET_TYPE_AR6001 1
65#define TARGET_TYPE_AR6002 2
66#define TARGET_TYPE_AR6003 3
67#define TARGET_TYPE_AR6004 5
68#define TARGET_TYPE_AR6006 6
69#define TARGET_TYPE_AR9888 7
70#define TARGET_TYPE_AR6320 8
71#define TARGET_TYPE_AR900B 9
72/* For attach Peregrine 2.0 board target_reg_tbl only */
73#define TARGET_TYPE_AR9888V2 10
74/* For attach Rome1.0 target_reg_tbl only*/
75#define TARGET_TYPE_AR6320V1 11
76/* For Rome2.0/2.1 target_reg_tbl ID*/
77#define TARGET_TYPE_AR6320V2 12
78/* For Rome3.0 target_reg_tbl ID*/
79#define TARGET_TYPE_AR6320V3 13
80/* For Tufello1.0 target_reg_tbl ID*/
81#define TARGET_TYPE_QCA9377V1 14
82/* For QCA6180 target */
83#define TARGET_TYPE_QCA6180 15
84/* For Adrastea target */
85#define TARGET_TYPE_ADRASTEA 16
86
87struct CE_state;
Sanjay Devnani9ce15772015-11-12 14:08:57 -080088#ifdef QCA_WIFI_3_0_ADRASTEA
89#define CE_COUNT_MAX 12
90#else
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -080091#define CE_COUNT_MAX 8
Sanjay Devnani9ce15772015-11-12 14:08:57 -080092#endif
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -080093
94/* These numbers are selected so that the product is close to current
95 higher limit of packets HIF services at one shot (1000) */
96#define QCA_NAPI_BUDGET 64
97#define QCA_NAPI_DEF_SCALE 16
98/* NOTE: This is to adapt non-NAPI solution to use
99 the same "budget" as NAPI. Will be removed
100 `once decision about NAPI is made */
101#define HIF_NAPI_MAX_RECEIVES (QCA_NAPI_BUDGET * QCA_NAPI_DEF_SCALE)
102
103/* NOTE: "napi->scale" can be changed,
104 but this does not change the number of buckets */
105#define QCA_NAPI_NUM_BUCKETS (QCA_NAPI_BUDGET / QCA_NAPI_DEF_SCALE)
106struct qca_napi_stat {
107 uint32_t napi_schedules;
108 uint32_t napi_polls;
109 uint32_t napi_completes;
110 uint32_t napi_workdone;
111 uint32_t napi_budget_uses[QCA_NAPI_NUM_BUCKETS];
112};
113
114/**
115 * per NAPI instance data structure
116 * This data structure holds stuff per NAPI instance.
117 * Note that, in the current implementation, though scale is
118 * an instance variable, it is set to the same value for all
119 * instances.
120 */
121struct qca_napi_info {
122 struct napi_struct napi; /* one NAPI Instance per CE in phase I */
123 uint8_t scale; /* currently same on all instances */
124 uint8_t id;
125 struct qca_napi_stat stats[NR_CPUS];
126};
127
128/**
129 * NAPI data-sructure common to all NAPI instances.
130 *
131 * A variable of this type will be stored in hif module context.
132 */
133
134struct qca_napi_data {
135 /* NOTE: make sure the mutex is inited only at the very beginning
136 once for the lifetime of the driver. For now, granularity of one
137 is OK, but we might want to have a better granularity later */
138 struct mutex mutex;
139 uint32_t state;
140 uint32_t ce_map; /* bitmap of created/registered NAPI
141 instances, indexed by pipe_id,
142 not used by clients (clients use an
143 id returned by create) */
144 struct net_device netdev; /* dummy net_dev */
145 struct qca_napi_info napis[CE_COUNT_MAX];
146};
147
148struct ol_softc {
149 void __iomem *mem; /* IO mapped memory base address */
150 cdf_dma_addr_t mem_pa;
151 uint32_t soc_version;
152 /*
153 * handle for code that uses the osdep.h version of OS
154 * abstraction primitives
155 */
156 struct _NIC_DEV aps_osdev;
157 enum ath_hal_bus_type bus_type;
158 uint32_t lcr_val;
159 bool pkt_log_init;
160 bool request_irq_done;
161 /*
162 * handle for code that uses cdf version of OS
163 * abstraction primitives
164 */
165 cdf_device_t cdf_dev;
166
167 struct ol_version version;
168
169 /* Packet statistics */
170 struct ol_ath_stats pkt_stats;
171
172 /* A_TARGET_TYPE_* */
173 uint32_t target_type;
174 uint32_t target_fw_version;
175 uint32_t target_version;
176 uint32_t target_revision;
177 uint8_t crm_version_string[64];
178 uint8_t wlan_version_string[64];
179 ol_target_status target_status;
180 bool is_sim;
181 /* calibration data is stored in flash */
182 uint8_t *cal_in_flash;
183 /* virtual address for the calibration data on the flash */
184 void *cal_mem;
185 /* status of target init */
186 WLAN_INIT_STATUS wlan_init_status;
187
188 /* BMI info */
189 /* OS-dependent private info for BMI */
190 void *bmi_ol_priv;
191 bool bmi_done;
192 bool bmi_ua_done;
193 uint8_t *bmi_cmd_buff;
194 dma_addr_t bmi_cmd_da;
195 OS_DMA_MEM_CONTEXT(bmicmd_dmacontext)
196
197 uint8_t *bmi_rsp_buff;
198 dma_addr_t bmi_rsp_da;
199 /* length of last response */
200 uint32_t last_rxlen;
201 OS_DMA_MEM_CONTEXT(bmirsp_dmacontext)
202
203 void *msi_magic;
204 dma_addr_t msi_magic_da;
205 OS_DMA_MEM_CONTEXT(msi_dmacontext)
206
207 /* Handles for Lower Layers : filled in at init time */
208 hif_handle_t hif_hdl;
209#ifdef HIF_PCI
210 struct hif_pci_softc *hif_sc;
211#endif
212
213#ifdef WLAN_FEATURE_FASTPATH
214 int fastpath_mode_on; /* Duplicating this for data path efficiency */
215#endif /* WLAN_FEATURE_FASTPATH */
216
217 /* HTC handles */
218 void *htc_handle;
219
220 bool fEnableBeaconEarlyTermination;
221 uint8_t bcnEarlyTermWakeInterval;
222
223 /* UTF event information */
224 struct {
225 uint8_t *data;
226 uint32_t length;
227 cdf_size_t offset;
228 uint8_t currentSeq;
229 uint8_t expectedSeq;
230 } utf_event_info;
231
232 struct ol_wow_info *scn_wowInfo;
233 /* enable uart/serial prints from target */
234 bool enableuartprint;
235 /* enable fwlog */
236 bool enablefwlog;
237
238 HAL_REG_CAPABILITIES hal_reg_capabilities;
239 struct ol_regdmn *ol_regdmn_handle;
240 uint8_t bcn_mode;
241 uint8_t arp_override;
242 /*
243 * Includes host side stack level stats +
244 * radio level athstats
245 */
246 struct wlan_dbg_stats ath_stats;
247 /* noise_floor */
248 int16_t chan_nf;
249 uint32_t min_tx_power;
250 uint32_t max_tx_power;
251 uint32_t txpowlimit2G;
252 uint32_t txpowlimit5G;
253 uint32_t txpower_scale;
254 uint32_t chan_tx_pwr;
255 uint32_t vdev_count;
256 uint32_t max_bcn_ie_size;
257 cdf_spinlock_t scn_lock;
258 uint8_t vow_extstats;
259 /* if dcs enabled or not */
260 uint8_t scn_dcs;
261 wdi_event_subscribe scn_rx_peer_invalid_subscriber;
262 uint8_t proxy_sta;
263 uint8_t bcn_enabled;
264 /* Dynamic Tx Chainmask Selection enabled/disabled */
265 uint8_t dtcs;
266 /* true if vht ies are set on target */
267 uint32_t set_ht_vht_ies:1;
268 /*CWM enable/disable state */
269 bool scn_cwmenable;
270 uint8_t max_no_of_peers;
271#ifdef CONFIG_CNSS
272 struct cnss_fw_files fw_files;
273#endif
274#if defined(CONFIG_CNSS)
275 void *ramdump_base;
276 unsigned long ramdump_address;
277 unsigned long ramdump_size;
278#endif
279 bool enable_self_recovery;
280#ifdef WLAN_FEATURE_LPSS
281 bool enablelpasssupport;
282#endif
283 bool enable_ramdump_collection;
284 struct targetdef_s *targetdef;
285 struct ce_reg_def *target_ce_def;
286 struct hostdef_s *hostdef;
287 struct host_shadow_regs_s *host_shadow_regs;
288 bool athdiag_procfs_inited;
289 /*
290 * Guard changes to Target HW state and to software
291 * structures that track hardware state.
292 */
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800293 unsigned int ce_count; /* Number of Copy Engines supported */
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800294 struct CE_state *ce_id_to_state[CE_COUNT_MAX]; /* CE id to CE_state */
295#ifdef FEATURE_NAPI
296 struct qca_napi_data napi_data;
297#endif /* FEATURE_NAPI */
298 int htc_endpoint;
299 bool recovery;
300 bool hif_init_done;
301 int linkstate_vote;
302 atomic_t link_suspended;
303 atomic_t wow_done;
304 atomic_t tasklet_from_intr;
305 atomic_t active_tasklet_cnt;
306 bool notice_send;
307#ifdef HIF_PCI
308 cdf_spinlock_t irq_lock;
309 uint32_t ce_irq_summary;
310#endif
Sanjay Devnanib925d7e2015-11-12 14:43:58 -0800311 uint32_t *vaddr_rri_on_ddr;
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800312};
313
314typedef enum {
315 HIF_DEVICE_POWER_UP, /* HIF layer should power up interface
316 * and/or module */
317 HIF_DEVICE_POWER_DOWN, /* HIF layer should initiate bus-specific
318 * measures to minimize power */
319 HIF_DEVICE_POWER_CUT /* HIF layer should initiate bus-specific
320 * AND/OR platform-specific measures
321 * to completely power-off the module and
322 * associated hardware (i.e. cut power
323 * supplies) */
324} HIF_DEVICE_POWER_CHANGE_TYPE;
325
326/**
327 * enum hif_enable_type: what triggered the enabling of hif
328 *
329 * @HIF_ENABLE_TYPE_PROBE: probe triggered enable
330 * @HIF_ENABLE_TYPE_REINIT: reinit triggered enable
331 */
332enum hif_enable_type {
333 HIF_ENABLE_TYPE_PROBE,
334 HIF_ENABLE_TYPE_REINIT,
335 HIF_ENABLE_TYPE_MAX
336};
337
338/**
339 * enum hif_disable_type: what triggered the disabling of hif
340 *
341 * @HIF_DISABLE_TYPE_PROBE_ERROR: probe error triggered disable
342 * @HIF_DISABLE_TYPE_REINIT_ERROR: reinit error triggered
343 * disable
344 * @HIF_DISABLE_TYPE_REMOVE: remove triggered disable
345 * @HIF_DISABLE_TYPE_SHUTDOWN: shutdown triggered disable
346 */
347enum hif_disable_type {
348 HIF_DISABLE_TYPE_PROBE_ERROR,
349 HIF_DISABLE_TYPE_REINIT_ERROR,
350 HIF_DISABLE_TYPE_REMOVE,
351 HIF_DISABLE_TYPE_SHUTDOWN,
352 HIF_DISABLE_TYPE_MAX
353};
354
355#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
356typedef struct _HID_ACCESS_LOG {
357 uint32_t seqnum;
358 bool is_write;
359 void *addr;
360 uint32_t value;
361} HIF_ACCESS_LOG;
362#endif
363
364#define HIF_MAX_DEVICES 1
365
366struct htc_callbacks {
367 void *context; /* context to pass to the dsrhandler
368 * note : rwCompletionHandler is provided
369 * the context passed to hif_read_write */
370 int (*rwCompletionHandler)(void *rwContext, int status);
371 int (*dsrHandler)(void *context);
372};
373
374typedef struct osdrv_callbacks {
375 void *context; /* context to pass for all callbacks
376 * except deviceRemovedHandler
377 * the deviceRemovedHandler is only
378 * called if the device is claimed */
379 int (*deviceInsertedHandler)(void *context, void *hif_handle);
380 int (*deviceRemovedHandler)(void *claimedContext,
381 void *hif_handle);
382 int (*deviceSuspendHandler)(void *context);
383 int (*deviceResumeHandler)(void *context);
384 int (*deviceWakeupHandler)(void *context);
385 int (*devicePowerChangeHandler)(void *context,
386 HIF_DEVICE_POWER_CHANGE_TYPE
387 config);
388} OSDRV_CALLBACKS;
389
390/*
391 * This API is used to perform any global initialization of the HIF layer
392 * and to set OS driver callbacks (i.e. insertion/removal) to the HIF layer
393 *
394 */
395int hif_init(OSDRV_CALLBACKS *callbacks);
396
397/*
398 * This API claims the HIF device and provides a context for handling removal.
399 * The device removal callback is only called when the OSDRV layer claims
400 * a device. The claimed context must be non-NULL */
401void hif_claim_device(struct ol_softc *scn, void *claimedContext);
402/* release the claimed device */
403void hif_release_device(struct ol_softc *scn);
404
405/* This API detaches the HTC layer from the HIF device */
406void hif_detach_htc(struct ol_softc *scn);
407
408/****************************************************************/
409/* BMI and Diag window abstraction */
410/****************************************************************/
411
412#define HIF_BMI_EXCHANGE_NO_TIMEOUT ((uint32_t)(0))
413
414#define DIAG_TRANSFER_LIMIT 2048U /* maximum number of bytes that can be
415 * handled atomically by
416 * DiagRead/DiagWrite */
417
418/*
419 * API to handle HIF-specific BMI message exchanges, this API is synchronous
420 * and only allowed to be called from a context that can block (sleep) */
421CDF_STATUS hif_exchange_bmi_msg(struct ol_softc *scn,
422 uint8_t *pSendMessage,
423 uint32_t Length,
424 uint8_t *pResponseMessage,
425 uint32_t *pResponseLength, uint32_t TimeoutMS);
426
427/*
428 * APIs to handle HIF specific diagnostic read accesses. These APIs are
429 * synchronous and only allowed to be called from a context that
430 * can block (sleep). They are not high performance APIs.
431 *
432 * hif_diag_read_access reads a 4 Byte aligned/length value from a
433 * Target register or memory word.
434 *
435 * hif_diag_read_mem reads an arbitrary length of arbitrarily aligned memory.
436 */
437CDF_STATUS hif_diag_read_access(struct ol_softc *scn, uint32_t address,
438 uint32_t *data);
439CDF_STATUS hif_diag_read_mem(struct ol_softc *scn, uint32_t address,
440 uint8_t *data, int nbytes);
441void hif_dump_target_memory(struct ol_softc *scn, void *ramdump_base,
442 uint32_t address, uint32_t size);
443/*
444 * APIs to handle HIF specific diagnostic write accesses. These APIs are
445 * synchronous and only allowed to be called from a context that
446 * can block (sleep).
447 * They are not high performance APIs.
448 *
449 * hif_diag_write_access writes a 4 Byte aligned/length value to a
450 * Target register or memory word.
451 *
452 * hif_diag_write_mem writes an arbitrary length of arbitrarily aligned memory.
453 */
454CDF_STATUS hif_diag_write_access(struct ol_softc *scn, uint32_t address,
455 uint32_t data);
456CDF_STATUS hif_diag_write_mem(struct ol_softc *scn, uint32_t address,
457 uint8_t *data, int nbytes);
458
459/*
460 * Set the FASTPATH_mode_on flag in sc, for use by data path
461 */
462#ifdef WLAN_FEATURE_FASTPATH
463void hif_enable_fastpath(struct ol_softc *hif_dev);
464#endif
465
466#if defined(HIF_PCI) && !defined(A_SIMOS_DEVHOST)
467/*
468 * This API allows the Host to access Target registers of a given
469 * A_target_id_t directly and relatively efficiently over PCIe.
470 * This allows the Host to avoid extra overhead associated with
471 * sending a message to firmware and waiting for a response message
472 * from firmware, as is done on other interconnects.
473 *
474 * Yet there is some complexity with direct accesses because the
475 * Target's power state is not known a priori. The Host must issue
476 * special PCIe reads/writes in order to explicitly wake the Target
477 * and to verify that it is awake and will remain awake.
478 *
479 * NB: Host endianness conversion is left for the caller to handle.
480 * These interfaces handle access; not interpretation.
481 *
482 * Usage:
483 * During initialization, use A_TARGET_ID to obtain an 'target ID'
484 * for use with these interfaces.
485 *
486 * Use A_TARGET_READ and A_TARGET_WRITE to access Target space.
487 * These calls must be bracketed by A_TARGET_ACCESS_BEGIN and
488 * A_TARGET_ACCESS_END. A single BEGIN/END pair is adequate for
489 * multiple READ/WRITE operations.
490 *
491 * Use A_TARGET_ACCESS_BEGIN to put the Target in a state in
492 * which it is legal for the Host to directly access it. This
493 * may involve waking the Target from a low power state, which
494 * may take up to 2Ms!
495 *
496 * Use A_TARGET_ACCESS_END to tell the Target that as far as
497 * this code path is concerned, it no longer needs to remain
498 * directly accessible. BEGIN/END is under a reference counter;
499 * multiple code paths may issue BEGIN/END on a single targid.
500 *
501 * For added efficiency, the Host may use A_TARGET_ACCESS_LIKELY.
502 * The LIKELY interface works just like A_TARGET_ACCESS_BEGIN,
503 * except that it may return before the Target is actually
504 * available. It's a vague indication that some Target accesses
505 * are expected "soon". When the LIKELY API is used,
506 * A_TARGET_ACCESS_BEGIN must be used before any access.
507 *
508 * There are several uses for the LIKELY/UNLIKELY API:
509 * -If there is some potential time before Target accesses
510 * and we want to get a head start on waking the Target
511 * (e.g. to overlap Target wake with Host-side malloc)
512 * -High-level code knows that it will call low-level
513 * functions that will use BEGIN/END, and we don't want
514 * to allow the Target to sleep until the entire sequence
515 * has completed.
516 *
517 * A_TARGET_ACCESS_OK verifies that the Target can be
518 * accessed. In general, this should not be needed, but it
519 * may be useful for debugging or for special uses.
520 *
521 * Note that there must be a matching END for each BEGIN
522 * AND there must be a matching UNLIKELY for each LIKELY!
523 *
524 * NB: This API is designed to allow some flexibility in tradeoffs
525 * between Target power utilization and Host efficiency and
526 * system performance.
527 */
528
529/*
530 * Enable/disable CDC max performance workaround
531 * For max-performace set this to 0
532 * To allow SoC to enter sleep set this to 1
533 */
534#define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
535#endif
536
537#ifdef IPA_OFFLOAD
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800538void hif_ipa_get_ce_resource(struct ol_softc *scn,
Leo Changd85f78d2015-11-13 10:55:34 -0800539 cdf_dma_addr_t *ce_sr_base_paddr,
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800540 uint32_t *ce_sr_ring_size,
541 cdf_dma_addr_t *ce_reg_paddr);
542#else
Leo Changd85f78d2015-11-13 10:55:34 -0800543/**
544 * hif_ipa_get_ce_resource() - get uc resource on hif
545 * @scn: bus context
546 * @ce_sr_base_paddr: copyengine source ring base physical address
547 * @ce_sr_ring_size: copyengine source ring size
548 * @ce_reg_paddr: copyengine register physical address
549 *
550 * IPA micro controller data path offload feature enabled,
551 * HIF should release copy engine related resource information to IPA UC
552 * IPA UC will access hardware resource with released information
553 *
554 * Return: None
555 */
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800556static inline void hif_ipa_get_ce_resource(struct ol_softc *scn,
Leo Changd85f78d2015-11-13 10:55:34 -0800557 cdf_dma_addr_t *ce_sr_base_paddr,
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800558 uint32_t *ce_sr_ring_size,
559 cdf_dma_addr_t *ce_reg_paddr)
560{
561 return;
562}
563#endif /* IPA_OFFLOAD */
564
565
566void hif_read_phy_mem_base(struct ol_softc *scn,
567 cdf_dma_addr_t *bar_value);
568
569/**
570 * @brief List of callbacks - filled in by HTC.
571 */
572struct hif_msg_callbacks {
573 void *Context;
574 /**< context meaningful to HTC */
575 CDF_STATUS (*txCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
576 uint32_t transferID,
577 uint32_t toeplitz_hash_result);
578 CDF_STATUS (*rxCompletionHandler)(void *Context, cdf_nbuf_t wbuf,
579 uint8_t pipeID);
580 void (*txResourceAvailHandler)(void *context, uint8_t pipe);
581 void (*fwEventHandler)(void *context, CDF_STATUS status);
582};
583
584#define HIF_DATA_ATTR_SET_TX_CLASSIFY(attr, v) \
585 (attr |= (v & 0x01) << 5)
586#define HIF_DATA_ATTR_SET_ENCAPSULATION_TYPE(attr, v) \
587 (attr |= (v & 0x03) << 6)
588#define HIF_DATA_ATTR_SET_ADDR_X_SEARCH_DISABLE(attr, v) \
589 (attr |= (v & 0x01) << 13)
590#define HIF_DATA_ATTR_SET_ADDR_Y_SEARCH_DISABLE(attr, v) \
591 (attr |= (v & 0x01) << 14)
592#define HIF_DATA_ATTR_SET_TOEPLITZ_HASH_ENABLE(attr, v) \
593 (attr |= (v & 0x01) << 15)
594#define HIF_DATA_ATTR_SET_PACKET_OR_RESULT_OFFSET(attr, v) \
595 (attr |= (v & 0x0FFF) << 16)
596#define HIF_DATA_ATTR_SET_ENABLE_11H(attr, v) \
597 (attr |= (v & 0x01) << 30)
598
599#ifdef HIF_PCI
600typedef struct pci_device_id hif_bus_id;
601#else
602typedef struct device hif_bus_id;
603#endif
604
605void hif_post_init(struct ol_softc *scn, void *hHTC,
606 struct hif_msg_callbacks *callbacks);
607CDF_STATUS hif_start(struct ol_softc *scn);
608void hif_stop(struct ol_softc *scn);
609void hif_flush_surprise_remove(struct ol_softc *scn);
610void hif_dump(struct ol_softc *scn, uint8_t CmdId, bool start);
611CDF_STATUS hif_send_head(struct ol_softc *scn, uint8_t PipeID,
612 uint32_t transferID, uint32_t nbytes,
613 cdf_nbuf_t wbuf, uint32_t data_attr);
614void hif_send_complete_check(struct ol_softc *scn, uint8_t PipeID,
615 int force);
616void hif_cancel_deferred_target_sleep(struct ol_softc *scn);
617void hif_get_default_pipe(struct ol_softc *scn, uint8_t *ULPipe,
618 uint8_t *DLPipe);
Sanjay Devnanic319c822015-11-06 16:44:28 -0800619int hif_map_service_to_pipe(struct ol_softc *scn, uint16_t svc_id,
620 uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled,
621 int *dl_is_polled);
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800622uint16_t hif_get_free_queue_number(struct ol_softc *scn, uint8_t PipeID);
623void *hif_get_targetdef(struct ol_softc *scn);
624void hi_fsuspendwow(struct ol_softc *scn);
625uint32_t hif_hia_item_address(uint32_t target_type, uint32_t item_offset);
626void hif_set_target_sleep(struct ol_softc *scn, bool sleep_ok,
627 bool wait_for_it);
628int hif_check_fw_reg(struct ol_softc *scn);
629int hif_check_soc_status(struct ol_softc *scn);
630void dump_ce_debug_register(struct ol_softc *scn);
631void hif_get_hw_info(void *scn, u32 *version, u32 *revision,
632 const char **target_name);
633void hif_set_fw_info(void *scn, u32 target_fw_version);
634void hif_disable_isr(void *scn);
635void hif_reset_soc(void *scn);
636void hif_disable_aspm(void);
637void hif_save_htc_htt_config_endpoint(int htc_endpoint);
638CDF_STATUS hif_open(void);
639void hif_close(void *hif_ctx);
640CDF_STATUS hif_enable(void *hif_ctx, struct device *dev, void *bdev,
641 const hif_bus_id *bid, enum ath_hal_bus_type bus_type,
642 enum hif_enable_type type);
643void hif_disable(void *hif_ctx, enum hif_disable_type type);
644void hif_enable_power_gating(void *hif_ctx);
Houston Hoffman9078a152015-11-02 16:15:02 -0800645
646#ifdef FEATURE_RUNTIME_PM
647struct hif_pm_runtime_lock;
648int hif_pm_runtime_get(void *hif_ctx);
Houston Hoffmanf4607852015-12-17 17:14:40 -0800649void hif_pm_runtime_get_noresume(void *hif_ctx);
Houston Hoffman9078a152015-11-02 16:15:02 -0800650int hif_pm_runtime_put(void *hif_ctx);
651struct hif_pm_runtime_lock *hif_runtime_lock_init(const char *name);
652void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock);
653int hif_pm_runtime_prevent_suspend(void *ol_sc,
654 struct hif_pm_runtime_lock *lock);
655int hif_pm_runtime_allow_suspend(void *ol_sc,
656 struct hif_pm_runtime_lock *lock);
657int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
658 struct hif_pm_runtime_lock *lock, unsigned int delay);
659#else
660struct hif_pm_runtime_lock {
661 const char *name;
662};
Houston Hoffmanf4607852015-12-17 17:14:40 -0800663
664static inline void hif_pm_runtime_get_noresume(void *hif_ctx)
665{}
666
Houston Hoffman9078a152015-11-02 16:15:02 -0800667static inline int hif_pm_runtime_get(void *hif_ctx)
668{ return 0; }
669static inline int hif_pm_runtime_put(void *hif_ctx)
670{ return 0; }
671static inline struct hif_pm_runtime_lock *hif_runtime_lock_init(
672 const char *name)
673{ return NULL; }
674static inline void hif_runtime_lock_deinit(struct hif_pm_runtime_lock *lock)
675{}
676
677static inline int hif_pm_runtime_prevent_suspend(void *ol_sc,
678 struct hif_pm_runtime_lock *lock)
679{ return 0; }
680static inline int hif_pm_runtime_allow_suspend(void *ol_sc,
681 struct hif_pm_runtime_lock *lock)
682{ return 0; }
683static inline int hif_pm_runtime_prevent_suspend_timeout(void *ol_sc,
684 struct hif_pm_runtime_lock *lock, unsigned int delay)
685{ return 0; }
686#endif
687
Houston Hoffman62aa58d2015-11-02 21:14:55 -0800688void hif_enable_power_management(void *hif_ctx);
Houston Hoffman53b34c42015-11-18 15:51:32 -0800689void hif_disable_power_management(void *hif_ctx);
Houston Hoffman78467a82016-01-05 20:08:56 -0800690
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800691void hif_vote_link_down(void);
692void hif_vote_link_up(void);
693bool hif_can_suspend_link(void);
Houston Hoffman78467a82016-01-05 20:08:56 -0800694
695int hif_bus_resume(void);
696int hif_bus_suspend(void);
Houston Hoffman692cc052015-11-10 18:42:47 -0800697
698#ifdef FEATURE_RUNTIME_PM
Houston Hoffman78467a82016-01-05 20:08:56 -0800699int hif_pre_runtime_suspend(void);
700void hif_pre_runtime_resume(void);
701int hif_runtime_suspend(void);
702int hif_runtime_resume(void);
703void hif_process_runtime_suspend_success(void);
704void hif_process_runtime_suspend_failure(void);
705void hif_process_runtime_resume_success(void);
Houston Hoffman692cc052015-11-10 18:42:47 -0800706#endif
707
Prakash Dhavalid5c9f1c2015-11-08 19:04:44 -0800708int dump_ce_register(struct ol_softc *scn);
709int ol_copy_ramdump(struct ol_softc *scn);
710void hif_pktlogmod_exit(void *hif_ctx);
711void hif_crash_shutdown(void *hif_ctx);
712#ifdef __cplusplus
713}
714#endif
715#endif /* _HIF_H_ */