blob: 72bc4719c9fc15e88401bcde9ee9627c23af7ed3 [file] [log] [blame]
Kai Chen6eca1a62017-01-12 10:17:53 -08001/*
Keyur Parekh25ee3162019-02-08 23:01:39 -08002 * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
Kai Chen6eca1a62017-01-12 10:17:53 -08003 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _HAL_API_MON_H_
20#define _HAL_API_MON_H_
21
22#include "qdf_types.h"
23#include "hal_internal.h"
Balamurugan Mahalingamd0159642018-07-11 15:02:29 +053024#include <target_type.h>
Kai Chen6eca1a62017-01-12 10:17:53 -080025
Kai Chen6eca1a62017-01-12 10:17:53 -080026#define HAL_RX_PHY_DATA_RADAR 0x01
Karunakar Dasineni40555682017-03-26 22:44:39 -070027#define HAL_SU_MU_CODING_LDPC 0x01
Kai Chen6eca1a62017-01-12 10:17:53 -080028
29#define HAL_RX_FCS_LEN (4)
30#define KEY_EXTIV 0x20
31
32#define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
33#define HAL_RX_USER_TLV32_TYPE_LSB 1
34#define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
35
36#define HAL_RX_USER_TLV32_LEN_OFFSET 0x00000000
37#define HAL_RX_USER_TLV32_LEN_LSB 10
38#define HAL_RX_USER_TLV32_LEN_MASK 0x003FFC00
39
40#define HAL_RX_USER_TLV32_USERID_OFFSET 0x00000000
41#define HAL_RX_USER_TLV32_USERID_LSB 26
42#define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
43
44#define HAL_ALIGN(x, a) HAL_ALIGN_MASK(x, (a)-1)
45#define HAL_ALIGN_MASK(x, mask) (typeof(x))(((uint32)(x) + (mask)) & ~(mask))
46
47#define HAL_RX_TLV32_HDR_SIZE 4
48
49#define HAL_RX_GET_USER_TLV32_TYPE(rx_status_tlv_ptr) \
50 ((*((uint32_t *)(rx_status_tlv_ptr)) & \
51 HAL_RX_USER_TLV32_TYPE_MASK) >> \
52 HAL_RX_USER_TLV32_TYPE_LSB)
53
54#define HAL_RX_GET_USER_TLV32_LEN(rx_status_tlv_ptr) \
55 ((*((uint32_t *)(rx_status_tlv_ptr)) & \
56 HAL_RX_USER_TLV32_LEN_MASK) >> \
57 HAL_RX_USER_TLV32_LEN_LSB)
58
59#define HAL_RX_GET_USER_TLV32_USERID(rx_status_tlv_ptr) \
60 ((*((uint32_t *)(rx_status_tlv_ptr)) & \
61 HAL_RX_USER_TLV32_USERID_MASK) >> \
62 HAL_RX_USER_TLV32_USERID_LSB)
63
Kai Chen52ef33f2019-03-05 18:33:40 -080064#define HAL_TLV_STATUS_PPDU_NOT_DONE 0
65#define HAL_TLV_STATUS_PPDU_DONE 1
66#define HAL_TLV_STATUS_BUF_DONE 2
67#define HAL_TLV_STATUS_PPDU_NON_STD_DONE 3
68#define HAL_TLV_STATUS_PPDU_START 4
69#define HAL_TLV_STATUS_HEADER 5
70#define HAL_TLV_STATUS_MPDU_END 6
71#define HAL_TLV_STATUS_MSDU_START 7
72#define HAL_TLV_STATUS_MSDU_END 8
Kai Chen6eca1a62017-01-12 10:17:53 -080073
Kai Chene0dd94d2019-06-07 13:10:49 -070074#define HAL_MAX_UL_MU_USERS 37
Kai Chen6eca1a62017-01-12 10:17:53 -080075
Karunakar Dasineni40555682017-03-26 22:44:39 -070076#define HAL_RX_PKT_TYPE_11A 0
77#define HAL_RX_PKT_TYPE_11B 1
78#define HAL_RX_PKT_TYPE_11N 2
79#define HAL_RX_PKT_TYPE_11AC 3
80#define HAL_RX_PKT_TYPE_11AX 4
81
82#define HAL_RX_RECEPTION_TYPE_SU 0
83#define HAL_RX_RECEPTION_TYPE_MU_MIMO 1
84#define HAL_RX_RECEPTION_TYPE_OFDMA 2
85#define HAL_RX_RECEPTION_TYPE_MU_OFDMA 3
86
sumedh baikady2a19fe42017-12-19 10:44:17 -080087/* Multiply rate by 2 to avoid float point
88 * and get rate in units of 500kbps
89 */
90#define HAL_11B_RATE_0MCS 11*2
91#define HAL_11B_RATE_1MCS 5.5*2
92#define HAL_11B_RATE_2MCS 2*2
93#define HAL_11B_RATE_3MCS 1*2
94#define HAL_11B_RATE_4MCS 11*2
95#define HAL_11B_RATE_5MCS 5.5*2
96#define HAL_11B_RATE_6MCS 2*2
sumedh baikady86a83e82017-08-25 16:56:31 -070097
sumedh baikady2a19fe42017-12-19 10:44:17 -080098#define HAL_11A_RATE_0MCS 48*2
99#define HAL_11A_RATE_1MCS 24*2
100#define HAL_11A_RATE_2MCS 12*2
101#define HAL_11A_RATE_3MCS 6*2
102#define HAL_11A_RATE_4MCS 54*2
103#define HAL_11A_RATE_5MCS 36*2
104#define HAL_11A_RATE_6MCS 18*2
105#define HAL_11A_RATE_7MCS 9*2
sumedh baikady86a83e82017-08-25 16:56:31 -0700106
Keyur Parekh76eadf42018-08-23 12:00:20 -0700107#define HAL_LEGACY_MCS0 0
108#define HAL_LEGACY_MCS1 1
109#define HAL_LEGACY_MCS2 2
110#define HAL_LEGACY_MCS3 3
111#define HAL_LEGACY_MCS4 4
112#define HAL_LEGACY_MCS5 5
113#define HAL_LEGACY_MCS6 6
114#define HAL_LEGACY_MCS7 7
115
sumedh baikadyf7bbb352017-11-06 16:24:13 -0800116#define HE_GI_0_8 0
Keyur Parekh25ee3162019-02-08 23:01:39 -0800117#define HE_GI_0_4 1
118#define HE_GI_1_6 2
119#define HE_GI_3_2 3
sumedh baikadyf7bbb352017-11-06 16:24:13 -0800120
sumedh baikady710c2522018-02-15 12:56:45 -0800121#define HT_SGI_PRESENT 0x80
122
Keyur Parekh44d8f8f2019-03-12 12:39:41 -0700123#define HE_LTF_1_X 0
124#define HE_LTF_2_X 1
125#define HE_LTF_4_X 2
126#define HE_LTF_UNKNOWN 3
Keyur Parekh5929a9f2017-12-20 17:55:26 -0800127#define VHT_SIG_SU_NSS_MASK 0x7
Keyur Parekhf72cbe52018-11-15 15:56:07 -0800128#define HT_SIG_SU_NSS_SHIFT 0x3
Anish Nataraj28490c42018-01-19 19:34:54 +0530129
130#define HAL_TID_INVALID 31
131#define HAL_AST_IDX_INVALID 0xFFFF
132
Keyur Parekh4d36b322018-01-18 14:30:15 -0800133#ifdef GET_MSDU_AGGREGATION
134#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)\
135{\
136 struct rx_msdu_end *rx_msdu_end;\
137 bool first_msdu, last_msdu; \
138 rx_msdu_end = &rx_desc->msdu_end_tlv.rx_msdu_end;\
139 first_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, FIRST_MSDU);\
140 last_msdu = HAL_RX_GET(rx_msdu_end, RX_MSDU_END_5, LAST_MSDU);\
141 if (first_msdu && last_msdu)\
142 rs->rs_flags &= (~IEEE80211_AMSDU_FLAG);\
143 else\
144 rs->rs_flags |= (IEEE80211_AMSDU_FLAG); \
145} \
146
147#else
148#define HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs)
149#endif
150
Amir Patel57e7e052019-05-15 20:49:57 +0530151/* Max MPDUs per status buffer */
Chaithanya Garrepalli1f89b972019-07-31 12:33:53 +0530152#define HAL_RX_MAX_MPDU 256
153#define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP (HAL_RX_MAX_MPDU >> 5)
Amir Patel57e7e052019-05-15 20:49:57 +0530154
Amir Patel5a8bbbe2019-07-17 21:59:39 +0530155/* Max pilot count */
156#define HAL_RX_MAX_SU_EVM_COUNT 32
157
158/*
159 * Struct hal_rx_su_evm_info - SU evm info
160 * @number_of_symbols: number of symbols
161 * @nss_count: nss count
162 * @pilot_count: pilot count
163 * @pilot_evm: Array of pilot evm values
164 */
165struct hal_rx_su_evm_info {
166 uint32_t number_of_symbols;
167 uint8_t nss_count;
168 uint8_t pilot_count;
169 uint32_t pilot_evm[HAL_RX_MAX_SU_EVM_COUNT];
170};
171
Kai Chen6eca1a62017-01-12 10:17:53 -0800172enum {
Kai Chen6eca1a62017-01-12 10:17:53 -0800173 DP_PPDU_STATUS_START,
174 DP_PPDU_STATUS_DONE,
175};
176
177static inline
178uint32_t HAL_RX_MON_HW_RX_DESC_SIZE(void)
179{
180 /* return the HW_RX_DESC size */
181 return sizeof(struct rx_pkt_tlvs);
182}
183
184static inline
185uint8_t *HAL_RX_MON_DEST_GET_DESC(uint8_t *data)
186{
187 return data;
188}
189
190static inline
191uint32_t HAL_RX_DESC_GET_MPDU_LENGTH_ERR(void *hw_desc_addr)
192{
193 struct rx_attention *rx_attn;
194 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
195
196 rx_attn = &rx_desc->attn_tlv.rx_attn;
197
198 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
199}
200
201static inline
202uint32_t HAL_RX_DESC_GET_MPDU_FCS_ERR(void *hw_desc_addr)
203{
204 struct rx_attention *rx_attn;
205 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
206
207 rx_attn = &rx_desc->attn_tlv.rx_attn;
208
209 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
210}
211
Kai Chen339b01d2018-07-22 11:34:13 -0700212/*
213 * HAL_RX_HW_DESC_MPDU_VALID() - check MPDU start TLV tag in MPDU
214 * start TLV of Hardware TLV descriptor
215 * @hw_desc_addr: Hardware desciptor address
216 *
217 * Return: bool: if TLV tag match
218 */
219static inline
220bool HAL_RX_HW_DESC_MPDU_VALID(void *hw_desc_addr)
221{
222 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
223 uint32_t tlv_tag;
224
225 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(
226 &rx_desc->mpdu_start_tlv);
227
228 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
229}
230
Kai Chen6eca1a62017-01-12 10:17:53 -0800231static inline
Tallapragada Kalyan70539512018-03-29 16:19:43 +0530232uint32_t HAL_RX_HW_DESC_GET_PPDUID_GET(void *hw_desc_addr)
Kai Chen6eca1a62017-01-12 10:17:53 -0800233{
Kai Chen634d53f2017-07-15 18:49:02 -0700234 struct rx_mpdu_info *rx_mpdu_info;
Kai Chen6eca1a62017-01-12 10:17:53 -0800235 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
236
Kai Chen634d53f2017-07-15 18:49:02 -0700237 rx_mpdu_info =
238 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
Kai Chen6eca1a62017-01-12 10:17:53 -0800239
Kai Chen634d53f2017-07-15 18:49:02 -0700240 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
Kai Chen6eca1a62017-01-12 10:17:53 -0800241}
242
Karunakar Dasineni40555682017-03-26 22:44:39 -0700243/* TODO: Move all Rx descriptor functions to hal_rx.h to avoid duplication */
Karunakar Dasineni40555682017-03-26 22:44:39 -0700244
Kai Chen6eca1a62017-01-12 10:17:53 -0800245#define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
246 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
247 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
248 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
249 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
250
251#define HAL_RX_REO_ENT_BUFFER_ADDR_39_32_GET(reo_ent_desc) \
252 (HAL_RX_BUFFER_ADDR_39_32_GET(& \
253 (((struct reo_entrance_ring *)reo_ent_desc) \
254 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
255
256#define HAL_RX_REO_ENT_BUFFER_ADDR_31_0_GET(reo_ent_desc) \
257 (HAL_RX_BUFFER_ADDR_31_0_GET(& \
258 (((struct reo_entrance_ring *)reo_ent_desc) \
259 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
260
261#define HAL_RX_REO_ENT_BUF_COOKIE_GET(reo_ent_desc) \
262 (HAL_RX_BUF_COOKIE_GET(& \
263 (((struct reo_entrance_ring *)reo_ent_desc) \
264 ->reo_level_mpdu_frame_info.msdu_link_desc_addr_info)))
265
266/**
267 * hal_rx_reo_ent_buf_paddr_get: Gets the physical address and
268 * cookie from the REO entrance ring element
269 *
270 * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
271 * the current descriptor
272 * @ buf_info: structure to return the buffer information
273 * @ msdu_cnt: pointer to msdu count in MPDU
274 * Return: void
275 */
276static inline
Akshay Kosigi8eda31c2019-07-10 14:42:42 +0530277void hal_rx_reo_ent_buf_paddr_get(hal_rxdma_desc_t rx_desc,
Akshay Kosigi91c56522019-07-02 11:49:39 +0530278 struct hal_buf_info *buf_info,
279 void **pp_buf_addr_info,
280 uint32_t *msdu_cnt
Kai Chen6eca1a62017-01-12 10:17:53 -0800281)
282{
283 struct reo_entrance_ring *reo_ent_ring =
284 (struct reo_entrance_ring *)rx_desc;
285 struct buffer_addr_info *buf_addr_info;
286 struct rx_mpdu_desc_info *rx_mpdu_desc_info_details;
287 uint32_t loop_cnt;
288
289 rx_mpdu_desc_info_details =
290 &reo_ent_ring->reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
291
292 *msdu_cnt = HAL_RX_GET(rx_mpdu_desc_info_details,
293 RX_MPDU_DESC_INFO_0, MSDU_COUNT);
294
295 loop_cnt = HAL_RX_GET(reo_ent_ring, REO_ENTRANCE_RING_7, LOOPING_COUNT);
296
297 buf_addr_info =
298 &reo_ent_ring->reo_level_mpdu_frame_info.msdu_link_desc_addr_info;
299
300 buf_info->paddr =
301 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
302 ((uint64_t)
303 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
304
305 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
306
307 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
Aditya Sathishded018e2018-07-02 16:25:21 +0530308 "[%s][%d] ReoAddr=%pK, addrInfo=%pK, paddr=0x%llx, loopcnt=%d",
Kai Chen6eca1a62017-01-12 10:17:53 -0800309 __func__, __LINE__, reo_ent_ring, buf_addr_info,
310 (unsigned long long)buf_info->paddr, loop_cnt);
311
312 *pp_buf_addr_info = (void *)buf_addr_info;
313}
314
315static inline
316void hal_rx_mon_next_link_desc_get(void *rx_msdu_link_desc,
317 struct hal_buf_info *buf_info, void **pp_buf_addr_info)
318{
319 struct rx_msdu_link *msdu_link =
320 (struct rx_msdu_link *)rx_msdu_link_desc;
321 struct buffer_addr_info *buf_addr_info;
322
323 buf_addr_info = &msdu_link->next_msdu_link_desc_addr_info;
324
325 buf_info->paddr =
326 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
327 ((uint64_t)
328 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
329
330 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info);
331
332 *pp_buf_addr_info = (void *)buf_addr_info;
333}
334
335/**
336 * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
337 *
338 * @ soc : HAL version of the SOC pointer
339 * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
340 * @ buf_addr_info : void pointer to the buffer_addr_info
341 *
342 * Return: void
343 */
344
Akshay Kosigia870c612019-07-08 23:10:30 +0530345static inline
346void hal_rx_mon_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
347 void *src_srng_desc,
348 void *buf_addr_info)
Kai Chen6eca1a62017-01-12 10:17:53 -0800349{
350 struct buffer_addr_info *wbm_srng_buffer_addr_info =
351 (struct buffer_addr_info *)src_srng_desc;
352 uint64_t paddr;
353 struct buffer_addr_info *p_buffer_addr_info =
354 (struct buffer_addr_info *)buf_addr_info;
355
356 paddr =
357 (HAL_RX_BUFFER_ADDR_31_0_GET(buf_addr_info) |
358 ((uint64_t)
359 (HAL_RX_BUFFER_ADDR_39_32_GET(buf_addr_info)) << 32));
360
361 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
Aditya Sathishded018e2018-07-02 16:25:21 +0530362 "[%s][%d] src_srng_desc=%pK, buf_addr=0x%llx, cookie=0x%llx",
Kai Chen6eca1a62017-01-12 10:17:53 -0800363 __func__, __LINE__, src_srng_desc, (unsigned long long)paddr,
364 (unsigned long long)p_buffer_addr_info->sw_buffer_cookie);
365
366 /* Structure copy !!! */
367 *wbm_srng_buffer_addr_info =
368 *((struct buffer_addr_info *)buf_addr_info);
369}
370
371static inline
372uint32 hal_get_rx_msdu_link_desc_size(void)
373{
374 return sizeof(struct rx_msdu_link);
375}
376
377enum {
378 HAL_PKT_TYPE_OFDM = 0,
Karunakar Dasineni40555682017-03-26 22:44:39 -0700379 HAL_PKT_TYPE_CCK,
Kai Chen6eca1a62017-01-12 10:17:53 -0800380 HAL_PKT_TYPE_HT,
381 HAL_PKT_TYPE_VHT,
382 HAL_PKT_TYPE_HE,
383};
384
385enum {
386 HAL_SGI_0_8_US,
387 HAL_SGI_0_4_US,
388 HAL_SGI_1_6_US,
389 HAL_SGI_3_2_US,
390};
391
392enum {
393 HAL_FULL_RX_BW_20,
394 HAL_FULL_RX_BW_40,
395 HAL_FULL_RX_BW_80,
396 HAL_FULL_RX_BW_160,
397};
398
399enum {
400 HAL_RX_TYPE_SU,
401 HAL_RX_TYPE_MU_MIMO,
402 HAL_RX_TYPE_MU_OFDMA,
403 HAL_RX_TYPE_MU_OFDMA_MIMO,
404};
405
Karunakar Dasineni40555682017-03-26 22:44:39 -0700406/**
Kai Chen783e0382018-01-25 16:29:08 -0800407 * enum
408 * @HAL_RX_MON_PPDU_START: PPDU start TLV is decoded in HAL
409 * @HAL_RX_MON_PPDU_END: PPDU end TLV is decided in HAL
410 */
411enum {
412 HAL_RX_MON_PPDU_START = 0,
413 HAL_RX_MON_PPDU_END,
414};
415
nobelj14531642019-06-25 17:41:55 -0700416/* struct hal_rx_ppdu_common_info - common ppdu info
417 * @ppdu_id - ppdu id number
418 * @ppdu_timestamp - timestamp at ppdu received
419 * @mpdu_cnt_fcs_ok - mpdu count in ppdu with fcs ok
420 * @mpdu_cnt_fcs_err - mpdu count in ppdu with fcs err
421 * @mpdu_fcs_ok_bitmap - fcs ok mpdu count in ppdu bitmap
422 * @last_ppdu_id - last received ppdu id
423 * @mpdu_cnt - total mpdu count
424 * @num_users - num users
425 */
Kai Chen6eca1a62017-01-12 10:17:53 -0800426struct hal_rx_ppdu_common_info {
427 uint32_t ppdu_id;
428 uint32_t ppdu_timestamp;
Pranita Solankeed0aba62018-01-12 19:14:31 +0530429 uint32_t mpdu_cnt_fcs_ok;
430 uint32_t mpdu_cnt_fcs_err;
Chaithanya Garrepalli1f89b972019-07-31 12:33:53 +0530431 uint32_t mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
Amir Patel57e7e052019-05-15 20:49:57 +0530432 uint32_t last_ppdu_id;
433 uint32_t mpdu_cnt;
Kai Chen93f7e1b2019-07-10 16:13:48 -0700434 uint8_t num_users;
Kai Chen6eca1a62017-01-12 10:17:53 -0800435};
436
Amir Patel57e7e052019-05-15 20:49:57 +0530437/**
438 * struct hal_rx_msdu_payload_info - msdu payload info
439 * @first_msdu_payload: pointer to first msdu payload
440 * @payload_len: payload len
441 * @nbuf: status network buffer to which msdu belongs to
442 */
Soumya Bhatdc8aca82018-03-13 14:10:24 +0530443struct hal_rx_msdu_payload_info {
444 uint8_t *first_msdu_payload;
445 uint32_t payload_len;
Amir Patel57e7e052019-05-15 20:49:57 +0530446 qdf_nbuf_t nbuf;
Soumya Bhatdc8aca82018-03-13 14:10:24 +0530447};
448
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530449/**
450 * struct hal_rx_nac_info - struct for neighbour info
451 * @fc_valid: flag indicate if it has valid frame control information
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700452 * @frame_control: frame control from each MPDU
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530453 * @to_ds_flag: flag indicate to_ds bit
454 * @mac_addr2_valid: flag indicate if mac_addr2 is valid
455 * @mac_addr2: mac address2 in wh
nobelj14531642019-06-25 17:41:55 -0700456 * @mcast_bcast: multicast/broadcast
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530457 */
458struct hal_rx_nac_info {
459 uint8_t fc_valid;
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700460 uint16_t frame_control;
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530461 uint8_t to_ds_flag;
462 uint8_t mac_addr2_valid;
Srinivas Girigowda2751b6d2019-02-27 12:28:13 -0800463 uint8_t mac_addr2[QDF_MAC_ADDR_SIZE];
nobelj14531642019-06-25 17:41:55 -0700464 uint8_t mcast_bcast;
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530465};
466
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700467/**
468 * struct hal_rx_ppdu_msdu_info - struct for msdu info from HW TLVs
Sumeet Raoc4fa4df2019-07-05 02:11:19 -0700469 * @cce_metadata: cached CCE metadata value received in the MSDU_END TLV
470 * @is_flow_idx_timeout: flag to indicate if flow search timeout occurred
471 * @is_flow_idx_invalid: flag to indicate if flow idx is valid or not
472 * @fse_metadata: cached FSE metadata value received in the MSDU END TLV
473 * @flow_idx: flow idx matched in FSE received in the MSDU END TLV
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700474 */
475struct hal_rx_ppdu_msdu_info {
476 uint16_t cce_metadata;
Sumeet Raoc4fa4df2019-07-05 02:11:19 -0700477 bool is_flow_idx_timeout;
478 bool is_flow_idx_invalid;
479 uint32_t fse_metadata;
480 uint32_t flow_idx;
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700481};
482
Kai Chen6eca1a62017-01-12 10:17:53 -0800483struct hal_rx_ppdu_info {
484 struct hal_rx_ppdu_common_info com_info;
Karunakar Dasineni40555682017-03-26 22:44:39 -0700485 struct mon_rx_status rx_status;
Kai Chen52ef33f2019-03-05 18:33:40 -0800486 struct mon_rx_user_status rx_user_status[HAL_MAX_UL_MU_USERS];
Soumya Bhatdc8aca82018-03-13 14:10:24 +0530487 struct hal_rx_msdu_payload_info msdu_info;
Amir Patel57e7e052019-05-15 20:49:57 +0530488 struct hal_rx_msdu_payload_info fcs_ok_msdu_info;
Chaithanya Garrepalli95fc62f2018-07-24 18:52:27 +0530489 struct hal_rx_nac_info nac_info;
Kai Chen783e0382018-01-25 16:29:08 -0800490 /* status ring PPDU start and end state */
491 uint32_t rx_state;
Kai Chen52ef33f2019-03-05 18:33:40 -0800492 /* MU user id for status ring TLV */
493 uint32_t user_id;
494 /* MPDU/MSDU truncated to 128 bytes header start addr in status skb */
495 unsigned char *data;
496 /* MPDU/MSDU truncated to 128 bytes header real length */
497 uint32_t hdr_len;
498 /* MPDU FCS error */
499 bool fcs_err;
Karunakar Dasineniacc8b562019-05-07 07:00:24 -0700500 struct hal_rx_ppdu_msdu_info rx_msdu_info[HAL_MAX_UL_MU_USERS];
Amir Patel57e7e052019-05-15 20:49:57 +0530501 /* first msdu payload for all mpdus in ppdu */
502 struct hal_rx_msdu_payload_info ppdu_msdu_info[HAL_RX_MAX_MPDU];
Amir Patel5a8bbbe2019-07-17 21:59:39 +0530503 /* evm info */
504 struct hal_rx_su_evm_info evm_info;
Kai Chen6eca1a62017-01-12 10:17:53 -0800505};
506
507static inline uint32_t
508hal_get_rx_status_buf_size(void) {
509 /* RX status buffer size is hard coded for now */
510 return 2048;
511}
512
513static inline uint8_t*
514hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
Karunakar Dasineni40555682017-03-26 22:44:39 -0700515 uint32_t tlv_len, tlv_tag;
Kai Chen6eca1a62017-01-12 10:17:53 -0800516
517 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
Karunakar Dasineni40555682017-03-26 22:44:39 -0700518 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
519
Jeff Johnsondc9c5592018-05-06 15:40:42 -0700520 /* The actual length of PPDU_END is the combined length of many PHY
Karunakar Dasineni40555682017-03-26 22:44:39 -0700521 * TLVs that follow. Skip the TLV header and
522 * rx_rxpcu_classification_overview that follows the header to get to
523 * next TLV.
524 */
525 if (tlv_tag == WIFIRX_PPDU_END_E)
526 tlv_len = sizeof(struct rx_rxpcu_classification_overview);
Kai Chen6eca1a62017-01-12 10:17:53 -0800527
528 return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
529 HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
530}
531
Balamurugan Mahalingam5d806412018-07-30 18:04:15 +0530532/**
533 * hal_rx_proc_phyrx_other_receive_info_tlv()
534 * - process other receive info TLV
535 * @rx_tlv_hdr: pointer to TLV header
536 * @ppdu_info: pointer to ppdu_info
537 *
538 * Return: None
539 */
540static inline void hal_rx_proc_phyrx_other_receive_info_tlv(struct hal_soc *hal_soc,
Balamurugan Mahalingamd0159642018-07-11 15:02:29 +0530541 void *rx_tlv_hdr,
542 struct hal_rx_ppdu_info
543 *ppdu_info)
Mohit Khanna6c22db32018-03-19 21:47:51 -0700544{
Balamurugan Mahalingamd0159642018-07-11 15:02:29 +0530545 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv(rx_tlv_hdr,
546 (void *)ppdu_info);
Mohit Khanna6c22db32018-03-19 21:47:51 -0700547}
Mohit Khanna6c22db32018-03-19 21:47:51 -0700548
549/**
550 * hal_rx_status_get_tlv_info() - process receive info TLV
551 * @rx_tlv_hdr: pointer to TLV header
552 * @ppdu_info: pointer to ppdu_info
Amir Patel57e7e052019-05-15 20:49:57 +0530553 * @hal_soc: HAL soc handle
554 * @nbuf: PPDU status netowrk buffer
Mohit Khanna6c22db32018-03-19 21:47:51 -0700555 *
556 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv
557 */
Kai Chen6eca1a62017-01-12 10:17:53 -0800558static inline uint32_t
Balamurugan Mahalingam5d806412018-07-30 18:04:15 +0530559hal_rx_status_get_tlv_info(void *rx_tlv_hdr, void *ppdu_info,
Akshay Kosigi6a206752019-06-10 23:14:52 +0530560 hal_soc_handle_t hal_soc_hdl,
Amir Patel57e7e052019-05-15 20:49:57 +0530561 qdf_nbuf_t nbuf)
Kai Chen6eca1a62017-01-12 10:17:53 -0800562{
Akshay Kosigi6a206752019-06-10 23:14:52 +0530563 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
564
565 return hal_soc->ops->hal_rx_status_get_tlv_info(
566 rx_tlv_hdr,
567 ppdu_info,
568 hal_soc_hdl,
569 nbuf);
Kai Chen6eca1a62017-01-12 10:17:53 -0800570}
571
572static inline
Akshay Kosigi8eda31c2019-07-10 14:42:42 +0530573uint32_t hal_get_rx_status_done_tlv_size(hal_soc_handle_t hal_soc_hdl)
Kai Chen6eca1a62017-01-12 10:17:53 -0800574{
575 return HAL_RX_TLV32_HDR_SIZE;
576}
577
578static inline QDF_STATUS
579hal_get_rx_status_done(uint8_t *rx_tlv)
580{
581 uint32_t tlv_tag;
582
583 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
584
585 if (tlv_tag == WIFIRX_STATUS_BUFFER_DONE_E)
586 return QDF_STATUS_SUCCESS;
587 else
588 return QDF_STATUS_E_EMPTY;
589}
590
591static inline QDF_STATUS
592hal_clear_rx_status_done(uint8_t *rx_tlv)
593{
594 *(uint32_t *)rx_tlv = 0;
595 return QDF_STATUS_SUCCESS;
596}
597
598#endif