Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 1 | /* |
Mohit Khanna | d31b666 | 2019-02-01 11:58:55 -0800 | [diff] [blame] | 2 | * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for |
| 5 | * any purpose with or without fee is hereby granted, provided that the |
| 6 | * above copyright notice and this permission notice appear in all |
| 7 | * copies. |
| 8 | * |
| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 10 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 11 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 12 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 13 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 14 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 15 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 16 | * PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 19 | /** |
| 20 | * hal_setup_link_idle_list - Setup scattered idle list using the |
| 21 | * buffer list provided |
| 22 | * |
| 23 | * @hal_soc: Opaque HAL SOC handle |
| 24 | * @scatter_bufs_base_paddr: Array of physical base addresses |
| 25 | * @scatter_bufs_base_vaddr: Array of virtual base addresses |
| 26 | * @num_scatter_bufs: Number of scatter buffers in the above lists |
| 27 | * @scatter_buf_size: Size of each scatter buffer |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 28 | * @last_buf_end_offset: Offset to the last entry |
| 29 | * @num_entries: Total entries of all scatter bufs |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 30 | * |
| 31 | */ |
Akshay Kosigi | 8eda31c | 2019-07-10 14:42:42 +0530 | [diff] [blame] | 32 | static void |
| 33 | hal_setup_link_idle_list_generic(struct hal_soc *soc, |
| 34 | qdf_dma_addr_t scatter_bufs_base_paddr[], |
| 35 | void *scatter_bufs_base_vaddr[], |
| 36 | uint32_t num_scatter_bufs, |
| 37 | uint32_t scatter_buf_size, |
| 38 | uint32_t last_buf_end_offset, |
| 39 | uint32_t num_entries) |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 40 | { |
| 41 | int i; |
| 42 | uint32_t *prev_buf_link_ptr = NULL; |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 43 | uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; |
Mohit Khanna | d31b666 | 2019-02-01 11:58:55 -0800 | [diff] [blame] | 44 | uint32_t val; |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 45 | |
| 46 | /* Link the scatter buffers */ |
| 47 | for (i = 0; i < num_scatter_bufs; i++) { |
| 48 | if (i > 0) { |
| 49 | prev_buf_link_ptr[0] = |
| 50 | scatter_bufs_base_paddr[i] & 0xffffffff; |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 51 | prev_buf_link_ptr[1] = HAL_SM( |
| 52 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, |
| 53 | BASE_ADDRESS_39_32, |
| 54 | ((uint64_t)(scatter_bufs_base_paddr[i]) |
| 55 | >> 32)) | HAL_SM( |
| 56 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, |
| 57 | ADDRESS_MATCH_TAG, |
| 58 | ADDRESS_MATCH_TAG_VAL); |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 59 | } |
| 60 | prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + |
| 61 | scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); |
| 62 | } |
| 63 | |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 64 | /* TBD: Register programming partly based on MLD & the rest based on |
| 65 | * inputs from HW team. Not complete yet. |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 66 | */ |
| 67 | |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 68 | reg_scatter_buf_size = (scatter_buf_size - |
| 69 | WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE)/64; |
| 70 | reg_tot_scatter_buf_size = ((scatter_buf_size - |
| 71 | WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs)/64; |
| 72 | |
| 73 | HAL_REG_WRITE(soc, |
| 74 | HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( |
| 75 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 76 | HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, |
| 77 | reg_scatter_buf_size) | |
| 78 | HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, |
| 79 | 0x1)); |
| 80 | |
| 81 | HAL_REG_WRITE(soc, |
| 82 | HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( |
| 83 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 84 | HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, |
| 85 | SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, |
| 86 | reg_tot_scatter_buf_size)); |
| 87 | |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 88 | HAL_REG_WRITE(soc, |
| 89 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( |
| 90 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 91 | scatter_bufs_base_paddr[0] & 0xffffffff); |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 92 | |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 93 | HAL_REG_WRITE(soc, |
| 94 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( |
| 95 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 96 | ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & |
| 97 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 98 | |
| 99 | HAL_REG_WRITE(soc, |
| 100 | HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( |
| 101 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 102 | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, |
| 103 | BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) |
| 104 | >> 32)) | |
| 105 | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, |
| 106 | ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); |
| 107 | |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 108 | /* ADDRESS_MATCH_TAG field in the above register is expected to match |
| 109 | * with the upper bits of link pointer. The above write sets this field |
| 110 | * to zero and we are also setting the upper bits of link pointers to |
| 111 | * zero while setting up the link list of scatter buffers above |
| 112 | */ |
| 113 | |
| 114 | /* Setup head and tail pointers for the idle list */ |
| 115 | HAL_REG_WRITE(soc, |
| 116 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( |
| 117 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 118 | scatter_bufs_base_paddr[num_scatter_bufs-1] & 0xffffffff); |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 119 | HAL_REG_WRITE(soc, |
| 120 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( |
| 121 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 122 | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, |
| 123 | BUFFER_ADDRESS_39_32, |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 124 | ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs-1]) |
| 125 | >> 32)) | |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 126 | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 127 | HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 128 | |
| 129 | HAL_REG_WRITE(soc, |
| 130 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( |
| 131 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 132 | scatter_bufs_base_paddr[0] & 0xffffffff); |
| 133 | |
| 134 | HAL_REG_WRITE(soc, |
| 135 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( |
| 136 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 137 | scatter_bufs_base_paddr[0] & 0xffffffff); |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 138 | HAL_REG_WRITE(soc, |
| 139 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( |
| 140 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 141 | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, |
| 142 | BUFFER_ADDRESS_39_32, |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 143 | ((uint64_t)(scatter_bufs_base_paddr[0]) >> |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 144 | 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 145 | TAIL_POINTER_OFFSET, 0)); |
| 146 | |
| 147 | HAL_REG_WRITE(soc, |
| 148 | HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( |
| 149 | SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 150 | 2*num_entries); |
| 151 | |
Mohit Khanna | d31b666 | 2019-02-01 11:58:55 -0800 | [diff] [blame] | 152 | /* Set RING_ID_DISABLE */ |
| 153 | val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); |
| 154 | |
| 155 | /* |
| 156 | * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence |
| 157 | * check the presence of the bit before toggling it. |
| 158 | */ |
| 159 | #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK |
| 160 | val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); |
| 161 | #endif |
Pramod Simha | ccb15fb | 2017-06-19 12:21:13 -0700 | [diff] [blame] | 162 | HAL_REG_WRITE(soc, |
Mohit Khanna | d31b666 | 2019-02-01 11:58:55 -0800 | [diff] [blame] | 163 | HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| 164 | val); |
Karunakar Dasineni | 9b814ce | 2016-09-01 15:00:09 -0700 | [diff] [blame] | 165 | } |