Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1 | /* |
Prashanth Bhatta | dfcae6b | 2015-12-04 11:56:47 -0800 | [diff] [blame] | 2 | * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 27 | #include "targcfg.h" |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 28 | #include "qdf_lock.h" |
| 29 | #include "qdf_status.h" |
| 30 | #include "qdf_status.h" |
| 31 | #include <qdf_atomic.h> /* qdf_atomic_read */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 32 | #include <targaddrs.h> |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 33 | #include "hif_io32.h" |
| 34 | #include <hif.h> |
| 35 | #include "regtable.h" |
| 36 | #define ATH_MODULE_NAME hif |
| 37 | #include <a_debug.h> |
| 38 | #include "hif_main.h" |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 39 | #include "ce_api.h" |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 40 | #include "qdf_trace.h" |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 41 | #ifdef CONFIG_CNSS |
| 42 | #include <net/cnss.h> |
| 43 | #endif |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 44 | #include "hif_debug.h" |
| 45 | #include "ce_internal.h" |
| 46 | #include "ce_reg.h" |
| 47 | #include "ce_assignment.h" |
| 48 | #include "ce_tasklet.h" |
Houston Hoffman | bc69349 | 2016-03-14 21:11:41 -0700 | [diff] [blame] | 49 | #include "platform_icnss.h" |
Houston Hoffman | 56e0d70 | 2016-05-05 17:48:06 -0700 | [diff] [blame] | 50 | #ifndef CONFIG_WIN |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 51 | #include "qwlan_version.h" |
Houston Hoffman | 56e0d70 | 2016-05-05 17:48:06 -0700 | [diff] [blame] | 52 | #endif |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 53 | |
| 54 | #define CE_POLL_TIMEOUT 10 /* ms */ |
| 55 | |
| 56 | /* Forward references */ |
| 57 | static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info); |
| 58 | |
| 59 | /* |
| 60 | * Fix EV118783, poll to check whether a BMI response comes |
| 61 | * other than waiting for the interruption which may be lost. |
| 62 | */ |
| 63 | /* #define BMI_RSP_POLLING */ |
| 64 | #define BMI_RSP_TO_MILLISEC 1000 |
| 65 | |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 66 | #ifdef CONFIG_BYPASS_QMI |
| 67 | #define BYPASS_QMI 1 |
| 68 | #else |
| 69 | #define BYPASS_QMI 0 |
| 70 | #endif |
| 71 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 72 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 73 | static int hif_post_recv_buffers(struct hif_softc *scn); |
| 74 | static void hif_config_rri_on_ddr(struct hif_softc *scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 75 | |
| 76 | static void ce_poll_timeout(void *arg) |
| 77 | { |
| 78 | struct CE_state *CE_state = (struct CE_state *)arg; |
| 79 | if (CE_state->timer_inited) { |
| 80 | ce_per_engine_service(CE_state->scn, CE_state->id); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 81 | qdf_timer_mod(&CE_state->poll_timer, CE_POLL_TIMEOUT); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 82 | } |
| 83 | } |
| 84 | |
| 85 | static unsigned int roundup_pwr2(unsigned int n) |
| 86 | { |
| 87 | int i; |
| 88 | unsigned int test_pwr2; |
| 89 | |
| 90 | if (!(n & (n - 1))) |
| 91 | return n; /* already a power of 2 */ |
| 92 | |
| 93 | test_pwr2 = 4; |
| 94 | for (i = 0; i < 29; i++) { |
| 95 | if (test_pwr2 > n) |
| 96 | return test_pwr2; |
| 97 | test_pwr2 = test_pwr2 << 1; |
| 98 | } |
| 99 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 100 | QDF_ASSERT(0); /* n too large */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 101 | return 0; |
| 102 | } |
| 103 | |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 104 | #define ADRASTEA_SRC_WR_INDEX_OFFSET 0x3C |
| 105 | #define ADRASTEA_DST_WR_INDEX_OFFSET 0x40 |
| 106 | |
| 107 | static struct shadow_reg_cfg target_shadow_reg_cfg_map[] = { |
| 108 | { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 109 | { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 110 | { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 111 | { 5, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 112 | { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 113 | { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 114 | { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 115 | { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 116 | { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 117 | #ifdef QCA_WIFI_3_0_ADRASTEA |
| 118 | { 9, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 119 | { 10, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 120 | #endif |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 121 | }; |
| 122 | |
Vishwajith Upendra | 70efc75 | 2016-04-18 11:23:49 -0700 | [diff] [blame] | 123 | static struct shadow_reg_cfg target_shadow_reg_cfg_epping[] = { |
| 124 | { 0, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 125 | { 3, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 126 | { 4, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 127 | { 7, ADRASTEA_SRC_WR_INDEX_OFFSET}, |
| 128 | { 1, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 129 | { 2, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 130 | { 5, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 131 | { 7, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 132 | { 8, ADRASTEA_DST_WR_INDEX_OFFSET}, |
| 133 | }; |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 134 | |
| 135 | /* CE_PCI TABLE */ |
| 136 | /* |
| 137 | * NOTE: the table below is out of date, though still a useful reference. |
| 138 | * Refer to target_service_to_ce_map and hif_map_service_to_pipe for the actual |
| 139 | * mapping of HTC services to HIF pipes. |
| 140 | */ |
| 141 | /* |
| 142 | * This authoritative table defines Copy Engine configuration and the mapping |
| 143 | * of services/endpoints to CEs. A subset of this information is passed to |
| 144 | * the Target during startup as a prerequisite to entering BMI phase. |
| 145 | * See: |
| 146 | * target_service_to_ce_map - Target-side mapping |
| 147 | * hif_map_service_to_pipe - Host-side mapping |
| 148 | * target_ce_config - Target-side configuration |
| 149 | * host_ce_config - Host-side configuration |
| 150 | ============================================================================ |
| 151 | Purpose | Service / Endpoint | CE | Dire | Xfer | Xfer |
| 152 | | | | ctio | Size | Frequency |
| 153 | | | | n | | |
| 154 | ============================================================================ |
| 155 | tx | HTT_DATA (downlink) | CE 0 | h->t | medium - | very frequent |
| 156 | descriptor | | | | O(100B) | and regular |
| 157 | download | | | | | |
| 158 | ---------------------------------------------------------------------------- |
| 159 | rx | HTT_DATA (uplink) | CE 1 | t->h | small - | frequent and |
| 160 | indication | | | | O(10B) | regular |
| 161 | upload | | | | | |
| 162 | ---------------------------------------------------------------------------- |
| 163 | MSDU | DATA_BK (uplink) | CE 2 | t->h | large - | rare |
| 164 | upload | | | | O(1000B) | (frequent |
| 165 | e.g. noise | | | | | during IP1.0 |
| 166 | packets | | | | | testing) |
| 167 | ---------------------------------------------------------------------------- |
| 168 | MSDU | DATA_BK (downlink) | CE 3 | h->t | large - | very rare |
| 169 | download | | | | O(1000B) | (frequent |
| 170 | e.g. | | | | | during IP1.0 |
| 171 | misdirecte | | | | | testing) |
| 172 | d EAPOL | | | | | |
| 173 | packets | | | | | |
| 174 | ---------------------------------------------------------------------------- |
| 175 | n/a | DATA_BE, DATA_VI | CE 2 | t->h | | never(?) |
| 176 | | DATA_VO (uplink) | | | | |
| 177 | ---------------------------------------------------------------------------- |
| 178 | n/a | DATA_BE, DATA_VI | CE 3 | h->t | | never(?) |
| 179 | | DATA_VO (downlink) | | | | |
| 180 | ---------------------------------------------------------------------------- |
| 181 | WMI events | WMI_CONTROL (uplink) | CE 4 | t->h | medium - | infrequent |
| 182 | | | | | O(100B) | |
| 183 | ---------------------------------------------------------------------------- |
| 184 | WMI | WMI_CONTROL | CE 5 | h->t | medium - | infrequent |
| 185 | messages | (downlink) | | | O(100B) | |
| 186 | | | | | | |
| 187 | ---------------------------------------------------------------------------- |
| 188 | n/a | HTC_CTRL_RSVD, | CE 1 | t->h | | never(?) |
| 189 | | HTC_RAW_STREAMS | | | | |
| 190 | | (uplink) | | | | |
| 191 | ---------------------------------------------------------------------------- |
| 192 | n/a | HTC_CTRL_RSVD, | CE 0 | h->t | | never(?) |
| 193 | | HTC_RAW_STREAMS | | | | |
| 194 | | (downlink) | | | | |
| 195 | ---------------------------------------------------------------------------- |
| 196 | diag | none (raw CE) | CE 7 | t<>h | 4 | Diag Window |
| 197 | | | | | | infrequent |
| 198 | ============================================================================ |
| 199 | */ |
| 200 | |
| 201 | /* |
| 202 | * Map from service/endpoint to Copy Engine. |
| 203 | * This table is derived from the CE_PCI TABLE, above. |
| 204 | * It is passed to the Target at startup for use by firmware. |
| 205 | */ |
| 206 | static struct service_to_pipe target_service_to_ce_map_wlan[] = { |
| 207 | { |
| 208 | WMI_DATA_VO_SVC, |
| 209 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 210 | 3, |
| 211 | }, |
| 212 | { |
| 213 | WMI_DATA_VO_SVC, |
| 214 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 215 | 2, |
| 216 | }, |
| 217 | { |
| 218 | WMI_DATA_BK_SVC, |
| 219 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 220 | 3, |
| 221 | }, |
| 222 | { |
| 223 | WMI_DATA_BK_SVC, |
| 224 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 225 | 2, |
| 226 | }, |
| 227 | { |
| 228 | WMI_DATA_BE_SVC, |
| 229 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 230 | 3, |
| 231 | }, |
| 232 | { |
| 233 | WMI_DATA_BE_SVC, |
| 234 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 235 | 2, |
| 236 | }, |
| 237 | { |
| 238 | WMI_DATA_VI_SVC, |
| 239 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 240 | 3, |
| 241 | }, |
| 242 | { |
| 243 | WMI_DATA_VI_SVC, |
| 244 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 245 | 2, |
| 246 | }, |
| 247 | { |
| 248 | WMI_CONTROL_SVC, |
| 249 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 250 | 3, |
| 251 | }, |
| 252 | { |
| 253 | WMI_CONTROL_SVC, |
| 254 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 255 | 2, |
| 256 | }, |
| 257 | { |
| 258 | HTC_CTRL_RSVD_SVC, |
| 259 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 260 | 0, /* could be moved to 3 (share with WMI) */ |
| 261 | }, |
| 262 | { |
| 263 | HTC_CTRL_RSVD_SVC, |
| 264 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 265 | 2, |
| 266 | }, |
| 267 | { |
| 268 | HTC_RAW_STREAMS_SVC, /* not currently used */ |
| 269 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 270 | 0, |
| 271 | }, |
| 272 | { |
| 273 | HTC_RAW_STREAMS_SVC, /* not currently used */ |
| 274 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 275 | 2, |
| 276 | }, |
| 277 | { |
| 278 | HTT_DATA_MSG_SVC, |
| 279 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 280 | 4, |
| 281 | }, |
| 282 | { |
| 283 | HTT_DATA_MSG_SVC, |
| 284 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 285 | 1, |
| 286 | }, |
| 287 | { |
| 288 | WDI_IPA_TX_SVC, |
| 289 | PIPEDIR_OUT, /* in = DL = target -> host */ |
| 290 | 5, |
| 291 | }, |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 292 | #if defined(QCA_WIFI_3_0_ADRASTEA) |
| 293 | { |
| 294 | HTT_DATA2_MSG_SVC, |
| 295 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 296 | 9, |
| 297 | }, |
| 298 | { |
| 299 | HTT_DATA3_MSG_SVC, |
| 300 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 301 | 10, |
| 302 | }, |
| 303 | #endif |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 304 | /* (Additions here) */ |
| 305 | |
| 306 | { /* Must be last */ |
| 307 | 0, |
| 308 | 0, |
| 309 | 0, |
| 310 | }, |
| 311 | }; |
| 312 | |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 313 | static struct service_to_pipe target_service_to_ce_map_ar900b[] = { |
| 314 | { |
| 315 | WMI_DATA_VO_SVC, |
| 316 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 317 | 3, |
| 318 | }, |
| 319 | { |
| 320 | WMI_DATA_VO_SVC, |
| 321 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 322 | 2, |
| 323 | }, |
| 324 | { |
| 325 | WMI_DATA_BK_SVC, |
| 326 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 327 | 3, |
| 328 | }, |
| 329 | { |
| 330 | WMI_DATA_BK_SVC, |
| 331 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 332 | 2, |
| 333 | }, |
| 334 | { |
| 335 | WMI_DATA_BE_SVC, |
| 336 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 337 | 3, |
| 338 | }, |
| 339 | { |
| 340 | WMI_DATA_BE_SVC, |
| 341 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 342 | 2, |
| 343 | }, |
| 344 | { |
| 345 | WMI_DATA_VI_SVC, |
| 346 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 347 | 3, |
| 348 | }, |
| 349 | { |
| 350 | WMI_DATA_VI_SVC, |
| 351 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 352 | 2, |
| 353 | }, |
| 354 | { |
| 355 | WMI_CONTROL_SVC, |
| 356 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 357 | 3, |
| 358 | }, |
| 359 | { |
| 360 | WMI_CONTROL_SVC, |
| 361 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 362 | 2, |
| 363 | }, |
| 364 | { |
| 365 | HTC_CTRL_RSVD_SVC, |
| 366 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 367 | 0, /* could be moved to 3 (share with WMI) */ |
| 368 | }, |
| 369 | { |
| 370 | HTC_CTRL_RSVD_SVC, |
| 371 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 372 | 1, |
| 373 | }, |
| 374 | { |
| 375 | HTC_RAW_STREAMS_SVC, /* not currently used */ |
| 376 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 377 | 0, |
| 378 | }, |
| 379 | { |
| 380 | HTC_RAW_STREAMS_SVC, /* not currently used */ |
| 381 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 382 | 1, |
| 383 | }, |
| 384 | { |
| 385 | HTT_DATA_MSG_SVC, |
| 386 | PIPEDIR_OUT, /* out = UL = host -> target */ |
| 387 | 4, |
| 388 | }, |
| 389 | #if WLAN_FEATURE_FASTPATH |
| 390 | { |
| 391 | HTT_DATA_MSG_SVC, |
| 392 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 393 | 5, |
| 394 | }, |
| 395 | #else /* WLAN_FEATURE_FASTPATH */ |
| 396 | { |
| 397 | HTT_DATA_MSG_SVC, |
| 398 | PIPEDIR_IN, /* in = DL = target -> host */ |
| 399 | 1, |
| 400 | }, |
| 401 | #endif /* WLAN_FEATURE_FASTPATH */ |
| 402 | |
| 403 | /* (Additions here) */ |
| 404 | |
| 405 | { /* Must be last */ |
| 406 | 0, |
| 407 | 0, |
| 408 | 0, |
| 409 | }, |
| 410 | }; |
| 411 | |
| 412 | |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 413 | static struct service_to_pipe *target_service_to_ce_map = |
| 414 | target_service_to_ce_map_wlan; |
| 415 | static int target_service_to_ce_map_sz = sizeof(target_service_to_ce_map_wlan); |
| 416 | |
| 417 | static struct shadow_reg_cfg *target_shadow_reg_cfg = target_shadow_reg_cfg_map; |
| 418 | static int shadow_cfg_sz = sizeof(target_shadow_reg_cfg_map); |
| 419 | |
| 420 | static struct service_to_pipe target_service_to_ce_map_wlan_epping[] = { |
| 421 | {WMI_DATA_VO_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ |
| 422 | {WMI_DATA_VO_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 423 | {WMI_DATA_BK_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ |
| 424 | {WMI_DATA_BK_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ |
| 425 | {WMI_DATA_BE_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ |
| 426 | {WMI_DATA_BE_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 427 | {WMI_DATA_VI_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ |
| 428 | {WMI_DATA_VI_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 429 | {WMI_CONTROL_SVC, PIPEDIR_OUT, 3,}, /* out = UL = host -> target */ |
| 430 | {WMI_CONTROL_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 431 | {HTC_CTRL_RSVD_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ |
| 432 | {HTC_CTRL_RSVD_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 433 | {HTC_RAW_STREAMS_SVC, PIPEDIR_OUT, 0,}, /* out = UL = host -> target */ |
| 434 | {HTC_RAW_STREAMS_SVC, PIPEDIR_IN, 2,}, /* in = DL = target -> host */ |
| 435 | {HTT_DATA_MSG_SVC, PIPEDIR_OUT, 4,}, /* out = UL = host -> target */ |
| 436 | {HTT_DATA_MSG_SVC, PIPEDIR_IN, 1,}, /* in = DL = target -> host */ |
| 437 | {0, 0, 0,}, /* Must be last */ |
| 438 | }; |
| 439 | |
| 440 | /** |
| 441 | * ce_mark_datapath() - marks the ce_state->htt_rx_data accordingly |
| 442 | * @ce_state : pointer to the state context of the CE |
| 443 | * |
| 444 | * Description: |
| 445 | * Sets htt_rx_data attribute of the state structure if the |
| 446 | * CE serves one of the HTT DATA services. |
| 447 | * |
| 448 | * Return: |
| 449 | * false (attribute set to false) |
| 450 | * true (attribute set to true); |
| 451 | */ |
| 452 | bool ce_mark_datapath(struct CE_state *ce_state) |
| 453 | { |
| 454 | struct service_to_pipe *svc_map; |
| 455 | size_t map_sz; |
| 456 | int i; |
| 457 | bool rc = false; |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 458 | struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(ce_state->scn); |
| 459 | struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 460 | |
| 461 | if (ce_state != NULL) { |
Houston Hoffman | 75ef5a5 | 2016-04-14 17:15:49 -0700 | [diff] [blame] | 462 | if (QDF_IS_EPPING_ENABLED(hif_get_conparam(ce_state->scn))) { |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 463 | svc_map = target_service_to_ce_map_wlan_epping; |
| 464 | map_sz = sizeof(target_service_to_ce_map_wlan_epping) / |
| 465 | sizeof(struct service_to_pipe); |
| 466 | } else { |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 467 | switch (tgt_info->target_type) { |
| 468 | default: |
| 469 | svc_map = target_service_to_ce_map_wlan; |
| 470 | map_sz = |
| 471 | sizeof(target_service_to_ce_map_wlan) / |
| 472 | sizeof(struct service_to_pipe); |
| 473 | break; |
| 474 | case TARGET_TYPE_AR900B: |
| 475 | case TARGET_TYPE_QCA9984: |
| 476 | case TARGET_TYPE_IPQ4019: |
| 477 | case TARGET_TYPE_QCA9888: |
| 478 | case TARGET_TYPE_AR9888: |
| 479 | case TARGET_TYPE_AR9888V2: |
| 480 | svc_map = target_service_to_ce_map_ar900b; |
| 481 | map_sz = |
| 482 | sizeof(target_service_to_ce_map_ar900b) |
| 483 | / sizeof(struct service_to_pipe); |
| 484 | break; |
| 485 | } |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 486 | } |
| 487 | for (i = 0; i < map_sz; i++) { |
| 488 | if ((svc_map[i].pipenum == ce_state->id) && |
| 489 | ((svc_map[i].service_id == HTT_DATA_MSG_SVC) || |
| 490 | (svc_map[i].service_id == HTT_DATA2_MSG_SVC) || |
| 491 | (svc_map[i].service_id == HTT_DATA3_MSG_SVC))) { |
| 492 | /* HTT CEs are unidirectional */ |
| 493 | if (svc_map[i].pipedir == PIPEDIR_IN) |
| 494 | ce_state->htt_rx_data = true; |
| 495 | else |
| 496 | ce_state->htt_tx_data = true; |
| 497 | rc = true; |
| 498 | } |
| 499 | } |
| 500 | } |
| 501 | return rc; |
| 502 | } |
| 503 | |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 504 | /** |
| 505 | * ce_ring_test_initial_indexes() - tests the initial ce ring indexes |
| 506 | * @ce_id: ce in question |
| 507 | * @ring: ring state being examined |
| 508 | * @type: "src_ring" or "dest_ring" string for identifying the ring |
| 509 | * |
| 510 | * Warns on non-zero index values. |
| 511 | * Causes a kernel panic if the ring is not empty durring initialization. |
| 512 | */ |
| 513 | static void ce_ring_test_initial_indexes(int ce_id, struct CE_ring_state *ring, |
| 514 | char *type) |
| 515 | { |
| 516 | if (ring->write_index != 0 || ring->sw_index != 0) |
| 517 | HIF_ERROR("ce %d, %s, initial sw_index = %d, initial write_index =%d", |
| 518 | ce_id, type, ring->sw_index, ring->write_index); |
| 519 | if (ring->write_index != ring->sw_index) |
| 520 | QDF_BUG(0); |
| 521 | } |
| 522 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 523 | /* |
| 524 | * Initialize a Copy Engine based on caller-supplied attributes. |
| 525 | * This may be called once to initialize both source and destination |
| 526 | * rings or it may be called twice for separate source and destination |
| 527 | * initialization. It may be that only one side or the other is |
| 528 | * initialized by software/firmware. |
Houston Hoffman | 233e909 | 2015-09-02 13:37:21 -0700 | [diff] [blame] | 529 | * |
| 530 | * This should be called durring the initialization sequence before |
| 531 | * interupts are enabled, so we don't have to worry about thread safety. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 532 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 533 | struct CE_handle *ce_init(struct hif_softc *scn, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 534 | unsigned int CE_id, struct CE_attr *attr) |
| 535 | { |
| 536 | struct CE_state *CE_state; |
| 537 | uint32_t ctrl_addr; |
| 538 | unsigned int nentries; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 539 | qdf_dma_addr_t base_addr; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 540 | bool malloc_CE_state = false; |
| 541 | bool malloc_src_ring = false; |
| 542 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 543 | QDF_ASSERT(CE_id < scn->ce_count); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 544 | ctrl_addr = CE_BASE_ADDRESS(CE_id); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 545 | CE_state = scn->ce_id_to_state[CE_id]; |
| 546 | |
| 547 | if (!CE_state) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 548 | CE_state = |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 549 | (struct CE_state *)qdf_mem_malloc(sizeof(*CE_state)); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 550 | if (!CE_state) { |
| 551 | HIF_ERROR("%s: CE_state has no mem", __func__); |
| 552 | return NULL; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 553 | } |
Houston Hoffman | 233e909 | 2015-09-02 13:37:21 -0700 | [diff] [blame] | 554 | malloc_CE_state = true; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 555 | qdf_mem_zero(CE_state, sizeof(*CE_state)); |
Houston Hoffman | 233e909 | 2015-09-02 13:37:21 -0700 | [diff] [blame] | 556 | scn->ce_id_to_state[CE_id] = CE_state; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 557 | qdf_spinlock_create(&CE_state->ce_index_lock); |
Houston Hoffman | 233e909 | 2015-09-02 13:37:21 -0700 | [diff] [blame] | 558 | |
| 559 | CE_state->id = CE_id; |
| 560 | CE_state->ctrl_addr = ctrl_addr; |
| 561 | CE_state->state = CE_RUNNING; |
| 562 | CE_state->attr_flags = attr->flags; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 563 | } |
| 564 | CE_state->scn = scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 565 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 566 | qdf_atomic_init(&CE_state->rx_pending); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 567 | if (attr == NULL) { |
| 568 | /* Already initialized; caller wants the handle */ |
| 569 | return (struct CE_handle *)CE_state; |
| 570 | } |
| 571 | |
| 572 | #ifdef ADRASTEA_SHADOW_REGISTERS |
| 573 | HIF_ERROR("%s: Using Shadow Registers instead of CE Registers\n", |
| 574 | __func__); |
| 575 | #endif |
| 576 | |
| 577 | if (CE_state->src_sz_max) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 578 | QDF_ASSERT(CE_state->src_sz_max == attr->src_sz_max); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 579 | else |
| 580 | CE_state->src_sz_max = attr->src_sz_max; |
| 581 | |
Houston Hoffman | 68e837e | 2015-12-04 12:57:24 -0800 | [diff] [blame] | 582 | ce_init_ce_desc_event_log(CE_id, |
| 583 | attr->src_nentries + attr->dest_nentries); |
| 584 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 585 | /* source ring setup */ |
| 586 | nentries = attr->src_nentries; |
| 587 | if (nentries) { |
| 588 | struct CE_ring_state *src_ring; |
| 589 | unsigned CE_nbytes; |
| 590 | char *ptr; |
| 591 | uint64_t dma_addr; |
| 592 | nentries = roundup_pwr2(nentries); |
| 593 | if (CE_state->src_ring) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 594 | QDF_ASSERT(CE_state->src_ring->nentries == nentries); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 595 | } else { |
| 596 | CE_nbytes = sizeof(struct CE_ring_state) |
| 597 | + (nentries * sizeof(void *)); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 598 | ptr = qdf_mem_malloc(CE_nbytes); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 599 | if (!ptr) { |
| 600 | /* cannot allocate src ring. If the |
| 601 | * CE_state is allocated locally free |
| 602 | * CE_State and return error. |
| 603 | */ |
| 604 | HIF_ERROR("%s: src ring has no mem", __func__); |
| 605 | if (malloc_CE_state) { |
| 606 | /* allocated CE_state locally */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 607 | scn->ce_id_to_state[CE_id] = NULL; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 608 | qdf_mem_free(CE_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 609 | malloc_CE_state = false; |
| 610 | } |
| 611 | return NULL; |
| 612 | } else { |
| 613 | /* we can allocate src ring. |
| 614 | * Mark that the src ring is |
| 615 | * allocated locally |
| 616 | */ |
| 617 | malloc_src_ring = true; |
| 618 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 619 | qdf_mem_zero(ptr, CE_nbytes); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 620 | |
| 621 | src_ring = CE_state->src_ring = |
| 622 | (struct CE_ring_state *)ptr; |
| 623 | ptr += sizeof(struct CE_ring_state); |
| 624 | src_ring->nentries = nentries; |
| 625 | src_ring->nentries_mask = nentries - 1; |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 626 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 627 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 628 | src_ring->hw_index = |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 629 | CE_SRC_RING_READ_IDX_GET_FROM_REGISTER(scn, |
| 630 | ctrl_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 631 | src_ring->sw_index = src_ring->hw_index; |
| 632 | src_ring->write_index = |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 633 | CE_SRC_RING_WRITE_IDX_GET_FROM_REGISTER(scn, |
| 634 | ctrl_addr); |
| 635 | |
| 636 | ce_ring_test_initial_indexes(CE_id, src_ring, |
| 637 | "src_ring"); |
| 638 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 639 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 640 | goto error_target_access; |
| 641 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 642 | src_ring->low_water_mark_nentries = 0; |
| 643 | src_ring->high_water_mark_nentries = nentries; |
| 644 | src_ring->per_transfer_context = (void **)ptr; |
| 645 | |
| 646 | /* Legacy platforms that do not support cache |
| 647 | * coherent DMA are unsupported |
| 648 | */ |
| 649 | src_ring->base_addr_owner_space_unaligned = |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 650 | qdf_mem_alloc_consistent(scn->qdf_dev, |
| 651 | scn->qdf_dev->dev, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 652 | (nentries * |
| 653 | sizeof(struct CE_src_desc) + |
| 654 | CE_DESC_RING_ALIGN), |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 655 | &base_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 656 | if (src_ring->base_addr_owner_space_unaligned |
| 657 | == NULL) { |
| 658 | HIF_ERROR("%s: src ring has no DMA mem", |
| 659 | __func__); |
| 660 | goto error_no_dma_mem; |
| 661 | } |
| 662 | src_ring->base_addr_CE_space_unaligned = base_addr; |
| 663 | |
| 664 | if (src_ring-> |
| 665 | base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN |
| 666 | - 1)) { |
| 667 | src_ring->base_addr_CE_space = |
| 668 | (src_ring->base_addr_CE_space_unaligned |
| 669 | + CE_DESC_RING_ALIGN - |
| 670 | 1) & ~(CE_DESC_RING_ALIGN - 1); |
| 671 | |
| 672 | src_ring->base_addr_owner_space = |
| 673 | (void |
| 674 | *)(((size_t) src_ring-> |
| 675 | base_addr_owner_space_unaligned + |
| 676 | CE_DESC_RING_ALIGN - |
| 677 | 1) & ~(CE_DESC_RING_ALIGN - 1)); |
| 678 | } else { |
| 679 | src_ring->base_addr_CE_space = |
| 680 | src_ring->base_addr_CE_space_unaligned; |
| 681 | src_ring->base_addr_owner_space = |
| 682 | src_ring-> |
| 683 | base_addr_owner_space_unaligned; |
| 684 | } |
| 685 | /* |
| 686 | * Also allocate a shadow src ring in |
| 687 | * regular mem to use for faster access. |
| 688 | */ |
| 689 | src_ring->shadow_base_unaligned = |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 690 | qdf_mem_malloc(nentries * |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 691 | sizeof(struct CE_src_desc) + |
| 692 | CE_DESC_RING_ALIGN); |
| 693 | if (src_ring->shadow_base_unaligned == NULL) { |
| 694 | HIF_ERROR("%s: src ring no shadow_base mem", |
| 695 | __func__); |
| 696 | goto error_no_dma_mem; |
| 697 | } |
| 698 | src_ring->shadow_base = (struct CE_src_desc *) |
| 699 | (((size_t) src_ring->shadow_base_unaligned + |
| 700 | CE_DESC_RING_ALIGN - 1) & |
| 701 | ~(CE_DESC_RING_ALIGN - 1)); |
| 702 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 703 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 704 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 705 | dma_addr = src_ring->base_addr_CE_space; |
| 706 | CE_SRC_RING_BASE_ADDR_SET(scn, ctrl_addr, |
| 707 | (uint32_t)(dma_addr & 0xFFFFFFFF)); |
Houston Hoffman | f789c66 | 2016-04-12 15:39:04 -0700 | [diff] [blame] | 708 | |
| 709 | /* if SR_BA_ADDRESS_HIGH register exists */ |
| 710 | if (SR_BA_ADDRESS_HIGH) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 711 | uint32_t tmp; |
| 712 | tmp = CE_SRC_RING_BASE_ADDR_HIGH_GET( |
| 713 | scn, ctrl_addr); |
| 714 | tmp &= ~0x1F; |
| 715 | dma_addr = ((dma_addr >> 32) & 0x1F)|tmp; |
| 716 | CE_SRC_RING_BASE_ADDR_HIGH_SET(scn, |
| 717 | ctrl_addr, (uint32_t)dma_addr); |
| 718 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 719 | CE_SRC_RING_SZ_SET(scn, ctrl_addr, nentries); |
| 720 | CE_SRC_RING_DMAX_SET(scn, ctrl_addr, attr->src_sz_max); |
| 721 | #ifdef BIG_ENDIAN_HOST |
| 722 | /* Enable source ring byte swap for big endian host */ |
| 723 | CE_SRC_RING_BYTE_SWAP_SET(scn, ctrl_addr, 1); |
| 724 | #endif |
| 725 | CE_SRC_RING_LOWMARK_SET(scn, ctrl_addr, 0); |
| 726 | CE_SRC_RING_HIGHMARK_SET(scn, ctrl_addr, nentries); |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 727 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 728 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 729 | } |
| 730 | } |
| 731 | |
| 732 | /* destination ring setup */ |
| 733 | nentries = attr->dest_nentries; |
| 734 | if (nentries) { |
| 735 | struct CE_ring_state *dest_ring; |
| 736 | unsigned CE_nbytes; |
| 737 | char *ptr; |
| 738 | uint64_t dma_addr; |
| 739 | |
| 740 | nentries = roundup_pwr2(nentries); |
| 741 | if (CE_state->dest_ring) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 742 | QDF_ASSERT(CE_state->dest_ring->nentries == nentries); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 743 | } else { |
| 744 | CE_nbytes = sizeof(struct CE_ring_state) |
| 745 | + (nentries * sizeof(void *)); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 746 | ptr = qdf_mem_malloc(CE_nbytes); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 747 | if (!ptr) { |
| 748 | /* cannot allocate dst ring. If the CE_state |
| 749 | * or src ring is allocated locally free |
| 750 | * CE_State and src ring and return error. |
| 751 | */ |
| 752 | HIF_ERROR("%s: dest ring has no mem", |
| 753 | __func__); |
| 754 | if (malloc_src_ring) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 755 | qdf_mem_free(CE_state->src_ring); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 756 | CE_state->src_ring = NULL; |
| 757 | malloc_src_ring = false; |
| 758 | } |
| 759 | if (malloc_CE_state) { |
| 760 | /* allocated CE_state locally */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 761 | scn->ce_id_to_state[CE_id] = NULL; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 762 | qdf_mem_free(CE_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 763 | malloc_CE_state = false; |
| 764 | } |
| 765 | return NULL; |
| 766 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 767 | qdf_mem_zero(ptr, CE_nbytes); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 768 | |
| 769 | dest_ring = CE_state->dest_ring = |
| 770 | (struct CE_ring_state *)ptr; |
| 771 | ptr += sizeof(struct CE_ring_state); |
| 772 | dest_ring->nentries = nentries; |
| 773 | dest_ring->nentries_mask = nentries - 1; |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 774 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 775 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 776 | dest_ring->sw_index = |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 777 | CE_DEST_RING_READ_IDX_GET_FROM_REGISTER(scn, |
| 778 | ctrl_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 779 | dest_ring->write_index = |
Houston Hoffman | 4780817 | 2016-05-06 10:04:21 -0700 | [diff] [blame] | 780 | CE_DEST_RING_WRITE_IDX_GET_FROM_REGISTER(scn, |
| 781 | ctrl_addr); |
| 782 | |
| 783 | ce_ring_test_initial_indexes(CE_id, dest_ring, |
| 784 | "dest_ring"); |
| 785 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 786 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 787 | goto error_target_access; |
| 788 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 789 | dest_ring->low_water_mark_nentries = 0; |
| 790 | dest_ring->high_water_mark_nentries = nentries; |
| 791 | dest_ring->per_transfer_context = (void **)ptr; |
| 792 | |
| 793 | /* Legacy platforms that do not support cache |
| 794 | * coherent DMA are unsupported */ |
| 795 | dest_ring->base_addr_owner_space_unaligned = |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 796 | qdf_mem_alloc_consistent(scn->qdf_dev, |
| 797 | scn->qdf_dev->dev, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 798 | (nentries * |
| 799 | sizeof(struct CE_dest_desc) + |
| 800 | CE_DESC_RING_ALIGN), |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 801 | &base_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 802 | if (dest_ring->base_addr_owner_space_unaligned |
| 803 | == NULL) { |
| 804 | HIF_ERROR("%s: dest ring has no DMA mem", |
| 805 | __func__); |
| 806 | goto error_no_dma_mem; |
| 807 | } |
| 808 | dest_ring->base_addr_CE_space_unaligned = base_addr; |
| 809 | |
| 810 | /* Correctly initialize memory to 0 to |
| 811 | * prevent garbage data crashing system |
| 812 | * when download firmware |
| 813 | */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 814 | qdf_mem_zero(dest_ring->base_addr_owner_space_unaligned, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 815 | nentries * sizeof(struct CE_dest_desc) + |
| 816 | CE_DESC_RING_ALIGN); |
| 817 | |
| 818 | if (dest_ring-> |
| 819 | base_addr_CE_space_unaligned & (CE_DESC_RING_ALIGN - |
| 820 | 1)) { |
| 821 | |
| 822 | dest_ring->base_addr_CE_space = |
| 823 | (dest_ring-> |
| 824 | base_addr_CE_space_unaligned + |
| 825 | CE_DESC_RING_ALIGN - |
| 826 | 1) & ~(CE_DESC_RING_ALIGN - 1); |
| 827 | |
| 828 | dest_ring->base_addr_owner_space = |
| 829 | (void |
| 830 | *)(((size_t) dest_ring-> |
| 831 | base_addr_owner_space_unaligned + |
| 832 | CE_DESC_RING_ALIGN - |
| 833 | 1) & ~(CE_DESC_RING_ALIGN - 1)); |
| 834 | } else { |
| 835 | dest_ring->base_addr_CE_space = |
| 836 | dest_ring->base_addr_CE_space_unaligned; |
| 837 | dest_ring->base_addr_owner_space = |
| 838 | dest_ring-> |
| 839 | base_addr_owner_space_unaligned; |
| 840 | } |
| 841 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 842 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 843 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 844 | dma_addr = dest_ring->base_addr_CE_space; |
| 845 | CE_DEST_RING_BASE_ADDR_SET(scn, ctrl_addr, |
| 846 | (uint32_t)(dma_addr & 0xFFFFFFFF)); |
Houston Hoffman | f789c66 | 2016-04-12 15:39:04 -0700 | [diff] [blame] | 847 | |
| 848 | /* if DR_BA_ADDRESS_HIGH exists */ |
| 849 | if (DR_BA_ADDRESS_HIGH) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 850 | uint32_t tmp; |
| 851 | tmp = CE_DEST_RING_BASE_ADDR_HIGH_GET(scn, |
| 852 | ctrl_addr); |
| 853 | tmp &= ~0x1F; |
| 854 | dma_addr = ((dma_addr >> 32) & 0x1F)|tmp; |
| 855 | CE_DEST_RING_BASE_ADDR_HIGH_SET(scn, |
| 856 | ctrl_addr, (uint32_t)dma_addr); |
| 857 | } |
Houston Hoffman | f789c66 | 2016-04-12 15:39:04 -0700 | [diff] [blame] | 858 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 859 | CE_DEST_RING_SZ_SET(scn, ctrl_addr, nentries); |
| 860 | #ifdef BIG_ENDIAN_HOST |
| 861 | /* Enable Dest ring byte swap for big endian host */ |
| 862 | CE_DEST_RING_BYTE_SWAP_SET(scn, ctrl_addr, 1); |
| 863 | #endif |
| 864 | CE_DEST_RING_LOWMARK_SET(scn, ctrl_addr, 0); |
| 865 | CE_DEST_RING_HIGHMARK_SET(scn, ctrl_addr, nentries); |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 866 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 867 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 868 | |
| 869 | /* epping */ |
| 870 | /* poll timer */ |
| 871 | if ((CE_state->attr_flags & CE_ATTR_ENABLE_POLL)) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 872 | qdf_timer_init(scn->qdf_dev, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 873 | &CE_state->poll_timer, |
| 874 | ce_poll_timeout, |
| 875 | CE_state, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 876 | QDF_TIMER_TYPE_SW); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 877 | CE_state->timer_inited = true; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 878 | qdf_timer_mod(&CE_state->poll_timer, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 879 | CE_POLL_TIMEOUT); |
| 880 | } |
| 881 | } |
| 882 | } |
| 883 | |
| 884 | /* Enable CE error interrupts */ |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 885 | if (Q_TARGET_ACCESS_BEGIN(scn) < 0) |
| 886 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 887 | CE_ERROR_INTR_ENABLE(scn, ctrl_addr); |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 888 | if (Q_TARGET_ACCESS_END(scn) < 0) |
| 889 | goto error_target_access; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 890 | |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 891 | /* update the htt_data attribute */ |
| 892 | ce_mark_datapath(CE_state); |
| 893 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 894 | return (struct CE_handle *)CE_state; |
| 895 | |
Houston Hoffman | 4411ad4 | 2016-03-14 21:12:04 -0700 | [diff] [blame] | 896 | error_target_access: |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 897 | error_no_dma_mem: |
| 898 | ce_fini((struct CE_handle *)CE_state); |
| 899 | return NULL; |
| 900 | } |
| 901 | |
| 902 | #ifdef WLAN_FEATURE_FASTPATH |
| 903 | /** |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 904 | * hif_enable_fastpath() Update that we have enabled fastpath mode |
| 905 | * @hif_ctx: HIF context |
| 906 | * |
| 907 | * For use in data path |
| 908 | * |
| 909 | * Retrun: void |
| 910 | */ |
| 911 | void hif_enable_fastpath(struct hif_opaque_softc *hif_ctx) |
| 912 | { |
| 913 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
| 914 | |
| 915 | HIF_INFO("Enabling fastpath mode\n"); |
| 916 | scn->fastpath_mode_on = true; |
| 917 | } |
| 918 | |
| 919 | /** |
| 920 | * hif_is_fastpath_mode_enabled - API to query if fasthpath mode is enabled |
| 921 | * @hif_ctx: HIF Context |
| 922 | * |
| 923 | * For use in data path to skip HTC |
| 924 | * |
| 925 | * Return: bool |
| 926 | */ |
| 927 | bool hif_is_fastpath_mode_enabled(struct hif_opaque_softc *hif_ctx) |
| 928 | { |
| 929 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
| 930 | |
| 931 | return scn->fastpath_mode_on; |
| 932 | } |
| 933 | |
| 934 | /** |
| 935 | * hif_get_ce_handle - API to get CE handle for FastPath mode |
| 936 | * @hif_ctx: HIF Context |
| 937 | * @id: CopyEngine Id |
| 938 | * |
| 939 | * API to return CE handle for fastpath mode |
| 940 | * |
| 941 | * Return: void |
| 942 | */ |
| 943 | void *hif_get_ce_handle(struct hif_opaque_softc *hif_ctx, int id) |
| 944 | { |
| 945 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
| 946 | |
| 947 | return scn->ce_id_to_state[id]; |
| 948 | } |
| 949 | |
| 950 | /** |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 951 | * ce_h2t_tx_ce_cleanup() Place holder function for H2T CE cleanup. |
| 952 | * No processing is required inside this function. |
| 953 | * @ce_hdl: Cope engine handle |
| 954 | * Using an assert, this function makes sure that, |
| 955 | * the TX CE has been processed completely. |
Houston Hoffman | 9a831ef | 2015-09-03 14:42:40 -0700 | [diff] [blame] | 956 | * |
| 957 | * This is called while dismantling CE structures. No other thread |
| 958 | * should be using these structures while dismantling is occuring |
| 959 | * therfore no locking is needed. |
| 960 | * |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 961 | * Return: none |
| 962 | */ |
| 963 | void |
| 964 | ce_h2t_tx_ce_cleanup(struct CE_handle *ce_hdl) |
| 965 | { |
| 966 | struct CE_state *ce_state = (struct CE_state *)ce_hdl; |
| 967 | struct CE_ring_state *src_ring = ce_state->src_ring; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 968 | struct hif_softc *sc = ce_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 969 | uint32_t sw_index, write_index; |
| 970 | |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 971 | if (sc->fastpath_mode_on && ce_state->htt_tx_data) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 972 | HIF_INFO("%s %d Fastpath mode ON, Cleaning up HTT Tx CE\n", |
| 973 | __func__, __LINE__); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 974 | sw_index = src_ring->sw_index; |
| 975 | write_index = src_ring->sw_index; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 976 | |
| 977 | /* At this point Tx CE should be clean */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 978 | qdf_assert_always(sw_index == write_index); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 979 | } |
| 980 | } |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 981 | |
| 982 | /** |
| 983 | * ce_t2h_msg_ce_cleanup() - Cleanup buffers on the t2h datapath msg queue. |
| 984 | * @ce_hdl: Handle to CE |
| 985 | * |
| 986 | * These buffers are never allocated on the fly, but |
| 987 | * are allocated only once during HIF start and freed |
| 988 | * only once during HIF stop. |
| 989 | * NOTE: |
| 990 | * The assumption here is there is no in-flight DMA in progress |
| 991 | * currently, so that buffers can be freed up safely. |
| 992 | * |
| 993 | * Return: NONE |
| 994 | */ |
| 995 | void ce_t2h_msg_ce_cleanup(struct CE_handle *ce_hdl) |
| 996 | { |
| 997 | struct CE_state *ce_state = (struct CE_state *)ce_hdl; |
| 998 | struct CE_ring_state *dst_ring = ce_state->dest_ring; |
| 999 | qdf_nbuf_t nbuf; |
| 1000 | int i; |
| 1001 | |
| 1002 | if (!ce_state->fastpath_handler) |
| 1003 | return; |
| 1004 | /* |
| 1005 | * when fastpath_mode is on and for datapath CEs. Unlike other CE's, |
| 1006 | * this CE is completely full: does not leave one blank space, to |
| 1007 | * distinguish between empty queue & full queue. So free all the |
| 1008 | * entries. |
| 1009 | */ |
| 1010 | for (i = 0; i < dst_ring->nentries; i++) { |
| 1011 | nbuf = dst_ring->per_transfer_context[i]; |
| 1012 | |
| 1013 | /* |
| 1014 | * The reasons for doing this check are: |
| 1015 | * 1) Protect against calling cleanup before allocating buffers |
| 1016 | * 2) In a corner case, FASTPATH_mode_on may be set, but we |
| 1017 | * could have a partially filled ring, because of a memory |
| 1018 | * allocation failure in the middle of allocating ring. |
| 1019 | * This check accounts for that case, checking |
| 1020 | * fastpath_mode_on flag or started flag would not have |
| 1021 | * covered that case. This is not in performance path, |
| 1022 | * so OK to do this. |
| 1023 | */ |
| 1024 | if (nbuf) |
| 1025 | qdf_nbuf_free(nbuf); |
| 1026 | } |
| 1027 | } |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 1028 | |
| 1029 | /** |
| 1030 | * hif_update_fastpath_recv_bufs_cnt() - Increments the Rx buf count by 1 |
| 1031 | * @scn: HIF handle |
| 1032 | * |
| 1033 | * Datapath Rx CEs are special case, where we reuse all the message buffers. |
| 1034 | * Hence we have to post all the entries in the pipe, even, in the beginning |
| 1035 | * unlike for other CE pipes where one less than dest_nentries are filled in |
| 1036 | * the beginning. |
| 1037 | * |
| 1038 | * Return: None |
| 1039 | */ |
| 1040 | static void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) |
| 1041 | { |
| 1042 | int pipe_num; |
| 1043 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
| 1044 | |
| 1045 | if (scn->fastpath_mode_on == false) |
| 1046 | return; |
| 1047 | |
| 1048 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 1049 | struct HIF_CE_pipe_info *pipe_info = |
| 1050 | &hif_state->pipe_info[pipe_num]; |
| 1051 | struct CE_state *ce_state = |
| 1052 | scn->ce_id_to_state[pipe_info->pipe_num]; |
| 1053 | |
| 1054 | if (ce_state->htt_rx_data) |
| 1055 | atomic_inc(&pipe_info->recv_bufs_needed); |
| 1056 | } |
| 1057 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1058 | #else |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 1059 | static inline void hif_update_fastpath_recv_bufs_cnt(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1060 | { |
| 1061 | } |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 1062 | |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 1063 | static inline bool ce_is_fastpath_enabled(struct hif_softc *scn) |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 1064 | { |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 1065 | return false; |
| 1066 | } |
| 1067 | |
| 1068 | static inline bool ce_is_fastpath_handler_registered(struct CE_state *ce_state) |
| 1069 | { |
| 1070 | return false; |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 1071 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1072 | #endif /* WLAN_FEATURE_FASTPATH */ |
| 1073 | |
| 1074 | void ce_fini(struct CE_handle *copyeng) |
| 1075 | { |
| 1076 | struct CE_state *CE_state = (struct CE_state *)copyeng; |
| 1077 | unsigned int CE_id = CE_state->id; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1078 | struct hif_softc *scn = CE_state->scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1079 | |
| 1080 | CE_state->state = CE_UNUSED; |
| 1081 | scn->ce_id_to_state[CE_id] = NULL; |
| 1082 | if (CE_state->src_ring) { |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 1083 | /* Cleanup the datapath Tx ring */ |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1084 | ce_h2t_tx_ce_cleanup(copyeng); |
| 1085 | |
| 1086 | if (CE_state->src_ring->shadow_base_unaligned) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1087 | qdf_mem_free(CE_state->src_ring->shadow_base_unaligned); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1088 | if (CE_state->src_ring->base_addr_owner_space_unaligned) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1089 | qdf_mem_free_consistent(scn->qdf_dev, |
| 1090 | scn->qdf_dev->dev, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1091 | (CE_state->src_ring->nentries * |
| 1092 | sizeof(struct CE_src_desc) + |
| 1093 | CE_DESC_RING_ALIGN), |
| 1094 | CE_state->src_ring-> |
| 1095 | base_addr_owner_space_unaligned, |
| 1096 | CE_state->src_ring-> |
| 1097 | base_addr_CE_space, 0); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1098 | qdf_mem_free(CE_state->src_ring); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1099 | } |
| 1100 | if (CE_state->dest_ring) { |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 1101 | /* Cleanup the datapath Rx ring */ |
| 1102 | ce_t2h_msg_ce_cleanup(copyeng); |
| 1103 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1104 | if (CE_state->dest_ring->base_addr_owner_space_unaligned) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1105 | qdf_mem_free_consistent(scn->qdf_dev, |
| 1106 | scn->qdf_dev->dev, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1107 | (CE_state->dest_ring->nentries * |
| 1108 | sizeof(struct CE_dest_desc) + |
| 1109 | CE_DESC_RING_ALIGN), |
| 1110 | CE_state->dest_ring-> |
| 1111 | base_addr_owner_space_unaligned, |
| 1112 | CE_state->dest_ring-> |
| 1113 | base_addr_CE_space, 0); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1114 | qdf_mem_free(CE_state->dest_ring); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1115 | |
| 1116 | /* epping */ |
| 1117 | if (CE_state->timer_inited) { |
| 1118 | CE_state->timer_inited = false; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1119 | qdf_timer_free(&CE_state->poll_timer); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1120 | } |
| 1121 | } |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1122 | qdf_mem_free(CE_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1123 | } |
| 1124 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1125 | void hif_detach_htc(struct hif_opaque_softc *hif_ctx) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1126 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1127 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1128 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1129 | qdf_mem_zero(&hif_state->msg_callbacks_pending, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1130 | sizeof(hif_state->msg_callbacks_pending)); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1131 | qdf_mem_zero(&hif_state->msg_callbacks_current, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1132 | sizeof(hif_state->msg_callbacks_current)); |
| 1133 | } |
| 1134 | |
| 1135 | /* Send the first nbytes bytes of the buffer */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1136 | QDF_STATUS |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1137 | hif_send_head(struct hif_opaque_softc *hif_ctx, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1138 | uint8_t pipe, unsigned int transfer_id, unsigned int nbytes, |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1139 | qdf_nbuf_t nbuf, unsigned int data_attr) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1140 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1141 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1142 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1143 | struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); |
| 1144 | struct CE_handle *ce_hdl = pipe_info->ce_hdl; |
| 1145 | int bytes = nbytes, nfrags = 0; |
| 1146 | struct ce_sendlist sendlist; |
| 1147 | int status, i = 0; |
| 1148 | unsigned int mux_id = 0; |
| 1149 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1150 | QDF_ASSERT(nbytes <= qdf_nbuf_len(nbuf)); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1151 | |
| 1152 | transfer_id = |
| 1153 | (mux_id & MUX_ID_MASK) | |
| 1154 | (transfer_id & TRANSACTION_ID_MASK); |
| 1155 | data_attr &= DESC_DATA_FLAG_MASK; |
| 1156 | /* |
| 1157 | * The common case involves sending multiple fragments within a |
| 1158 | * single download (the tx descriptor and the tx frame header). |
| 1159 | * So, optimize for the case of multiple fragments by not even |
| 1160 | * checking whether it's necessary to use a sendlist. |
| 1161 | * The overhead of using a sendlist for a single buffer download |
| 1162 | * is not a big deal, since it happens rarely (for WMI messages). |
| 1163 | */ |
| 1164 | ce_sendlist_init(&sendlist); |
| 1165 | do { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1166 | qdf_dma_addr_t frag_paddr; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1167 | int frag_bytes; |
| 1168 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1169 | frag_paddr = qdf_nbuf_get_frag_paddr(nbuf, nfrags); |
| 1170 | frag_bytes = qdf_nbuf_get_frag_len(nbuf, nfrags); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1171 | /* |
| 1172 | * Clear the packet offset for all but the first CE desc. |
| 1173 | */ |
| 1174 | if (i++ > 0) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1175 | data_attr &= ~QDF_CE_TX_PKT_OFFSET_BIT_M; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1176 | |
| 1177 | status = ce_sendlist_buf_add(&sendlist, frag_paddr, |
| 1178 | frag_bytes > |
| 1179 | bytes ? bytes : frag_bytes, |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1180 | qdf_nbuf_get_frag_is_wordstream |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1181 | (nbuf, |
| 1182 | nfrags) ? 0 : |
| 1183 | CE_SEND_FLAG_SWAP_DISABLE, |
| 1184 | data_attr); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1185 | if (status != QDF_STATUS_SUCCESS) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1186 | HIF_ERROR("%s: error, frag_num %d larger than limit", |
| 1187 | __func__, nfrags); |
| 1188 | return status; |
| 1189 | } |
| 1190 | bytes -= frag_bytes; |
| 1191 | nfrags++; |
| 1192 | } while (bytes > 0); |
| 1193 | |
| 1194 | /* Make sure we have resources to handle this request */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1195 | qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1196 | if (pipe_info->num_sends_allowed < nfrags) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1197 | qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1198 | ce_pkt_error_count_incr(hif_state, HIF_PIPE_NO_RESOURCE); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1199 | return QDF_STATUS_E_RESOURCES; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1200 | } |
| 1201 | pipe_info->num_sends_allowed -= nfrags; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1202 | qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1203 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1204 | if (qdf_unlikely(ce_hdl == NULL)) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1205 | HIF_ERROR("%s: error CE handle is null", __func__); |
| 1206 | return A_ERROR; |
| 1207 | } |
| 1208 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1209 | QDF_NBUF_UPDATE_TX_PKT_COUNT(nbuf, QDF_NBUF_TX_PKT_HIF); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1210 | DPTRACE(qdf_dp_trace(nbuf, QDF_DP_TRACE_HIF_PACKET_PTR_RECORD, |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1211 | (uint8_t *)(qdf_nbuf_data(nbuf)), |
| 1212 | sizeof(qdf_nbuf_data(nbuf)))); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1213 | status = ce_sendlist_send(ce_hdl, nbuf, &sendlist, transfer_id); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1214 | QDF_ASSERT(status == QDF_STATUS_SUCCESS); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1215 | |
| 1216 | return status; |
| 1217 | } |
| 1218 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1219 | void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe, |
| 1220 | int force) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1221 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1222 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
| 1223 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1224 | if (!force) { |
| 1225 | int resources; |
| 1226 | /* |
| 1227 | * Decide whether to actually poll for completions, or just |
| 1228 | * wait for a later chance. If there seem to be plenty of |
| 1229 | * resources left, then just wait, since checking involves |
| 1230 | * reading a CE register, which is a relatively expensive |
| 1231 | * operation. |
| 1232 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1233 | resources = hif_get_free_queue_number(hif_ctx, pipe); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1234 | /* |
| 1235 | * If at least 50% of the total resources are still available, |
| 1236 | * don't bother checking again yet. |
| 1237 | */ |
| 1238 | if (resources > (host_ce_config[pipe].src_nentries >> 1)) { |
| 1239 | return; |
| 1240 | } |
| 1241 | } |
Houston Hoffman | 56e0d70 | 2016-05-05 17:48:06 -0700 | [diff] [blame] | 1242 | #if ATH_11AC_TXCOMPACT |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1243 | ce_per_engine_servicereap(scn, pipe); |
| 1244 | #else |
| 1245 | ce_per_engine_service(scn, pipe); |
| 1246 | #endif |
| 1247 | } |
| 1248 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1249 | uint16_t |
| 1250 | hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx, uint8_t pipe) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1251 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1252 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1253 | struct HIF_CE_pipe_info *pipe_info = &(hif_state->pipe_info[pipe]); |
| 1254 | uint16_t rv; |
| 1255 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1256 | qdf_spin_lock_bh(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1257 | rv = pipe_info->num_sends_allowed; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1258 | qdf_spin_unlock_bh(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1259 | return rv; |
| 1260 | } |
| 1261 | |
| 1262 | /* Called by lower (CE) layer when a send to Target completes. */ |
| 1263 | void |
| 1264 | hif_pci_ce_send_done(struct CE_handle *copyeng, void *ce_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1265 | void *transfer_context, qdf_dma_addr_t CE_data, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1266 | unsigned int nbytes, unsigned int transfer_id, |
| 1267 | unsigned int sw_index, unsigned int hw_index, |
| 1268 | unsigned int toeplitz_hash_result) |
| 1269 | { |
| 1270 | struct HIF_CE_pipe_info *pipe_info = |
| 1271 | (struct HIF_CE_pipe_info *)ce_context; |
| 1272 | struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1273 | struct hif_softc *scn = HIF_GET_SOFTC(hif_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1274 | unsigned int sw_idx = sw_index, hw_idx = hw_index; |
Houston Hoffman | 8511851 | 2015-09-28 14:17:11 -0700 | [diff] [blame] | 1275 | struct hif_msg_callbacks *msg_callbacks = |
| 1276 | &hif_state->msg_callbacks_current; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1277 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1278 | do { |
| 1279 | /* |
Houston Hoffman | 8511851 | 2015-09-28 14:17:11 -0700 | [diff] [blame] | 1280 | * The upper layer callback will be triggered |
| 1281 | * when last fragment is complteted. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1282 | */ |
Houston Hoffman | 8511851 | 2015-09-28 14:17:11 -0700 | [diff] [blame] | 1283 | if (transfer_context != CE_SENDLIST_ITEM_CTXT) { |
Komal Seelam | 6ee5590 | 2016-04-11 17:11:07 +0530 | [diff] [blame] | 1284 | if (scn->target_status == TARGET_STATUS_RESET) |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1285 | qdf_nbuf_free(transfer_context); |
Houston Hoffman | 49794a3 | 2015-12-21 12:14:56 -0800 | [diff] [blame] | 1286 | else |
| 1287 | msg_callbacks->txCompletionHandler( |
Houston Hoffman | 8511851 | 2015-09-28 14:17:11 -0700 | [diff] [blame] | 1288 | msg_callbacks->Context, |
| 1289 | transfer_context, transfer_id, |
| 1290 | toeplitz_hash_result); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1291 | } |
| 1292 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1293 | qdf_spin_lock(&pipe_info->completion_freeq_lock); |
Houston Hoffman | 8511851 | 2015-09-28 14:17:11 -0700 | [diff] [blame] | 1294 | pipe_info->num_sends_allowed++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1295 | qdf_spin_unlock(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1296 | } while (ce_completed_send_next(copyeng, |
| 1297 | &ce_context, &transfer_context, |
| 1298 | &CE_data, &nbytes, &transfer_id, |
| 1299 | &sw_idx, &hw_idx, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1300 | &toeplitz_hash_result) == QDF_STATUS_SUCCESS); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1301 | } |
| 1302 | |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1303 | /** |
| 1304 | * hif_ce_do_recv(): send message from copy engine to upper layers |
| 1305 | * @msg_callbacks: structure containing callback and callback context |
| 1306 | * @netbuff: skb containing message |
| 1307 | * @nbytes: number of bytes in the message |
| 1308 | * @pipe_info: used for the pipe_number info |
| 1309 | * |
| 1310 | * Checks the packet length, configures the lenght in the netbuff, |
| 1311 | * and calls the upper layer callback. |
| 1312 | * |
| 1313 | * return: None |
| 1314 | */ |
| 1315 | static inline void hif_ce_do_recv(struct hif_msg_callbacks *msg_callbacks, |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1316 | qdf_nbuf_t netbuf, int nbytes, |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1317 | struct HIF_CE_pipe_info *pipe_info) { |
| 1318 | if (nbytes <= pipe_info->buf_sz) { |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1319 | qdf_nbuf_set_pktlen(netbuf, nbytes); |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1320 | msg_callbacks-> |
| 1321 | rxCompletionHandler(msg_callbacks->Context, |
| 1322 | netbuf, pipe_info->pipe_num); |
| 1323 | } else { |
| 1324 | HIF_ERROR("%s: Invalid Rx msg buf:%p nbytes:%d", |
| 1325 | __func__, netbuf, nbytes); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1326 | qdf_nbuf_free(netbuf); |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1327 | } |
| 1328 | } |
| 1329 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1330 | /* Called by lower (CE) layer when data is received from the Target. */ |
| 1331 | void |
| 1332 | hif_pci_ce_recv_data(struct CE_handle *copyeng, void *ce_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1333 | void *transfer_context, qdf_dma_addr_t CE_data, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1334 | unsigned int nbytes, unsigned int transfer_id, |
| 1335 | unsigned int flags) |
| 1336 | { |
| 1337 | struct HIF_CE_pipe_info *pipe_info = |
| 1338 | (struct HIF_CE_pipe_info *)ce_context; |
| 1339 | struct HIF_CE_state *hif_state = pipe_info->HIF_CE_state; |
Houston Hoffman | 18c7fc5 | 2015-09-02 11:44:42 -0700 | [diff] [blame] | 1340 | struct CE_state *ce_state = (struct CE_state *) copyeng; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1341 | struct hif_softc *scn = HIF_GET_SOFTC(hif_state); |
Houston Hoffman | e02e12d | 2016-03-14 21:11:36 -0700 | [diff] [blame] | 1342 | #ifdef HIF_PCI |
| 1343 | struct hif_pci_softc *hif_pci_sc = HIF_GET_PCI_SOFTC(hif_state); |
| 1344 | #endif |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1345 | struct hif_msg_callbacks *msg_callbacks = |
| 1346 | &hif_state->msg_callbacks_current; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1347 | uint32_t count; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1348 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1349 | do { |
Houston Hoffman | e02e12d | 2016-03-14 21:11:36 -0700 | [diff] [blame] | 1350 | #ifdef HIF_PCI |
| 1351 | hif_pm_runtime_mark_last_busy(hif_pci_sc->dev); |
| 1352 | #endif |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1353 | qdf_nbuf_unmap_single(scn->qdf_dev, |
| 1354 | (qdf_nbuf_t) transfer_context, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1355 | QDF_DMA_FROM_DEVICE); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1356 | |
Houston Hoffman | 910c626 | 2015-09-28 12:56:25 -0700 | [diff] [blame] | 1357 | atomic_inc(&pipe_info->recv_bufs_needed); |
| 1358 | hif_post_recv_buffers_for_pipe(pipe_info); |
Komal Seelam | 6ee5590 | 2016-04-11 17:11:07 +0530 | [diff] [blame] | 1359 | if (scn->target_status == TARGET_STATUS_RESET) |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1360 | qdf_nbuf_free(transfer_context); |
Houston Hoffman | 49794a3 | 2015-12-21 12:14:56 -0800 | [diff] [blame] | 1361 | else |
| 1362 | hif_ce_do_recv(msg_callbacks, transfer_context, |
Houston Hoffman | 9c0f80a | 2015-09-28 18:36:36 -0700 | [diff] [blame] | 1363 | nbytes, pipe_info); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1364 | |
| 1365 | /* Set up force_break flag if num of receices reaches |
| 1366 | * MAX_NUM_OF_RECEIVES */ |
Houston Hoffman | 5bf441a | 2015-09-02 11:52:10 -0700 | [diff] [blame] | 1367 | ce_state->receive_count++; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1368 | count = ce_state->receive_count; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1369 | if (qdf_unlikely(hif_max_num_receives_reached(scn, count))) { |
Houston Hoffman | 18c7fc5 | 2015-09-02 11:44:42 -0700 | [diff] [blame] | 1370 | ce_state->force_break = 1; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1371 | break; |
| 1372 | } |
| 1373 | } while (ce_completed_recv_next(copyeng, &ce_context, &transfer_context, |
| 1374 | &CE_data, &nbytes, &transfer_id, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1375 | &flags) == QDF_STATUS_SUCCESS); |
Houston Hoffman | f460785 | 2015-12-17 17:14:40 -0800 | [diff] [blame] | 1376 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1377 | } |
| 1378 | |
| 1379 | /* TBDXXX: Set CE High Watermark; invoke txResourceAvailHandler in response */ |
| 1380 | |
| 1381 | void |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1382 | hif_post_init(struct hif_opaque_softc *hif_ctx, void *unused, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1383 | struct hif_msg_callbacks *callbacks) |
| 1384 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1385 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1386 | |
| 1387 | #ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG |
| 1388 | spin_lock_init(&pcie_access_log_lock); |
| 1389 | #endif |
| 1390 | /* Save callbacks for later installation */ |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1391 | qdf_mem_copy(&hif_state->msg_callbacks_pending, callbacks, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1392 | sizeof(hif_state->msg_callbacks_pending)); |
| 1393 | |
| 1394 | } |
| 1395 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1396 | int hif_completion_thread_startup(struct HIF_CE_state *hif_state) |
| 1397 | { |
| 1398 | struct CE_handle *ce_diag = hif_state->ce_diag; |
| 1399 | int pipe_num; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1400 | struct hif_softc *scn = HIF_GET_SOFTC(hif_state); |
Houston Hoffman | 9c12f7f | 2015-09-28 16:52:14 -0700 | [diff] [blame] | 1401 | struct hif_msg_callbacks *hif_msg_callbacks = |
| 1402 | &hif_state->msg_callbacks_current; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1403 | |
| 1404 | /* daemonize("hif_compl_thread"); */ |
| 1405 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1406 | if (scn->ce_count == 0) { |
| 1407 | HIF_ERROR("%s: Invalid ce_count\n", __func__); |
| 1408 | return -EINVAL; |
| 1409 | } |
Houston Hoffman | 9c12f7f | 2015-09-28 16:52:14 -0700 | [diff] [blame] | 1410 | |
| 1411 | if (!hif_msg_callbacks || |
| 1412 | !hif_msg_callbacks->rxCompletionHandler || |
| 1413 | !hif_msg_callbacks->txCompletionHandler) { |
| 1414 | HIF_ERROR("%s: no completion handler registered", __func__); |
| 1415 | return -EFAULT; |
| 1416 | } |
| 1417 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1418 | A_TARGET_ACCESS_LIKELY(scn); |
| 1419 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 1420 | struct CE_attr attr; |
| 1421 | struct HIF_CE_pipe_info *pipe_info; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1422 | |
| 1423 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1424 | if (pipe_info->ce_hdl == ce_diag) { |
| 1425 | continue; /* Handle Diagnostic CE specially */ |
| 1426 | } |
| 1427 | attr = host_ce_config[pipe_num]; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1428 | if (attr.src_nentries) { |
| 1429 | /* pipe used to send to target */ |
| 1430 | HIF_INFO_MED("%s: pipe_num:%d pipe_info:0x%p", |
| 1431 | __func__, pipe_num, pipe_info); |
| 1432 | ce_send_cb_register(pipe_info->ce_hdl, |
| 1433 | hif_pci_ce_send_done, pipe_info, |
| 1434 | attr.flags & CE_ATTR_DISABLE_INTR); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1435 | pipe_info->num_sends_allowed = attr.src_nentries - 1; |
| 1436 | } |
| 1437 | if (attr.dest_nentries) { |
| 1438 | /* pipe used to receive from target */ |
| 1439 | ce_recv_cb_register(pipe_info->ce_hdl, |
| 1440 | hif_pci_ce_recv_data, pipe_info, |
| 1441 | attr.flags & CE_ATTR_DISABLE_INTR); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1442 | } |
Houston Hoffman | 6666df7 | 2015-11-30 16:48:35 -0800 | [diff] [blame] | 1443 | |
| 1444 | if (attr.src_nentries) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1445 | qdf_spinlock_create(&pipe_info->completion_freeq_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1446 | } |
Houston Hoffman | 6666df7 | 2015-11-30 16:48:35 -0800 | [diff] [blame] | 1447 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1448 | A_TARGET_ACCESS_UNLIKELY(scn); |
| 1449 | return 0; |
| 1450 | } |
| 1451 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1452 | /* |
| 1453 | * Install pending msg callbacks. |
| 1454 | * |
| 1455 | * TBDXXX: This hack is needed because upper layers install msg callbacks |
| 1456 | * for use with HTC before BMI is done; yet this HIF implementation |
| 1457 | * needs to continue to use BMI msg callbacks. Really, upper layers |
| 1458 | * should not register HTC callbacks until AFTER BMI phase. |
| 1459 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1460 | static void hif_msg_callbacks_install(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1461 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1462 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1463 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1464 | qdf_mem_copy(&hif_state->msg_callbacks_current, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1465 | &hif_state->msg_callbacks_pending, |
| 1466 | sizeof(hif_state->msg_callbacks_pending)); |
| 1467 | } |
| 1468 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1469 | void hif_get_default_pipe(struct hif_opaque_softc *hif_hdl, uint8_t *ULPipe, |
| 1470 | uint8_t *DLPipe) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1471 | { |
| 1472 | int ul_is_polled, dl_is_polled; |
| 1473 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1474 | (void)hif_map_service_to_pipe(hif_hdl, HTC_CTRL_RSVD_SVC, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1475 | ULPipe, DLPipe, &ul_is_polled, &dl_is_polled); |
| 1476 | } |
| 1477 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1478 | /** |
| 1479 | * hif_dump_pipe_debug_count() - Log error count |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1480 | * @scn: hif_softc pointer. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1481 | * |
| 1482 | * Output the pipe error counts of each pipe to log file |
| 1483 | * |
| 1484 | * Return: N/A |
| 1485 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1486 | void hif_dump_pipe_debug_count(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1487 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1488 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1489 | int pipe_num; |
| 1490 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1491 | if (hif_state == NULL) { |
| 1492 | HIF_ERROR("%s hif_state is NULL", __func__); |
| 1493 | return; |
| 1494 | } |
| 1495 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 1496 | struct HIF_CE_pipe_info *pipe_info; |
| 1497 | |
| 1498 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1499 | |
| 1500 | if (pipe_info->nbuf_alloc_err_count > 0 || |
| 1501 | pipe_info->nbuf_dma_err_count > 0 || |
| 1502 | pipe_info->nbuf_ce_enqueue_err_count) |
| 1503 | HIF_ERROR( |
| 1504 | "%s: pipe_id = %d, recv_bufs_needed = %d, nbuf_alloc_err_count = %u, nbuf_dma_err_count = %u, nbuf_ce_enqueue_err_count = %u", |
| 1505 | __func__, pipe_info->pipe_num, |
| 1506 | atomic_read(&pipe_info->recv_bufs_needed), |
| 1507 | pipe_info->nbuf_alloc_err_count, |
| 1508 | pipe_info->nbuf_dma_err_count, |
| 1509 | pipe_info->nbuf_ce_enqueue_err_count); |
| 1510 | } |
| 1511 | } |
| 1512 | |
| 1513 | static int hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) |
| 1514 | { |
| 1515 | struct CE_handle *ce_hdl; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1516 | qdf_size_t buf_sz; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1517 | struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1518 | QDF_STATUS ret; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1519 | uint32_t bufs_posted = 0; |
| 1520 | |
| 1521 | buf_sz = pipe_info->buf_sz; |
| 1522 | if (buf_sz == 0) { |
| 1523 | /* Unused Copy Engine */ |
| 1524 | return 0; |
| 1525 | } |
| 1526 | |
| 1527 | ce_hdl = pipe_info->ce_hdl; |
| 1528 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1529 | qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1530 | while (atomic_read(&pipe_info->recv_bufs_needed) > 0) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1531 | qdf_dma_addr_t CE_data; /* CE space buffer address */ |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1532 | qdf_nbuf_t nbuf; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1533 | int status; |
| 1534 | |
| 1535 | atomic_dec(&pipe_info->recv_bufs_needed); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1536 | qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1537 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1538 | nbuf = qdf_nbuf_alloc(scn->qdf_dev, buf_sz, 0, 4, false); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1539 | if (!nbuf) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1540 | qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1541 | pipe_info->nbuf_alloc_err_count++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1542 | qdf_spin_unlock_bh( |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1543 | &pipe_info->recv_bufs_needed_lock); |
| 1544 | HIF_ERROR( |
| 1545 | "%s buf alloc error [%d] needed %d, nbuf_alloc_err_count = %u", |
| 1546 | __func__, pipe_info->pipe_num, |
| 1547 | atomic_read(&pipe_info->recv_bufs_needed), |
| 1548 | pipe_info->nbuf_alloc_err_count); |
| 1549 | atomic_inc(&pipe_info->recv_bufs_needed); |
| 1550 | return 1; |
| 1551 | } |
| 1552 | |
| 1553 | /* |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1554 | * qdf_nbuf_peek_header(nbuf, &data, &unused); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1555 | * CE_data = dma_map_single(dev, data, buf_sz, ); |
| 1556 | * DMA_FROM_DEVICE); |
| 1557 | */ |
| 1558 | ret = |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1559 | qdf_nbuf_map_single(scn->qdf_dev, nbuf, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1560 | QDF_DMA_FROM_DEVICE); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1561 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1562 | if (unlikely(ret != QDF_STATUS_SUCCESS)) { |
| 1563 | qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1564 | pipe_info->nbuf_dma_err_count++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1565 | qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1566 | HIF_ERROR( |
| 1567 | "%s buf alloc error [%d] needed %d, nbuf_dma_err_count = %u", |
| 1568 | __func__, pipe_info->pipe_num, |
| 1569 | atomic_read(&pipe_info->recv_bufs_needed), |
| 1570 | pipe_info->nbuf_dma_err_count); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1571 | qdf_nbuf_free(nbuf); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1572 | atomic_inc(&pipe_info->recv_bufs_needed); |
| 1573 | return 1; |
| 1574 | } |
| 1575 | |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1576 | CE_data = qdf_nbuf_get_frag_paddr(nbuf, 0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1577 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1578 | qdf_mem_dma_sync_single_for_device(scn->qdf_dev, CE_data, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1579 | buf_sz, DMA_FROM_DEVICE); |
| 1580 | status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1581 | QDF_ASSERT(status == QDF_STATUS_SUCCESS); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1582 | if (status != EOK) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1583 | qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1584 | pipe_info->nbuf_ce_enqueue_err_count++; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1585 | qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1586 | HIF_ERROR( |
| 1587 | "%s buf alloc error [%d] needed %d, nbuf_alloc_err_count = %u", |
| 1588 | __func__, pipe_info->pipe_num, |
| 1589 | atomic_read(&pipe_info->recv_bufs_needed), |
| 1590 | pipe_info->nbuf_ce_enqueue_err_count); |
| 1591 | atomic_inc(&pipe_info->recv_bufs_needed); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1592 | qdf_nbuf_free(nbuf); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1593 | return 1; |
| 1594 | } |
| 1595 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1596 | qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1597 | bufs_posted++; |
| 1598 | } |
| 1599 | pipe_info->nbuf_alloc_err_count = |
Houston Hoffman | 5693683 | 2016-03-16 12:16:24 -0700 | [diff] [blame] | 1600 | (pipe_info->nbuf_alloc_err_count > bufs_posted) ? |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1601 | pipe_info->nbuf_alloc_err_count - bufs_posted : 0; |
| 1602 | pipe_info->nbuf_dma_err_count = |
Houston Hoffman | 5693683 | 2016-03-16 12:16:24 -0700 | [diff] [blame] | 1603 | (pipe_info->nbuf_dma_err_count > bufs_posted) ? |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1604 | pipe_info->nbuf_dma_err_count - bufs_posted : 0; |
| 1605 | pipe_info->nbuf_ce_enqueue_err_count = |
Houston Hoffman | 5693683 | 2016-03-16 12:16:24 -0700 | [diff] [blame] | 1606 | (pipe_info->nbuf_ce_enqueue_err_count > bufs_posted) ? |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1607 | pipe_info->nbuf_ce_enqueue_err_count - bufs_posted : 0; |
| 1608 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1609 | qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1610 | |
| 1611 | return 0; |
| 1612 | } |
| 1613 | |
| 1614 | /* |
| 1615 | * Try to post all desired receive buffers for all pipes. |
| 1616 | * Returns 0 if all desired buffers are posted, |
| 1617 | * non-zero if were were unable to completely |
| 1618 | * replenish receive buffers. |
| 1619 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1620 | static int hif_post_recv_buffers(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1621 | { |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1622 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1623 | int pipe_num, rv = 0; |
| 1624 | |
| 1625 | A_TARGET_ACCESS_LIKELY(scn); |
| 1626 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 1627 | struct HIF_CE_pipe_info *pipe_info; |
| 1628 | |
| 1629 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1630 | if (hif_post_recv_buffers_for_pipe(pipe_info)) { |
| 1631 | rv = 1; |
| 1632 | goto done; |
| 1633 | } |
| 1634 | } |
| 1635 | |
| 1636 | done: |
| 1637 | A_TARGET_ACCESS_UNLIKELY(scn); |
| 1638 | |
| 1639 | return rv; |
| 1640 | } |
| 1641 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1642 | QDF_STATUS hif_start(struct hif_opaque_softc *hif_ctx) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1643 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1644 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1645 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1646 | |
Manjunathappa Prakash | 4a9c3a8 | 2016-04-14 01:12:14 -0700 | [diff] [blame] | 1647 | hif_update_fastpath_recv_bufs_cnt(scn); |
| 1648 | |
Houston Hoffman | 9c12f7f | 2015-09-28 16:52:14 -0700 | [diff] [blame] | 1649 | hif_msg_callbacks_install(scn); |
| 1650 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1651 | if (hif_completion_thread_startup(hif_state)) |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1652 | return QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1653 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1654 | /* Post buffers once to start things off. */ |
| 1655 | (void)hif_post_recv_buffers(scn); |
| 1656 | |
| 1657 | hif_state->started = true; |
| 1658 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1659 | return QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1660 | } |
| 1661 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1662 | void hif_recv_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) |
| 1663 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1664 | struct hif_softc *scn; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1665 | struct CE_handle *ce_hdl; |
| 1666 | uint32_t buf_sz; |
| 1667 | struct HIF_CE_state *hif_state; |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1668 | qdf_nbuf_t netbuf; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1669 | qdf_dma_addr_t CE_data; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1670 | void *per_CE_context; |
| 1671 | |
| 1672 | buf_sz = pipe_info->buf_sz; |
| 1673 | if (buf_sz == 0) { |
| 1674 | /* Unused Copy Engine */ |
| 1675 | return; |
| 1676 | } |
| 1677 | |
| 1678 | hif_state = pipe_info->HIF_CE_state; |
| 1679 | if (!hif_state->started) { |
| 1680 | return; |
| 1681 | } |
| 1682 | |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1683 | scn = HIF_GET_SOFTC(hif_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1684 | ce_hdl = pipe_info->ce_hdl; |
| 1685 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1686 | if (scn->qdf_dev == NULL) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1687 | return; |
| 1688 | } |
| 1689 | while (ce_revoke_recv_next |
| 1690 | (ce_hdl, &per_CE_context, (void **)&netbuf, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1691 | &CE_data) == QDF_STATUS_SUCCESS) { |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1692 | qdf_nbuf_unmap_single(scn->qdf_dev, netbuf, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1693 | QDF_DMA_FROM_DEVICE); |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1694 | qdf_nbuf_free(netbuf); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1695 | } |
| 1696 | } |
| 1697 | |
| 1698 | void hif_send_buffer_cleanup_on_pipe(struct HIF_CE_pipe_info *pipe_info) |
| 1699 | { |
| 1700 | struct CE_handle *ce_hdl; |
| 1701 | struct HIF_CE_state *hif_state; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1702 | struct hif_softc *scn; |
Vishwajith Upendra | 70f8b6e | 2016-03-01 16:28:23 +0530 | [diff] [blame] | 1703 | qdf_nbuf_t netbuf; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1704 | void *per_CE_context; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1705 | qdf_dma_addr_t CE_data; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1706 | unsigned int nbytes; |
| 1707 | unsigned int id; |
| 1708 | uint32_t buf_sz; |
| 1709 | uint32_t toeplitz_hash_result; |
| 1710 | |
| 1711 | buf_sz = pipe_info->buf_sz; |
| 1712 | if (buf_sz == 0) { |
| 1713 | /* Unused Copy Engine */ |
| 1714 | return; |
| 1715 | } |
| 1716 | |
| 1717 | hif_state = pipe_info->HIF_CE_state; |
| 1718 | if (!hif_state->started) { |
| 1719 | return; |
| 1720 | } |
| 1721 | |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1722 | scn = HIF_GET_SOFTC(hif_state); |
| 1723 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1724 | ce_hdl = pipe_info->ce_hdl; |
| 1725 | |
| 1726 | while (ce_cancel_send_next |
| 1727 | (ce_hdl, &per_CE_context, |
| 1728 | (void **)&netbuf, &CE_data, &nbytes, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1729 | &id, &toeplitz_hash_result) == QDF_STATUS_SUCCESS) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1730 | if (netbuf != CE_SENDLIST_ITEM_CTXT) { |
| 1731 | /* |
| 1732 | * Packets enqueued by htt_h2t_ver_req_msg() and |
| 1733 | * htt_h2t_rx_ring_cfg_msg_ll() have already been |
| 1734 | * freed in htt_htc_misc_pkt_pool_free() in |
| 1735 | * wlantl_close(), so do not free them here again |
Houston Hoffman | 29573d9 | 2015-10-20 17:49:44 -0700 | [diff] [blame] | 1736 | * by checking whether it's the endpoint |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1737 | * which they are queued in. |
| 1738 | */ |
Nirav Shah | d7f9159 | 2016-04-21 14:18:43 +0530 | [diff] [blame] | 1739 | if (id == scn->htc_htt_tx_endpoint) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1740 | return; |
Nirav Shah | d7f9159 | 2016-04-21 14:18:43 +0530 | [diff] [blame] | 1741 | /* Indicate the completion to higher |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1742 | * layer to free the buffer */ |
| 1743 | hif_state->msg_callbacks_current. |
| 1744 | txCompletionHandler(hif_state-> |
| 1745 | msg_callbacks_current.Context, |
| 1746 | netbuf, id, toeplitz_hash_result); |
| 1747 | } |
| 1748 | } |
| 1749 | } |
| 1750 | |
| 1751 | /* |
| 1752 | * Cleanup residual buffers for device shutdown: |
| 1753 | * buffers that were enqueued for receive |
| 1754 | * buffers that were to be sent |
| 1755 | * Note: Buffers that had completed but which were |
| 1756 | * not yet processed are on a completion queue. They |
| 1757 | * are handled when the completion thread shuts down. |
| 1758 | */ |
| 1759 | void hif_buffer_cleanup(struct HIF_CE_state *hif_state) |
| 1760 | { |
| 1761 | int pipe_num; |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1762 | struct hif_softc *scn = HIF_GET_SOFTC(hif_state); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1763 | |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1764 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1765 | struct HIF_CE_pipe_info *pipe_info; |
| 1766 | |
| 1767 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1768 | hif_recv_buffer_cleanup_on_pipe(pipe_info); |
| 1769 | hif_send_buffer_cleanup_on_pipe(pipe_info); |
| 1770 | } |
| 1771 | } |
| 1772 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1773 | void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1774 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1775 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1776 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1777 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1778 | hif_buffer_cleanup(hif_state); |
| 1779 | } |
| 1780 | |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 1781 | void hif_stop(struct hif_opaque_softc *hif_ctx) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1782 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 1783 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 1784 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_ctx); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1785 | int pipe_num; |
| 1786 | |
| 1787 | scn->hif_init_done = false; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1788 | |
| 1789 | /* |
| 1790 | * At this point, asynchronous threads are stopped, |
| 1791 | * The Target should not DMA nor interrupt, Host code may |
| 1792 | * not initiate anything more. So we just need to clean |
| 1793 | * up Host-side state. |
| 1794 | */ |
| 1795 | |
| 1796 | if (scn->athdiag_procfs_inited) { |
| 1797 | athdiag_procfs_remove(); |
| 1798 | scn->athdiag_procfs_inited = false; |
| 1799 | } |
| 1800 | |
| 1801 | hif_buffer_cleanup(hif_state); |
| 1802 | |
| 1803 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 1804 | struct HIF_CE_pipe_info *pipe_info; |
| 1805 | |
| 1806 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1807 | if (pipe_info->ce_hdl) { |
| 1808 | ce_fini(pipe_info->ce_hdl); |
| 1809 | pipe_info->ce_hdl = NULL; |
| 1810 | pipe_info->buf_sz = 0; |
| 1811 | } |
| 1812 | } |
| 1813 | |
| 1814 | if (hif_state->sleep_timer_init) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1815 | qdf_timer_stop(&hif_state->sleep_timer); |
| 1816 | qdf_timer_free(&hif_state->sleep_timer); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1817 | hif_state->sleep_timer_init = false; |
| 1818 | } |
| 1819 | |
| 1820 | hif_state->started = false; |
| 1821 | } |
| 1822 | |
Houston Hoffman | 854e67f | 2016-03-14 21:11:39 -0700 | [diff] [blame] | 1823 | /** |
| 1824 | * hif_get_target_ce_config() - get copy engine configuration |
| 1825 | * @target_ce_config_ret: basic copy engine configuration |
| 1826 | * @target_ce_config_sz_ret: size of the basic configuration in bytes |
| 1827 | * @target_service_to_ce_map_ret: service mapping for the copy engines |
| 1828 | * @target_service_to_ce_map_sz_ret: size of the mapping in bytes |
| 1829 | * @target_shadow_reg_cfg_ret: shadow register configuration |
| 1830 | * @shadow_cfg_sz_ret: size of the shadow register configuration in bytes |
| 1831 | * |
| 1832 | * providing accessor to these values outside of this file. |
| 1833 | * currently these are stored in static pointers to const sections. |
| 1834 | * there are multiple configurations that are selected from at compile time. |
| 1835 | * Runtime selection would need to consider mode, target type and bus type. |
| 1836 | * |
| 1837 | * Return: return by parameter. |
| 1838 | */ |
| 1839 | void hif_get_target_ce_config(struct CE_pipe_config **target_ce_config_ret, |
| 1840 | int *target_ce_config_sz_ret, |
| 1841 | struct service_to_pipe **target_service_to_ce_map_ret, |
| 1842 | int *target_service_to_ce_map_sz_ret, |
| 1843 | struct shadow_reg_cfg **target_shadow_reg_cfg_ret, |
| 1844 | int *shadow_cfg_sz_ret) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1845 | { |
Houston Hoffman | 854e67f | 2016-03-14 21:11:39 -0700 | [diff] [blame] | 1846 | *target_ce_config_ret = target_ce_config; |
| 1847 | *target_ce_config_sz_ret = target_ce_config_sz; |
| 1848 | *target_service_to_ce_map_ret = target_service_to_ce_map; |
| 1849 | *target_service_to_ce_map_sz_ret = target_service_to_ce_map_sz; |
| 1850 | |
| 1851 | if (target_shadow_reg_cfg_ret) |
| 1852 | *target_shadow_reg_cfg_ret = target_shadow_reg_cfg; |
| 1853 | |
| 1854 | if (shadow_cfg_sz_ret) |
| 1855 | *shadow_cfg_sz_ret = shadow_cfg_sz; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1856 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1857 | |
| 1858 | /** |
| 1859 | * hif_wlan_enable(): call the platform driver to enable wlan |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1860 | * @scn: HIF Context |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1861 | * |
| 1862 | * This function passes the con_mode and CE configuration to |
| 1863 | * platform driver to enable wlan. |
| 1864 | * |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1865 | * Return: linux error code |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1866 | */ |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1867 | int hif_wlan_enable(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1868 | { |
| 1869 | struct icnss_wlan_enable_cfg cfg; |
| 1870 | enum icnss_driver_mode mode; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1871 | uint32_t con_mode = hif_get_conparam(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1872 | |
Houston Hoffman | 854e67f | 2016-03-14 21:11:39 -0700 | [diff] [blame] | 1873 | hif_get_target_ce_config((struct CE_pipe_config **)&cfg.ce_tgt_cfg, |
| 1874 | &cfg.num_ce_tgt_cfg, |
| 1875 | (struct service_to_pipe **)&cfg.ce_svc_cfg, |
| 1876 | &cfg.num_ce_svc_pipe_cfg, |
| 1877 | (struct shadow_reg_cfg **)&cfg.shadow_reg_cfg, |
| 1878 | &cfg.num_shadow_reg_cfg); |
| 1879 | |
| 1880 | /* translate from structure size to array size */ |
| 1881 | cfg.num_ce_tgt_cfg /= sizeof(struct CE_pipe_config); |
| 1882 | cfg.num_ce_svc_pipe_cfg /= sizeof(struct service_to_pipe); |
| 1883 | cfg.num_shadow_reg_cfg /= sizeof(struct shadow_reg_cfg); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1884 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1885 | if (QDF_GLOBAL_FTM_MODE == con_mode) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1886 | mode = ICNSS_FTM; |
Houston Hoffman | 75ef5a5 | 2016-04-14 17:15:49 -0700 | [diff] [blame] | 1887 | else if (QDF_IS_EPPING_ENABLED(con_mode)) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1888 | mode = ICNSS_EPPING; |
Peng Xu | 7b96253 | 2015-10-02 17:17:03 -0700 | [diff] [blame] | 1889 | else |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1890 | mode = ICNSS_MISSION; |
Peng Xu | 7b96253 | 2015-10-02 17:17:03 -0700 | [diff] [blame] | 1891 | |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 1892 | if (BYPASS_QMI) |
| 1893 | return 0; |
| 1894 | else |
| 1895 | return icnss_wlan_enable(&cfg, mode, QWLAN_VERSIONSTR); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1896 | } |
| 1897 | |
Houston Hoffman | 75ef5a5 | 2016-04-14 17:15:49 -0700 | [diff] [blame] | 1898 | #define CE_EPPING_USES_IRQ true |
| 1899 | |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1900 | /** |
| 1901 | * hif_ce_prepare_config() - load the correct static tables. |
| 1902 | * @scn: hif context |
| 1903 | * |
| 1904 | * Epping uses different static attribute tables than mission mode. |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1905 | */ |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1906 | void hif_ce_prepare_config(struct hif_softc *scn) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1907 | { |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 1908 | uint32_t mode = hif_get_conparam(scn); |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 1909 | struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); |
| 1910 | struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); |
| 1911 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1912 | /* if epping is enabled we need to use the epping configuration. */ |
Houston Hoffman | 75ef5a5 | 2016-04-14 17:15:49 -0700 | [diff] [blame] | 1913 | if (QDF_IS_EPPING_ENABLED(mode)) { |
| 1914 | if (CE_EPPING_USES_IRQ) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1915 | host_ce_config = host_ce_config_wlan_epping_irq; |
| 1916 | else |
| 1917 | host_ce_config = host_ce_config_wlan_epping_poll; |
| 1918 | target_ce_config = target_ce_config_wlan_epping; |
| 1919 | target_ce_config_sz = sizeof(target_ce_config_wlan_epping); |
| 1920 | target_service_to_ce_map = |
| 1921 | target_service_to_ce_map_wlan_epping; |
| 1922 | target_service_to_ce_map_sz = |
| 1923 | sizeof(target_service_to_ce_map_wlan_epping); |
Vishwajith Upendra | 70efc75 | 2016-04-18 11:23:49 -0700 | [diff] [blame] | 1924 | target_shadow_reg_cfg = target_shadow_reg_cfg_epping; |
| 1925 | shadow_cfg_sz = sizeof(target_shadow_reg_cfg_epping); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1926 | } |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 1927 | |
| 1928 | switch (tgt_info->target_type) { |
| 1929 | default: |
| 1930 | break; |
| 1931 | case TARGET_TYPE_AR900B: |
| 1932 | case TARGET_TYPE_QCA9984: |
| 1933 | case TARGET_TYPE_IPQ4019: |
| 1934 | case TARGET_TYPE_QCA9888: |
| 1935 | host_ce_config = host_ce_config_wlan_ar900b; |
| 1936 | target_ce_config = target_ce_config_wlan_ar900b; |
| 1937 | target_ce_config_sz = sizeof(target_ce_config_wlan_ar900b); |
| 1938 | |
| 1939 | target_service_to_ce_map = target_service_to_ce_map_ar900b; |
| 1940 | target_service_to_ce_map_sz = |
| 1941 | sizeof(target_service_to_ce_map_ar900b); |
| 1942 | break; |
| 1943 | |
| 1944 | case TARGET_TYPE_AR9888: |
| 1945 | case TARGET_TYPE_AR9888V2: |
| 1946 | host_ce_config = host_ce_config_wlan_ar9888; |
| 1947 | target_ce_config = target_ce_config_wlan_ar9888; |
| 1948 | target_ce_config_sz = sizeof(target_ce_config_wlan_ar9888); |
| 1949 | |
| 1950 | target_service_to_ce_map = target_service_to_ce_map_ar900b; |
| 1951 | target_service_to_ce_map_sz = |
| 1952 | sizeof(target_service_to_ce_map_ar900b); |
| 1953 | break; |
| 1954 | } |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1955 | } |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1956 | |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1957 | /** |
| 1958 | * hif_ce_open() - do ce specific allocations |
| 1959 | * @hif_sc: pointer to hif context |
| 1960 | * |
| 1961 | * return: 0 for success or QDF_STATUS_E_NOMEM |
| 1962 | */ |
| 1963 | QDF_STATUS hif_ce_open(struct hif_softc *hif_sc) |
| 1964 | { |
| 1965 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 1966 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 1967 | qdf_spinlock_create(&hif_state->keep_awake_lock); |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 1968 | return QDF_STATUS_SUCCESS; |
| 1969 | } |
| 1970 | |
| 1971 | /** |
| 1972 | * hif_ce_close() - do ce specific free |
| 1973 | * @hif_sc: pointer to hif context |
| 1974 | */ |
| 1975 | void hif_ce_close(struct hif_softc *hif_sc) |
| 1976 | { |
| 1977 | } |
| 1978 | |
| 1979 | /** |
| 1980 | * hif_unconfig_ce() - ensure resources from hif_config_ce are freed |
| 1981 | * @hif_sc: hif context |
| 1982 | * |
| 1983 | * uses state variables to support cleaning up when hif_config_ce fails. |
| 1984 | */ |
| 1985 | void hif_unconfig_ce(struct hif_softc *hif_sc) |
| 1986 | { |
| 1987 | int pipe_num; |
| 1988 | struct HIF_CE_pipe_info *pipe_info; |
| 1989 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(hif_sc); |
| 1990 | |
| 1991 | for (pipe_num = 0; pipe_num < hif_sc->ce_count; pipe_num++) { |
| 1992 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 1993 | if (pipe_info->ce_hdl) { |
| 1994 | ce_unregister_irq(hif_state, (1 << pipe_num)); |
| 1995 | hif_sc->request_irq_done = false; |
| 1996 | ce_fini(pipe_info->ce_hdl); |
| 1997 | pipe_info->ce_hdl = NULL; |
| 1998 | pipe_info->buf_sz = 0; |
| 1999 | } |
| 2000 | } |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 2001 | if (hif_sc->athdiag_procfs_inited) { |
| 2002 | athdiag_procfs_remove(); |
| 2003 | hif_sc->athdiag_procfs_inited = false; |
| 2004 | } |
| 2005 | } |
| 2006 | |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 2007 | #ifdef CONFIG_BYPASS_QMI |
| 2008 | #define FW_SHARED_MEM (2 * 1024 * 1024) |
| 2009 | |
| 2010 | /** |
| 2011 | * hif_post_static_buf_to_target() - post static buffer to WLAN FW |
| 2012 | * @scn: pointer to HIF structure |
| 2013 | * |
| 2014 | * WLAN FW needs 2MB memory from DDR when QMI is disabled. |
| 2015 | * |
| 2016 | * Return: void |
| 2017 | */ |
| 2018 | static void hif_post_static_buf_to_target(struct hif_softc *scn) |
| 2019 | { |
Hardik Kantilal Patel | c5dc5f2 | 2016-04-21 14:11:33 -0700 | [diff] [blame] | 2020 | void *target_va; |
| 2021 | phys_addr_t target_pa; |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 2022 | |
Hardik Kantilal Patel | c5dc5f2 | 2016-04-21 14:11:33 -0700 | [diff] [blame] | 2023 | target_va = qdf_mem_alloc_consistent(scn->qdf_dev, scn->qdf_dev->dev, |
| 2024 | FW_SHARED_MEM, &target_pa); |
| 2025 | if (NULL == target_va) { |
| 2026 | HIF_TRACE("Memory allocation failed could not post target buf"); |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 2027 | return; |
| 2028 | } |
Hardik Kantilal Patel | c5dc5f2 | 2016-04-21 14:11:33 -0700 | [diff] [blame] | 2029 | hif_write32_mb(scn->mem + BYPASS_QMI_TEMP_REGISTER, target_pa); |
| 2030 | HIF_TRACE("target va %pK target pa %pa", target_va, &target_pa); |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 2031 | } |
| 2032 | #else |
| 2033 | static inline void hif_post_static_buf_to_target(struct hif_softc *scn) |
| 2034 | { |
| 2035 | return; |
| 2036 | } |
| 2037 | #endif |
| 2038 | |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 2039 | /** |
| 2040 | * hif_config_ce() - configure copy engines |
| 2041 | * @scn: hif context |
| 2042 | * |
| 2043 | * Prepares fw, copy engine hardware and host sw according |
| 2044 | * to the attributes selected by hif_ce_prepare_config. |
| 2045 | * |
| 2046 | * also calls athdiag_procfs_init |
| 2047 | * |
| 2048 | * return: 0 for success nonzero for failure. |
| 2049 | */ |
| 2050 | int hif_config_ce(struct hif_softc *scn) |
| 2051 | { |
| 2052 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
| 2053 | struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); |
| 2054 | struct HIF_CE_pipe_info *pipe_info; |
| 2055 | int pipe_num; |
| 2056 | #ifdef ADRASTEA_SHADOW_REGISTERS |
| 2057 | int i; |
| 2058 | #endif |
| 2059 | QDF_STATUS rv = QDF_STATUS_SUCCESS; |
| 2060 | |
| 2061 | scn->notice_send = true; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2062 | |
Yuanyuan Liu | a7a282f | 2016-04-15 12:55:04 -0700 | [diff] [blame] | 2063 | hif_post_static_buf_to_target(scn); |
| 2064 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2065 | hif_state->fw_indicator_address = FW_INDICATOR_ADDRESS; |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 2066 | |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2067 | hif_config_rri_on_ddr(scn); |
| 2068 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2069 | /* During CE initializtion */ |
| 2070 | scn->ce_count = HOST_CE_COUNT; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2071 | for (pipe_num = 0; pipe_num < scn->ce_count; pipe_num++) { |
| 2072 | struct CE_attr *attr; |
| 2073 | |
| 2074 | pipe_info = &hif_state->pipe_info[pipe_num]; |
| 2075 | pipe_info->pipe_num = pipe_num; |
| 2076 | pipe_info->HIF_CE_state = hif_state; |
| 2077 | attr = &host_ce_config[pipe_num]; |
| 2078 | pipe_info->ce_hdl = ce_init(scn, pipe_num, attr); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2079 | QDF_ASSERT(pipe_info->ce_hdl != NULL); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2080 | if (pipe_info->ce_hdl == NULL) { |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2081 | rv = QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2082 | A_TARGET_ACCESS_UNLIKELY(scn); |
| 2083 | goto err; |
| 2084 | } |
| 2085 | |
| 2086 | if (pipe_num == DIAG_CE_ID) { |
| 2087 | /* Reserve the ultimate CE for |
| 2088 | * Diagnostic Window support */ |
Houston Hoffman | c1d9a41 | 2016-03-30 21:07:57 -0700 | [diff] [blame] | 2089 | hif_state->ce_diag = pipe_info->ce_hdl; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2090 | continue; |
| 2091 | } |
| 2092 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2093 | pipe_info->buf_sz = (qdf_size_t) (attr->src_sz_max); |
| 2094 | qdf_spinlock_create(&pipe_info->recv_bufs_needed_lock); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2095 | if (attr->dest_nentries > 0) { |
| 2096 | atomic_set(&pipe_info->recv_bufs_needed, |
| 2097 | init_buffer_count(attr->dest_nentries - 1)); |
| 2098 | } else { |
| 2099 | atomic_set(&pipe_info->recv_bufs_needed, 0); |
| 2100 | } |
| 2101 | ce_tasklet_init(hif_state, (1 << pipe_num)); |
| 2102 | ce_register_irq(hif_state, (1 << pipe_num)); |
| 2103 | scn->request_irq_done = true; |
| 2104 | } |
| 2105 | |
| 2106 | if (athdiag_procfs_init(scn) != 0) { |
| 2107 | A_TARGET_ACCESS_UNLIKELY(scn); |
| 2108 | goto err; |
| 2109 | } |
| 2110 | scn->athdiag_procfs_inited = true; |
| 2111 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2112 | HIF_INFO_MED("%s: ce_init done", __func__); |
| 2113 | |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 2114 | init_tasklet_workers(hif_hdl); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2115 | |
| 2116 | HIF_TRACE("%s: X, ret = %d\n", __func__, rv); |
| 2117 | |
| 2118 | #ifdef ADRASTEA_SHADOW_REGISTERS |
| 2119 | HIF_ERROR("Using Shadow Registers instead of CE Registers\n"); |
| 2120 | for (i = 0; i < NUM_SHADOW_REGISTERS; i++) { |
| 2121 | HIF_ERROR("%s Shadow Register%d is mapped to address %x\n", |
| 2122 | __func__, i, |
| 2123 | (A_TARGET_READ(scn, (SHADOW_ADDRESS(i))) << 2)); |
| 2124 | } |
| 2125 | #endif |
| 2126 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2127 | return rv != QDF_STATUS_SUCCESS; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2128 | |
| 2129 | err: |
| 2130 | /* Failure, so clean up */ |
Houston Hoffman | 108da40 | 2016-03-14 21:11:24 -0700 | [diff] [blame] | 2131 | hif_unconfig_ce(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2132 | HIF_TRACE("%s: X, ret = %d\n", __func__, rv); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2133 | return QDF_STATUS_SUCCESS != QDF_STATUS_E_FAILURE; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2134 | } |
| 2135 | |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2136 | #ifdef WLAN_FEATURE_FASTPATH |
| 2137 | /** |
| 2138 | * hif_ce_fastpath_cb_register() - Register callback for fastpath msg handler |
| 2139 | * @handler: Callback funtcion |
| 2140 | * @context: handle for callback function |
| 2141 | * |
| 2142 | * Return: QDF_STATUS_SUCCESS on success or QDF_STATUS_E_FAILURE |
| 2143 | */ |
Houston Hoffman | 127467f | 2016-04-26 22:37:14 -0700 | [diff] [blame] | 2144 | int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx, |
| 2145 | fastpath_msg_handler handler, |
| 2146 | void *context) |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2147 | { |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2148 | struct CE_state *ce_state; |
Houston Hoffman | 127467f | 2016-04-26 22:37:14 -0700 | [diff] [blame] | 2149 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2150 | int i; |
| 2151 | |
| 2152 | QDF_ASSERT(scn != NULL); |
| 2153 | |
| 2154 | if (!scn->fastpath_mode_on) { |
| 2155 | HIF_WARN("Fastpath mode disabled\n"); |
| 2156 | return QDF_STATUS_E_FAILURE; |
| 2157 | } |
| 2158 | |
Houston Hoffman | d6f946c | 2016-04-06 15:16:00 -0700 | [diff] [blame] | 2159 | for (i = 0; i < scn->ce_count; i++) { |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2160 | ce_state = scn->ce_id_to_state[i]; |
| 2161 | if (ce_state->htt_rx_data) { |
| 2162 | ce_state->fastpath_handler = handler; |
| 2163 | ce_state->context = context; |
| 2164 | } |
| 2165 | } |
| 2166 | |
| 2167 | return QDF_STATUS_SUCCESS; |
| 2168 | } |
Manjunathappa Prakash | 7399f14 | 2016-04-13 23:38:16 -0700 | [diff] [blame] | 2169 | #endif |
| 2170 | |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2171 | #ifdef IPA_OFFLOAD |
Leo Chang | d85f78d | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 2172 | /** |
| 2173 | * hif_ipa_get_ce_resource() - get uc resource on hif |
| 2174 | * @scn: bus context |
| 2175 | * @ce_sr_base_paddr: copyengine source ring base physical address |
| 2176 | * @ce_sr_ring_size: copyengine source ring size |
| 2177 | * @ce_reg_paddr: copyengine register physical address |
| 2178 | * |
| 2179 | * IPA micro controller data path offload feature enabled, |
| 2180 | * HIF should release copy engine related resource information to IPA UC |
| 2181 | * IPA UC will access hardware resource with released information |
| 2182 | * |
| 2183 | * Return: None |
| 2184 | */ |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2185 | void hif_ipa_get_ce_resource(struct hif_opaque_softc *hif_ctx, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2186 | qdf_dma_addr_t *ce_sr_base_paddr, |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2187 | uint32_t *ce_sr_ring_size, |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2188 | qdf_dma_addr_t *ce_reg_paddr) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2189 | { |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2190 | struct hif_softc *scn = HIF_GET_SOFTC(hif_ctx); |
Komal Seelam | 02cf2f8 | 2016-02-22 20:44:25 +0530 | [diff] [blame] | 2191 | struct HIF_CE_state *hif_state = HIF_GET_CE_STATE(scn); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2192 | struct HIF_CE_pipe_info *pipe_info = |
| 2193 | &(hif_state->pipe_info[HIF_PCI_IPA_UC_ASSIGNED_CE]); |
| 2194 | struct CE_handle *ce_hdl = pipe_info->ce_hdl; |
| 2195 | |
| 2196 | ce_ipa_get_resource(ce_hdl, ce_sr_base_paddr, ce_sr_ring_size, |
| 2197 | ce_reg_paddr); |
| 2198 | return; |
| 2199 | } |
| 2200 | #endif /* IPA_OFFLOAD */ |
| 2201 | |
| 2202 | |
| 2203 | #ifdef ADRASTEA_SHADOW_REGISTERS |
| 2204 | |
| 2205 | /* |
| 2206 | Current shadow register config |
| 2207 | |
| 2208 | ----------------------------------------------------------- |
| 2209 | Shadow Register | CE | src/dst write index |
| 2210 | ----------------------------------------------------------- |
| 2211 | 0 | 0 | src |
| 2212 | 1 No Config - Doesn't point to anything |
| 2213 | 2 No Config - Doesn't point to anything |
| 2214 | 3 | 3 | src |
| 2215 | 4 | 4 | src |
| 2216 | 5 | 5 | src |
| 2217 | 6 No Config - Doesn't point to anything |
| 2218 | 7 | 7 | src |
| 2219 | 8 No Config - Doesn't point to anything |
| 2220 | 9 No Config - Doesn't point to anything |
| 2221 | 10 No Config - Doesn't point to anything |
| 2222 | 11 No Config - Doesn't point to anything |
| 2223 | ----------------------------------------------------------- |
| 2224 | 12 No Config - Doesn't point to anything |
| 2225 | 13 | 1 | dst |
| 2226 | 14 | 2 | dst |
| 2227 | 15 No Config - Doesn't point to anything |
| 2228 | 16 No Config - Doesn't point to anything |
| 2229 | 17 No Config - Doesn't point to anything |
| 2230 | 18 No Config - Doesn't point to anything |
| 2231 | 19 | 7 | dst |
| 2232 | 20 | 8 | dst |
| 2233 | 21 No Config - Doesn't point to anything |
| 2234 | 22 No Config - Doesn't point to anything |
| 2235 | 23 No Config - Doesn't point to anything |
| 2236 | ----------------------------------------------------------- |
| 2237 | |
| 2238 | |
| 2239 | ToDo - Move shadow register config to following in the future |
| 2240 | This helps free up a block of shadow registers towards the end. |
| 2241 | Can be used for other purposes |
| 2242 | |
| 2243 | ----------------------------------------------------------- |
| 2244 | Shadow Register | CE | src/dst write index |
| 2245 | ----------------------------------------------------------- |
| 2246 | 0 | 0 | src |
| 2247 | 1 | 3 | src |
| 2248 | 2 | 4 | src |
| 2249 | 3 | 5 | src |
| 2250 | 4 | 7 | src |
| 2251 | ----------------------------------------------------------- |
| 2252 | 5 | 1 | dst |
| 2253 | 6 | 2 | dst |
| 2254 | 7 | 7 | dst |
| 2255 | 8 | 8 | dst |
| 2256 | ----------------------------------------------------------- |
| 2257 | 9 No Config - Doesn't point to anything |
| 2258 | 12 No Config - Doesn't point to anything |
| 2259 | 13 No Config - Doesn't point to anything |
| 2260 | 14 No Config - Doesn't point to anything |
| 2261 | 15 No Config - Doesn't point to anything |
| 2262 | 16 No Config - Doesn't point to anything |
| 2263 | 17 No Config - Doesn't point to anything |
| 2264 | 18 No Config - Doesn't point to anything |
| 2265 | 19 No Config - Doesn't point to anything |
| 2266 | 20 No Config - Doesn't point to anything |
| 2267 | 21 No Config - Doesn't point to anything |
| 2268 | 22 No Config - Doesn't point to anything |
| 2269 | 23 No Config - Doesn't point to anything |
| 2270 | ----------------------------------------------------------- |
| 2271 | */ |
| 2272 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2273 | u32 shadow_sr_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2274 | { |
| 2275 | u32 addr = 0; |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2276 | u32 ce = COPY_ENGINE_ID(ctrl_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2277 | |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2278 | switch (ce) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2279 | case 0: |
| 2280 | addr = SHADOW_VALUE0; |
| 2281 | break; |
| 2282 | case 3: |
| 2283 | addr = SHADOW_VALUE3; |
| 2284 | break; |
| 2285 | case 4: |
| 2286 | addr = SHADOW_VALUE4; |
| 2287 | break; |
| 2288 | case 5: |
| 2289 | addr = SHADOW_VALUE5; |
| 2290 | break; |
| 2291 | case 7: |
| 2292 | addr = SHADOW_VALUE7; |
| 2293 | break; |
| 2294 | default: |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2295 | HIF_ERROR("invalid CE ctrl_addr (CE=%d)", ce); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2296 | QDF_ASSERT(0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2297 | } |
| 2298 | return addr; |
| 2299 | |
| 2300 | } |
| 2301 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2302 | u32 shadow_dst_wr_ind_addr(struct hif_softc *scn, u32 ctrl_addr) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2303 | { |
| 2304 | u32 addr = 0; |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2305 | u32 ce = COPY_ENGINE_ID(ctrl_addr); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2306 | |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2307 | switch (ce) { |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2308 | case 1: |
| 2309 | addr = SHADOW_VALUE13; |
| 2310 | break; |
| 2311 | case 2: |
| 2312 | addr = SHADOW_VALUE14; |
| 2313 | break; |
Vishwajith Upendra | 70efc75 | 2016-04-18 11:23:49 -0700 | [diff] [blame] | 2314 | case 5: |
| 2315 | addr = SHADOW_VALUE17; |
| 2316 | break; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2317 | case 7: |
| 2318 | addr = SHADOW_VALUE19; |
| 2319 | break; |
| 2320 | case 8: |
| 2321 | addr = SHADOW_VALUE20; |
| 2322 | break; |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2323 | case 9: |
| 2324 | addr = SHADOW_VALUE21; |
| 2325 | break; |
| 2326 | case 10: |
| 2327 | addr = SHADOW_VALUE22; |
| 2328 | break; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2329 | default: |
Houston Hoffman | e633044 | 2016-02-26 12:19:11 -0800 | [diff] [blame] | 2330 | HIF_ERROR("invalid CE ctrl_addr (CE=%d)", ce); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2331 | QDF_ASSERT(0); |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2332 | } |
| 2333 | |
| 2334 | return addr; |
| 2335 | |
| 2336 | } |
| 2337 | #endif |
| 2338 | |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2339 | #if defined(FEATURE_LRO) |
| 2340 | /** |
| 2341 | * ce_lro_flush_cb_register() - register the LRO flush |
| 2342 | * callback |
| 2343 | * @scn: HIF context |
| 2344 | * @handler: callback function |
| 2345 | * @data: opaque data pointer to be passed back |
| 2346 | * |
| 2347 | * Store the LRO flush callback provided |
| 2348 | * |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2349 | * Return: Number of instances the callback is registered for |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2350 | */ |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2351 | int ce_lro_flush_cb_register(struct hif_opaque_softc *hif_hdl, |
| 2352 | void (handler)(void *), void *data) |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2353 | { |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2354 | int rc = 0; |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 2355 | int i; |
| 2356 | struct CE_state *ce_state; |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2357 | struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2358 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2359 | QDF_ASSERT(scn != NULL); |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2360 | |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2361 | if (scn != NULL) { |
| 2362 | for (i = 0; i < scn->ce_count; i++) { |
| 2363 | ce_state = scn->ce_id_to_state[i]; |
| 2364 | if ((ce_state != NULL) && (ce_state->htt_rx_data)) { |
| 2365 | ce_state->lro_flush_cb = handler; |
| 2366 | ce_state->lro_data = data; |
| 2367 | rc++; |
| 2368 | } |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 2369 | } |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2370 | } else { |
| 2371 | HIF_ERROR("%s: hif_state NULL!", __func__); |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2372 | } |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2373 | return rc; |
Prakash Dhavali | d5c9f1c | 2015-11-08 19:04:44 -0800 | [diff] [blame] | 2374 | } |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2375 | |
| 2376 | /** |
| 2377 | * ce_lro_flush_cb_deregister() - deregister the LRO flush |
| 2378 | * callback |
| 2379 | * @scn: HIF context |
| 2380 | * |
| 2381 | * Remove the LRO flush callback |
| 2382 | * |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2383 | * Return: Number of instances the callback is de-registered |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2384 | */ |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2385 | int ce_lro_flush_cb_deregister(struct hif_opaque_softc *hif_hdl) |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2386 | { |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2387 | int rc = 0; |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 2388 | int i; |
| 2389 | struct CE_state *ce_state; |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2390 | struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2391 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2392 | QDF_ASSERT(scn != NULL); |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2393 | if (scn != NULL) { |
| 2394 | for (i = 0; i < scn->ce_count; i++) { |
| 2395 | ce_state = scn->ce_id_to_state[i]; |
| 2396 | if ((ce_state != NULL) && (ce_state->htt_rx_data)) { |
| 2397 | ce_state->lro_flush_cb = NULL; |
| 2398 | ce_state->lro_data = NULL; |
| 2399 | rc++; |
| 2400 | } |
Houston Hoffman | c7d5429 | 2016-04-13 18:55:37 -0700 | [diff] [blame] | 2401 | } |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2402 | } else { |
| 2403 | HIF_ERROR("%s: hif_state NULL!", __func__); |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2404 | } |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2405 | return rc; |
Dhanashri Atre | 65b674f | 2015-10-30 15:12:03 -0700 | [diff] [blame] | 2406 | } |
| 2407 | #endif |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2408 | |
| 2409 | /** |
| 2410 | * hif_map_service_to_pipe() - returns the ce ids pertaining to |
| 2411 | * this service |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2412 | * @scn: hif_softc pointer. |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2413 | * @svc_id: Service ID for which the mapping is needed. |
| 2414 | * @ul_pipe: address of the container in which ul pipe is returned. |
| 2415 | * @dl_pipe: address of the container in which dl pipe is returned. |
| 2416 | * @ul_is_polled: address of the container in which a bool |
| 2417 | * indicating if the UL CE for this service |
| 2418 | * is polled is returned. |
| 2419 | * @dl_is_polled: address of the container in which a bool |
| 2420 | * indicating if the DL CE for this service |
| 2421 | * is polled is returned. |
| 2422 | * |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2423 | * Return: Indicates whether the service has been found in the table. |
| 2424 | * Upon return, ul_is_polled is updated only if ul_pipe is updated. |
| 2425 | * There will be warning logs if either leg has not been updated |
| 2426 | * because it missed the entry in the table (but this is not an err). |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2427 | */ |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2428 | int hif_map_service_to_pipe(struct hif_opaque_softc *hif_hdl, uint16_t svc_id, |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2429 | uint8_t *ul_pipe, uint8_t *dl_pipe, int *ul_is_polled, |
| 2430 | int *dl_is_polled) |
| 2431 | { |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2432 | int status = QDF_STATUS_E_INVAL; |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2433 | unsigned int i; |
| 2434 | struct service_to_pipe element; |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2435 | struct service_to_pipe *tgt_svc_map_to_use; |
| 2436 | size_t sz_tgt_svc_map_to_use; |
Komal Seelam | bd7c51d | 2016-02-24 10:27:30 +0530 | [diff] [blame] | 2437 | struct hif_softc *scn = HIF_GET_SOFTC(hif_hdl); |
| 2438 | uint32_t mode = hif_get_conparam(scn); |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 2439 | struct hif_target_info *tgt_info = hif_get_target_info_handle(hif_hdl); |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2440 | bool dl_updated = false; |
| 2441 | bool ul_updated = false; |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2442 | |
Houston Hoffman | 75ef5a5 | 2016-04-14 17:15:49 -0700 | [diff] [blame] | 2443 | if (QDF_IS_EPPING_ENABLED(mode)) { |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2444 | tgt_svc_map_to_use = target_service_to_ce_map_wlan_epping; |
| 2445 | sz_tgt_svc_map_to_use = |
| 2446 | sizeof(target_service_to_ce_map_wlan_epping); |
| 2447 | } else { |
Houston Hoffman | fb698ef | 2016-05-05 19:50:44 -0700 | [diff] [blame^] | 2448 | switch (tgt_info->target_type) { |
| 2449 | default: |
| 2450 | tgt_svc_map_to_use = target_service_to_ce_map_wlan; |
| 2451 | sz_tgt_svc_map_to_use = |
| 2452 | sizeof(target_service_to_ce_map_wlan); |
| 2453 | break; |
| 2454 | case TARGET_TYPE_AR900B: |
| 2455 | case TARGET_TYPE_QCA9984: |
| 2456 | case TARGET_TYPE_IPQ4019: |
| 2457 | case TARGET_TYPE_QCA9888: |
| 2458 | case TARGET_TYPE_AR9888: |
| 2459 | case TARGET_TYPE_AR9888V2: |
| 2460 | tgt_svc_map_to_use = target_service_to_ce_map_ar900b; |
| 2461 | sz_tgt_svc_map_to_use = |
| 2462 | sizeof(target_service_to_ce_map_ar900b); |
| 2463 | break; |
| 2464 | } |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2465 | } |
| 2466 | |
| 2467 | *dl_is_polled = 0; /* polling for received messages not supported */ |
| 2468 | |
| 2469 | for (i = 0; i < (sz_tgt_svc_map_to_use/sizeof(element)); i++) { |
| 2470 | |
| 2471 | memcpy(&element, &tgt_svc_map_to_use[i], sizeof(element)); |
| 2472 | if (element.service_id == svc_id) { |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2473 | if (element.pipedir == PIPEDIR_OUT) { |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2474 | *ul_pipe = element.pipenum; |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2475 | *ul_is_polled = |
| 2476 | (host_ce_config[*ul_pipe].flags & |
| 2477 | CE_ATTR_DISABLE_INTR) != 0; |
| 2478 | ul_updated = true; |
| 2479 | } else if (element.pipedir == PIPEDIR_IN) { |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2480 | *dl_pipe = element.pipenum; |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2481 | dl_updated = true; |
| 2482 | } |
| 2483 | status = QDF_STATUS_SUCCESS; |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2484 | } |
| 2485 | } |
Manjunathappa Prakash | 32afe37 | 2016-04-29 11:12:41 -0700 | [diff] [blame] | 2486 | if (ul_updated == false) |
| 2487 | HIF_WARN("%s: ul pipe is NOT updated for service %d", |
| 2488 | __func__, svc_id); |
| 2489 | if (dl_updated == false) |
| 2490 | HIF_WARN("%s: dl pipe is NOT updated for service %d", |
| 2491 | __func__, svc_id); |
Sanjay Devnani | c319c82 | 2015-11-06 16:44:28 -0800 | [diff] [blame] | 2492 | |
| 2493 | return status; |
| 2494 | } |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2495 | |
| 2496 | #ifdef SHADOW_REG_DEBUG |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2497 | inline uint32_t DEBUG_CE_SRC_RING_READ_IDX_GET(struct hif_softc *scn, |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2498 | uint32_t CE_ctrl_addr) |
| 2499 | { |
| 2500 | uint32_t read_from_hw, srri_from_ddr = 0; |
| 2501 | |
| 2502 | read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_SRRI_ADDRESS); |
| 2503 | |
| 2504 | srri_from_ddr = SRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); |
| 2505 | |
| 2506 | if (read_from_hw != srri_from_ddr) { |
| 2507 | HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n", |
| 2508 | srri_from_ddr, read_from_hw, |
| 2509 | CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2510 | QDF_ASSERT(0); |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2511 | } |
| 2512 | return srri_from_ddr; |
| 2513 | } |
| 2514 | |
| 2515 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2516 | inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct hif_softc *scn, |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2517 | uint32_t CE_ctrl_addr) |
| 2518 | { |
| 2519 | uint32_t read_from_hw, drri_from_ddr = 0; |
| 2520 | |
| 2521 | read_from_hw = A_TARGET_READ(scn, CE_ctrl_addr + CURRENT_DRRI_ADDRESS); |
| 2522 | |
| 2523 | drri_from_ddr = DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr)); |
| 2524 | |
| 2525 | if (read_from_hw != drri_from_ddr) { |
| 2526 | HIF_ERROR("error: read from ddr = %d actual read from register = %d, CE_MISC_INT_STATUS_GET = 0x%x\n", |
| 2527 | drri_from_ddr, read_from_hw, |
| 2528 | CE_MISC_INT_STATUS_GET(scn, CE_ctrl_addr)); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2529 | QDF_ASSERT(0); |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2530 | } |
| 2531 | return drri_from_ddr; |
| 2532 | } |
| 2533 | |
| 2534 | #endif |
| 2535 | |
Houston Hoffman | 3d0cda8 | 2015-12-03 13:25:05 -0800 | [diff] [blame] | 2536 | #ifdef ADRASTEA_RRI_ON_DDR |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2537 | /** |
| 2538 | * hif_get_src_ring_read_index(): Called to get the SRRI |
| 2539 | * |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2540 | * @scn: hif_softc pointer |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2541 | * @CE_ctrl_addr: base address of the CE whose RRI is to be read |
| 2542 | * |
| 2543 | * This function returns the SRRI to the caller. For CEs that |
| 2544 | * dont have interrupts enabled, we look at the DDR based SRRI |
| 2545 | * |
| 2546 | * Return: SRRI |
| 2547 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2548 | inline unsigned int hif_get_src_ring_read_index(struct hif_softc *scn, |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2549 | uint32_t CE_ctrl_addr) |
| 2550 | { |
| 2551 | struct CE_attr attr; |
| 2552 | |
| 2553 | attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; |
| 2554 | if (attr.flags & CE_ATTR_DISABLE_INTR) |
| 2555 | return CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); |
| 2556 | else |
| 2557 | return A_TARGET_READ(scn, |
| 2558 | (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS); |
| 2559 | } |
| 2560 | |
| 2561 | /** |
| 2562 | * hif_get_dst_ring_read_index(): Called to get the DRRI |
| 2563 | * |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2564 | * @scn: hif_softc pointer |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2565 | * @CE_ctrl_addr: base address of the CE whose RRI is to be read |
| 2566 | * |
| 2567 | * This function returns the DRRI to the caller. For CEs that |
| 2568 | * dont have interrupts enabled, we look at the DDR based DRRI |
| 2569 | * |
| 2570 | * Return: DRRI |
| 2571 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2572 | inline unsigned int hif_get_dst_ring_read_index(struct hif_softc *scn, |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2573 | uint32_t CE_ctrl_addr) |
| 2574 | { |
| 2575 | struct CE_attr attr; |
| 2576 | |
| 2577 | attr = host_ce_config[COPY_ENGINE_ID(CE_ctrl_addr)]; |
| 2578 | |
| 2579 | if (attr.flags & CE_ATTR_DISABLE_INTR) |
| 2580 | return CE_DEST_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr); |
| 2581 | else |
| 2582 | return A_TARGET_READ(scn, |
| 2583 | (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS); |
| 2584 | } |
| 2585 | |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2586 | /** |
| 2587 | * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism |
| 2588 | * |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2589 | * @scn: hif_softc pointer |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2590 | * |
| 2591 | * This function allocates non cached memory on ddr and sends |
| 2592 | * the physical address of this memory to the CE hardware. The |
| 2593 | * hardware updates the RRI on this particular location. |
| 2594 | * |
| 2595 | * Return: None |
| 2596 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2597 | static inline void hif_config_rri_on_ddr(struct hif_softc *scn) |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2598 | { |
| 2599 | unsigned int i; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2600 | qdf_dma_addr_t paddr_rri_on_ddr; |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2601 | uint32_t high_paddr, low_paddr; |
| 2602 | scn->vaddr_rri_on_ddr = |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2603 | (uint32_t *)qdf_mem_alloc_consistent(scn->qdf_dev, |
| 2604 | scn->qdf_dev->dev, (CE_COUNT*sizeof(uint32_t)), |
| 2605 | &paddr_rri_on_ddr); |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2606 | |
| 2607 | low_paddr = BITS0_TO_31(paddr_rri_on_ddr); |
| 2608 | high_paddr = BITS32_TO_35(paddr_rri_on_ddr); |
| 2609 | |
| 2610 | HIF_ERROR("%s using srri and drri from DDR\n", __func__); |
| 2611 | |
| 2612 | WRITE_CE_DDR_ADDRESS_FOR_RRI_LOW(scn, low_paddr); |
| 2613 | WRITE_CE_DDR_ADDRESS_FOR_RRI_HIGH(scn, high_paddr); |
| 2614 | |
| 2615 | for (i = 0; i < CE_COUNT; i++) |
| 2616 | CE_IDX_UPD_EN_SET(scn, CE_BASE_ADDRESS(i)); |
| 2617 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2618 | qdf_mem_zero(scn->vaddr_rri_on_ddr, CE_COUNT*sizeof(uint32_t)); |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2619 | |
| 2620 | return; |
| 2621 | } |
| 2622 | #else |
| 2623 | |
| 2624 | /** |
| 2625 | * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism |
| 2626 | * |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2627 | * @scn: hif_softc pointer |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2628 | * |
| 2629 | * This is a dummy implementation for platforms that don't |
| 2630 | * support this functionality. |
| 2631 | * |
| 2632 | * Return: None |
| 2633 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2634 | static inline void hif_config_rri_on_ddr(struct hif_softc *scn) |
Sanjay Devnani | b925d7e | 2015-11-12 14:43:58 -0800 | [diff] [blame] | 2635 | { |
| 2636 | return; |
| 2637 | } |
| 2638 | #endif |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2639 | |
| 2640 | /** |
| 2641 | * hif_dump_ce_registers() - dump ce registers |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2642 | * @scn: hif_opaque_softc pointer. |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2643 | * |
| 2644 | * Output the copy engine registers |
| 2645 | * |
| 2646 | * Return: 0 for success or error code |
| 2647 | */ |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2648 | int hif_dump_ce_registers(struct hif_softc *scn) |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2649 | { |
Komal Seelam | 5584a7c | 2016-02-24 19:22:48 +0530 | [diff] [blame] | 2650 | struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(scn); |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2651 | uint32_t ce_reg_address = CE0_BASE_ADDRESS; |
| 2652 | uint32_t ce_reg_values[CE_COUNT_MAX][CE_USEFUL_SIZE >> 2]; |
| 2653 | uint32_t ce_reg_word_size = CE_USEFUL_SIZE >> 2; |
| 2654 | uint16_t i; |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2655 | QDF_STATUS status; |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2656 | |
Houston Hoffman | d6f946c | 2016-04-06 15:16:00 -0700 | [diff] [blame] | 2657 | for (i = 0; i < scn->ce_count; i++, ce_reg_address += CE_OFFSET) { |
| 2658 | if (scn->ce_id_to_state[i] == NULL) { |
| 2659 | HIF_DBG("CE%d not used.", i); |
| 2660 | continue; |
| 2661 | } |
| 2662 | |
Komal Seelam | 644263d | 2016-02-22 20:45:49 +0530 | [diff] [blame] | 2663 | status = hif_diag_read_mem(hif_hdl, ce_reg_address, |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2664 | (uint8_t *) &ce_reg_values[i][0], |
| 2665 | ce_reg_word_size * sizeof(uint32_t)); |
| 2666 | |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2667 | if (status != QDF_STATUS_SUCCESS) { |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2668 | HIF_ERROR("Dumping CE register failed!"); |
| 2669 | return -EACCES; |
| 2670 | } |
| 2671 | HIF_ERROR("CE%d Registers:", i); |
Chouhan, Anurag | fc06aa9 | 2016-03-03 19:05:05 +0530 | [diff] [blame] | 2672 | qdf_trace_hex_dump(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG, |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2673 | (uint8_t *) &ce_reg_values[i][0], |
| 2674 | ce_reg_word_size * sizeof(uint32_t)); |
| 2675 | } |
Govind Singh | 2443fb3 | 2016-01-13 17:44:48 +0530 | [diff] [blame] | 2676 | return 0; |
| 2677 | } |