| commit | d87a3b89cb5535dc222237e6d48b923523673bbb | [log] [tgz] |
|---|---|---|
| author | sheenam monga <shebala@codeaurora.org> | Tue Dec 17 16:34:25 2019 +0530 |
| committer | nshrivas <nshrivas@codeaurora.org> | Sat Dec 21 12:15:05 2019 -0800 |
| tree | 87b49540046ba877339b366fb664121d839a5513 | |
| parent | febc981b59229ab93b7d869001fb451ac1448be1 [diff] |
qcacld-3.0: Handle bus bandwidth in start and stop modules Currently, bus bandwidth is initialized and deinitialized in different memory domains which may cause leaks due to async bandwidth init and deinit. Fix is to initialize and de-initialize bus bandwidth in active domain. Change-Id: I67cf9ecdd47c8f3ca6e9b272ca379f0cac9a6c7b CRs-Fixed: 2568881