Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1 | /* |
Ahmad Kholaif | 30a966e | 2016-02-08 15:58:32 -0800 | [diff] [blame] | 2 | * Copyright (c) 2004-2010, 2013-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __WLANDEFS_H__ |
| 29 | #define __WLANDEFS_H__ |
| 30 | |
| 31 | /* A_COMPILE_TIME_ASSERT */ |
| 32 | #include <a_osapi.h> |
| 33 | #include <osdep.h> |
| 34 | |
| 35 | /* |
| 36 | * This file contains WLAN definitions that may be used across both |
| 37 | * Host and Target software. |
| 38 | */ |
| 39 | /* |
| 40 | * MAX_SPATIAL_STREAM should be defined in a fwconfig_xxx.h file, |
| 41 | * but for now provide a default value here in case it's not defined |
| 42 | * in the fwconfig_xxx.h file. |
| 43 | */ |
| 44 | #ifndef MAX_SPATIAL_STREAM |
| 45 | #define MAX_SPATIAL_STREAM 3 |
| 46 | #endif |
| 47 | |
| 48 | /* |
| 49 | * MAX_SPATIAL_STREAM_ANY - |
| 50 | * what is the largest number of spatial streams that any target supports |
| 51 | */ |
| 52 | #define MAX_SPATIAL_STREAM_ANY 4 |
| 53 | |
| 54 | #ifndef CONFIG_160MHZ_SUPPORT |
| 55 | #define CONFIG_160MHZ_SUPPORT 0 |
| 56 | #endif |
| 57 | |
Govind Singh | d24f5e4 | 2016-02-22 15:16:46 +0530 | [diff] [blame] | 58 | #ifndef SUPPORT_11AX |
| 59 | #define SUPPORT_11AX 0 /* 11ax not supported by default */ |
| 60 | #endif |
| 61 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 62 | typedef enum { |
| 63 | MODE_11A = 0, /* 11a Mode */ |
| 64 | MODE_11G = 1, /* 11b/g Mode */ |
| 65 | MODE_11B = 2, /* 11b Mode */ |
| 66 | MODE_11GONLY = 3, /* 11g only Mode */ |
| 67 | MODE_11NA_HT20 = 4, /* 11a HT20 mode */ |
| 68 | MODE_11NG_HT20 = 5, /* 11g HT20 mode */ |
| 69 | MODE_11NA_HT40 = 6, /* 11a HT40 mode */ |
| 70 | MODE_11NG_HT40 = 7, /* 11g HT40 mode */ |
| 71 | MODE_11AC_VHT20 = 8, |
| 72 | MODE_11AC_VHT40 = 9, |
| 73 | MODE_11AC_VHT80 = 10, |
| 74 | MODE_11AC_VHT20_2G = 11, |
| 75 | MODE_11AC_VHT40_2G = 12, |
| 76 | MODE_11AC_VHT80_2G = 13, |
| 77 | #if CONFIG_160MHZ_SUPPORT != 0 |
| 78 | MODE_11AC_VHT80_80 = 14, |
| 79 | MODE_11AC_VHT160 = 15, |
| 80 | #endif |
| 81 | |
Govind Singh | d24f5e4 | 2016-02-22 15:16:46 +0530 | [diff] [blame] | 82 | #if SUPPORT_11AX |
| 83 | MODE_11AX_HE20 = 16, |
| 84 | MODE_11AX_HE40 = 17, |
| 85 | MODE_11AX_HE80 = 18, |
| 86 | MODE_11AX_HE80_80 = 19, |
| 87 | MODE_11AX_HE160 = 20, |
| 88 | MODE_11AX_HE20_2G = 21, |
| 89 | MODE_11AX_HE40_2G = 22, |
| 90 | MODE_11AX_HE80_2G = 23, |
| 91 | #endif |
| 92 | |
| 93 | /* |
| 94 | * MODE_UNKNOWN should not be used within the host / target interface. |
| 95 | * Thus, it is permissible for ODE_UNKNOWN to be conditionally-defined, |
| 96 | * taking different values when compiling for different targets. |
| 97 | */ |
| 98 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 99 | MODE_UNKNOWN, |
Govind Singh | d24f5e4 | 2016-02-22 15:16:46 +0530 | [diff] [blame] | 100 | MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */ |
| 101 | /* MODE_UNKNOWN_NO_11AX_SUPPORT = 16,*/ /* not needed? */ |
| 102 | /* MODE_UNKNOWN_11AX_SUPPORT = 24,*/ /* not needed? */ |
| 103 | MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */ |
| 104 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 105 | MODE_MAX = MODE_UNKNOWN, |
| 106 | MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, |
| 107 | MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, |
| 108 | } WLAN_PHY_MODE; |
| 109 | |
| 110 | #if CONFIG_160MHZ_SUPPORT == 0 |
| 111 | A_COMPILE_TIME_ASSERT( |
| 112 | mode_unknown_value_consistency_Check, |
| 113 | MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT); |
| 114 | #else |
| 115 | A_COMPILE_TIME_ASSERT( |
| 116 | mode_unknown_value_consistency_Check, |
| 117 | MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT); |
| 118 | #endif |
| 119 | |
| 120 | typedef enum { |
| 121 | VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */ |
| 122 | VHT_MODE_20M = 1, |
| 123 | VHT_MODE_40M = 2, |
| 124 | VHT_MODE_80M = 3, |
| 125 | VHT_MODE_160M = 4 |
| 126 | } VHT_OPER_MODE; |
| 127 | |
| 128 | typedef enum { |
| 129 | WLAN_11A_CAPABILITY = 1, |
| 130 | WLAN_11G_CAPABILITY = 2, |
| 131 | WLAN_11AG_CAPABILITY = 3, |
| 132 | } WLAN_CAPABILITY; |
| 133 | |
| 134 | #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) |
| 135 | #define A_RATEMASK A_UINT64 |
| 136 | #else |
| 137 | #define A_RATEMASK A_UINT32 |
| 138 | #endif |
| 139 | |
| 140 | #define A_RATEMASK_NUM_OCTET (sizeof (A_RATEMASK)) |
| 141 | #define A_RATEMASK_NUM_BITS ((sizeof (A_RATEMASK)) << 3) |
| 142 | |
| 143 | #if CONFIG_160MHZ_SUPPORT != 0 |
| 144 | #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ |
| 145 | ((mode) == MODE_11AC_VHT40) || \ |
| 146 | ((mode) == MODE_11AC_VHT80) || \ |
| 147 | ((mode) == MODE_11AC_VHT80_80) || \ |
| 148 | ((mode) == MODE_11AC_VHT160)) |
| 149 | #else |
| 150 | #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ |
| 151 | ((mode) == MODE_11AC_VHT40) || \ |
| 152 | ((mode) == MODE_11AC_VHT80)) |
| 153 | #endif |
| 154 | |
Krishna Kumaar Natarajan | 489bf8d | 2016-03-25 14:30:11 -0700 | [diff] [blame] | 155 | #define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \ |
| 156 | ((mode) == MODE_11AX_HE40) || \ |
| 157 | ((mode) == MODE_11AX_HE80) || \ |
| 158 | ((mode) == MODE_11AX_HE80_80) || \ |
| 159 | ((mode) == MODE_11AX_HE160) || \ |
| 160 | ((mode) == MODE_11AX_HE20_2G) || \ |
| 161 | ((mode) == MODE_11AX_HE40_2G) || \ |
| 162 | ((mode) == MODE_11AX_HE80_2G)) |
| 163 | |
| 164 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 165 | #define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ |
| 166 | ((mode) == MODE_11AC_VHT40_2G) || \ |
| 167 | ((mode) == MODE_11AC_VHT80_2G)) |
| 168 | |
| 169 | #define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ |
| 170 | ((mode) == MODE_11NA_HT20) || \ |
| 171 | ((mode) == MODE_11NA_HT40) || \ |
| 172 | (IS_MODE_VHT(mode))) |
| 173 | |
| 174 | #define IS_MODE_11B(mode) ((mode) == MODE_11B) |
| 175 | #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ |
| 176 | ((mode) == MODE_11GONLY) || \ |
| 177 | ((mode) == MODE_11NG_HT20) || \ |
| 178 | ((mode) == MODE_11NG_HT40) || \ |
| 179 | (IS_MODE_VHT_2G(mode))) |
| 180 | #define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \ |
| 181 | ((mode) == MODE_11NG_HT40)) |
| 182 | #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) |
| 183 | |
| 184 | enum { |
| 185 | /* 11a channels */ |
| 186 | REGDMN_MODE_11A = 0x00000001, |
| 187 | /* 11a turbo-only channels */ |
| 188 | REGDMN_MODE_TURBO = 0x00000002, |
| 189 | /* 11b channels */ |
| 190 | REGDMN_MODE_11B = 0x00000004, |
| 191 | /* 11g channels (OFDM only) */ |
| 192 | REGDMN_MODE_PUREG = 0x00000008, |
| 193 | /* XXX historical */ |
| 194 | REGDMN_MODE_11G = 0x00000008, |
| 195 | /* 11g+Turbo channels */ |
| 196 | REGDMN_MODE_108G = 0x00000020, |
| 197 | /* 11a+Turbo channels */ |
| 198 | REGDMN_MODE_108A = 0x00000040, |
| 199 | /* XR channels */ |
| 200 | REGDMN_MODE_XR = 0x00000100, |
| 201 | /* 11A half rate channels */ |
| 202 | REGDMN_MODE_11A_HALF_RATE = 0x00000200, |
| 203 | /* 11A quarter rate channels */ |
| 204 | REGDMN_MODE_11A_QUARTER_RATE = 0x00000400, |
| 205 | /* 11N-G HT20 channels */ |
| 206 | REGDMN_MODE_11NG_HT20 = 0x00000800, |
| 207 | /* 11N-A HT20 channels */ |
| 208 | REGDMN_MODE_11NA_HT20 = 0x00001000, |
| 209 | /* 11N-G HT40 + channels */ |
| 210 | REGDMN_MODE_11NG_HT40PLUS = 0x00002000, |
| 211 | /* 11N-G HT40 - channels */ |
| 212 | REGDMN_MODE_11NG_HT40MINUS = 0x00004000, |
| 213 | /* 11N-A HT40 + channels */ |
| 214 | REGDMN_MODE_11NA_HT40PLUS = 0x00008000, |
| 215 | /* 11N-A HT40 - channels */ |
| 216 | REGDMN_MODE_11NA_HT40MINUS = 0x00010000, |
| 217 | /* 5Ghz, VHT20 */ |
| 218 | REGDMN_MODE_11AC_VHT20 = 0x00020000, |
| 219 | /* 5Ghz, VHT40 + channels */ |
| 220 | REGDMN_MODE_11AC_VHT40PLUS = 0x00040000, |
| 221 | /* 5Ghz VHT40 - channels */ |
| 222 | REGDMN_MODE_11AC_VHT40MINUS = 0x00080000, |
| 223 | /* 5Ghz, VHT80 channels */ |
| 224 | REGDMN_MODE_11AC_VHT80 = 0x000100000, |
| 225 | REGDMN_MODE_11AC_VHT20_2G = 0x000200000, /* 2Ghz, VHT20 */ |
| 226 | REGDMN_MODE_11AC_VHT40_2G = 0x000400000, /* 2Ghz, VHT40 */ |
| 227 | REGDMN_MODE_11AC_VHT80_2G = 0x000800000, /* 2Ghz, VHT80 */ |
| 228 | REGDMN_MODE_11AC_VHT160 = 0x001000000, /* 5Ghz, VHT160 */ |
Manikandan Mohan | 7a32f7e | 2015-12-23 12:35:12 -0800 | [diff] [blame] | 229 | REGDMN_MODE_11AC_VHT40_2GPLUS = 0x002000000, /* 2Ghz, VHT40+ */ |
| 230 | REGDMN_MODE_11AC_VHT40_2GMINUS = 0x004000000, /* 2Ghz, VHT40- */ |
| 231 | REGDMN_MODE_11AC_VHT80_80 = 0x008000000, /* 5GHz, VHT80+80 */ |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 232 | }; |
| 233 | |
| 234 | #define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum |
| 235 | * to prevent the ARM compile "warning #66: |
| 236 | * enumeration value is out of int range" |
| 237 | * Anyway, this is a BIT-OR of all possible values. |
| 238 | */ |
| 239 | |
| 240 | #define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001 |
| 241 | #define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002 |
| 242 | #define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004 |
| 243 | |
| 244 | /* regulatory capabilities */ |
| 245 | #define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 |
| 246 | #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 |
| 247 | #define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100 |
| 248 | #define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 |
| 249 | #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 |
| 250 | #define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 |
| 251 | |
| 252 | typedef struct { |
| 253 | A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */ |
| 254 | A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */ |
| 255 | A_UINT32 eeprom_rd_ext; /* regdomain */ |
| 256 | A_UINT32 regcap1; /* CAP1 capabilities bit map. */ |
| 257 | A_UINT32 regcap2; /* REGDMN EEPROM CAP. */ |
| 258 | A_UINT32 wireless_modes; /* REGDMN MODE */ |
| 259 | A_UINT32 low_2ghz_chan; |
| 260 | A_UINT32 high_2ghz_chan; |
| 261 | A_UINT32 low_5ghz_chan; |
| 262 | A_UINT32 high_5ghz_chan; |
| 263 | } HAL_REG_CAPABILITIES; |
| 264 | |
| 265 | typedef enum { |
| 266 | WHAL_REG_EXT_FCC_MIDBAND = 0, |
| 267 | WHAL_REG_EXT_JAPAN_MIDBAND = 1, |
| 268 | WHAL_REG_EXT_FCC_DFS_HT40 = 2, |
| 269 | WHAL_REG_EXT_JAPAN_NONDFS_HT40 = 3, |
| 270 | WHAL_REG_EXT_JAPAN_DFS_HT40 = 4, |
| 271 | WHAL_REG_EXT_FCC_CH_144 = 5, |
| 272 | } WHAL_REG_EXT_BITMAP; |
| 273 | |
| 274 | /* |
| 275 | * Used to update rate-control logic with the status of the tx-completion. |
| 276 | * In host-based implementation of the rate-control feature, this struture is used to |
| 277 | * create the payload for HTT message/s from target to host. |
| 278 | */ |
| 279 | |
| 280 | typedef struct { |
| 281 | A_UINT8 rateCode; |
| 282 | A_UINT8 flags; |
| 283 | } RATE_CODE; |
| 284 | |
| 285 | typedef struct { |
| 286 | RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */ |
| 287 | A_UINT8 reserved[2]; |
| 288 | A_UINT32 flags; /* Encodes information such as excessive |
| 289 | retransmission, aggregate, some info |
| 290 | from .11 frame control, |
| 291 | STBC, LDPC, (SGI and Tx Chain Mask |
| 292 | are encoded in ptx_rc->flags field), |
| 293 | AMPDU truncation (BT/time based etc.), |
| 294 | RTS/CTS attempt */ |
| 295 | A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ |
| 296 | A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ |
| 297 | A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ |
| 298 | A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ |
| 299 | A_UINT32 time_stamp; /* ACK timestamp (helps determine age) */ |
| 300 | A_UINT32 is_probe; /* Valid if probing. Else, 0 */ |
| 301 | A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */ |
| 302 | A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */ |
| 303 | A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */ |
| 304 | A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */ |
| 305 | A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */ |
| 306 | } RC_TX_DONE_PARAMS; |
| 307 | |
| 308 | #define RC_SET_TX_DONE_INFO(_dst, _rc, _f, _nq, _nr, _nf, _rssi, _ts) \ |
| 309 | do { \ |
| 310 | (_dst).ptx_rc.rateCode = (_rc).rateCode; \ |
| 311 | (_dst).ptx_rc.flags = (_rc).flags; \ |
| 312 | (_dst).flags = (_f); \ |
| 313 | (_dst).num_enqued = (_nq); \ |
| 314 | (_dst).num_retries = (_nr); \ |
| 315 | (_dst).num_failed = (_nf); \ |
| 316 | (_dst).ack_rssi = (_rssi); \ |
| 317 | (_dst).time_stamp = (_ts); \ |
| 318 | } while (0) |
| 319 | |
| 320 | #define RC_SET_TXBF_DONE_INFO(_dst, _f) \ |
| 321 | do { \ |
| 322 | (_dst).flags |= (_f); \ |
| 323 | } while (0) |
| 324 | |
| 325 | /* NOTE: NUM_DYN_BW and NUM_SCHED_ENTRIES cannot be changed without breaking WMI Compatibility */ |
| 326 | #define NUM_SCHED_ENTRIES 2 |
| 327 | #define NUM_DYN_BW_MAX 4 |
| 328 | |
| 329 | /* Some products only use 20/40/80; some use 20/40/80/160 */ |
| 330 | #ifndef NUM_DYN_BW |
| 331 | /* default: support up through 80 MHz */ |
| 332 | #define NUM_DYN_BW 3 |
| 333 | #endif |
| 334 | |
| 335 | #define NUM_DYN_BW_MASK 0x3 |
| 336 | |
| 337 | #define PROD_SCHED_BW_ENTRIES (NUM_SCHED_ENTRIES * NUM_DYN_BW) |
| 338 | typedef A_UINT8 A_RATE; |
| 339 | |
| 340 | #if NUM_DYN_BW > 4 |
| 341 | /* Extend rate table module first*/ |
| 342 | #error "Extend rate table module first" |
| 343 | #endif |
| 344 | |
| 345 | #define MAX_IBSS_PEERS 32 |
| 346 | |
| 347 | #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) |
| 348 | typedef struct { |
| 349 | A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 350 | A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW]; |
| 351 | A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW]; |
| 352 | A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW]; |
| 353 | A_UINT32 antmask[NUM_SCHED_ENTRIES]; |
| 354 | A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 355 | A_UINT16 txbf_cv_len; |
| 356 | A_UINT32 txbf_cv_ptr; |
| 357 | A_UINT16 txbf_flags; |
| 358 | A_UINT16 txbf_cv_size; |
| 359 | A_UINT8 txbf_nc_idx; |
| 360 | A_UINT8 tries[NUM_SCHED_ENTRIES]; |
| 361 | A_UINT8 bw_mask[NUM_SCHED_ENTRIES]; |
| 362 | A_UINT8 max_bw[NUM_SCHED_ENTRIES]; |
| 363 | A_UINT8 num_sched_entries; |
| 364 | A_UINT8 paprd_mask; |
| 365 | A_UINT8 rts_rix; |
| 366 | A_UINT8 sh_pream; |
| 367 | A_UINT8 min_spacing_1_4_us; |
| 368 | A_UINT8 fixed_delims; |
| 369 | A_UINT8 bw_in_service; |
| 370 | A_RATE probe_rix; |
| 371 | A_UINT8 num_valid_rates; |
| 372 | A_UINT8 rtscts_tpc; |
Manikandan Mohan | 46b95c0 | 2015-12-09 12:23:08 -0800 | [diff] [blame] | 373 | A_UINT8 dd_profile; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 374 | } RC_TX_RATE_SCHEDULE; |
| 375 | |
| 376 | #else |
| 377 | typedef struct { |
| 378 | A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 379 | A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 380 | A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 381 | A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 382 | A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 383 | A_UINT32 antmask[NUM_SCHED_ENTRIES]; |
| 384 | A_UINT32 txbf_cv_ptr; |
| 385 | A_UINT16 txbf_cv_len; |
| 386 | A_UINT8 tries[NUM_SCHED_ENTRIES]; |
| 387 | A_UINT8 num_valid_rates; |
| 388 | A_UINT8 paprd_mask; |
| 389 | A_UINT8 rts_rix; |
| 390 | A_UINT8 sh_pream; |
| 391 | A_UINT8 min_spacing_1_4_us; |
| 392 | A_UINT8 fixed_delims; |
| 393 | A_UINT8 bw_in_service; |
| 394 | A_RATE probe_rix; |
| 395 | } RC_TX_RATE_SCHEDULE; |
| 396 | #endif |
| 397 | |
| 398 | typedef struct { |
| 399 | A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 400 | A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 401 | #ifdef DYN_TPC_ENABLE |
| 402 | A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; |
| 403 | #endif |
| 404 | #ifdef SECTORED_ANTENNA |
| 405 | A_UINT32 antmask[NUM_SCHED_ENTRIES]; |
| 406 | #endif |
| 407 | A_UINT8 tries[NUM_SCHED_ENTRIES]; |
| 408 | A_UINT8 num_valid_rates; |
| 409 | A_UINT8 rts_rix; |
| 410 | A_UINT8 sh_pream; |
| 411 | A_UINT8 bw_in_service; |
| 412 | A_RATE probe_rix; |
| 413 | A_UINT8 dd_profile; |
| 414 | } RC_TX_RATE_INFO; |
| 415 | |
| 416 | /* |
| 417 | * Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defsh |
| 418 | * for older targets. |
| 419 | * The WHAL_RX_INIT_RC_MASKS macro def needs to be moved into ratectrl_11ac.h |
| 420 | * for all targets, but until this is complete, the WHAL_RC_INIT_RC_MASKS def |
| 421 | * will be maintained here in its old location. |
| 422 | */ |
| 423 | #if CONFIG_160MHZ_SUPPORT == 0 |
| 424 | |
| 425 | #define WHAL_RC_INIT_RC_MASKS(_rm) do { \ |
| 426 | _rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \ |
| 427 | _rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \ |
| 428 | _rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \ |
| 429 | _rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \ |
| 430 | _rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \ |
| 431 | _rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \ |
| 432 | } while (0) |
| 433 | #endif |
| 434 | |
| 435 | /** |
| 436 | * strucutre describing host memory chunk. |
| 437 | */ |
| 438 | typedef struct { |
| 439 | A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */ |
| 440 | /** id of the request that is passed up in service ready */ |
| 441 | A_UINT32 req_id; |
| 442 | /** the physical address the memory chunk */ |
| 443 | A_UINT32 ptr; |
| 444 | /** size of the chunk */ |
| 445 | A_UINT32 size; |
| 446 | } wlan_host_memory_chunk; |
| 447 | |
Manikandan Mohan | 7a32f7e | 2015-12-23 12:35:12 -0800 | [diff] [blame] | 448 | #define NUM_UNITS_IS_NUM_VDEVS 0x1 |
| 449 | #define NUM_UNITS_IS_NUM_PEERS 0x2 |
| 450 | #define NUM_UNITS_IS_NUM_ACTIVE_PEERS 0x4 |
| 451 | /* request host to allocate memory contiguously */ |
| 452 | #define REQ_TO_HOST_FOR_CONT_MEMORY 0x8 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 453 | |
| 454 | /** |
| 455 | * structure used by FW for requesting host memory |
| 456 | */ |
| 457 | typedef struct { |
| 458 | A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */ |
| 459 | |
| 460 | /** ID of the request */ |
| 461 | A_UINT32 req_id; |
| 462 | /** size of the of each unit */ |
| 463 | A_UINT32 unit_size; |
| 464 | /** |
| 465 | * flags to indicate that |
| 466 | * the number units is dependent |
| 467 | * on number of resources(num vdevs num peers .. etc) |
| 468 | */ |
| 469 | A_UINT32 num_unit_info; |
| 470 | /* |
| 471 | * actual number of units to allocate . if flags in the num_unit_info |
| 472 | * indicate that number of units is tied to number of a particular |
| 473 | * resource to allocate then num_units filed is set to 0 and host |
| 474 | * will derive the number units from number of the resources it is |
| 475 | * requesting. |
| 476 | */ |
| 477 | A_UINT32 num_units; |
| 478 | } wlan_host_mem_req; |
| 479 | |
| 480 | typedef enum { |
| 481 | IGNORE_DTIM = 0x01, |
| 482 | NORMAL_DTIM = 0x02, |
| 483 | STICK_DTIM = 0x03, |
| 484 | AUTO_DTIM = 0x04, |
| 485 | } BEACON_DTIM_POLICY; |
| 486 | |
| 487 | /* During test it is observed that 6 * 400 = 2400 can |
| 488 | * be alloced in addition to CFG_TGT_NUM_MSDU_DESC. |
| 489 | * If there is any change memory requirement, this number |
| 490 | * needs to be revisited. */ |
| 491 | #define TOTAL_VOW_ALLOCABLE 2400 |
| 492 | #define VOW_DESC_GRAB_MAX 800 |
| 493 | |
| 494 | #define VOW_GET_NUM_VI_STA(vow_config) (((vow_config) & 0xffff0000) >> 16) |
| 495 | #define VOW_GET_DESC_PER_VI_STA(vow_config) ((vow_config) & 0x0000ffff) |
| 496 | |
| 497 | /***TODO!!! Get these values dynamically in WMI_READY event and use it to calculate the mem req*/ |
| 498 | /* size in bytes required for msdu descriptor. If it changes, this should be updated. LARGE_AP |
| 499 | * case is not considered. LARGE_AP is disabled when VoW is enabled.*/ |
| 500 | #define MSDU_DESC_SIZE 20 |
| 501 | |
| 502 | /* size in bytes required to support a peer in target. |
| 503 | * This obtained by considering Two tids per peer. |
| 504 | * peer structure = 168 bytes |
| 505 | * tid = 96 bytes (per sta 2 means we need 192 bytes) |
| 506 | * peer_cb = 16 * 2 |
| 507 | * key = 52 * 2 |
| 508 | * AST = 12 * 2 |
| 509 | * rate, reorder.. = 384 |
| 510 | * smart antenna = 50 |
| 511 | */ |
| 512 | #define MEMORY_REQ_FOR_PEER 800 |
| 513 | |
| 514 | /* |
| 515 | * NB: it is important to keep all the fields in the structure dword long |
| 516 | * so that it is easy to handle the statistics in BE host. |
| 517 | */ |
| 518 | |
| 519 | struct wlan_dbg_tx_stats { |
| 520 | /* Num HTT cookies queued to dispatch list */ |
| 521 | A_INT32 comp_queued; |
| 522 | /* Num HTT cookies dispatched */ |
| 523 | A_INT32 comp_delivered; |
| 524 | /* Num MSDU queued to WAL */ |
| 525 | A_INT32 msdu_enqued; |
| 526 | /* Num MPDU queue to WAL */ |
| 527 | A_INT32 mpdu_enqued; |
| 528 | /* Num MSDUs dropped by WMM limit */ |
| 529 | A_INT32 wmm_drop; |
| 530 | /* Num Local frames queued */ |
| 531 | A_INT32 local_enqued; |
| 532 | /* Num Local frames done */ |
| 533 | A_INT32 local_freed; |
| 534 | /* Num queued to HW */ |
| 535 | A_INT32 hw_queued; |
| 536 | /* Num PPDU reaped from HW */ |
| 537 | A_INT32 hw_reaped; |
| 538 | /* Num underruns */ |
| 539 | A_INT32 underrun; |
| 540 | #if defined(AR900B) |
| 541 | /* HW Paused. */ |
| 542 | A_UINT32 hw_paused; |
| 543 | #endif |
| 544 | /* Num PPDUs cleaned up in TX abort */ |
| 545 | A_INT32 tx_abort; |
| 546 | /* Num MPDUs requed by SW */ |
| 547 | A_INT32 mpdus_requed; |
| 548 | /* excessive retries */ |
| 549 | A_UINT32 tx_ko; |
| 550 | #if defined(AR900B) |
| 551 | A_UINT32 tx_xretry; |
| 552 | #endif |
| 553 | /* data hw rate code */ |
| 554 | A_UINT32 data_rc; |
| 555 | /* Scheduler self triggers */ |
| 556 | A_UINT32 self_triggers; |
| 557 | /* frames dropped due to excessive sw retries */ |
| 558 | A_UINT32 sw_retry_failure; |
| 559 | /* illegal rate phy errors */ |
| 560 | A_UINT32 illgl_rate_phy_err; |
| 561 | /* wal pdev continous xretry */ |
| 562 | A_UINT32 pdev_cont_xretry; |
| 563 | /* wal pdev continous xretry */ |
| 564 | A_UINT32 pdev_tx_timeout; |
| 565 | /* wal pdev resets */ |
| 566 | A_UINT32 pdev_resets; |
| 567 | /* frames dropped due to non-availability of stateless TIDs */ |
| 568 | A_UINT32 stateless_tid_alloc_failure; |
| 569 | /* PhY/BB underrun */ |
| 570 | A_UINT32 phy_underrun; |
| 571 | /* MPDU is more than txop limit */ |
| 572 | A_UINT32 txop_ovf; |
| 573 | #if defined(AR900B) |
| 574 | /* Number of Sequences posted */ |
| 575 | A_UINT32 seq_posted; |
| 576 | /* Number of Sequences failed queueing */ |
| 577 | A_UINT32 seq_failed_queueing; |
| 578 | /* Number of Sequences completed */ |
| 579 | A_UINT32 seq_completed; |
| 580 | /* Number of Sequences restarted */ |
| 581 | A_UINT32 seq_restarted; |
| 582 | /* Number of MU Sequences posted */ |
| 583 | A_UINT32 mu_seq_posted; |
| 584 | /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ |
| 585 | A_INT32 mpdus_sw_flush; |
| 586 | /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ |
| 587 | A_INT32 mpdus_hw_filter; |
| 588 | /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ |
| 589 | A_INT32 mpdus_truncated; |
| 590 | /* Num MPDUs that was tried but didn't receive ACK or BA */ |
| 591 | A_INT32 mpdus_ack_failed; |
| 592 | /* Num MPDUs that was dropped du to expiry. */ |
| 593 | A_INT32 mpdus_expired; |
| 594 | /* Num mc drops */ |
| 595 | /* A_UINT32 mc_drop; */ |
| 596 | #endif |
| 597 | }; |
| 598 | |
| 599 | struct wlan_dbg_rx_stats { |
| 600 | /* Cnts any change in ring routing mid-ppdu */ |
| 601 | A_INT32 mid_ppdu_route_change; |
| 602 | /* Total number of statuses processed */ |
| 603 | A_INT32 status_rcvd; |
| 604 | /* Extra frags on rings 0-3 */ |
| 605 | A_INT32 r0_frags; |
| 606 | A_INT32 r1_frags; |
| 607 | A_INT32 r2_frags; |
| 608 | A_INT32 r3_frags; |
| 609 | /* MSDUs / MPDUs delivered to HTT */ |
| 610 | A_INT32 htt_msdus; |
| 611 | A_INT32 htt_mpdus; |
| 612 | /* MSDUs / MPDUs delivered to local stack */ |
| 613 | A_INT32 loc_msdus; |
| 614 | A_INT32 loc_mpdus; |
| 615 | /* AMSDUs that have more MSDUs than the status ring size */ |
| 616 | A_INT32 oversize_amsdu; |
| 617 | /* Number of PHY errors */ |
| 618 | A_INT32 phy_errs; |
| 619 | /* Number of PHY errors drops */ |
| 620 | A_INT32 phy_err_drop; |
| 621 | /* Number of mpdu errors - FCS, MIC, ENC etc. */ |
| 622 | A_INT32 mpdu_errs; |
| 623 | #if defined(AR900B) |
| 624 | /* Number of rx overflow errors. */ |
| 625 | A_INT32 rx_ovfl_errs; |
| 626 | #endif |
| 627 | }; |
| 628 | |
| 629 | struct wlan_dbg_mem_stats { |
| 630 | A_UINT32 iram_free_size; |
| 631 | A_UINT32 dram_free_size; |
| 632 | }; |
| 633 | |
| 634 | struct wlan_dbg_peer_stats { |
| 635 | |
| 636 | A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ |
| 637 | }; |
| 638 | |
| 639 | typedef struct { |
| 640 | A_UINT32 mcs[10]; |
| 641 | A_UINT32 sgi[10]; |
| 642 | A_UINT32 nss[4]; |
| 643 | A_UINT32 nsts; |
| 644 | A_UINT32 stbc[10]; |
| 645 | A_UINT32 bw[3]; |
| 646 | A_UINT32 pream[6]; |
| 647 | A_UINT32 ldpc; |
| 648 | A_UINT32 txbf; |
| 649 | A_UINT32 mgmt_rssi; |
| 650 | A_UINT32 data_rssi; |
| 651 | A_UINT32 rssi_chain0; |
| 652 | A_UINT32 rssi_chain1; |
| 653 | A_UINT32 rssi_chain2; |
| 654 | #if defined(AR900B) |
| 655 | A_UINT32 rssi_chain3; |
| 656 | #endif |
| 657 | } wlan_dbg_rx_rate_info_t; |
| 658 | |
| 659 | typedef struct { |
| 660 | A_UINT32 mcs[10]; |
| 661 | A_UINT32 sgi[10]; |
| 662 | #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) |
| 663 | A_UINT32 nss[4]; |
| 664 | #else |
| 665 | A_UINT32 nss[3]; |
| 666 | #endif |
| 667 | A_UINT32 stbc[10]; |
| 668 | A_UINT32 bw[3]; |
| 669 | A_UINT32 pream[4]; |
| 670 | A_UINT32 ldpc; |
| 671 | A_UINT32 rts_cnt; |
| 672 | A_UINT32 ack_rssi; |
| 673 | } wlan_dbg_tx_rate_info_t ; |
| 674 | |
| 675 | #define WLAN_MAX_MCS 10 |
| 676 | |
| 677 | typedef struct { |
| 678 | A_UINT32 mcs[WLAN_MAX_MCS]; |
| 679 | A_UINT32 sgi[WLAN_MAX_MCS]; |
| 680 | A_UINT32 nss[MAX_SPATIAL_STREAM_ANY]; |
| 681 | A_UINT32 nsts; |
| 682 | A_UINT32 stbc[WLAN_MAX_MCS]; |
| 683 | A_UINT32 bw[NUM_DYN_BW_MAX]; |
| 684 | A_UINT32 pream[6]; |
| 685 | A_UINT32 ldpc; |
| 686 | A_UINT32 txbf; |
| 687 | A_UINT32 mgmt_rssi; |
| 688 | A_UINT32 data_rssi; |
| 689 | A_UINT32 rssi_chain0; |
| 690 | A_UINT32 rssi_chain1; |
| 691 | A_UINT32 rssi_chain2; |
| 692 | A_UINT32 rssi_chain3; |
| 693 | A_UINT32 reserved[8]; |
| 694 | } wlan_dbg_rx_rate_info_v2_t ; |
| 695 | |
| 696 | typedef struct { |
| 697 | A_UINT32 mcs[WLAN_MAX_MCS]; |
| 698 | A_UINT32 sgi[WLAN_MAX_MCS]; |
| 699 | A_UINT32 nss[MAX_SPATIAL_STREAM_ANY]; |
| 700 | A_UINT32 stbc[WLAN_MAX_MCS]; |
| 701 | A_UINT32 bw[NUM_DYN_BW_MAX]; |
| 702 | A_UINT32 pream[4]; |
| 703 | A_UINT32 ldpc; |
| 704 | A_UINT32 rts_cnt; |
| 705 | A_UINT32 ack_rssi; |
| 706 | A_UINT32 reserved[8]; |
| 707 | } wlan_dbg_tx_rate_info_v2_t ; |
| 708 | |
| 709 | #define WHAL_DBG_PHY_ERR_MAXCNT 18 |
| 710 | #define WHAL_DBG_SIFS_STATUS_MAXCNT 8 |
| 711 | #define WHAL_DBG_SIFS_ERR_MAXCNT 8 |
Ahmad Kholaif | 30a966e | 2016-02-08 15:58:32 -0800 | [diff] [blame] | 712 | #define WHAL_DBG_CMD_RESULT_MAXCNT 11 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 713 | #define WHAL_DBG_CMD_STALL_ERR_MAXCNT 4 |
| 714 | #define WHAL_DBG_FLUSH_REASON_MAXCNT 40 |
| 715 | |
| 716 | typedef enum { |
| 717 | WIFI_URRN_STATS_FIRST_PKT, |
| 718 | WIFI_URRN_STATS_BETWEEN_MPDU, |
| 719 | WIFI_URRN_STATS_WITHIN_MPDU, |
| 720 | WHAL_MAX_URRN_STATS |
| 721 | } wifi_urrn_type_t; |
| 722 | |
| 723 | typedef struct wlan_dbg_txbf_snd_stats { |
| 724 | A_UINT32 cbf_20[4]; |
| 725 | A_UINT32 cbf_40[4]; |
| 726 | A_UINT32 cbf_80[4]; |
| 727 | A_UINT32 sounding[9]; |
Anurag Chouhan | fbaefe2 | 2016-04-28 15:06:31 +0530 | [diff] [blame] | 728 | A_UINT32 cbf_160[4]; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 729 | } wlan_dbg_txbf_snd_stats_t; |
| 730 | |
| 731 | typedef struct wlan_dbg_wifi2_error_stats { |
| 732 | A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS]; |
| 733 | A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT]; |
| 734 | A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; |
| 735 | A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT]; |
| 736 | A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT]; |
| 737 | A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT]; |
| 738 | A_UINT32 rx_rate_inval; |
| 739 | } wlan_dbg_wifi2_error_stats_t; |
| 740 | |
| 741 | typedef struct wlan_dbg_wifi2_error2_stats { |
| 742 | A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; |
| 743 | A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT]; |
| 744 | } wlan_dbg_wifi2_error2_stats_t; |
| 745 | |
| 746 | #define WLAN_DBG_STATS_SIZE_TXBF_VHT 10 |
| 747 | #define WLAN_DBG_STATS_SIZE_TXBF_HT 8 |
| 748 | #define WLAN_DBG_STATS_SIZE_TXBF_OFDM 8 |
| 749 | #define WLAN_DBG_STATS_SIZE_TXBF_CCK 7 |
| 750 | |
| 751 | typedef struct wlan_dbg_txbf_data_stats { |
| 752 | A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; |
| 753 | A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; |
| 754 | A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT]; |
| 755 | A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM]; |
| 756 | A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK]; |
| 757 | } wlan_dbg_txbf_data_stats_t; |
| 758 | |
| 759 | struct wlan_dbg_tx_mu_stats { |
| 760 | A_UINT32 mu_sch_nusers_2; |
| 761 | A_UINT32 mu_sch_nusers_3; |
| 762 | A_UINT32 mu_mpdus_queued_usr[4]; |
| 763 | A_UINT32 mu_mpdus_tried_usr[4]; |
| 764 | A_UINT32 mu_mpdus_failed_usr[4]; |
| 765 | A_UINT32 mu_mpdus_requeued_usr[4]; |
| 766 | A_UINT32 mu_err_no_ba_usr[4]; |
| 767 | A_UINT32 mu_mpdu_underrun_usr[4]; |
| 768 | A_UINT32 mu_ampdu_underrun_usr[4]; |
| 769 | }; |
| 770 | |
| 771 | struct wlan_dbg_tx_selfgen_stats { |
| 772 | A_UINT32 su_ndpa; |
| 773 | A_UINT32 su_ndp; |
| 774 | A_UINT32 mu_ndpa; |
| 775 | A_UINT32 mu_ndp; |
| 776 | A_UINT32 mu_brpoll_1; |
| 777 | A_UINT32 mu_brpoll_2; |
| 778 | A_UINT32 mu_bar_1; |
| 779 | A_UINT32 mu_bar_2; |
| 780 | A_UINT32 cts_burst; |
| 781 | A_UINT32 su_ndp_err; |
| 782 | A_UINT32 su_ndpa_err; |
| 783 | A_UINT32 mu_ndp_err; |
| 784 | A_UINT32 mu_brp1_err; |
| 785 | A_UINT32 mu_brp2_err; |
| 786 | }; |
| 787 | |
| 788 | typedef struct wlan_dbg_sifs_resp_stats { |
| 789 | A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */ |
| 790 | A_UINT32 uapsd_trigger; /* num uapsd trigger frames */ |
| 791 | A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */ |
| 792 | A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */ |
| 793 | A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */ |
| 794 | A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */ |
| 795 | } wlan_dgb_sifs_resp_stats_t; |
| 796 | |
| 797 | /** wlan_dbg_wifi2_error_stats_t is not grouped with the |
| 798 | * following structure as it is allocated differently and only |
| 799 | * belongs to whal |
| 800 | */ |
| 801 | typedef struct wlan_dbg_stats_wifi2 { |
| 802 | wlan_dbg_txbf_snd_stats_t txbf_snd_info; |
| 803 | wlan_dbg_txbf_data_stats_t txbf_data_info; |
| 804 | struct wlan_dbg_tx_selfgen_stats tx_selfgen; |
| 805 | struct wlan_dbg_tx_mu_stats tx_mu; |
| 806 | wlan_dgb_sifs_resp_stats_t sifs_resp_info; |
| 807 | } wlan_dbg_wifi2_stats_t; |
| 808 | |
| 809 | typedef struct { |
| 810 | wlan_dbg_rx_rate_info_t rx_phy_info; |
| 811 | wlan_dbg_tx_rate_info_t tx_rate_info; |
| 812 | } wlan_dbg_rate_info_t; |
| 813 | |
| 814 | typedef struct { |
| 815 | wlan_dbg_rx_rate_info_v2_t rx_phy_info; |
| 816 | wlan_dbg_tx_rate_info_v2_t tx_rate_info; |
| 817 | } wlan_dbg_rate_info_v2_t; |
| 818 | |
| 819 | struct wlan_dbg_stats { |
| 820 | struct wlan_dbg_tx_stats tx; |
| 821 | struct wlan_dbg_rx_stats rx; |
| 822 | #if defined(AR900B) |
| 823 | struct wlan_dbg_mem_stats mem; |
| 824 | #endif |
| 825 | struct wlan_dbg_peer_stats peer; |
| 826 | }; |
| 827 | |
| 828 | #define DBG_STATS_MAX_HWQ_NUM 10 |
| 829 | #define DBG_STATS_MAX_TID_NUM 20 |
| 830 | #define DBG_STATS_MAX_CONG_NUM 16 |
| 831 | struct wlan_dbg_txq_stats { |
| 832 | A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM]; |
| 833 | A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ |
| 834 | A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ |
| 835 | }; |
| 836 | |
| 837 | struct wlan_dbg_tidq_stats { |
| 838 | A_UINT32 wlan_dbg_tid_txq_status; |
| 839 | struct wlan_dbg_txq_stats txq_st; |
| 840 | }; |
| 841 | |
| 842 | #endif /* __WLANDEFS_H__ */ |