Blame - target/inc/efuse_reg.h - platform/vendor/qcom-opensource/wlan/qcacld-3.0

Prakash Dhavali

7090c5f

2015-11-02 17:55:19 -0800

[diff] [blame]

/*

*

* Previously licensed under the ISC license by Qualcomm Atheros, Inc.

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*

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*

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* Permission to use, copy, modify, and/or distribute this software for

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* any purpose with or without fee is hereby granted, provided that the

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* above copyright notice and this permission notice appear in all

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* copies.

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*

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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL

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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED

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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE

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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL

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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR

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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER

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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR

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* PERFORMANCE OF THIS SOFTWARE.

*/

/*

* This file was originally distributed by Qualcomm Atheros, Inc.

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* under proprietary terms before Copyright ownership was assigned

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* to the Linux Foundation.

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*/

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#ifndef _EFUSE_REG_REG_H_

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#define _EFUSE_REG_REG_H_

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#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000

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#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000

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#define EFUSE_WR_ENABLE_REG_V_MSB 0

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#define EFUSE_WR_ENABLE_REG_V_LSB 0

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#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001

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#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)

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#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)

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#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004

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#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004

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#define EFUSE_INT_ENABLE_REG_V_MSB 0

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#define EFUSE_INT_ENABLE_REG_V_LSB 0

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#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001

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#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)

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#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)

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#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008

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#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008

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#define EFUSE_INT_STATUS_REG_V_MSB 0

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#define EFUSE_INT_STATUS_REG_V_LSB 0

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#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001

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#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)

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#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)

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#define BITMASK_WR_REG_ADDRESS 0x0000000c

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#define BITMASK_WR_REG_OFFSET 0x0000000c

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#define BITMASK_WR_REG_V_MSB 31

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#define BITMASK_WR_REG_V_LSB 0

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#define BITMASK_WR_REG_V_MASK 0xffffffff

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#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)

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#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)

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#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010

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#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010

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#define VDDQ_SETTLE_TIME_REG_V_MSB 31

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#define VDDQ_SETTLE_TIME_REG_V_LSB 0

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#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff

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#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)

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#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)

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#define VDDQ_HOLD_TIME_REG_ADDRESS 0x00000014

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#define VDDQ_HOLD_TIME_REG_OFFSET 0x00000014

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#define VDDQ_HOLD_TIME_REG_V_MSB 31

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#define VDDQ_HOLD_TIME_REG_V_LSB 0

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#define VDDQ_HOLD_TIME_REG_V_MASK 0xffffffff

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#define VDDQ_HOLD_TIME_REG_V_GET(x) (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB)

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#define VDDQ_HOLD_TIME_REG_V_SET(x) (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK)

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#define RD_STROBE_PW_REG_ADDRESS 0x00000018

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#define RD_STROBE_PW_REG_OFFSET 0x00000018

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#define RD_STROBE_PW_REG_V_MSB 31

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#define RD_STROBE_PW_REG_V_LSB 0

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#define RD_STROBE_PW_REG_V_MASK 0xffffffff

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#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)

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#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)

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#define PG_STROBE_PW_REG_ADDRESS 0x0000001c

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#define PG_STROBE_PW_REG_OFFSET 0x0000001c

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#define PG_STROBE_PW_REG_V_MSB 31

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#define PG_STROBE_PW_REG_V_LSB 0

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#define PG_STROBE_PW_REG_V_MASK 0xffffffff

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#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)

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#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)

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#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS 0x00000020

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#define PGENB_SETUP_HOLD_TIME_REG_OFFSET 0x00000020

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#define PGENB_SETUP_HOLD_TIME_REG_V_MSB 31

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#define PGENB_SETUP_HOLD_TIME_REG_V_LSB 0

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#define PGENB_SETUP_HOLD_TIME_REG_V_MASK 0xffffffff

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#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x) (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB)

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#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x) (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK)

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#define STROBE_PULSE_INTERVAL_REG_ADDRESS 0x00000024

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#define STROBE_PULSE_INTERVAL_REG_OFFSET 0x00000024

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#define STROBE_PULSE_INTERVAL_REG_V_MSB 31

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#define STROBE_PULSE_INTERVAL_REG_V_LSB 0

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#define STROBE_PULSE_INTERVAL_REG_V_MASK 0xffffffff

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#define STROBE_PULSE_INTERVAL_REG_V_GET(x) (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB)

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#define STROBE_PULSE_INTERVAL_REG_V_SET(x) (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK)

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS 0x00000028

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET 0x00000028

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB 31

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB 0

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK 0xffffffff

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x) (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB)

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#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x) (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK)

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#define EFUSE_INTF0_ADDRESS 0x00000800

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#define EFUSE_INTF0_OFFSET 0x00000800

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#define EFUSE_INTF0_R_MSB 31

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#define EFUSE_INTF0_R_LSB 0

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#define EFUSE_INTF0_R_MASK 0xffffffff

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#define EFUSE_INTF0_R_GET(x) (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB)

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#define EFUSE_INTF0_R_SET(x) (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK)

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#define EFUSE_INTF1_ADDRESS 0x00001000

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#define EFUSE_INTF1_OFFSET 0x00001000

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#define EFUSE_INTF1_R_MSB 31

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#define EFUSE_INTF1_R_LSB 0

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#define EFUSE_INTF1_R_MASK 0xffffffff

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#define EFUSE_INTF1_R_GET(x) (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB)

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#define EFUSE_INTF1_R_SET(x) (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK)

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#ifndef __ASSEMBLER__

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typedef struct efuse_reg_reg_s {

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volatile unsigned int efuse_wr_enable_reg;

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volatile unsigned int efuse_int_enable_reg;

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volatile unsigned int efuse_int_status_reg;

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volatile unsigned int bitmask_wr_reg;

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volatile unsigned int vddq_settle_time_reg;

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volatile unsigned int vddq_hold_time_reg;

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volatile unsigned int rd_strobe_pw_reg;

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volatile unsigned int pg_strobe_pw_reg;

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volatile unsigned int pgenb_setup_hold_time_reg;

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volatile unsigned int strobe_pulse_interval_reg;

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volatile unsigned int csb_addr_load_setup_hold_reg;

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unsigned char pad0[2004]; /* pad to 0x800 */

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volatile unsigned int efuse_intf0[512];

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volatile unsigned int efuse_intf1[512];

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} efuse_reg_reg_t;

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#endif /* __ASSEMBLER__ */

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#endif /* _EFUSE_REG_H_ */