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gerrit-public.fairphone.software / platform / vendor / qcom-opensource / wlan / qcacld-3.0 / 7090c5fd8d2bc46a463549bf26505e67a32d1d0e / . / core / hif / inc / regtable_ce.h
blob: e5f5a9f10ccab38fd624e95dad5414a7948ba57e [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -0800[diff] [blame^]1/*
2 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef _REGTABLE_CE_H_
29#define _REGTABLE_CE_H_
30
31/*
32 * @d_DST_WR_INDEX_ADDRESS: Destination ring write index
33 *
34 * @d_SRC_WATERMARK_ADDRESS: Source ring watermark
35 *
36 * @d_SRC_WATERMARK_LOW_MASK: Bits indicating low watermark from Source ring
37 * watermark
38 *
39 * @d_SRC_WATERMARK_HIGH_MASK: Bits indicating high watermark from Source ring
40 * watermark
41 *
42 * @d_DST_WATERMARK_LOW_MASK: Bits indicating low watermark from Destination
43 * ring watermark
44 *
45 * @d_DST_WATERMARK_HIGH_MASK: Bits indicating high watermark from Destination
46 * ring watermark
47 *
48 * @d_CURRENT_SRRI_ADDRESS: Current source ring read index.The Start Offset
49 * will be reflected after a CE transfer is completed.
50 *
51 * @d_CURRENT_DRRI_ADDRESS: Current Destination ring read index. The Start
52 * Offset will be reflected after a CE transfer
53 * is completed.
54 *
55 * @d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK: Source ring high watermark
56 * Interrupt Status
57 *
58 * @d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK: Source ring low watermark
59 * Interrupt Status
60 *
61 * @d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK: Destination ring high watermark
62 * Interrupt Status
63 *
64 * @d_HOST_IS_DST_RING_LOW_WATERMARK_MASK: Source ring low watermark
65 * Interrupt Status
66 *
67 * @d_HOST_IS_ADDRESS: Host Interrupt Status Register
68 *
69 * @d_MISC_IS_ADDRESS: Miscellaneous Interrupt Status Register
70 *
71 * @d_HOST_IS_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
72 * status from the Host Interrupt Status
73 * register
74 *
75 * @d_CE_WRAPPER_BASE_ADDRESS: Copy Engine Wrapper Base Address
76 *
77 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS: CE Wrapper summary for interrupts
78 * to host
79 *
80 * @d_CE_WRAPPER_INDEX_BASE_LOW: The LSB Base address to which source and
81 * destination read indices are written
82 *
83 * @d_CE_WRAPPER_INDEX_BASE_HIGH: The MSB Base address to which source and
84 * destination read indices are written
85 *
86 * @d_HOST_IE_ADDRESS: Host Line Interrupt Enable Register
87 *
88 * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
89 * enable from the IE register
90 *
91 * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address
92 *
93 * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address
94 *
95 * @d_SR_SIZE_ADDRESS: Source Ring size - number of entries and Start Offset
96 *
97 * @d_CE_CTRL1_ADDRESS: CE Control register
98 *
99 * @d_CE_CTRL1_DMAX_LENGTH_MASK: Destination buffer Max Length used for error
100 * check
101 *
102 * @d_DR_BA_ADDRESS: Destination Ring Base Address Low
103 *
104 * @d_DR_BA_ADDRESS_HIGH: Destination Ring Base Address High
105 *
106 * @d_DR_SIZE_ADDRESS: Destination Ring size - number of entries Start Offset
107 *
108 * @d_CE_CMD_REGISTER: Implements commands to all CE Halt Flush
109 *
110 * @d_CE_MSI_ADDRESS: CE MSI LOW Address register
111 *
112 * @d_CE_MSI_ADDRESS_HIGH: CE MSI High Address register
113 *
114 * @d_CE_MSI_DATA: CE MSI Data Register
115 *
116 * @d_CE_MSI_ENABLE_BIT: Bit in CTRL1 register indication the MSI enable
117 *
118 * @d_MISC_IE_ADDRESS: Miscellaneous Interrupt Enable Register
119 *
120 * @d_MISC_IS_AXI_ERR_MASK: Bit in Misc IS indicating AXI Timeout Interrupt
121 * status
122 *
123 * @d_MISC_IS_DST_ADDR_ERR_MASK: Bit in Misc IS indicating Destination Address
124 * Error
125 *
126 * @d_MISC_IS_SRC_LEN_ERR_MASK: Bit in Misc IS indicating Source Zero Length
127 * Error Interrupt status
128 *
129 * @d_MISC_IS_DST_MAX_LEN_VIO_MASK: Bit in Misc IS indicating Destination Max
130 * Length Violated Interrupt status
131 *
132 * @d_MISC_IS_DST_RING_OVERFLOW_MASK: Bit in Misc IS indicating Destination
133 * Ring Overflow Interrupt status
134 *
135 * @d_MISC_IS_SRC_RING_OVERFLOW_MASK: Bit in Misc IS indicating Source Ring
136 * Overflow Interrupt status
137 *
138 * @d_SRC_WATERMARK_LOW_LSB: Source Ring Low Watermark LSB
139 *
140 * @d_SRC_WATERMARK_HIGH_LSB: Source Ring Low Watermark MSB
141 *
142 * @d_DST_WATERMARK_LOW_LSB: Destination Ring Low Watermark LSB
143 *
144 * @d_DST_WATERMARK_HIGH_LSB: Destination Ring High Watermark LSB
145 *
146 *
147 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK: Bits in
148 * d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
149 * indicating Copy engine
150 * miscellaneous interrupt summary
151 *
152 * @d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB:Bits in
153 * d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDR
154 * indicating Host interrupts summary
155 *
156 * @d_CE_CTRL1_DMAX_LENGTH_LSB: LSB of Destination buffer Max Length used for
157 * error check
158 *
159 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK: Bits indicating Source ring Byte Swap
160 * enable. Treats source ring memory
161 * organisation as big-endian
162 *
163 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK: Bits indicating Destination ring
164 * byte swap enable. Treats destination
165 * ring memory organisation as big-endian
166 *
167 * @d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB: LSB of Source ring Byte Swap enable
168 *
169 * @d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB: LSB of Destination ring Byte Swap enable
170 *
171 * @d_CE_WRAPPER_DEBUG_OFFSET: Offset of CE OBS BUS Select register
172 *
173 * @d_CE_WRAPPER_DEBUG_SEL_MSB: MSB of Control register selecting inputs for
174 * trace/debug
175 *
176 * @d_CE_WRAPPER_DEBUG_SEL_LSB: LSB of Control register selecting inputs for
177 * trace/debug
178 *
179 * @d_CE_WRAPPER_DEBUG_SEL_MASK: Bits indicating Control register selecting
180 * inputs for trace/debug
181 *
182 * @d_CE_DEBUG_OFFSET: Offset of Copy Engine FSM Debug Status
183 *
184 * @d_CE_DEBUG_SEL_MSB: MSB of Copy Engine FSM Debug Status
185 *
186 * @d_CE_DEBUG_SEL_LSB: LSB of Copy Engine FSM Debug Status
187 *
188 * @d_CE_DEBUG_SEL_MASK: Bits indicating Copy Engine FSM Debug Status
189 *
190*/
191
192struct ce_reg_def {
193 /* copy_engine.c */
194 uint32_t d_DST_WR_INDEX_ADDRESS;
195 uint32_t d_SRC_WATERMARK_ADDRESS;
196 uint32_t d_SRC_WATERMARK_LOW_MASK;
197 uint32_t d_SRC_WATERMARK_HIGH_MASK;
198 uint32_t d_DST_WATERMARK_LOW_MASK;
199 uint32_t d_DST_WATERMARK_HIGH_MASK;
200 uint32_t d_CURRENT_SRRI_ADDRESS;
201 uint32_t d_CURRENT_DRRI_ADDRESS;
202 uint32_t d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK;
203 uint32_t d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK;
204 uint32_t d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK;
205 uint32_t d_HOST_IS_DST_RING_LOW_WATERMARK_MASK;
206 uint32_t d_HOST_IS_ADDRESS;
207 uint32_t d_MISC_IS_ADDRESS;
208 uint32_t d_HOST_IS_COPY_COMPLETE_MASK;
209 uint32_t d_CE_WRAPPER_BASE_ADDRESS;
210 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS;
211 uint32_t d_CE_WRAPPER_INDEX_BASE_LOW;
212 uint32_t d_CE_WRAPPER_INDEX_BASE_HIGH;
213 uint32_t d_HOST_IE_ADDRESS;
214 uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
215 uint32_t d_SR_BA_ADDRESS;
216 uint32_t d_SR_BA_ADDRESS_HIGH;
217 uint32_t d_SR_SIZE_ADDRESS;
218 uint32_t d_CE_CTRL1_ADDRESS;
219 uint32_t d_CE_CTRL1_DMAX_LENGTH_MASK;
220 uint32_t d_DR_BA_ADDRESS;
221 uint32_t d_DR_BA_ADDRESS_HIGH;
222 uint32_t d_DR_SIZE_ADDRESS;
223 uint32_t d_CE_CMD_REGISTER;
224 uint32_t d_CE_MSI_ADDRESS;
225 uint32_t d_CE_MSI_ADDRESS_HIGH;
226 uint32_t d_CE_MSI_DATA;
227 uint32_t d_CE_MSI_ENABLE_BIT;
228 uint32_t d_MISC_IE_ADDRESS;
229 uint32_t d_MISC_IS_AXI_ERR_MASK;
230 uint32_t d_MISC_IS_DST_ADDR_ERR_MASK;
231 uint32_t d_MISC_IS_SRC_LEN_ERR_MASK;
232 uint32_t d_MISC_IS_DST_MAX_LEN_VIO_MASK;
233 uint32_t d_MISC_IS_DST_RING_OVERFLOW_MASK;
234 uint32_t d_MISC_IS_SRC_RING_OVERFLOW_MASK;
235 uint32_t d_SRC_WATERMARK_LOW_LSB;
236 uint32_t d_SRC_WATERMARK_HIGH_LSB;
237 uint32_t d_DST_WATERMARK_LOW_LSB;
238 uint32_t d_DST_WATERMARK_HIGH_LSB;
239 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK;
240 uint32_t d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB;
241 uint32_t d_CE_CTRL1_DMAX_LENGTH_LSB;
242 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK;
243 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
244 uint32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
245 uint32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
246 uint32_t d_CE_WRAPPER_DEBUG_OFFSET;
247 uint32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
248 uint32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
249 uint32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
250 uint32_t d_CE_DEBUG_OFFSET;
251 uint32_t d_CE_DEBUG_SEL_MSB;
252 uint32_t d_CE_DEBUG_SEL_LSB;
253 uint32_t d_CE_DEBUG_SEL_MASK;
254 uint32_t d_CE0_BASE_ADDRESS;
255 uint32_t d_CE1_BASE_ADDRESS;
256 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES;
257 uint32_t d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS;
258};
259#endif /* _REGTABLE_CE_H_ */