Blame - core/hif/src/ar9888def.h - platform/vendor/qcom-opensource/wlan/qcacld-3.0

Prakash Dhavali

7090c5f

2015-11-02 17:55:19 -0800

[diff] [blame^]

/*

*

* Previously licensed under the ISC license by Qualcomm Atheros, Inc.

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*

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*

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* Permission to use, copy, modify, and/or distribute this software for

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* any purpose with or without fee is hereby granted, provided that the

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* above copyright notice and this permission notice appear in all

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* copies.

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*

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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL

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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED

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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE

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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL

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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR

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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER

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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR

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* PERFORMANCE OF THIS SOFTWARE.

*/

/*

* This file was originally distributed by Qualcomm Atheros, Inc.

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* under proprietary terms before Copyright ownership was assigned

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* to the Linux Foundation.

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*/

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#ifndef _AR9888DEF_H_

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#define AR9888__AR9888DEF_H_

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/* Base Addresses */

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#define AR9888_RTC_SOC_BASE_ADDRESS 0x00004000

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#define AR9888_RTC_WMAC_BASE_ADDRESS 0x00005000

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#define AR9888_MAC_COEX_BASE_ADDRESS 0x00006000

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#define AR9888_BT_COEX_BASE_ADDRESS 0x00007000

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#define AR9888_SOC_PCIE_BASE_ADDRESS 0x00008000

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#define AR9888_SOC_CORE_BASE_ADDRESS 0x00009000

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#define AR9888_WLAN_UART_BASE_ADDRESS 0x0000c000

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#define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000

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#define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000

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#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000

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#define AR9888_WLAN_MAC_BASE_ADDRESS 0x00020000

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#define AR9888_EFUSE_BASE_ADDRESS 0x00030000

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#define AR9888_FPGA_REG_BASE_ADDRESS 0x00039000

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#define AR9888_WLAN_UART2_BASE_ADDRESS 0x00054c00

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#define AR9888_CE_WRAPPER_BASE_ADDRESS 0x00057000

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#define AR9888_CE0_BASE_ADDRESS 0x00057400

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#define AR9888_CE1_BASE_ADDRESS 0x00057800

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#define AR9888_CE2_BASE_ADDRESS 0x00057c00

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#define AR9888_CE3_BASE_ADDRESS 0x00058000

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#define AR9888_CE4_BASE_ADDRESS 0x00058400

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#define AR9888_CE5_BASE_ADDRESS 0x00058800

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#define AR9888_CE6_BASE_ADDRESS 0x00058c00

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#define AR9888_CE7_BASE_ADDRESS 0x00059000

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#define AR9888_DBI_BASE_ADDRESS 0x00060000

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#define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000

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#define AR9888_SCRATCH_3_ADDRESS 0x0030

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#define AR9888_TARG_DRAM_START 0x00400000

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#define AR9888_SOC_SYSTEM_SLEEP_OFFSET 0x000000c4

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#define AR9888_SOC_RESET_CONTROL_OFFSET 0x00000000

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#define AR9888_SOC_CLOCK_CONTROL_OFFSET 0x00000028

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#define AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001

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#define AR9888_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001

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#define AR9888_WLAN_GPIO_BASE_ADDRESS 0x00014000

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#define AR9888_WLAN_GPIO_PIN0_ADDRESS 0x00000028

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#define AR9888_WLAN_GPIO_PIN1_ADDRESS 0x0000002c

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#define AR9888_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800

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#define AR9888_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800

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#define AR9888_WLAN_SI_BASE_ADDRESS 0x00010000

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#define AR9888_SOC_CPU_CLOCK_OFFSET 0x00000020

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#define AR9888_SOC_LPO_CAL_OFFSET 0x000000e0

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#define AR9888_WLAN_GPIO_PIN10_ADDRESS 0x00000050

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#define AR9888_WLAN_GPIO_PIN11_ADDRESS 0x00000054

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#define AR9888_WLAN_GPIO_PIN12_ADDRESS 0x00000058

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#define AR9888_WLAN_GPIO_PIN13_ADDRESS 0x0000005c

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#define AR9888_SOC_CPU_CLOCK_STANDARD_LSB 0

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#define AR9888_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003

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#define AR9888_SOC_LPO_CAL_ENABLE_LSB 20

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#define AR9888_SOC_LPO_CAL_ENABLE_MASK 0x00100000

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#define AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000

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#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0

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#define AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001

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#define AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008

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#define AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004

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#define AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB 18

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#define AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000

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#define AR9888_SI_CONFIG_I2C_LSB 16

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#define AR9888_SI_CONFIG_I2C_MASK 0x00010000

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#define AR9888_SI_CONFIG_POS_SAMPLE_LSB 7

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#define AR9888_SI_CONFIG_POS_SAMPLE_MASK 0x00000080

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#define AR9888_SI_CONFIG_INACTIVE_CLK_LSB 4

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#define AR9888_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010

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#define AR9888_SI_CONFIG_INACTIVE_DATA_LSB 5

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#define AR9888_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020

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#define AR9888_SI_CONFIG_DIVIDER_LSB 0

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#define AR9888_SI_CONFIG_DIVIDER_MASK 0x0000000f

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#define AR9888_SI_CONFIG_OFFSET 0x00000000

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#define AR9888_SI_TX_DATA0_OFFSET 0x00000008

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#define AR9888_SI_TX_DATA1_OFFSET 0x0000000c

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#define AR9888_SI_RX_DATA0_OFFSET 0x00000010

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#define AR9888_SI_RX_DATA1_OFFSET 0x00000014

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#define AR9888_SI_CS_OFFSET 0x00000004

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#define AR9888_SI_CS_DONE_ERR_MASK 0x00000400

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#define AR9888_SI_CS_DONE_INT_MASK 0x00000200

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#define AR9888_SI_CS_START_LSB 8

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#define AR9888_SI_CS_START_MASK 0x00000100

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#define AR9888_SI_CS_RX_CNT_LSB 4

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#define AR9888_SI_CS_RX_CNT_MASK 0x000000f0

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#define AR9888_SI_CS_TX_CNT_LSB 0

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#define AR9888_SI_CS_TX_CNT_MASK 0x0000000f

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#define AR9888_CE_COUNT 8

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#define AR9888_SR_WR_INDEX_ADDRESS 0x003c

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#define AR9888_DST_WATERMARK_ADDRESS 0x0050

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#define AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB 14

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#define AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000

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#define AR9888_RX_MPDU_START_0_SEQ_NUM_LSB 16

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#define AR9888_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000

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#define AR9888_RX_MPDU_START_2_PN_47_32_LSB 0

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#define AR9888_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff

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#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff

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#define AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB 0

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#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16

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#define AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000

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#define AR9888_RX_MSDU_END_4_LAST_MSDU_LSB 15

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#define AR9888_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000

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#define AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB 2

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#define AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004

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#define AR9888_RX_ATTENTION_0_FRAGMENT_LSB 13

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#define AR9888_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000

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#define AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000

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#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16

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#define AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000

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#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB 0

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#define AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff

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#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008

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#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB 8

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#define AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300

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#define AR9888_RX_MPDU_START_0_ENCRYPTED_LSB 13

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#define AR9888_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000

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#define AR9888_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400

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#define AR9888_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000

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#define AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000

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#define AR9888_DST_WR_INDEX_ADDRESS 0x0040

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#define AR9888_SRC_WATERMARK_ADDRESS 0x004c

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#define AR9888_SRC_WATERMARK_LOW_MASK 0xffff0000

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#define AR9888_SRC_WATERMARK_HIGH_MASK 0x0000ffff

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#define AR9888_DST_WATERMARK_LOW_MASK 0xffff0000

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#define AR9888_DST_WATERMARK_HIGH_MASK 0x0000ffff

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#define AR9888_CURRENT_SRRI_ADDRESS 0x0044

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#define AR9888_CURRENT_DRRI_ADDRESS 0x0048

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#define AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002

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#define AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK 0x00000004

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#define AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK 0x00000008

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#define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010

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#define AR9888_HOST_IS_ADDRESS 0x0030

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#define AR9888_HOST_IS_COPY_COMPLETE_MASK 0x00000001

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#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000

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#define AR9888_HOST_IE_ADDRESS 0x002c

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#define AR9888_HOST_IE_COPY_COMPLETE_MASK 0x00000001

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#define AR9888_SR_BA_ADDRESS 0x0000

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#define AR9888_SR_SIZE_ADDRESS 0x0004

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#define AR9888_CE_CTRL1_ADDRESS 0x0010

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#define AR9888_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff

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#define AR9888_DR_BA_ADDRESS 0x0008

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#define AR9888_DR_SIZE_ADDRESS 0x000c

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#define AR9888_MISC_IE_ADDRESS 0x0034

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#define AR9888_MISC_IS_AXI_ERR_MASK 0x00000400

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#define AR9888_MISC_IS_DST_ADDR_ERR_MASK 0x00000200

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#define AR9888_MISC_IS_SRC_LEN_ERR_MASK 0x00000100

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#define AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK 0x00000080

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#define AR9888_MISC_IS_DST_RING_OVERFLOW_MASK 0x00000040

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#define AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK 0x00000020

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#define AR9888_SRC_WATERMARK_LOW_LSB 16

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#define AR9888_SRC_WATERMARK_HIGH_LSB 0

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#define AR9888_DST_WATERMARK_LOW_LSB 16

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#define AR9888_DST_WATERMARK_HIGH_LSB 0

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#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00

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#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8

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#define AR9888_CE_CTRL1_DMAX_LENGTH_LSB 0

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#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000

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#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000

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#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16

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#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17

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#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004

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#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2

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#define AR9888_SOC_GLOBAL_RESET_ADDRESS 0x0008

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#define AR9888_RTC_STATE_ADDRESS 0x0000

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#define AR9888_RTC_STATE_COLD_RESET_MASK 0x00000400

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#define AR9888_PCIE_SOC_WAKE_RESET 0x00000000

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#define AR9888_PCIE_SOC_WAKE_ADDRESS 0x0004

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#define AR9888_PCIE_SOC_WAKE_V_MASK 0x00000001

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#define AR9888_RTC_STATE_V_MASK 0x00000007

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#define AR9888_RTC_STATE_V_LSB 0

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#define AR9888_RTC_STATE_V_ON 3

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#define AR9888_MUX_ID_MASK 0x0000

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#define AR9888_TRANSACTION_ID_MASK 0x3fff

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#define AR9888_PCIE_LOCAL_BASE_ADDRESS 0x80000

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#define AR9888_FW_IND_EVENT_PENDING 1

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#define AR9888_FW_IND_INITIALIZED 2

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#define AR9888_PCIE_INTR_ENABLE_ADDRESS 0x0008

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#define AR9888_PCIE_INTR_CLR_ADDRESS 0x0014

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#define AR9888_PCIE_INTR_FIRMWARE_MASK 0x00000400

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#define AR9888_PCIE_INTR_CE0_MASK 0x00000800

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#define AR9888_PCIE_INTR_CE_MASK_ALL 0x0007f800

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#define AR9888_PCIE_INTR_CAUSE_ADDRESS 0x000c

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#define AR9888_CPU_INTR_ADDRESS 0x0010

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#define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050

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#define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004

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#define AR9888_SOC_RESET_CONTROL_ADDRESS 0x00000000

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#define AR9888_SOC_RESET_CONTROL_CE_RST_MASK 0x00040000

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#define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040

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#define AR9888_CORE_CTRL_ADDRESS 0x0000

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#define AR9888_CORE_CTRL_CPU_INTR_MASK 0x00002000

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#define AR9888_LOCAL_SCRATCH_OFFSET 0x18

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#define AR9888_CLOCK_GPIO_OFFSET 0xffffffff

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#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0

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#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0

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#define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))

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#define AR9888_FW_EVENT_PENDING_ADDRESS \

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(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)

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#define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START

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#define AR9888_FW_INDICATOR_ADDRESS \

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(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)

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#define AR9888_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET

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#define AR9888_WLAN_SYSTEM_SLEEP_OFFSET AR9888_SOC_SYSTEM_SLEEP_OFFSET

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#define AR9888_WLAN_RESET_CONTROL_OFFSET AR9888_SOC_RESET_CONTROL_OFFSET

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#define AR9888_CLOCK_CONTROL_OFFSET AR9888_SOC_CLOCK_CONTROL_OFFSET

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#define AR9888_CLOCK_CONTROL_SI0_CLK_MASK AR9888_SOC_CLOCK_CONTROL_SI0_CLK_MASK

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#define AR9888_RESET_CONTROL_MBOX_RST_MASK MISSING

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#define AR9888_RESET_CONTROL_SI0_RST_MASK AR9888_SOC_RESET_CONTROL_SI0_RST_MASK

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#define AR9888_GPIO_BASE_ADDRESS AR9888_WLAN_GPIO_BASE_ADDRESS

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#define AR9888_GPIO_PIN0_OFFSET AR9888_WLAN_GPIO_PIN0_ADDRESS

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#define AR9888_GPIO_PIN1_OFFSET AR9888_WLAN_GPIO_PIN1_ADDRESS

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#define AR9888_GPIO_PIN0_CONFIG_MASK AR9888_WLAN_GPIO_PIN0_CONFIG_MASK

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#define AR9888_GPIO_PIN1_CONFIG_MASK AR9888_WLAN_GPIO_PIN1_CONFIG_MASK

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#define AR9888_SI_BASE_ADDRESS AR9888_WLAN_SI_BASE_ADDRESS

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#define AR9888_SCRATCH_BASE_ADDRESS AR9888_SOC_CORE_BASE_ADDRESS

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#define AR9888_CPU_CLOCK_OFFSET AR9888_SOC_CPU_CLOCK_OFFSET

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#define AR9888_LPO_CAL_OFFSET AR9888_SOC_LPO_CAL_OFFSET

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#define AR9888_GPIO_PIN10_OFFSET AR9888_WLAN_GPIO_PIN10_ADDRESS

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#define AR9888_GPIO_PIN11_OFFSET AR9888_WLAN_GPIO_PIN11_ADDRESS

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#define AR9888_GPIO_PIN12_OFFSET AR9888_WLAN_GPIO_PIN12_ADDRESS

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#define AR9888_GPIO_PIN13_OFFSET AR9888_WLAN_GPIO_PIN13_ADDRESS

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#define AR9888_CPU_CLOCK_STANDARD_LSB AR9888_SOC_CPU_CLOCK_STANDARD_LSB

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#define AR9888_CPU_CLOCK_STANDARD_MASK AR9888_SOC_CPU_CLOCK_STANDARD_MASK

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#define AR9888_LPO_CAL_ENABLE_LSB AR9888_SOC_LPO_CAL_ENABLE_LSB

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#define AR9888_LPO_CAL_ENABLE_MASK AR9888_SOC_LPO_CAL_ENABLE_MASK

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#define AR9888_ANALOG_INTF_BASE_ADDRESS AR9888_WLAN_ANALOG_INTF_BASE_ADDRESS

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#define AR9888_MBOX_BASE_ADDRESS MISSING

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#define AR9888_INT_STATUS_ENABLE_ERROR_LSB MISSING

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#define AR9888_INT_STATUS_ENABLE_ERROR_MASK MISSING

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#define AR9888_INT_STATUS_ENABLE_CPU_LSB MISSING

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#define AR9888_INT_STATUS_ENABLE_CPU_MASK MISSING

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#define AR9888_INT_STATUS_ENABLE_COUNTER_LSB MISSING

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#define AR9888_INT_STATUS_ENABLE_COUNTER_MASK MISSING

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#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING

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#define AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING

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#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING

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#define AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING

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#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING

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#define AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING

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#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING

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#define AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING

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#define AR9888_INT_STATUS_ENABLE_ADDRESS MISSING

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#define AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB MISSING

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#define AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK MISSING

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#define AR9888_HOST_INT_STATUS_ADDRESS MISSING

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#define AR9888_CPU_INT_STATUS_ADDRESS MISSING

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#define AR9888_ERROR_INT_STATUS_ADDRESS MISSING

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#define AR9888_ERROR_INT_STATUS_WAKEUP_MASK MISSING

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#define AR9888_ERROR_INT_STATUS_WAKEUP_LSB MISSING

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#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING

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#define AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING

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#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING

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#define AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING

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#define AR9888_COUNT_DEC_ADDRESS MISSING

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#define AR9888_HOST_INT_STATUS_CPU_MASK MISSING

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#define AR9888_HOST_INT_STATUS_CPU_LSB MISSING

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#define AR9888_HOST_INT_STATUS_ERROR_MASK MISSING

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#define AR9888_HOST_INT_STATUS_ERROR_LSB MISSING

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#define AR9888_HOST_INT_STATUS_COUNTER_MASK MISSING

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#define AR9888_HOST_INT_STATUS_COUNTER_LSB MISSING

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#define AR9888_RX_LOOKAHEAD_VALID_ADDRESS MISSING

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#define AR9888_WINDOW_DATA_ADDRESS MISSING

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#define AR9888_WINDOW_READ_ADDR_ADDRESS MISSING

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#define AR9888_WINDOW_WRITE_ADDR_ADDRESS MISSING

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struct targetdef_s ar9888_targetdef = {

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.d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS,

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.d_RTC_WMAC_BASE_ADDRESS = AR9888_RTC_WMAC_BASE_ADDRESS,

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.d_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,

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.d_WLAN_SYSTEM_SLEEP_OFFSET = AR9888_WLAN_SYSTEM_SLEEP_OFFSET,

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.d_WLAN_SYSTEM_SLEEP_DISABLE_LSB =

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AR9888_WLAN_SYSTEM_SLEEP_DISABLE_LSB,

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.d_WLAN_SYSTEM_SLEEP_DISABLE_MASK =

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AR9888_WLAN_SYSTEM_SLEEP_DISABLE_MASK,

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.d_CLOCK_CONTROL_OFFSET = AR9888_CLOCK_CONTROL_OFFSET,

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.d_CLOCK_CONTROL_SI0_CLK_MASK = AR9888_CLOCK_CONTROL_SI0_CLK_MASK,

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.d_RESET_CONTROL_OFFSET = AR9888_SOC_RESET_CONTROL_OFFSET,

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.d_RESET_CONTROL_MBOX_RST_MASK = AR9888_RESET_CONTROL_MBOX_RST_MASK,

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.d_RESET_CONTROL_SI0_RST_MASK = AR9888_RESET_CONTROL_SI0_RST_MASK,

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.d_WLAN_RESET_CONTROL_OFFSET = AR9888_WLAN_RESET_CONTROL_OFFSET,

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.d_WLAN_RESET_CONTROL_COLD_RST_MASK =

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AR9888_WLAN_RESET_CONTROL_COLD_RST_MASK,

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.d_WLAN_RESET_CONTROL_WARM_RST_MASK =

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AR9888_WLAN_RESET_CONTROL_WARM_RST_MASK,

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.d_GPIO_BASE_ADDRESS = AR9888_GPIO_BASE_ADDRESS,

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.d_GPIO_PIN0_OFFSET = AR9888_GPIO_PIN0_OFFSET,

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.d_GPIO_PIN1_OFFSET = AR9888_GPIO_PIN1_OFFSET,

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.d_GPIO_PIN0_CONFIG_MASK = AR9888_GPIO_PIN0_CONFIG_MASK,

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.d_GPIO_PIN1_CONFIG_MASK = AR9888_GPIO_PIN1_CONFIG_MASK,

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.d_SI_CONFIG_BIDIR_OD_DATA_LSB = AR9888_SI_CONFIG_BIDIR_OD_DATA_LSB,

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.d_SI_CONFIG_BIDIR_OD_DATA_MASK = AR9888_SI_CONFIG_BIDIR_OD_DATA_MASK,

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.d_SI_CONFIG_I2C_LSB = AR9888_SI_CONFIG_I2C_LSB,

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.d_SI_CONFIG_I2C_MASK = AR9888_SI_CONFIG_I2C_MASK,

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.d_SI_CONFIG_POS_SAMPLE_LSB = AR9888_SI_CONFIG_POS_SAMPLE_LSB,

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.d_SI_CONFIG_POS_SAMPLE_MASK = AR9888_SI_CONFIG_POS_SAMPLE_MASK,

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.d_SI_CONFIG_INACTIVE_CLK_LSB = AR9888_SI_CONFIG_INACTIVE_CLK_LSB,

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.d_SI_CONFIG_INACTIVE_CLK_MASK = AR9888_SI_CONFIG_INACTIVE_CLK_MASK,

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.d_SI_CONFIG_INACTIVE_DATA_LSB = AR9888_SI_CONFIG_INACTIVE_DATA_LSB,

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.d_SI_CONFIG_INACTIVE_DATA_MASK = AR9888_SI_CONFIG_INACTIVE_DATA_MASK,

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.d_SI_CONFIG_DIVIDER_LSB = AR9888_SI_CONFIG_DIVIDER_LSB,

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.d_SI_CONFIG_DIVIDER_MASK = AR9888_SI_CONFIG_DIVIDER_MASK,

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.d_SI_BASE_ADDRESS = AR9888_SI_BASE_ADDRESS,

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.d_SI_CONFIG_OFFSET = AR9888_SI_CONFIG_OFFSET,

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.d_SI_TX_DATA0_OFFSET = AR9888_SI_TX_DATA0_OFFSET,

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.d_SI_TX_DATA1_OFFSET = AR9888_SI_TX_DATA1_OFFSET,

331

.d_SI_RX_DATA0_OFFSET = AR9888_SI_RX_DATA0_OFFSET,

332

.d_SI_RX_DATA1_OFFSET = AR9888_SI_RX_DATA1_OFFSET,

333

.d_SI_CS_OFFSET = AR9888_SI_CS_OFFSET,

334

.d_SI_CS_DONE_ERR_MASK = AR9888_SI_CS_DONE_ERR_MASK,

335

.d_SI_CS_DONE_INT_MASK = AR9888_SI_CS_DONE_INT_MASK,

336

.d_SI_CS_START_LSB = AR9888_SI_CS_START_LSB,

337

.d_SI_CS_START_MASK = AR9888_SI_CS_START_MASK,

338

.d_SI_CS_RX_CNT_LSB = AR9888_SI_CS_RX_CNT_LSB,

339

.d_SI_CS_RX_CNT_MASK = AR9888_SI_CS_RX_CNT_MASK,

340

.d_SI_CS_TX_CNT_LSB = AR9888_SI_CS_TX_CNT_LSB,

341

.d_SI_CS_TX_CNT_MASK = AR9888_SI_CS_TX_CNT_MASK,

342

.d_BOARD_DATA_SZ = AR9888_BOARD_DATA_SZ,

343

.d_BOARD_EXT_DATA_SZ = AR9888_BOARD_EXT_DATA_SZ,

344

.d_MBOX_BASE_ADDRESS = AR9888_MBOX_BASE_ADDRESS,

345

.d_LOCAL_SCRATCH_OFFSET = AR9888_LOCAL_SCRATCH_OFFSET,

346

.d_CPU_CLOCK_OFFSET = AR9888_CPU_CLOCK_OFFSET,

347

.d_LPO_CAL_OFFSET = AR9888_LPO_CAL_OFFSET,

348

.d_GPIO_PIN10_OFFSET = AR9888_GPIO_PIN10_OFFSET,

349

.d_GPIO_PIN11_OFFSET = AR9888_GPIO_PIN11_OFFSET,

350

.d_GPIO_PIN12_OFFSET = AR9888_GPIO_PIN12_OFFSET,

351

.d_GPIO_PIN13_OFFSET = AR9888_GPIO_PIN13_OFFSET,

352

.d_CLOCK_GPIO_OFFSET = AR9888_CLOCK_GPIO_OFFSET,

353

.d_CPU_CLOCK_STANDARD_LSB = AR9888_CPU_CLOCK_STANDARD_LSB,

354

.d_CPU_CLOCK_STANDARD_MASK = AR9888_CPU_CLOCK_STANDARD_MASK,

355

.d_LPO_CAL_ENABLE_LSB = AR9888_LPO_CAL_ENABLE_LSB,

356

.d_LPO_CAL_ENABLE_MASK = AR9888_LPO_CAL_ENABLE_MASK,

357

.d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB,

358

.d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK =

359

AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK,

360

.d_ANALOG_INTF_BASE_ADDRESS = AR9888_ANALOG_INTF_BASE_ADDRESS,

361

.d_WLAN_MAC_BASE_ADDRESS = AR9888_WLAN_MAC_BASE_ADDRESS,

362

.d_FW_INDICATOR_ADDRESS = AR9888_FW_INDICATOR_ADDRESS,

363

.d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS,

364

.d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS,

365

.d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS,

366

.d_CE_COUNT = AR9888_CE_COUNT,

367

.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,

368

.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,

369

.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,

370

.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,

371

.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,

372

.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,

373

.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,

374

.d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK,

375

.d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS,

376

.d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS,

377

/* htt_rx.c */

378

.d_RX_MSDU_END_4_FIRST_MSDU_MASK =

379

AR9888_RX_MSDU_END_4_FIRST_MSDU_MASK,

380

.d_RX_MSDU_END_4_FIRST_MSDU_LSB = AR9888_RX_MSDU_END_4_FIRST_MSDU_LSB,

381

.d_RX_MPDU_START_0_SEQ_NUM_MASK = AR9888_RX_MPDU_START_0_SEQ_NUM_MASK,

382

.d_RX_MPDU_START_0_SEQ_NUM_LSB = AR9888_RX_MPDU_START_0_SEQ_NUM_LSB,

383

.d_RX_MPDU_START_2_PN_47_32_LSB = AR9888_RX_MPDU_START_2_PN_47_32_LSB,

384

.d_RX_MPDU_START_2_PN_47_32_MASK =

385

AR9888_RX_MPDU_START_2_PN_47_32_MASK,

386

.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK =

387

AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK,

388

.d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB =

389

AR9888_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB,

390

.d_RX_MSDU_END_1_KEY_ID_OCT_MASK =

391

AR9888_RX_MSDU_END_1_KEY_ID_OCT_MASK,

392

.d_RX_MSDU_END_1_KEY_ID_OCT_LSB = AR9888_RX_MSDU_END_1_KEY_ID_OCT_LSB,

393

.d_RX_MSDU_END_4_LAST_MSDU_MASK = AR9888_RX_MSDU_END_4_LAST_MSDU_MASK,

394

.d_RX_MSDU_END_4_LAST_MSDU_LSB = AR9888_RX_MSDU_END_4_LAST_MSDU_LSB,

395

.d_RX_ATTENTION_0_MCAST_BCAST_MASK =

396

AR9888_RX_ATTENTION_0_MCAST_BCAST_MASK,

397

.d_RX_ATTENTION_0_MCAST_BCAST_LSB =

398

AR9888_RX_ATTENTION_0_MCAST_BCAST_LSB,

399

.d_RX_ATTENTION_0_FRAGMENT_MASK = AR9888_RX_ATTENTION_0_FRAGMENT_MASK,

400

.d_RX_ATTENTION_0_FRAGMENT_LSB = AR9888_RX_ATTENTION_0_FRAGMENT_LSB,

401

.d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK =

402

AR9888_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK,

403

.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK =

404

AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK,

405

.d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB =

406

AR9888_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB,

407

.d_RX_MSDU_START_0_MSDU_LENGTH_MASK =

408

AR9888_RX_MSDU_START_0_MSDU_LENGTH_MASK,

409

.d_RX_MSDU_START_0_MSDU_LENGTH_LSB =

410

AR9888_RX_MSDU_START_0_MSDU_LENGTH_LSB,

411

.d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET =

412

AR9888_RX_MSDU_START_2_DECAP_FORMAT_OFFSET,

413

.d_RX_MSDU_START_2_DECAP_FORMAT_MASK =

414

AR9888_RX_MSDU_START_2_DECAP_FORMAT_MASK,

415

.d_RX_MSDU_START_2_DECAP_FORMAT_LSB =

416

AR9888_RX_MSDU_START_2_DECAP_FORMAT_LSB,

417

.d_RX_MPDU_START_0_ENCRYPTED_MASK =

418

AR9888_RX_MPDU_START_0_ENCRYPTED_MASK,

419

.d_RX_MPDU_START_0_ENCRYPTED_LSB =

420

AR9888_RX_MPDU_START_0_ENCRYPTED_LSB,

421

.d_RX_ATTENTION_0_MORE_DATA_MASK =

422

AR9888_RX_ATTENTION_0_MORE_DATA_MASK,

423

.d_RX_ATTENTION_0_MSDU_DONE_MASK =

424

AR9888_RX_ATTENTION_0_MSDU_DONE_MASK,

425

.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =

426

AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,

427

428

.d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS,

429

.d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS,

430

.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =

431

AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,

432

.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB =

433

AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,

434

.d_SOC_RESET_CONTROL_CE_RST_MASK =

435

AR9888_SOC_RESET_CONTROL_CE_RST_MASK,

436

.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =

437

AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,

438

.d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS,

439

.d_SOC_LF_TIMER_CONTROL0_ADDRESS =

440

AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS,

441

.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =

442

AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,

443

};

444

445

struct hostdef_s ar9888_hostdef = {

446

.d_INT_STATUS_ENABLE_ERROR_LSB = AR9888_INT_STATUS_ENABLE_ERROR_LSB,

447

.d_INT_STATUS_ENABLE_ERROR_MASK = AR9888_INT_STATUS_ENABLE_ERROR_MASK,

448

.d_INT_STATUS_ENABLE_CPU_LSB = AR9888_INT_STATUS_ENABLE_CPU_LSB,

449

.d_INT_STATUS_ENABLE_CPU_MASK = AR9888_INT_STATUS_ENABLE_CPU_MASK,

450

.d_INT_STATUS_ENABLE_COUNTER_LSB =

451

AR9888_INT_STATUS_ENABLE_COUNTER_LSB,

452

.d_INT_STATUS_ENABLE_COUNTER_MASK =

453

AR9888_INT_STATUS_ENABLE_COUNTER_MASK,

454

.d_INT_STATUS_ENABLE_MBOX_DATA_LSB =

455

AR9888_INT_STATUS_ENABLE_MBOX_DATA_LSB,

456

.d_INT_STATUS_ENABLE_MBOX_DATA_MASK =

457

AR9888_INT_STATUS_ENABLE_MBOX_DATA_MASK,

458

.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB =

459

AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB,

460

.d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK =

461

AR9888_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK,

462

.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB =

463

AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB,

464

.d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK =

465

AR9888_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK,

466

.d_COUNTER_INT_STATUS_ENABLE_BIT_LSB =

467

AR9888_COUNTER_INT_STATUS_ENABLE_BIT_LSB,

468

.d_COUNTER_INT_STATUS_ENABLE_BIT_MASK =

469

AR9888_COUNTER_INT_STATUS_ENABLE_BIT_MASK,

470

.d_INT_STATUS_ENABLE_ADDRESS = AR9888_INT_STATUS_ENABLE_ADDRESS,

471

.d_CPU_INT_STATUS_ENABLE_BIT_LSB =

472

AR9888_CPU_INT_STATUS_ENABLE_BIT_LSB,

473

.d_CPU_INT_STATUS_ENABLE_BIT_MASK =

474

AR9888_CPU_INT_STATUS_ENABLE_BIT_MASK,

475

.d_HOST_INT_STATUS_ADDRESS = AR9888_HOST_INT_STATUS_ADDRESS,

476

.d_CPU_INT_STATUS_ADDRESS = AR9888_CPU_INT_STATUS_ADDRESS,

477

.d_ERROR_INT_STATUS_ADDRESS = AR9888_ERROR_INT_STATUS_ADDRESS,

478

.d_ERROR_INT_STATUS_WAKEUP_MASK = AR9888_ERROR_INT_STATUS_WAKEUP_MASK,

479

.d_ERROR_INT_STATUS_WAKEUP_LSB = AR9888_ERROR_INT_STATUS_WAKEUP_LSB,

480

.d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK =

481

AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_MASK,

482

.d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB =

483

AR9888_ERROR_INT_STATUS_RX_UNDERFLOW_LSB,

484

.d_ERROR_INT_STATUS_TX_OVERFLOW_MASK =

485

AR9888_ERROR_INT_STATUS_TX_OVERFLOW_MASK,

486

.d_ERROR_INT_STATUS_TX_OVERFLOW_LSB =

487

AR9888_ERROR_INT_STATUS_TX_OVERFLOW_LSB,

488

.d_COUNT_DEC_ADDRESS = AR9888_COUNT_DEC_ADDRESS,

489

.d_HOST_INT_STATUS_CPU_MASK = AR9888_HOST_INT_STATUS_CPU_MASK,

490

.d_HOST_INT_STATUS_CPU_LSB = AR9888_HOST_INT_STATUS_CPU_LSB,

491

.d_HOST_INT_STATUS_ERROR_MASK = AR9888_HOST_INT_STATUS_ERROR_MASK,

492

.d_HOST_INT_STATUS_ERROR_LSB = AR9888_HOST_INT_STATUS_ERROR_LSB,

493

.d_HOST_INT_STATUS_COUNTER_MASK = AR9888_HOST_INT_STATUS_COUNTER_MASK,

494

.d_HOST_INT_STATUS_COUNTER_LSB = AR9888_HOST_INT_STATUS_COUNTER_LSB,

495

.d_RX_LOOKAHEAD_VALID_ADDRESS = AR9888_RX_LOOKAHEAD_VALID_ADDRESS,

496

.d_WINDOW_DATA_ADDRESS = AR9888_WINDOW_DATA_ADDRESS,

497

.d_WINDOW_READ_ADDR_ADDRESS = AR9888_WINDOW_READ_ADDR_ADDRESS,

498

.d_WINDOW_WRITE_ADDR_ADDRESS = AR9888_WINDOW_WRITE_ADDR_ADDRESS,

499

.d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS,

500

.d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS,

501

.d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK,

502

.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,

503

.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,

504

.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,

505

.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,

506

.d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK,

507

.d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB,

508

.d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING,

509

.d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED,

510

.d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON,

511

.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,

512

.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,

513

#if defined(SDIO_3_0)

514

.d_HOST_INT_STATUS_MBOX_DATA_MASK =

515

AR9888_HOST_INT_STATUS_MBOX_DATA_MASK,

516

.d_HOST_INT_STATUS_MBOX_DATA_LSB =

517

AR9888_HOST_INT_STATUS_MBOX_DATA_LSB,

518

#endif

519

.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,

520

.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,

521

.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,

522

.d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS,

523

.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,

524

.d_HOST_CE_COUNT = 8,

.d_ENABLE_MSI = 0,

};

struct ce_reg_def ar9888_ce_targetdef = {

530

/* copy_engine.c */

531

.d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS,

532

.d_SRC_WATERMARK_ADDRESS = AR9888_SRC_WATERMARK_ADDRESS,

533

.d_SRC_WATERMARK_LOW_MASK = AR9888_SRC_WATERMARK_LOW_MASK,

534

.d_SRC_WATERMARK_HIGH_MASK = AR9888_SRC_WATERMARK_HIGH_MASK,

535

.d_DST_WATERMARK_LOW_MASK = AR9888_DST_WATERMARK_LOW_MASK,

536

.d_DST_WATERMARK_HIGH_MASK = AR9888_DST_WATERMARK_HIGH_MASK,

537

.d_CURRENT_SRRI_ADDRESS = AR9888_CURRENT_SRRI_ADDRESS,

538

.d_CURRENT_DRRI_ADDRESS = AR9888_CURRENT_DRRI_ADDRESS,

539

.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =

540

AR9888_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,

541

.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =

542

AR9888_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,

543

.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =

544

AR9888_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,

545

.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =

546

AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK,

547

.d_HOST_IS_ADDRESS = AR9888_HOST_IS_ADDRESS,

548

.d_HOST_IS_COPY_COMPLETE_MASK = AR9888_HOST_IS_COPY_COMPLETE_MASK,

549

.d_CE_WRAPPER_BASE_ADDRESS = AR9888_CE_WRAPPER_BASE_ADDRESS,

550

.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =

551

AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS,

552

.d_HOST_IE_ADDRESS = AR9888_HOST_IE_ADDRESS,

553

.d_HOST_IE_COPY_COMPLETE_MASK = AR9888_HOST_IE_COPY_COMPLETE_MASK,

554

.d_SR_BA_ADDRESS = AR9888_SR_BA_ADDRESS,

555

.d_SR_SIZE_ADDRESS = AR9888_SR_SIZE_ADDRESS,

556

.d_CE_CTRL1_ADDRESS = AR9888_CE_CTRL1_ADDRESS,

557

.d_CE_CTRL1_DMAX_LENGTH_MASK = AR9888_CE_CTRL1_DMAX_LENGTH_MASK,

558

.d_DR_BA_ADDRESS = AR9888_DR_BA_ADDRESS,

559

.d_DR_SIZE_ADDRESS = AR9888_DR_SIZE_ADDRESS,

560

.d_MISC_IE_ADDRESS = AR9888_MISC_IE_ADDRESS,

561

.d_MISC_IS_AXI_ERR_MASK = AR9888_MISC_IS_AXI_ERR_MASK,

562

.d_MISC_IS_DST_ADDR_ERR_MASK = AR9888_MISC_IS_DST_ADDR_ERR_MASK,

563

.d_MISC_IS_SRC_LEN_ERR_MASK = AR9888_MISC_IS_SRC_LEN_ERR_MASK,

564

.d_MISC_IS_DST_MAX_LEN_VIO_MASK = AR9888_MISC_IS_DST_MAX_LEN_VIO_MASK,

565

.d_MISC_IS_DST_RING_OVERFLOW_MASK =

566

AR9888_MISC_IS_DST_RING_OVERFLOW_MASK,

567

.d_MISC_IS_SRC_RING_OVERFLOW_MASK =

568

AR9888_MISC_IS_SRC_RING_OVERFLOW_MASK,

569

.d_SRC_WATERMARK_LOW_LSB = AR9888_SRC_WATERMARK_LOW_LSB,

570

.d_SRC_WATERMARK_HIGH_LSB = AR9888_SRC_WATERMARK_HIGH_LSB,

571

.d_DST_WATERMARK_LOW_LSB = AR9888_DST_WATERMARK_LOW_LSB,

572

.d_DST_WATERMARK_HIGH_LSB = AR9888_DST_WATERMARK_HIGH_LSB,

573

.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =

574

AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,

575

.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =

576

AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,

577

.d_CE_CTRL1_DMAX_LENGTH_LSB = AR9888_CE_CTRL1_DMAX_LENGTH_LSB,

578

.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =

579

AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,

580

.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =

581

AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,

582

.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =

583

AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,

584

.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =

585

AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,

586

.d_CE0_BASE_ADDRESS = AR9888_CE0_BASE_ADDRESS,

587

.d_CE1_BASE_ADDRESS = AR9888_CE1_BASE_ADDRESS,

588

589

};

590

#endif