blob: 570fd41fd7996d9de00fa21aaa500eb7ace67dc5 [file] [log] [blame]
Prakash Dhavali7090c5f2015-11-02 17:55:19 -08001/*
2 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
3 *
4 * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
5 *
6 *
7 * Permission to use, copy, modify, and/or distribute this software for
8 * any purpose with or without fee is hereby granted, provided that the
9 * above copyright notice and this permission notice appear in all
10 * copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
13 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
14 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
15 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
16 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
17 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
18 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
19 * PERFORMANCE OF THIS SOFTWARE.
20 */
21
22/*
23 * This file was originally distributed by Qualcomm Atheros, Inc.
24 * under proprietary terms before Copyright ownership was assigned
25 * to the Linux Foundation.
26 */
27
28#ifndef __CE_H__
29#define __CE_H__
30
31#include "cdf_atomic.h"
32#include "cdf_lock.h"
33#include "hif.h"
34
35#define CE_HTT_T2H_MSG 1
36#define CE_HTT_H2T_MSG 4
37
38/**
39 * enum ce_id_type
40 *
41 * @ce_id_type: Copy engine ID
42 */
43enum ce_id_type {
44 CE_ID_0,
45 CE_ID_1,
46 CE_ID_2,
47 CE_ID_3,
48 CE_ID_4,
49 CE_ID_5,
50 CE_ID_6,
51 CE_ID_7,
52 CE_ID_8,
53 CE_ID_9,
54 CE_ID_10,
55 CE_ID_11,
56 CE_ID_MAX
57};
58struct HIF_CE_completion_state {
59 struct HIF_CE_completion_state *next;
60 int send_or_recv;
61 struct CE_handle *copyeng;
62 void *ce_context;
63 void *transfer_context;
64 cdf_dma_addr_t data;
65 unsigned int nbytes;
66 unsigned int transfer_id;
67 unsigned int flags;
68 uint32_t toeplitz_hash_result;
69};
70
71/* compl_state.send_or_recv */
72#define HIF_CE_COMPLETE_FREE 0
73#define HIF_CE_COMPLETE_SEND 1
74#define HIF_CE_COMPLETE_RECV 2
75
76enum ol_ath_hif_pkt_ecodes {
77 HIF_PIPE_NO_RESOURCE = 0
78};
79
80struct HIF_CE_state;
81#define HIF_CE_COMPLETE_STATE_NUM 18 /* 56 * 18 + 4/8 = 1012/1016 bytes */
82struct HIF_CE_completion_state_list {
83 struct HIF_CE_completion_state_list *next;
84};
85
86/* Per-pipe state. */
87struct HIF_CE_pipe_info {
88 /* Handle of underlying Copy Engine */
89 struct CE_handle *ce_hdl;
90
91 /* Our pipe number; facilitiates use of pipe_info ptrs. */
92 uint8_t pipe_num;
93
94 /* Convenience back pointer to HIF_CE_state. */
95 struct HIF_CE_state *HIF_CE_state;
96
97 /* Instantaneous number of receive buffers that should be posted */
98 atomic_t recv_bufs_needed;
99 cdf_size_t buf_sz;
100 cdf_spinlock_t recv_bufs_needed_lock;
101
102 cdf_spinlock_t completion_freeq_lock;
103 /* Limit the number of outstanding send requests. */
104 int num_sends_allowed;
105 struct HIF_CE_completion_state_list *completion_space_list;
106 struct HIF_CE_completion_state *completion_freeq_head;
107 struct HIF_CE_completion_state *completion_freeq_tail;
108 /* adding three counts for debugging ring buffer errors */
109 uint32_t nbuf_alloc_err_count;
110 uint32_t nbuf_dma_err_count;
111 uint32_t nbuf_ce_enqueue_err_count;
112};
113
114/**
115 * struct ce_tasklet_entry
116 *
117 * @intr_tq: intr_tq
118 * @ce_id: ce_id
119 * @inited: inited
120 * @hif_ce_state: hif_ce_state
121 * @from_irq: from_irq
122 */
123struct ce_tasklet_entry {
124 struct tasklet_struct intr_tq;
125 enum ce_id_type ce_id;
126 bool inited;
127 void *hif_ce_state;
128 bool from_irq;
129};
130
131struct HIF_CE_state {
132 struct ol_softc *scn;
133 bool started;
134 struct ce_tasklet_entry tasklets[CE_COUNT_MAX];
135 cdf_spinlock_t keep_awake_lock;
136 unsigned int keep_awake_count;
137 bool verified_awake;
138 bool fake_sleep;
139 cdf_softirq_timer_t sleep_timer;
140 bool sleep_timer_init;
141 unsigned long sleep_ticks;
142 cdf_spinlock_t completion_pendingq_lock;
143 /* Queue of send/recv completions that need to be processed */
144 struct HIF_CE_completion_state *completion_pendingq_head;
145 struct HIF_CE_completion_state *completion_pendingq_tail;
146 atomic_t fw_event_pending;
147 cdf_atomic_t hif_thread_idle;
148
149 /* wait_queue_head_t service_waitq; */
150 /* struct task_struct *compl_thread; */
151 /* struct completion compl_thread_done; */
152
153 /* Per-pipe state. */
154 struct HIF_CE_pipe_info pipe_info[CE_COUNT_MAX];
155 /* to be activated after BMI_DONE */
156 struct hif_msg_callbacks msg_callbacks_pending;
157 /* current msg callbacks in use */
158 struct hif_msg_callbacks msg_callbacks_current;
159
160 void *claimedContext;
161
162 /* Target address used to signal a pending firmware event */
163 uint32_t fw_indicator_address;
164
165 /* Copy Engine used for Diagnostic Accesses */
166 struct CE_handle *ce_diag;
167};
168#endif /* __CE_H__ */