Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2015 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | /** |
| 29 | * DOC: hif_io32_snoc.h |
| 30 | * |
| 31 | * snoc specific implementations and configurations |
| 32 | */ |
| 33 | |
| 34 | #ifndef __HIF_IO32_SNOC_H__ |
| 35 | #define __HIF_IO32_SNOC_H__ |
| 36 | |
| 37 | #ifdef HIF_PCI |
| 38 | #error snoc and pci cannot be supported in parrallel at this time |
| 39 | #endif |
| 40 | |
| 41 | #include "hif.h" |
| 42 | #include "regtable.h" |
| 43 | #include "ce_reg.h" |
| 44 | #include "cdf_atomic.h" |
| 45 | #include <soc/qcom/icnss.h> |
| 46 | #include "hif_main.h" |
| 47 | #include "hif_debug.h" |
| 48 | |
| 49 | /** |
| 50 | * Following features are not supported for snoc bus |
| 51 | * Force 0 and consider moving corresponding code into |
| 52 | * pci specific files |
| 53 | */ |
| 54 | #define CONFIG_ATH_PCIE_MAX_PERF 0 |
| 55 | #define CONFIG_ATH_PCIE_AWAKE_WHILE_DRIVER_LOAD 0 |
| 56 | #define CONFIG_ATH_PCIE_ACCESS_LIKELY 0 |
| 57 | #define CONFIG_PCIE_ENABLE_L1_CLOCK_GATE 0 |
| 58 | |
| 59 | #define A_TARGET_ACCESS_LIKELY(scn) |
| 60 | #define A_TARGET_ACCESS_UNLIKELY(scn) |
| 61 | #define A_TARGET_ACCESS_BEGIN_RET_PTR(scn) |
| 62 | #define A_TARGET_ACCESS_END_RET_PTR(scn) |
| 63 | #define A_TARGET_ACCESS_BEGIN(scn) |
| 64 | #define A_TARGET_ACCESS_END(scn) |
| 65 | #define A_TARGET_ACCESS_BEGIN_RET(scn) |
| 66 | #define A_TARGET_ACCESS_END_RET(scn) |
| 67 | #define A_TARGET_ACCESS_BEGIN_RET_EXT(scn, val) |
| 68 | #define A_TARGET_ACCESS_END_RET_EXT(scn, val) |
| 69 | |
| 70 | #define Q_TARGET_ACCESS_BEGIN(scn) 0 |
| 71 | #define Q_TARGET_ACCESS_END(scn) 0 |
| 72 | |
| 73 | static inline void hif_pci_cancel_deferred_target_sleep(struct ol_softc *scn) |
| 74 | { |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | static inline void hif_target_sleep_state_adjust(struct ol_softc *scn, |
| 79 | bool sleep_ok, bool wait_for_it) |
| 80 | { |
| 81 | return; |
| 82 | } |
| 83 | |
| 84 | /** |
| 85 | * soc_wake_reset() - soc_wake_reset |
| 86 | * @scn: ol_softc |
| 87 | * |
| 88 | * Return: void |
| 89 | */ |
| 90 | static inline void soc_wake_reset(struct ol_softc *scn) |
| 91 | { |
| 92 | } |
| 93 | |
| 94 | /** |
| 95 | * hif_write32_mb - SNOC write 32 |
| 96 | * @addr: physical address |
| 97 | * @value: value |
| 98 | * |
| 99 | * Return: N/A |
| 100 | */ |
| 101 | static inline void hif_write32_mb(void __iomem *addr, uint32_t value) |
| 102 | { |
| 103 | wmb(); /* write memory barrier */ |
| 104 | writel_relaxed((value), (addr)); |
| 105 | wmb(); /* write memory barrier */ |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * hif_read32_mb - SNOC read 32 |
| 110 | * @addr: physical address |
| 111 | * |
| 112 | * Return: N/A |
| 113 | */ |
| 114 | static inline uint32_t hif_read32_mb(void __iomem *addr) |
| 115 | { |
| 116 | uint32_t tmp; |
| 117 | rmb(); /* read memory barrier */ |
| 118 | tmp = readl_relaxed(addr); |
| 119 | rmb(); /* read memory barrier */ |
| 120 | return tmp; |
| 121 | } |
| 122 | |
| 123 | #define A_TARGET_READ(scn, offset) \ |
| 124 | hif_read32_mb(scn->mem + (offset)) |
| 125 | #define A_TARGET_WRITE(scn, offset, value) \ |
| 126 | hif_write32_mb((scn->mem + offset), (value)) |
| 127 | |
| 128 | #define ADRASTEA_CE_INTR_ENABLES 0x002F00A8 |
| 129 | #define ADRASTEA_CE_INTR_ENABLES_SET "COMING IN REGISTER SET36" |
| 130 | #define ADRASTEA_CE_INTR_ENABLES_CLEAR "COMING IN REGISTER SET36" |
| 131 | |
| 132 | #define ADRASTEA_CE_INTR_STATUS 0x002F00AC |
| 133 | |
| 134 | static inline void ce_enable_irq_in_individual_register(struct ol_softc *scn, |
| 135 | int ce_id) |
| 136 | { |
| 137 | uint32_t offset; |
| 138 | offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id); |
| 139 | hif_write32_mb(scn->mem + offset, 1); |
| 140 | hif_read32_mb(scn->mem + offset); |
| 141 | } |
| 142 | |
| 143 | static inline void ce_disable_irq_in_individual_register(struct ol_softc *scn, |
| 144 | int ce_id) |
| 145 | { |
| 146 | uint32_t offset; |
| 147 | offset = HOST_IE_ADDRESS + CE_BASE_ADDRESS(ce_id); |
| 148 | hif_write32_mb(scn->mem + offset, 0); |
| 149 | hif_read32_mb(scn->mem + offset); |
| 150 | } |
| 151 | |
| 152 | static inline void ce_read_irq_group_status(struct ol_softc *scn) |
| 153 | { |
| 154 | uint32_t group_status = 0; |
| 155 | group_status = hif_read32_mb(scn->mem + |
| 156 | ADRASTEA_CE_INTR_STATUS); |
| 157 | } |
| 158 | |
| 159 | static inline void ce_clear_irq_group_status(struct ol_softc *scn, int mask) |
| 160 | { |
| 161 | uint32_t group_status = 0; |
| 162 | group_status = hif_read32_mb(scn->mem + |
| 163 | ADRASTEA_CE_INTR_STATUS); |
| 164 | |
| 165 | hif_write32_mb(scn->mem + |
| 166 | ADRASTEA_CE_INTR_STATUS, mask); |
| 167 | |
| 168 | group_status = hif_read32_mb(scn->mem + |
| 169 | ADRASTEA_CE_INTR_STATUS); |
| 170 | } |
| 171 | |
| 172 | /* this will need to be changed when we move to reg set 36 |
| 173 | * because we will have set & clear registers provided |
| 174 | */ |
| 175 | static inline void ce_enable_irq_in_group_reg(struct ol_softc *scn, |
| 176 | int mask) |
| 177 | { |
| 178 | int new_mask = 0; |
| 179 | new_mask = hif_read32_mb(scn->mem + |
| 180 | ADRASTEA_CE_INTR_ENABLES); |
| 181 | |
| 182 | new_mask |= mask; |
| 183 | |
| 184 | hif_write32_mb(scn->mem + |
| 185 | ADRASTEA_CE_INTR_ENABLES, new_mask); |
| 186 | mask = hif_read32_mb(scn->mem + |
| 187 | ADRASTEA_CE_INTR_ENABLES); |
| 188 | } |
| 189 | |
| 190 | /* this will need to be changed when we move to reg set 36 |
| 191 | * because we will have set & clear registers provided |
| 192 | */ |
| 193 | static inline void ce_disable_irq_in_group_reg(struct ol_softc *scn, |
| 194 | int mask) |
| 195 | { |
| 196 | int new_mask = 0; |
| 197 | new_mask = hif_read32_mb(scn->mem + |
| 198 | ADRASTEA_CE_INTR_ENABLES); |
| 199 | |
| 200 | new_mask &= ~mask; |
| 201 | |
| 202 | hif_write32_mb(scn->mem + |
| 203 | ADRASTEA_CE_INTR_ENABLES, new_mask); |
| 204 | mask = hif_read32_mb(scn->mem + |
| 205 | ADRASTEA_CE_INTR_ENABLES); |
| 206 | } |
| 207 | |
| 208 | /** |
| 209 | * ce_irq_enable() - enable copy engine IRQ |
| 210 | * @scn: struct ol_softc |
| 211 | * @ce_id: ce_id |
| 212 | * |
| 213 | * Return: N/A |
| 214 | */ |
| 215 | static inline void ce_irq_enable(struct ol_softc *scn, |
| 216 | int ce_id) |
| 217 | { |
| 218 | icnss_enable_irq(ce_id); |
| 219 | ce_enable_irq_in_individual_register(scn, ce_id); |
| 220 | ce_enable_irq_in_group_reg(scn, 1<<ce_id); |
| 221 | } |
| 222 | |
| 223 | /** |
| 224 | * ce_irq_disable() - disable copy engine IRQ |
| 225 | * @scn: struct ol_softc |
| 226 | * @ce_id: ce_id |
| 227 | * |
| 228 | * Return: N/A |
| 229 | */ |
| 230 | static inline void ce_irq_disable(struct ol_softc *scn, int ce_id) |
| 231 | { |
| 232 | ce_disable_irq_in_group_reg(scn, 1<<ce_id); |
| 233 | ce_clear_irq_group_status(scn, 1<<ce_id); |
| 234 | ce_disable_irq_in_individual_register(scn, ce_id); |
| 235 | } |
| 236 | #endif |