Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2011-2015 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | /** |
| 29 | * @file htt.h |
| 30 | * |
| 31 | * @details the public header file of HTT layer |
| 32 | */ |
| 33 | |
| 34 | #ifndef _HTT_H_ |
| 35 | #define _HTT_H_ |
| 36 | |
| 37 | #include <a_types.h> /* A_UINT32 */ |
| 38 | #include <a_osapi.h> /* PREPACK, POSTPACK */ |
| 39 | #ifdef ATHR_WIN_NWF |
| 40 | #pragma warning(disable:4214) /*bit field types other than int */ |
| 41 | #endif |
| 42 | #include "wlan_defs.h" |
| 43 | #include <htt_common.h> |
| 44 | |
| 45 | /* |
| 46 | * Unless explicitly specified to use 64 bits to represent physical addresses |
| 47 | * (or more precisely, bus addresses), default to 32 bits. |
| 48 | */ |
| 49 | #ifndef HTT_PADDR64 |
| 50 | #define HTT_PADDR64 0 |
| 51 | #endif |
| 52 | |
| 53 | #ifndef offsetof |
| 54 | #define offsetof(type, field) ((unsigned int)(&((type *)0)->field)) |
| 55 | #endif |
| 56 | |
| 57 | /* |
| 58 | * HTT version history: |
| 59 | * 1.0 initial numbered version |
| 60 | * 1.1 modifications to STATS messages. |
| 61 | * These modifications are not backwards compatible, but since the |
| 62 | * STATS messages themselves are non-essential (they are for debugging), |
| 63 | * the 1.1 version of the HTT message library as a whole is compatible |
| 64 | * with the 1.0 version. |
| 65 | * 1.2 reset mask IE added to STATS_REQ message |
| 66 | * 1.3 stat config IE added to STATS_REQ message |
| 67 | *---- |
| 68 | * 2.0 FW rx PPDU desc added to RX_IND message |
| 69 | * 2.1 Enable msdu_ext/frag_desc banking change for WIFI2.0 |
| 70 | *---- |
| 71 | * 3.0 Remove HTT_H2T_MSG_TYPE_MGMT_TX message |
| 72 | * 3.1 Added HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND message |
| 73 | * 3.2 Added HTT_H2T_MSG_TYPE_WDI_IPA_CFG, |
| 74 | * HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST messages |
| 75 | * 3.3 Added HTT_H2T_MSG_TYPE_AGGR_CFG_EX message |
| 76 | * 3.4 Added tx_compl_req flag in HTT tx descriptor |
| 77 | * 3.5 Added flush and fail stats in rx_reorder stats structure |
| 78 | * 3.6 Added frag flag in HTT RX INORDER PADDR IND header |
| 79 | * 3.7 Made changes to support EOS Mac_core 3.0 |
| 80 | * 3.8 Added txq_group information element definition; |
| 81 | * added optional txq_group suffix to TX_CREDIT_UPDATE_IND message |
| 82 | * 3.9 Added HTT_T2H CHAN_CHANGE message; |
| 83 | * Allow buffer addresses in bus-address format to be stored as |
| 84 | * either 32 bits or 64 bits. |
| 85 | * 3.10 Add optional TLV extensions to the VERSION_REQ and VERSION_CONF |
| 86 | * messages to specify which HTT options to use. |
| 87 | * Initial TLV options cover: |
| 88 | * - whether to use 32 or 64 bits to represent LL bus addresses |
| 89 | * - whether to use TX_COMPL_IND or TX_CREDIT_UPDATE_IND in HL systems |
| 90 | * - how many tx queue groups to use |
| 91 | * 3.11 Expand rx debug stats: |
| 92 | * - Expand the rx_reorder_stats struct with stats about successful and |
| 93 | * failed rx buffer allcoations. |
| 94 | * - Add a new rx_remote_buffer_mgmt_stats struct with stats about |
| 95 | * the supply, allocation, use, and recycling of rx buffers for the |
| 96 | * "remote ring" of rx buffers in host member in LL systems. |
| 97 | * Add RX_REMOTE_RING_BUFFER_INFO stats type for uploading these stats. |
| 98 | * 3.12 Add "rx offload packet error" message with initial "MIC error" subtype |
| 99 | * 3.13 Add constants + macros to support 64-bit address format for the |
| 100 | * tx fragments descriptor, the rx ring buffer, and the rx ring |
| 101 | * index shadow register. |
| 102 | * 3.14 Add a method for the host to provide detailed per-frame tx specs: |
| 103 | * - Add htt_tx_msdu_desc_ext_t struct def. |
| 104 | * - Add TLV to specify whether the target supports the HTT tx MSDU |
| 105 | * extension descriptor. |
| 106 | * - Change a reserved bit in the HTT tx MSDU descriptor to an |
| 107 | * "extension" bit, to specify whether a HTT tx MSDU extension |
| 108 | * descriptor is present. |
| 109 | * 3.15 Add HW rx desc info to per-MSDU info elems in RX_IN_ORD_PADDR_IND msg. |
| 110 | * (This allows the host to obtain key information about the MSDU |
| 111 | * from a memory location already in the cache, rather than taking a |
| 112 | * cache miss for each MSDU by reading the HW rx descs.) |
| 113 | * 3.16 Add htt_pkt_type_eth2 and define pkt_subtype flags to indicate |
| 114 | * whether a copy-engine classification result is appended to TX_FRM. |
| 115 | * 3.17 Add a version of the WDI_IPA_CFG message; add RX_RING2 to WDI_IPA_CFG |
| 116 | * 3.18 Add a PEER_DEL tx completion indication status, for HL cleanup of |
| 117 | * tx frames in the target after the peer has already been deleted. |
| 118 | * 3.19 Add HTT_DBG_STATS_RX_RATE_INFO_V2 and HTT_DBG_STATS_TX_RATE_INFO_V2 |
| 119 | * 3.20 Expand rx_reorder_stats. |
| 120 | * 3.21 Add optional rx channel spec to HL RX_IND. |
| 121 | * 3.22 Expand rx_reorder_stats |
| 122 | * (distinguish duplicates within vs. outside block ack window) |
| 123 | * 3.23 Add HTT_T2H_MSG_TYPE_RATE_REPORT to report peer justified rate. |
| 124 | * The justified rate is calculated by two steps. The first is to multiply |
| 125 | * user-rate by (1 - PER) and the other is to smooth the step 1's result |
| 126 | * by a low pass filter. |
| 127 | * This change allows HL download scheduling to consider the WLAN rate |
| 128 | * that will be used for transmitting the downloaded frames. |
| 129 | * 3.24 Expand rx_reorder_stats |
| 130 | * (add counter for decrypt / MIC errors) |
| 131 | * 3.25 Expand rx_reorder_stats |
| 132 | * (add counter of frames received into both local + remote rings) |
| 133 | * 3.26 Add stats struct for counting rx of tx BF, MU, SU, and NDPA frames |
| 134 | * (HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT, rx_txbf_musu_ndpa_pkts_stats) |
| 135 | * 3.27 Add a new interface for flow-control. The following t2h messages have |
| 136 | * been included: HTT_T2H_MSG_TYPE_FLOW_POOL_MAP and |
| 137 | * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP |
| 138 | */ |
| 139 | #define HTT_CURRENT_VERSION_MAJOR 3 |
| 140 | #define HTT_CURRENT_VERSION_MINOR 27 |
| 141 | |
| 142 | #define HTT_NUM_TX_FRAG_DESC 1024 |
| 143 | |
| 144 | #define HTT_WIFI_IP_VERSION(x, y) ((x) == (y)) |
| 145 | |
| 146 | #define HTT_CHECK_SET_VAL(field, val) \ |
| 147 | A_ASSERT(!((val) & ~((field ## _M) >> (field ## _S)))) |
| 148 | |
| 149 | /* macros to assist in sign-extending fields from HTT messages */ |
| 150 | #define HTT_SIGN_BIT_MASK(field) \ |
| 151 | ((field ## _M + (1 << field ## _S)) >> 1) |
| 152 | #define HTT_SIGN_BIT(_val, field) \ |
| 153 | (_val & HTT_SIGN_BIT_MASK(field)) |
| 154 | #define HTT_SIGN_BIT_UNSHIFTED(_val, field) \ |
| 155 | (HTT_SIGN_BIT(_val, field) >> field ## _S) |
| 156 | #define HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field) \ |
| 157 | (HTT_SIGN_BIT_UNSHIFTED(_val, field) - 1) |
| 158 | #define HTT_SIGN_BIT_EXTENSION(_val, field) \ |
| 159 | (~(HTT_SIGN_BIT_UNSHIFTED(_val, field) | \ |
| 160 | HTT_SIGN_BIT_UNSHIFTED_MINUS_ONE(_val, field))) |
| 161 | #define HTT_SIGN_BIT_EXTENSION_MASK(_val, field) \ |
| 162 | (HTT_SIGN_BIT_EXTENSION(_val, field) & ~(field ## _M >> field ## _S)) |
| 163 | |
| 164 | |
| 165 | /* |
| 166 | * TEMPORARY: |
| 167 | * Provide HTT_H2T_MSG_TYPE_MGMT_TX as an alias for |
| 168 | * DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX until all code |
| 169 | * that refers to HTT_H2T_MSG_TYPE_MGMT_TX has been |
| 170 | * updated. |
| 171 | */ |
| 172 | #define HTT_H2T_MSG_TYPE_MGMT_TX DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX |
| 173 | |
| 174 | /* |
| 175 | * TEMPORARY: |
| 176 | * Provide HTT_T2H_MSG_TYPE_RC_UPDATE_IND as an alias for |
| 177 | * DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND until all code |
| 178 | * that refers to HTT_T2H_MSG_TYPE_RC_UPDATE_IND has been |
| 179 | * updated. |
| 180 | */ |
| 181 | #define HTT_T2H_MSG_TYPE_RC_UPDATE_IND DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND |
| 182 | |
| 183 | /* HTT Access Category values */ |
| 184 | enum HTT_AC_WMM { |
| 185 | /* WMM Access Categories */ |
| 186 | HTT_AC_WMM_BE = 0x0, |
| 187 | HTT_AC_WMM_BK = 0x1, |
| 188 | HTT_AC_WMM_VI = 0x2, |
| 189 | HTT_AC_WMM_VO = 0x3, |
| 190 | /* extension Access Categories */ |
| 191 | HTT_AC_EXT_NON_QOS = 0x4, |
| 192 | HTT_AC_EXT_UCAST_MGMT = 0x5, |
| 193 | HTT_AC_EXT_MCAST_DATA = 0x6, |
| 194 | HTT_AC_EXT_MCAST_MGMT = 0x7, |
| 195 | }; |
| 196 | enum HTT_AC_WMM_MASK { |
| 197 | /* WMM Access Categories */ |
| 198 | HTT_AC_WMM_BE_MASK = (1 << HTT_AC_WMM_BE), |
| 199 | HTT_AC_WMM_BK_MASK = (1 << HTT_AC_WMM_BK), |
| 200 | HTT_AC_WMM_VI_MASK = (1 << HTT_AC_WMM_VI), |
| 201 | HTT_AC_WMM_VO_MASK = (1 << HTT_AC_WMM_VO), |
| 202 | /* extension Access Categories */ |
| 203 | HTT_AC_EXT_NON_QOS_MASK = (1 << HTT_AC_EXT_NON_QOS), |
| 204 | HTT_AC_EXT_UCAST_MGMT_MASK = (1 << HTT_AC_EXT_UCAST_MGMT), |
| 205 | HTT_AC_EXT_MCAST_DATA_MASK = (1 << HTT_AC_EXT_MCAST_DATA), |
| 206 | HTT_AC_EXT_MCAST_MGMT_MASK = (1 << HTT_AC_EXT_MCAST_MGMT), |
| 207 | }; |
| 208 | #define HTT_AC_MASK_WMM \ |
| 209 | (HTT_AC_WMM_BE_MASK | HTT_AC_WMM_BK_MASK | \ |
| 210 | HTT_AC_WMM_VI_MASK | HTT_AC_WMM_VO_MASK) |
| 211 | #define HTT_AC_MASK_EXT \ |
| 212 | (HTT_AC_EXT_NON_QOS_MASK | HTT_AC_EXT_UCAST_MGMT_MASK | \ |
| 213 | HTT_AC_EXT_MCAST_DATA_MASK | HTT_AC_EXT_MCAST_MGMT_MASK) |
| 214 | #define HTT_AC_MASK_ALL (HTT_AC_MASK_WMM | HTT_AC_MASK_EXT) |
| 215 | |
| 216 | /* |
| 217 | * htt_dbg_stats_type - |
| 218 | * bit positions for each stats type within a stats type bitmask |
| 219 | * The bitmask contains 24 bits. |
| 220 | */ |
| 221 | enum htt_dbg_stats_type { |
| 222 | HTT_DBG_STATS_WAL_PDEV_TXRX = 0, /* bit 0 -> 0x1 */ |
| 223 | HTT_DBG_STATS_RX_REORDER = 1, /* bit 1 -> 0x2 */ |
| 224 | HTT_DBG_STATS_RX_RATE_INFO = 2, /* bit 2 -> 0x4 */ |
| 225 | HTT_DBG_STATS_TX_PPDU_LOG = 3, /* bit 3 -> 0x8 */ |
| 226 | HTT_DBG_STATS_TX_RATE_INFO = 4, /* bit 4 -> 0x10 */ |
| 227 | HTT_DBG_STATS_TIDQ = 5, /* bit 5 -> 0x20 */ |
| 228 | HTT_DBG_STATS_TXBF_INFO = 6, /* bit 6 -> 0x40 */ |
| 229 | HTT_DBG_STATS_SND_INFO = 7, /* bit 7 -> 0x80 */ |
| 230 | HTT_DBG_STATS_ERROR_INFO = 8, /* bit 8 -> 0x100 */ |
| 231 | HTT_DBG_STATS_TX_SELFGEN_INFO = 9, /* bit 9 -> 0x200 */ |
| 232 | HTT_DBG_STATS_TX_MU_INFO = 10, /* bit 10 -> 0x400 */ |
| 233 | HTT_DBG_STATS_SIFS_RESP_INFO = 11, /* bit 11 -> 0x800 */ |
| 234 | HTT_DBG_STATS_RX_REMOTE_RING_BUFFER_INFO = 12, /* bit 12 -> 0x1000 */ |
| 235 | HTT_DBG_STATS_RX_RATE_INFO_V2 = 13, /* bit 13 -> 0x2000 */ |
| 236 | HTT_DBG_STATS_TX_RATE_INFO_V2 = 14, /* bit 14 -> 0x4000 */ |
| 237 | HTT_DBG_STATS_TXBF_MUSU_NDPA_PKT = 15, /* bit 15 -> 0x8000 */ |
| 238 | /* bits 16-23 currently reserved */ |
| 239 | |
| 240 | /* keep this last */ |
| 241 | HTT_DBG_NUM_STATS |
| 242 | }; |
| 243 | |
| 244 | /*=== HTT option selection TLVs === |
| 245 | * Certain HTT messages have alternatives or options. |
| 246 | * For such cases, the host and target need to agree on which option to use. |
| 247 | * Option specification TLVs can be appended to the VERSION_REQ and |
| 248 | * VERSION_CONF messages to select options other than the default. |
| 249 | * These TLVs are entirely optional - if they are not provided, there is a |
| 250 | * well-defined default for each option. If they are provided, they can be |
| 251 | * provided in any order. Each TLV can be present or absent independent of |
| 252 | * the presence / absence of other TLVs. |
| 253 | * |
| 254 | * The HTT option selection TLVs use the following format: |
| 255 | * |31 16|15 8|7 0| |
| 256 | * |---------------------------------+----------------+----------------| |
| 257 | * | value (payload) | length | tag | |
| 258 | * |-------------------------------------------------------------------| |
| 259 | * The value portion need not be only 2 bytes; it can be extended by any |
| 260 | * integer number of 4-byte units. The total length of the TLV, including |
| 261 | * the tag and length fields, must be a multiple of 4 bytes. The length |
| 262 | * field specifies the total TLV size in 4-byte units. Thus, the typical |
| 263 | * TLV, with a 1-byte tag field, a 1-byte length field, and a 2-byte value |
| 264 | * field, would store 0x1 in its length field, to show that the TLV occupies |
| 265 | * a single 4-byte unit. |
| 266 | */ |
| 267 | |
| 268 | /*--- TLV header format - applies to all HTT option TLVs ---*/ |
| 269 | |
| 270 | enum HTT_OPTION_TLV_TAGS { |
| 271 | HTT_OPTION_TLV_TAG_RESERVED0 = 0x0, |
| 272 | HTT_OPTION_TLV_TAG_LL_BUS_ADDR_SIZE = 0x1, |
| 273 | HTT_OPTION_TLV_TAG_HL_SUPPRESS_TX_COMPL_IND = 0x2, |
| 274 | HTT_OPTION_TLV_TAG_MAX_TX_QUEUE_GROUPS = 0x3, |
| 275 | HTT_OPTION_TLV_TAG_SUPPORT_TX_MSDU_DESC_EXT = 0x4, |
| 276 | }; |
| 277 | |
| 278 | PREPACK struct htt_option_tlv_header_t { |
| 279 | A_UINT8 tag; |
| 280 | A_UINT8 length; |
| 281 | } POSTPACK; |
| 282 | |
| 283 | #define HTT_OPTION_TLV_TAG_M 0x000000ff |
| 284 | #define HTT_OPTION_TLV_TAG_S 0 |
| 285 | #define HTT_OPTION_TLV_LENGTH_M 0x0000ff00 |
| 286 | #define HTT_OPTION_TLV_LENGTH_S 8 |
| 287 | /* |
| 288 | * value0 - 16 bit value field stored in word0 |
| 289 | * The TLV's value field may be longer than 2 bytes, in which case |
| 290 | * the remainder of the value is stored in word1, word2, etc. |
| 291 | */ |
| 292 | #define HTT_OPTION_TLV_VALUE0_M 0xffff0000 |
| 293 | #define HTT_OPTION_TLV_VALUE0_S 16 |
| 294 | |
| 295 | #define HTT_OPTION_TLV_TAG_SET(word, tag) \ |
| 296 | do { \ |
| 297 | HTT_CHECK_SET_VAL(HTT_OPTION_TLV_TAG, tag); \ |
| 298 | (word) |= ((tag) << HTT_OPTION_TLV_TAG_S); \ |
| 299 | } while (0) |
| 300 | #define HTT_OPTION_TLV_TAG_GET(word) \ |
| 301 | (((word) & HTT_OPTION_TLV_TAG_M) >> HTT_OPTION_TLV_TAG_S) |
| 302 | |
| 303 | #define HTT_OPTION_TLV_LENGTH_SET(word, tag) \ |
| 304 | do { \ |
| 305 | HTT_CHECK_SET_VAL(HTT_OPTION_TLV_LENGTH, tag); \ |
| 306 | (word) |= ((tag) << HTT_OPTION_TLV_LENGTH_S); \ |
| 307 | } while (0) |
| 308 | #define HTT_OPTION_TLV_LENGTH_GET(word) \ |
| 309 | (((word) & HTT_OPTION_TLV_LENGTH_M) >> HTT_OPTION_TLV_LENGTH_S) |
| 310 | |
| 311 | #define HTT_OPTION_TLV_VALUE0_SET(word, tag) \ |
| 312 | do { \ |
| 313 | HTT_CHECK_SET_VAL(HTT_OPTION_TLV_VALUE0, tag); \ |
| 314 | (word) |= ((tag) << HTT_OPTION_TLV_VALUE0_S); \ |
| 315 | } while (0) |
| 316 | #define HTT_OPTION_TLV_VALUE0_GET(word) \ |
| 317 | (((word) & HTT_OPTION_TLV_VALUE0_M) >> HTT_OPTION_TLV_VALUE0_S) |
| 318 | |
| 319 | /*--- format of specific HTT option TLVs ---*/ |
| 320 | |
| 321 | /* |
| 322 | * HTT option TLV for specifying LL bus address size |
| 323 | * Some chips require bus addresses used by the target to access buffers |
| 324 | * within the host's memory to be 32 bits; others require bus addresses |
| 325 | * used by the target to access buffers within the host's memory to be |
| 326 | * 64 bits. |
| 327 | * The LL_BUS_ADDR_SIZE TLV can be sent from the target to the host as |
| 328 | * a suffix to the VERSION_CONF message to specify which bus address format |
| 329 | * the target requires. |
| 330 | * If this LL_BUS_ADDR_SIZE TLV is not sent by the target, the host should |
| 331 | * default to providing bus addresses to the target in 32-bit format. |
| 332 | */ |
| 333 | enum HTT_OPTION_TLV_LL_BUS_ADDR_SIZE_VALUES { |
| 334 | HTT_OPTION_TLV_LL_BUS_ADDR_SIZE32 = 0x0, |
| 335 | HTT_OPTION_TLV_LL_BUS_ADDR_SIZE64 = 0x1, |
| 336 | }; |
| 337 | PREPACK struct htt_option_tlv_ll_bus_addr_size_t { |
| 338 | struct htt_option_tlv_header_t hdr; |
| 339 | A_UINT16 ll_bus_addr_size; /* LL_BUS_ADDR_SIZE_VALUES enum */ |
| 340 | } POSTPACK; |
| 341 | |
| 342 | /* |
| 343 | * HTT option TLV for specifying whether HL systems should indicate |
| 344 | * over-the-air tx completion for individual frames, or should instead |
| 345 | * send a bulk TX_CREDIT_UPDATE_IND except when the host explicitly |
| 346 | * requests an OTA tx completion for a particular tx frame. |
| 347 | * This option does not apply to LL systems, where the TX_COMPL_IND |
| 348 | * is mandatory. |
| 349 | * This option is primarily intended for HL systems in which the tx frame |
| 350 | * downloads over the host --> target bus are as slow as or slower than |
| 351 | * the transmissions over the WLAN PHY. For cases where the bus is faster |
| 352 | * than the WLAN PHY, the target will transmit relatively large A-MPDUs, |
| 353 | * and consquently will send one TX_COMPL_IND message that covers several |
| 354 | * tx frames. For cases where the WLAN PHY is faster than the bus, |
| 355 | * the target will end up transmitting very short A-MPDUs, and consequently |
| 356 | * sending many TX_COMPL_IND messages, which each cover a very small number |
| 357 | * of tx frames. |
| 358 | * The HL_SUPPRESS_TX_COMPL_IND TLV can be sent by the host to the target as |
| 359 | * a suffix to the VERSION_REQ message to request whether the host desires to |
| 360 | * use TX_CREDIT_UPDATE_IND rather than TX_COMPL_IND. The target can then |
| 361 | * send a HTT_SUPPRESS_TX_COMPL_IND TLV to the host as a suffix to the |
| 362 | * VERSION_CONF message to confirm whether TX_CREDIT_UPDATE_IND will be used |
| 363 | * rather than TX_COMPL_IND. TX_CREDIT_UPDATE_IND shall only be used if the |
| 364 | * host sends a HL_SUPPRESS_TX_COMPL_IND TLV requesting use of |
| 365 | * TX_CREDIT_UPDATE_IND, and the target sends a HL_SUPPRESS_TX_COMPLE_IND TLV |
| 366 | * back to the host confirming use of TX_CREDIT_UPDATE_IND. |
| 367 | * Lack of a HL_SUPPRESS_TX_COMPL_IND TLV from either host --> target or |
| 368 | * target --> host is equivalent to a HL_SUPPRESS_TX_COMPL_IND that |
| 369 | * explicitly specifies HL_ALLOW_TX_COMPL_IND in the value payload of the |
| 370 | * TLV. |
| 371 | */ |
| 372 | enum HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND_VALUES { |
| 373 | HTT_OPTION_TLV_HL_ALLOW_TX_COMPL_IND = 0x0, |
| 374 | HTT_OPTION_TLV_HL_SUPPRESS_TX_COMPL_IND = 0x1, |
| 375 | }; |
| 376 | PREPACK struct htt_option_tlv_hl_suppress_tx_compl_ind_t { |
| 377 | struct htt_option_tlv_header_t hdr; |
| 378 | A_UINT16 hl_suppress_tx_compl_ind;/*HL_SUPPRESS_TX_COMPL_IND enum*/ |
| 379 | } POSTPACK; |
| 380 | |
| 381 | /* |
| 382 | * HTT option TLV for specifying how many tx queue groups the target |
| 383 | * may establish. |
| 384 | * This TLV specifies the maximum value the target may send in the |
| 385 | * txq_group_id field of any TXQ_GROUP information elements sent by |
| 386 | * the target to the host. This allows the host to pre-allocate an |
| 387 | * appropriate number of tx queue group structs. |
| 388 | * |
| 389 | * The MAX_TX_QUEUE_GROUPS_TLV can be sent from the host to the target as |
| 390 | * a suffix to the VERSION_REQ message to specify whether the host supports |
| 391 | * tx queue groups at all, and if so if there is any limit on the number of |
| 392 | * tx queue groups that the host supports. |
| 393 | * The MAX_TX_QUEUE_GROUPS TLV can be sent from the target to the host as |
| 394 | * a suffix to the VERSION_CONF message. If the host has specified in the |
| 395 | * VER_REQ message a limit on the number of tx queue groups the host can |
| 396 | * supprt, the target shall limit its specification of the maximum tx groups |
| 397 | * to be no larger than this host-specified limit. |
| 398 | * |
| 399 | * If the target does not provide a MAX_TX_QUEUE_GROUPS TLV, then the host |
| 400 | * shall preallocate 4 tx queue group structs, and the target shall not |
| 401 | * specify a txq_group_id larger than 3. |
| 402 | */ |
| 403 | enum HTT_OPTION_TLV_MAX_TX_QUEUE_GROUPS_VALUES { |
| 404 | HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNSUPPORTED = 0, |
| 405 | /* |
| 406 | * values 1 through N specify the max number of tx queue groups |
| 407 | * the sender supports |
| 408 | */ |
| 409 | HTT_OPTION_TLV_TX_QUEUE_GROUPS_UNLIMITED = 0xffff, |
| 410 | }; |
| 411 | /* TEMPORARY backwards-compatibility alias for a typo fix - |
| 412 | * The htt_option_tlv_mac_tx_queue_groups_t typo has been corrected |
| 413 | * to htt_option_tlv_max_tx_queue_groups_t, but an alias is provided |
| 414 | * to support the old name (with the typo) until all references to the |
| 415 | * old name are replaced with the new name. |
| 416 | */ |
| 417 | #define htt_option_tlv_mac_tx_queue_groups_t \ |
| 418 | htt_option_tlv_max_tx_queue_groups_t |
| 419 | PREPACK struct htt_option_tlv_max_tx_queue_groups_t { |
| 420 | struct htt_option_tlv_header_t hdr; |
| 421 | A_UINT16 max_tx_queue_groups; /* max txq_group_id + 1 */ |
| 422 | } POSTPACK; |
| 423 | |
| 424 | /* |
| 425 | * HTT option TLV for specifying whether the target supports an extended |
| 426 | * version of the HTT tx descriptor. If the target provides this TLV |
| 427 | * and specifies in the TLV that the target supports an extended version |
| 428 | * of the HTT tx descriptor, the target must check the "extension" bit in |
| 429 | * the HTT tx descriptor, and if the extension bit is set, to expect a |
| 430 | * HTT tx MSDU extension descriptor immediately following the HTT tx MSDU |
| 431 | * descriptor. Furthermore, the target must provide room for the HTT |
| 432 | * tx MSDU extension descriptor in the target's TX_FRM buffer. |
| 433 | * This option is intended for systems where the host needs to explicitly |
| 434 | * control the transmission parameters such as tx power for individual |
| 435 | * tx frames. |
| 436 | * The SUPPORT_TX_MSDU_DESC_EXT TLB can be sent by the target to the host |
| 437 | * as a suffix to the VERSION_CONF message to explicitly specify whether |
| 438 | * the target supports the HTT tx MSDU extension descriptor. |
| 439 | * Lack of a SUPPORT_TX_MSDU_DESC_EXT from the target shall be interpreted |
| 440 | * by the host as lack of target support for the HTT tx MSDU extension |
| 441 | * descriptor; the host shall provide HTT tx MSDU extension descriptors in |
| 442 | * the HTT_H2T TX_FRM messages only if the target indicates it supports |
| 443 | * the HTT tx MSDU extension descriptor. |
| 444 | * The host is not required to provide the HTT tx MSDU extension descriptor |
| 445 | * just because the target supports it; the target must check the |
| 446 | * "extension" bit in the HTT tx MSDU descriptor to determine whether an |
| 447 | * extension descriptor is present. |
| 448 | */ |
| 449 | enum HTT_OPTION_TLV_SUPPORT_TX_MSDU_DESC_EXT_VALUES { |
| 450 | HTT_OPTION_TLV_TX_MSDU_DESC_EXT_NO_SUPPORT = 0x0, |
| 451 | HTT_OPTION_TLV_TX_MSDU_DESC_EXT_SUPPORT = 0x1, |
| 452 | }; |
| 453 | PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { |
| 454 | struct htt_option_tlv_header_t hdr; |
| 455 | A_UINT16 tx_msdu_desc_ext_support;/*SUPPORT_TX_MSDU_DESC_EXT enum*/ |
| 456 | } POSTPACK; |
| 457 | |
| 458 | |
| 459 | /*=== host -> target messages ===============================================*/ |
| 460 | |
| 461 | enum htt_h2t_msg_type { |
| 462 | HTT_H2T_MSG_TYPE_VERSION_REQ = 0x0, |
| 463 | HTT_H2T_MSG_TYPE_TX_FRM = 0x1, |
| 464 | HTT_H2T_MSG_TYPE_RX_RING_CFG = 0x2, |
| 465 | HTT_H2T_MSG_TYPE_STATS_REQ = 0x3, |
| 466 | HTT_H2T_MSG_TYPE_SYNC = 0x4, |
| 467 | HTT_H2T_MSG_TYPE_AGGR_CFG = 0x5, |
| 468 | HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 0x6, |
| 469 | DEPRECATED_HTT_H2T_MSG_TYPE_MGMT_TX = 0x7, /* no longer used */ |
| 470 | HTT_H2T_MSG_TYPE_WDI_IPA_CFG = 0x8, |
| 471 | HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQ = 0x9, |
| 472 | HTT_H2T_MSG_TYPE_AGGR_CFG_EX = 0xa, /*per vdev amsdu subfrm limit*/ |
| 473 | /* keep this last */ |
| 474 | HTT_H2T_NUM_MSGS |
| 475 | }; |
| 476 | |
| 477 | /* |
| 478 | * HTT host to target message type - |
| 479 | * stored in bits 7:0 of the first word of the message |
| 480 | */ |
| 481 | #define HTT_H2T_MSG_TYPE_M 0xff |
| 482 | #define HTT_H2T_MSG_TYPE_S 0 |
| 483 | |
| 484 | #define HTT_H2T_MSG_TYPE_SET(word, msg_type) \ |
| 485 | do { \ |
| 486 | HTT_CHECK_SET_VAL(HTT_H2T_MSG_TYPE, msg_type); \ |
| 487 | (word) |= ((msg_type) << HTT_H2T_MSG_TYPE_S); \ |
| 488 | } while (0) |
| 489 | #define HTT_H2T_MSG_TYPE_GET(word) \ |
| 490 | (((word) & HTT_H2T_MSG_TYPE_M) >> HTT_H2T_MSG_TYPE_S) |
| 491 | |
| 492 | /** |
| 493 | * @brief target -> host version number request message definition |
| 494 | * |
| 495 | * |31 24|23 16|15 8|7 0| |
| 496 | * |----------------+----------------+----------------+----------------| |
| 497 | * | reserved | msg type | |
| 498 | * |-------------------------------------------------------------------| |
| 499 | * : option request TLV (optional) | |
| 500 | * :...................................................................: |
| 501 | * |
| 502 | * The VER_REQ message may consist of a single 4-byte word, or may be |
| 503 | * extended with TLVs that specify which HTT options the host is requesting |
| 504 | * from the target. |
| 505 | * The following option TLVs may be appended to the VER_REQ message: |
| 506 | * - HL_SUPPRESS_TX_COMPL_IND |
| 507 | * - HL_MAX_TX_QUEUE_GROUPS |
| 508 | * These TLVs may appear in an arbitrary order. Any number of these TLVs |
| 509 | * may be appended to the VER_REQ message (but only one TLV of each type). |
| 510 | * |
| 511 | * Header fields: |
| 512 | * - MSG_TYPE |
| 513 | * Bits 7:0 |
| 514 | * Purpose: identifies this as a version number request message |
| 515 | * Value: 0x0 |
| 516 | */ |
| 517 | |
| 518 | #define HTT_VER_REQ_BYTES 4 |
| 519 | |
| 520 | /* TBDXXX: figure out a reasonable number */ |
| 521 | #define HTT_HL_DATA_SVC_PIPE_DEPTH 24 |
| 522 | #define HTT_LL_DATA_SVC_PIPE_DEPTH 64 |
| 523 | |
| 524 | /** |
| 525 | * @brief HTT tx MSDU descriptor |
| 526 | * |
| 527 | * @details |
| 528 | * The HTT tx MSDU descriptor is created by the host HTT SW for each |
| 529 | * tx MSDU. The HTT tx MSDU descriptor contains the information that |
| 530 | * the target firmware needs for the FW's tx processing, particularly |
| 531 | * for creating the HW msdu descriptor. |
| 532 | * The same HTT tx descriptor is used for HL and LL systems, though |
| 533 | * a few fields within the tx descriptor are used only by LL or |
| 534 | * only by HL. |
| 535 | * The HTT tx descriptor is defined in two manners: by a struct with |
| 536 | * bitfields, and by a series of [dword offset, bit mask, bit shift] |
| 537 | * definitions. |
| 538 | * The target should use the struct def, for simplicitly and clarity, |
| 539 | * but the host shall use the bit-mast + bit-shift defs, to be endian- |
| 540 | * neutral. Specifically, the host shall use the get/set macros built |
| 541 | * around the mask + shift defs. |
| 542 | */ |
| 543 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_S 0 |
| 544 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_80211_HDR_M 0x1 |
| 545 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_S 1 |
| 546 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_AGGR_M 0x2 |
| 547 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_S 2 |
| 548 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_ENCRYPT_M 0x4 |
| 549 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_S 3 |
| 550 | #define HTT_TX_MSDU_DESC_RAW_SUBTYPE_NO_CLASSIFY_M 0x8 |
| 551 | |
| 552 | #define HTT_TX_VDEV_ID_WORD 0 |
| 553 | #define HTT_TX_VDEV_ID_MASK 0x3f |
| 554 | #define HTT_TX_VDEV_ID_SHIFT 16 |
| 555 | |
| 556 | #define HTT_TX_L3_CKSUM_OFFLOAD 1 |
| 557 | #define HTT_TX_L4_CKSUM_OFFLOAD 2 |
| 558 | |
| 559 | #define HTT_TX_MSDU_LEN_DWORD 1 |
| 560 | #define HTT_TX_MSDU_LEN_MASK 0xffff; |
| 561 | |
| 562 | /* |
| 563 | * HTT_VAR_PADDR macros |
| 564 | * Allow physical / bus addresses to be either a single 32-bit value, |
| 565 | * or a 64-bit value, stored as a little-endian lo,hi pair of 32-bit parts |
| 566 | */ |
| 567 | |
| 568 | /* |
| 569 | * Note that in this macro A_UINT32 has been converted to |
| 570 | * uint32_t only to address checkpath errors caused by declaring |
| 571 | * var_name as A_UINT32. |
| 572 | */ |
| 573 | #define HTT_VAR_PADDR32(var_name) uint32_t (var_name) |
| 574 | |
| 575 | #define HTT_VAR_PADDR64_LE(var_name) \ |
| 576 | struct { \ |
| 577 | /* little-endian: lo precedes hi */ \ |
| 578 | A_UINT32 lo; \ |
| 579 | A_UINT32 hi; \ |
| 580 | } var_name |
| 581 | |
| 582 | /* |
| 583 | * TEMPLATE_HTT_TX_MSDU_DESC_T: |
| 584 | * This macro defines a htt_tx_msdu_descXXX_t in which any physical |
| 585 | * addresses are stored in a XXX-bit field. |
| 586 | * This macro is used to define both htt_tx_msdu_desc32_t and |
| 587 | * htt_tx_msdu_desc64_t structs. |
| 588 | */ |
| 589 | #define TEMPLATE_HTT_TX_MSDU_DESC_T(_paddr_bits_, _paddr__frags_desc_ptr_) \ |
| 590 | PREPACK struct htt_tx_msdu_desc ## _paddr_bits_ ## _t \ |
| 591 | { \ |
| 592 | /* DWORD 0: flags and meta-data */ \ |
| 593 | A_UINT32 \ |
| 594 | msg_type:8, /* HTT_H2T_MSG_TYPE_TX_FRM */ \ |
| 595 | \ |
| 596 | /* pkt_subtype - \ |
| 597 | * Detailed specification of the tx frame contents, extending the \ |
| 598 | * general specification provided by pkt_type. \ |
| 599 | * FIX THIS: ADD COMPLETE SPECS FOR THIS FIELDS VALUE, e.g. \ |
| 600 | *pkt_type | pkt_subtype \ |
| 601 | *============================================================== \ |
| 602 | *802.3 | bit 0:3 - Reserved \ |
| 603 | * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| 604 | * | not appended to the HTT message \ |
| 605 | * | 0x1 - Copy-Engine Classification Results \ |
| 606 | * | appended to the HTT message in the \ |
| 607 | * | format: \ |
| 608 | * | [HTT tx desc, frame header, \ |
| 609 | * | CE classification results] \ |
| 610 | * | The CE classification results begin \ |
| 611 | * | at the next 4-byte boundary after \ |
| 612 | * | the frame header. \ |
| 613 | *------------+------------------------------------------------- \ |
| 614 | *Eth2 | bit 0:3 - Reserved \ |
| 615 | * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| 616 | * | not appended to the HTT message \ |
| 617 | * | 0x1 - Copy-Engine Classification Results \ |
| 618 | * | appended to the HTT message. \ |
| 619 | * | See the above specification of the \ |
| 620 | * | CE classification results location. \ |
| 621 | *------------+------------------------------------------------- \ |
| 622 | *native WiFi | bit 0:3 - Reserved \ |
| 623 | * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| 624 | * | not appended to the HTT message \ |
| 625 | * | 0x1 - Copy-Engine Classification Results \ |
| 626 | * | appended to the HTT message. \ |
| 627 | * | See the above specification of the \ |
| 628 | * | CE classification results location. \ |
| 629 | *------------+------------------------------------------------- \ |
| 630 | *mgmt | 0x0 - 802.11 MAC header absent \ |
| 631 | * | 0x1 - 802.11 MAC header present \ |
| 632 | *------------+------------------------------------------------- \ |
| 633 | *raw | bit 0: 0x0 - 802.11 MAC header absent \ |
| 634 | * | 0x1 - 802.11 MAC header present \ |
| 635 | * | bit 1: 0x0 - allow aggregation \ |
| 636 | * | 0x1 - don't allow aggregation \ |
| 637 | * | bit 2: 0x0 - perform encryption \ |
| 638 | * | 0x1 - don't perform encryption \ |
| 639 | * | bit 3: 0x0 - perform tx classification / queuing \ |
| 640 | * | 0x1 - don't perform tx classification; \ |
| 641 | * | insert the frame into the "misc" \ |
| 642 | * | tx queue \ |
| 643 | * | bit 4: 0x0 - Copy-Engine Classification Results \ |
| 644 | * | not appended to the HTT message \ |
| 645 | * | 0x1 - Copy-Engine Classification Results \ |
| 646 | * | appended to the HTT message. \ |
| 647 | * | See the above specification of the \ |
| 648 | * | CE classification results location. \ |
| 649 | */ \ |
| 650 | pkt_subtype:5, \ |
| 651 | \ |
| 652 | /* pkt_type - \ |
| 653 | * General specification of the tx frame contents. \ |
| 654 | * The htt_pkt_type enum should be used to specify \ |
| 655 | * and check the value of this field. \ |
| 656 | */ \ |
| 657 | pkt_type:3, \ |
| 658 | \ |
| 659 | /* vdev_id - \ |
| 660 | * ID for the vdev that is sending this tx frame. \ |
| 661 | * For certain non-standard packet types, e.g. pkt_type == raw \ |
| 662 | * and (pkt_subtype >> 3) == 1, this field is not relevant/valid. \ |
| 663 | * This field is used primarily for determining where to queue \ |
| 664 | * broadcast and multicast frames. \ |
| 665 | */ \ |
| 666 | vdev_id:6, \ |
| 667 | /* ext_tid - \ |
| 668 | * The extended traffic ID. \ |
| 669 | * If the TID is unknown, the extended TID is set to \ |
| 670 | * HTT_TX_EXT_TID_INVALID. \ |
| 671 | * If the tx frame is QoS data, then the extended TID has the 0-15 \ |
| 672 | * value of the QoS TID. \ |
| 673 | * If the tx frame is non-QoS data, then the extended TID is set to \ |
| 674 | * HTT_TX_EXT_TID_NON_QOS. \ |
| 675 | * If the tx frame is multicast or broadcast, then the extended TID \ |
| 676 | * is set to HTT_TX_EXT_TID_MCAST_BCAST. \ |
| 677 | */ \ |
| 678 | ext_tid:5, \ |
| 679 | \ |
| 680 | /* postponed - \ |
| 681 | * This flag indicates whether the tx frame has been downloaded to \ |
| 682 | * the target before but discarded by the target, and now is being \ |
| 683 | * downloaded again; or if this is a new frame that is being \ |
| 684 | * downloaded for the first time. \ |
| 685 | * This flag allows the target to determine the correct order for \ |
| 686 | * transmitting new vs. old frames. \ |
| 687 | * value: 0 -> new frame, 1 -> re-send of a previously |
| 688 | * sent frame \ |
| 689 | * This flag only applies to HL systems, since in LL systems, \ |
| 690 | * the tx flow control is handled entirely within the target. \ |
| 691 | */ \ |
| 692 | postponed:1, \ |
| 693 | \ |
| 694 | /* extension - \ |
| 695 | * This flag indicates whether a HTT tx MSDU extension descriptor\ |
| 696 | * (htt_tx_msdu_desc_ext_t) follows this HTT tx MSDU descriptor.\ |
| 697 | * \ |
| 698 | * 0x0 - no extension MSDU descriptor is present \ |
| 699 | * 0x1 - an extension MSDU descriptor immediately follows the \ |
| 700 | * regular MSDU descriptor \ |
| 701 | */ \ |
| 702 | extension:1, \ |
| 703 | \ |
| 704 | /* cksum_offload - \ |
| 705 | * This flag indicates whether checksum offload is enabled or not \ |
| 706 | * for this frame. Target FW use this flag to turn on HW checksumming \ |
| 707 | * 0x0 - No checksum offload \ |
| 708 | * 0x1 - L3 header checksum only \ |
| 709 | * 0x2 - L4 checksum only \ |
| 710 | * 0x3 - L3 header checksum + L4 checksum \ |
| 711 | */ \ |
| 712 | cksum_offload:2, \ |
| 713 | \ |
| 714 | /* tx_comp_req - \ |
| 715 | * This flag indicates whether Tx Completion \ |
| 716 | * from fw is required or not. \ |
| 717 | * This flag is only relevant if tx completion is not \ |
| 718 | * universally enabled. \ |
| 719 | * For all LL systems, tx completion is mandatory, \ |
| 720 | * so this flag will be irrelevant. \ |
| 721 | * For HL systems tx completion is optional, but HL systems in which \ |
| 722 | * the bus throughput exceeds the WLAN throughput will \ |
| 723 | * probably want to always use tx completion, and thus \ |
| 724 | * would not check this flag. \ |
| 725 | * This flag is required when tx completions are not used universally, \ |
| 726 | * but are still required for certain tx frames for which \ |
| 727 | * an OTA delivery acknowledgment is needed by the host. \ |
| 728 | * In practice, this would be for HL systems in which the \ |
| 729 | * bus throughput is less than the WLAN throughput. \ |
| 730 | * \ |
| 731 | * 0x0 - Tx Completion Indication from Fw not required \ |
| 732 | * 0x1 - Tx Completion Indication from Fw is required \ |
| 733 | */ \ |
| 734 | tx_compl_req:1; \ |
| 735 | \ |
| 736 | \ |
| 737 | /* DWORD 1: MSDU length and ID */ \ |
| 738 | A_UINT32 \ |
| 739 | len:16, /* MSDU length, in bytes */ \ |
| 740 | id:16; /* MSDU ID used to identify the MSDU to the host, \ |
| 741 | * and this id is used to calculate fragmentation \ |
| 742 | * descriptor pointer inside the target based on \ |
| 743 | * the base address, configured inside the target. \ |
| 744 | */ \ |
| 745 | \ |
| 746 | /* DWORD 2 (or 2-3): fragmentation descriptor bus address */ \ |
| 747 | /* frags_desc_ptr - \ |
| 748 | * The fragmentation descriptor pointer tells the HW's MAC DMA \ |
| 749 | * where the tx frame's fragments reside in memory. \ |
| 750 | * This field only applies to LL systems, since in HL systems the \ |
| 751 | * (degenerate single-fragment) fragmentation descriptor is created \ |
| 752 | * within the target. \ |
| 753 | */ \ |
| 754 | _paddr__frags_desc_ptr_; \ |
| 755 | \ |
| 756 | /* DWORD 3 (or 4): peerid, chanfreq */ \ |
| 757 | /* \ |
| 758 | * Peer ID : Target can use this value to know which peer-id packet \ |
| 759 | * destined to. \ |
| 760 | * It's intended to be specified by host in case of NAWDS. \ |
| 761 | */ \ |
| 762 | A_UINT16 peerid; \ |
| 763 | \ |
| 764 | /* \ |
| 765 | * Channel frequency: This identifies the desired channel \ |
| 766 | * frequency (in mhz) for tx frames. This is used by FW to help \ |
| 767 | * determine when it is safe to transmit or drop frames for \ |
| 768 | * off-channel operation. \ |
| 769 | * The default value of zero indicates to FW that the \ |
| 770 | * corresponding VDEV's home channel (if there is one) is \ |
| 771 | * the desired channel frequency. \ |
| 772 | */ \ |
| 773 | A_UINT16 chanfreq; \ |
| 774 | \ |
| 775 | /* Reason reserved is commented is increasing the htt |
| 776 | * structure size leads to some wierd issues. |
| 777 | * A_UINT32 reserved_dword3_bits0_31; \ |
| 778 | */ \ |
| 779 | } POSTPACK |
| 780 | /* define a htt_tx_msdu_desc32_t type */ |
| 781 | TEMPLATE_HTT_TX_MSDU_DESC_T(32, HTT_VAR_PADDR32(frags_desc_ptr)); |
| 782 | /* define a htt_tx_msdu_desc64_t type */ |
| 783 | TEMPLATE_HTT_TX_MSDU_DESC_T(64, HTT_VAR_PADDR64_LE(frags_desc_ptr)); |
| 784 | /* |
| 785 | * Make htt_tx_msdu_desc_t be an alias for either |
| 786 | * htt_tx_msdu_desc32_t or htt_tx_msdu_desc64_t |
| 787 | */ |
| 788 | #if HTT_PADDR64 |
| 789 | #define htt_tx_msdu_desc_t htt_tx_msdu_desc64_t |
| 790 | #else |
| 791 | #define htt_tx_msdu_desc_t htt_tx_msdu_desc32_t |
| 792 | #endif |
| 793 | |
| 794 | /* decriptor information for Management frame*/ |
| 795 | /* |
| 796 | * THIS htt_mgmt_tx_desc_t STRUCT IS DEPRECATED - DON'T USE IT. |
| 797 | * BOTH MANAGEMENT AND DATA FRAMES SHOULD USE htt_tx_msdu_desc_t. |
| 798 | */ |
| 799 | #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32 |
| 800 | extern A_UINT32 mgmt_hdr_len; |
| 801 | PREPACK struct htt_mgmt_tx_desc_t { |
| 802 | A_UINT32 msg_type; |
| 803 | #if HTT_PADDR64 |
| 804 | A_UINT64 frag_paddr; /* DMAble address of the data */ |
| 805 | #else |
| 806 | A_UINT32 frag_paddr; /* DMAble address of the data */ |
| 807 | #endif |
| 808 | A_UINT32 desc_id; /* returned to host during completion |
| 809 | * to free the meory*/ |
| 810 | A_UINT32 len; /* Fragment length */ |
| 811 | A_UINT32 vdev_id; /* virtual device ID */ |
| 812 | A_UINT8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN]; /* frm header */ |
| 813 | } POSTPACK; |
| 814 | |
| 815 | PREPACK struct htt_mgmt_tx_compl_ind { |
| 816 | A_UINT32 desc_id; |
| 817 | A_UINT32 status; |
| 818 | } POSTPACK; |
| 819 | |
| 820 | /* |
| 821 | * This SDU header size comes from the summation of the following: |
| 822 | * 1. Max of: |
| 823 | * a. Native WiFi header, for native WiFi frames: 24 bytes |
| 824 | * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4) |
| 825 | * b. 802.11 header, for raw frames: 36 bytes |
| 826 | * (frame control, duration / ID, addr1, addr2, addr3, seq ctrl, addr4, |
| 827 | * QoS header, HT header) |
| 828 | * c. 802.3 header, for ethernet frames: 14 bytes |
| 829 | * (destination address, source address, ethertype / length) |
| 830 | * 2. Max of: |
| 831 | * a. IPv4 header, up through the DiffServ Code Point: 2 bytes |
| 832 | * b. IPv6 header, up through the Traffic Class: 2 bytes |
| 833 | * 3. 802.1Q VLAN header: 4 bytes |
| 834 | * 4. LLC/SNAP header: 8 bytes |
| 835 | */ |
| 836 | #define HTT_TX_HDR_SIZE_NATIVE_WIFI 30 |
| 837 | #define HTT_TX_HDR_SIZE_802_11_RAW 36 |
| 838 | #define HTT_TX_HDR_SIZE_ETHERNET 14 |
| 839 | |
| 840 | #define HTT_TX_HDR_SIZE_OUTER_HDR_MAX HTT_TX_HDR_SIZE_802_11_RAW |
| 841 | A_COMPILE_TIME_ASSERT(htt_encap_hdr_size_max_check_nwifi, |
| 842 | HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= |
| 843 | HTT_TX_HDR_SIZE_NATIVE_WIFI); |
| 844 | A_COMPILE_TIME_ASSERT(htt_encap_hdr_size_max_check_enet, |
| 845 | HTT_TX_HDR_SIZE_OUTER_HDR_MAX >= |
| 846 | HTT_TX_HDR_SIZE_ETHERNET); |
| 847 | |
| 848 | #define HTT_HL_TX_HDR_SIZE_IP 1600 /* also include payload */ |
| 849 | #define HTT_LL_TX_HDR_SIZE_IP 16 /*up to the end of UDP hdr for v4*/ |
| 850 | |
| 851 | #define HTT_TX_HDR_SIZE_802_1Q 4 |
| 852 | #define HTT_TX_HDR_SIZE_LLC_SNAP 8 |
| 853 | |
| 854 | |
| 855 | #define HTT_COMMON_TX_FRM_HDR_LEN \ |
| 856 | (HTT_TX_HDR_SIZE_OUTER_HDR_MAX + \ |
| 857 | HTT_TX_HDR_SIZE_802_1Q + \ |
| 858 | HTT_TX_HDR_SIZE_LLC_SNAP) |
| 859 | |
| 860 | #define HTT_HL_TX_FRM_HDR_LEN \ |
| 861 | (HTT_COMMON_TX_FRM_HDR_LEN + HTT_HL_TX_HDR_SIZE_IP) |
| 862 | |
| 863 | #define HTT_LL_TX_FRM_HDR_LEN \ |
| 864 | (HTT_COMMON_TX_FRM_HDR_LEN + HTT_LL_TX_HDR_SIZE_IP) |
| 865 | |
| 866 | #define HTT_TX_DESC_LEN sizeof(struct htt_tx_msdu_desc_t) |
| 867 | |
| 868 | /* dword 0 */ |
| 869 | #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_BYTES 0 |
| 870 | #define HTT_TX_DESC_PKT_SUBTYPE_OFFSET_DWORD 0 |
| 871 | #define HTT_TX_DESC_PKT_SUBTYPE_M 0x00001f00 |
| 872 | #define HTT_TX_DESC_PKT_SUBTYPE_S 8 |
| 873 | |
| 874 | #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_BYTES 0 |
| 875 | #define HTT_TX_DESC_NO_ENCRYPT_OFFSET_DWORD 0 |
| 876 | #define HTT_TX_DESC_NO_ENCRYPT_M 0x00000400 |
| 877 | #define HTT_TX_DESC_NO_ENCRYPT_S 10 |
| 878 | |
| 879 | #define HTT_TX_DESC_PKT_TYPE_OFFSET_BYTES 0 |
| 880 | #define HTT_TX_DESC_PKT_TYPE_OFFSET_DWORD 0 |
| 881 | #define HTT_TX_DESC_PKT_TYPE_M 0x0000e000 |
| 882 | #define HTT_TX_DESC_PKT_TYPE_S 13 |
| 883 | |
| 884 | #define HTT_TX_DESC_VDEV_ID_OFFSET_BYTES 0 |
| 885 | #define HTT_TX_DESC_VDEV_ID_OFFSET_DWORD 0 |
| 886 | #define HTT_TX_DESC_VDEV_ID_M 0x003f0000 |
| 887 | #define HTT_TX_DESC_VDEV_ID_S 16 |
| 888 | |
| 889 | #define HTT_TX_DESC_EXT_TID_OFFSET_BYTES 0 |
| 890 | #define HTT_TX_DESC_EXT_TID_OFFSET_DWORD 0 |
| 891 | #define HTT_TX_DESC_EXT_TID_M 0x07c00000 |
| 892 | #define HTT_TX_DESC_EXT_TID_S 22 |
| 893 | |
| 894 | #define HTT_TX_DESC_POSTPONED_OFFSET_BYTES 0 |
| 895 | #define HTT_TX_DESC_POSTPONED_OFFSET_DWORD 0 |
| 896 | #define HTT_TX_DESC_POSTPONED_M 0x08000000 |
| 897 | #define HTT_TX_DESC_POSTPONED_S 27 |
| 898 | |
| 899 | #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_BYTES 0 |
| 900 | #define HTT_TX_DESC_CKSUM_OFFLOAD_OFFSET_DWORD 0 |
| 901 | #define HTT_TX_DESC_CKSUM_OFFLOAD_M 0x60000000 |
| 902 | #define HTT_TX_DESC_CKSUM_OFFLOAD_S 29 |
| 903 | |
| 904 | #define HTT_TX_DESC_TX_COMP_OFFSET_BYTES 0 |
| 905 | #define HTT_TX_DESC_TX_COMP_OFFSET_DWORD 0 |
| 906 | #define HTT_TX_DESC_TX_COMP_M 0x80000000 |
| 907 | #define HTT_TX_DESC_TX_COMP_S 31 |
| 908 | |
| 909 | /* dword 1 */ |
| 910 | #define HTT_TX_DESC_FRM_LEN_OFFSET_BYTES 4 |
| 911 | #define HTT_TX_DESC_FRM_LEN_OFFSET_DWORD 1 |
| 912 | #define HTT_TX_DESC_FRM_LEN_M 0x0000ffff |
| 913 | #define HTT_TX_DESC_FRM_LEN_S 0 |
| 914 | |
| 915 | #define HTT_TX_DESC_FRM_ID_OFFSET_BYTES 4 |
| 916 | #define HTT_TX_DESC_FRM_ID_OFFSET_DWORD 1 |
| 917 | #define HTT_TX_DESC_FRM_ID_M 0xffff0000 |
| 918 | #define HTT_TX_DESC_FRM_ID_S 16 |
| 919 | |
| 920 | /* dword 2 */ |
| 921 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_BYTES 8 |
| 922 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_OFFSET_DWORD 2 |
| 923 | /* for systems using 64-bit format for bus addresses */ |
| 924 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_M 0xffffffff |
| 925 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_HI_S 0 |
| 926 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_M 0xffffffff |
| 927 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_LO_S 0 |
| 928 | /* for systems using 32-bit format for bus addresses */ |
| 929 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_M 0xffffffff |
| 930 | #define HTT_TX_DESC_FRAGS_DESC_PADDR_S 0 |
| 931 | |
| 932 | /* dword 3 */ |
| 933 | #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 16 |
| 934 | #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 12 |
| 935 | #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 \ |
| 936 | (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 >> 2) |
| 937 | #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 \ |
| 938 | (HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 >> 2) |
| 939 | |
| 940 | #if HTT_PADDR64 |
| 941 | #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_64 |
| 942 | #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_64 |
| 943 | #else |
| 944 | #define HTT_TX_DESC_PEER_ID_OFFSET_BYTES HTT_TX_DESC_PEER_ID_OFFSET_BYTES_32 |
| 945 | #define HTT_TX_DESC_PEER_ID_OFFSET_DWORD HTT_TX_DESC_PEER_ID_OFFSET_DWORD_32 |
| 946 | #endif |
| 947 | |
| 948 | #define HTT_TX_DESC_PEER_ID_M 0x0000ffff |
| 949 | #define HTT_TX_DESC_PEER_ID_S 0 |
| 950 | /* |
| 951 | * TEMPORARY: |
| 952 | * The original definitions for the PEER_ID fields contained typos |
| 953 | * (with _DESC_PADDR appended to this PEER_ID field name). |
| 954 | * Retain deprecated original names for PEER_ID fields until all code that |
| 955 | * refers to them has been updated. |
| 956 | */ |
| 957 | #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_BYTES \ |
| 958 | HTT_TX_DESC_PEER_ID_OFFSET_BYTES |
| 959 | #define HTT_TX_DESC_PEERID_DESC_PADDR_OFFSET_DWORD \ |
| 960 | HTT_TX_DESC_PEER_ID_OFFSET_DWORD |
| 961 | #define HTT_TX_DESC_PEERID_DESC_PADDR_M \ |
| 962 | HTT_TX_DESC_PEER_ID_M |
| 963 | #define HTT_TX_DESC_PEERID_DESC_PADDR_S \ |
| 964 | HTT_TX_DESC_PEER_ID_S |
| 965 | |
| 966 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 16 /* to dword with chan freq */ |
| 967 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 12 /* to dword with chan freq */ |
| 968 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 \ |
| 969 | (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 >> 2) |
| 970 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 \ |
| 971 | (HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 >> 2) |
| 972 | |
| 973 | #if HTT_PADDR64 |
| 974 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_64 |
| 975 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_64 |
| 976 | #else |
| 977 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES HTT_TX_DESC_CHAN_FREQ_OFFSET_BYTES_32 |
| 978 | #define HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD HTT_TX_DESC_CHAN_FREQ_OFFSET_DWORD_32 |
| 979 | #endif |
| 980 | |
| 981 | #define HTT_TX_DESC_CHAN_FREQ_M 0xffff0000 |
| 982 | #define HTT_TX_DESC_CHAN_FREQ_S 16 |
| 983 | |
| 984 | #define HTT_TX_DESC_PKT_SUBTYPE_GET(_var) \ |
| 985 | (((_var) & HTT_TX_DESC_PKT_SUBTYPE_M) >> HTT_TX_DESC_PKT_SUBTYPE_S) |
| 986 | #define HTT_TX_DESC_PKT_SUBTYPE_SET(_var, _val) \ |
| 987 | do { \ |
| 988 | HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_SUBTYPE, _val); \ |
| 989 | ((_var) |= ((_val) << HTT_TX_DESC_PKT_SUBTYPE_S)); \ |
| 990 | } while (0) |
| 991 | |
| 992 | #define HTT_TX_DESC_NO_ENCRYPT_GET(_var) \ |
| 993 | (((_var) & HTT_TX_DESC_NO_ENCRYPT_M) >> HTT_TX_DESC_NO_ENCRYPT_S) |
| 994 | #define HTT_TX_DESC_NO_ENCRYPT_SET(_var, _val) \ |
| 995 | do { \ |
| 996 | HTT_CHECK_SET_VAL(HTT_TX_DESC_NO_ENCRYPT, _val); \ |
| 997 | ((_var) |= ((_val) << HTT_TX_DESC_NO_ENCRYPT_S)); \ |
| 998 | } while (0) |
| 999 | |
| 1000 | #define HTT_TX_DESC_PKT_TYPE_GET(_var) \ |
| 1001 | (((_var) & HTT_TX_DESC_PKT_TYPE_M) >> HTT_TX_DESC_PKT_TYPE_S) |
| 1002 | #define HTT_TX_DESC_PKT_TYPE_SET(_var, _val) \ |
| 1003 | do { \ |
| 1004 | HTT_CHECK_SET_VAL(HTT_TX_DESC_PKT_TYPE, _val); \ |
| 1005 | ((_var) |= ((_val) << HTT_TX_DESC_PKT_TYPE_S)); \ |
| 1006 | } while (0) |
| 1007 | |
| 1008 | #define HTT_TX_DESC_VDEV_ID_GET(_var) \ |
| 1009 | (((_var) & HTT_TX_DESC_VDEV_ID_M) >> HTT_TX_DESC_VDEV_ID_S) |
| 1010 | #define HTT_TX_DESC_VDEV_ID_SET(_var, _val) \ |
| 1011 | do { \ |
| 1012 | HTT_CHECK_SET_VAL(HTT_TX_DESC_VDEV_ID, _val); \ |
| 1013 | ((_var) |= ((_val) << HTT_TX_DESC_VDEV_ID_S)); \ |
| 1014 | } while (0) |
| 1015 | |
| 1016 | #define HTT_TX_DESC_EXT_TID_GET(_var) \ |
| 1017 | (((_var) & HTT_TX_DESC_EXT_TID_M) >> HTT_TX_DESC_EXT_TID_S) |
| 1018 | #define HTT_TX_DESC_EXT_TID_SET(_var, _val) \ |
| 1019 | do { \ |
| 1020 | HTT_CHECK_SET_VAL(HTT_TX_DESC_EXT_TID, _val); \ |
| 1021 | ((_var) |= ((_val) << HTT_TX_DESC_EXT_TID_S)); \ |
| 1022 | } while (0) |
| 1023 | |
| 1024 | #define HTT_TX_DESC_POSTPONED_GET(_var) \ |
| 1025 | (((_var) & HTT_TX_DESC_POSTPONED_M) >> HTT_TX_DESC_POSTPONED_S) |
| 1026 | #define HTT_TX_DESC_POSTPONED_SET(_var, _val) \ |
| 1027 | do { \ |
| 1028 | HTT_CHECK_SET_VAL(HTT_TX_DESC_POSTPONED, _val); \ |
| 1029 | ((_var) |= ((_val) << HTT_TX_DESC_POSTPONED_S)); \ |
| 1030 | } while (0) |
| 1031 | |
| 1032 | #define HTT_TX_DESC_FRM_LEN_GET(_var) \ |
| 1033 | (((_var) & HTT_TX_DESC_FRM_LEN_M) >> HTT_TX_DESC_FRM_LEN_S) |
| 1034 | #define HTT_TX_DESC_FRM_LEN_SET(_var, _val) \ |
| 1035 | do { \ |
| 1036 | HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_LEN, _val); \ |
| 1037 | ((_var) |= ((_val) << HTT_TX_DESC_FRM_LEN_S)); \ |
| 1038 | } while (0) |
| 1039 | |
| 1040 | #define HTT_TX_DESC_FRM_ID_GET(_var) \ |
| 1041 | (((_var) & HTT_TX_DESC_FRM_ID_M) >> HTT_TX_DESC_FRM_ID_S) |
| 1042 | #define HTT_TX_DESC_FRM_ID_SET(_var, _val) \ |
| 1043 | do { \ |
| 1044 | HTT_CHECK_SET_VAL(HTT_TX_DESC_FRM_ID, _val); \ |
| 1045 | ((_var) |= ((_val) << HTT_TX_DESC_FRM_ID_S)); \ |
| 1046 | } while (0) |
| 1047 | |
| 1048 | #define HTT_TX_DESC_CKSUM_OFFLOAD_GET(_var) \ |
| 1049 | (((_var) & HTT_TX_DESC_CKSUM_OFFLOAD_M) >> HTT_TX_DESC_CKSUM_OFFLOAD_S) |
| 1050 | #define HTT_TX_DESC_CKSUM_OFFLOAD_SET(_var, _val) \ |
| 1051 | do { \ |
| 1052 | HTT_CHECK_SET_VAL(HTT_TX_DESC_CKSUM_OFFLOAD, _val); \ |
| 1053 | ((_var) |= ((_val) << HTT_TX_DESC_CKSUM_OFFLOAD_S)); \ |
| 1054 | } while (0) |
| 1055 | |
| 1056 | #define HTT_TX_DESC_TX_COMP_GET(_var) \ |
| 1057 | (((_var) & HTT_TX_DESC_TX_COMP_M) >> HTT_TX_DESC_TX_COMP_S) |
| 1058 | #define HTT_TX_DESC_TX_COMP_SET(_var, _val) \ |
| 1059 | do { \ |
| 1060 | HTT_CHECK_SET_VAL(HTT_TX_DESC_TX_COMP, _val); \ |
| 1061 | ((_var) |= ((_val) << HTT_TX_DESC_TX_COMP_S)); \ |
| 1062 | } while (0) |
| 1063 | |
| 1064 | #define HTT_TX_DESC_PEER_ID_GET(_var) \ |
| 1065 | (((_var) & HTT_TX_DESC_PEER_ID_M) >> HTT_TX_DESC_PEER_ID_S) |
| 1066 | #define HTT_TX_DESC_PEER_ID_SET(_var, _val) \ |
| 1067 | do { \ |
| 1068 | HTT_CHECK_SET_VAL(HTT_TX_DESC_PEER_ID, _val); \ |
| 1069 | ((_var) |= ((_val) << HTT_TX_DESC_PEER_ID_S)); \ |
| 1070 | } while (0) |
| 1071 | |
| 1072 | #define HTT_TX_DESC_CHAN_FREQ_GET(_var) \ |
| 1073 | (((_var) & HTT_TX_DESC_CHAN_FREQ_M) >> HTT_TX_DESC_CHAN_FREQ_S) |
| 1074 | #define HTT_TX_DESC_CHAN_FREQ_SET(_var, _val) \ |
| 1075 | do { \ |
| 1076 | HTT_CHECK_SET_VAL(HTT_TX_DESC_CHAN_FREQ, _val); \ |
| 1077 | ((_var) |= ((_val) << HTT_TX_DESC_CHAN_FREQ_S)); \ |
| 1078 | } while (0) |
| 1079 | |
| 1080 | |
| 1081 | /* enums used in the HTT tx MSDU extension descriptor */ |
| 1082 | enum { |
| 1083 | htt_tx_guard_interval_regular = 0, |
| 1084 | htt_tx_guard_interval_short = 1, |
| 1085 | }; |
| 1086 | |
| 1087 | enum { |
| 1088 | htt_tx_preamble_type_ofdm = 0, |
| 1089 | htt_tx_preamble_type_cck = 1, |
| 1090 | htt_tx_preamble_type_ht = 2, |
| 1091 | htt_tx_preamble_type_vht = 3, |
| 1092 | }; |
| 1093 | |
| 1094 | enum { |
| 1095 | htt_tx_bandwidth_5MHz = 0, |
| 1096 | htt_tx_bandwidth_10MHz = 1, |
| 1097 | htt_tx_bandwidth_20MHz = 2, |
| 1098 | htt_tx_bandwidth_40MHz = 3, |
| 1099 | htt_tx_bandwidth_80MHz = 4, |
| 1100 | htt_tx_bandwidth_160MHz = 5, /* includes 80+80 */ |
| 1101 | }; |
| 1102 | |
| 1103 | /** |
| 1104 | * @brief HTT tx MSDU extension descriptor |
| 1105 | * @details |
| 1106 | * If the target supports HTT tx MSDU extension descriptors, the host has |
| 1107 | * the option of appending the following struct following the regular |
| 1108 | * HTT tx MSDU descriptor (and setting the "extension" flag in the regular |
| 1109 | * HTT tx MSDU descriptor, to show that the extension descriptor is present). |
| 1110 | * The HTT tx MSDU extension descriptors allows the host to provide detailed |
| 1111 | * tx specs for each frame. |
| 1112 | */ |
| 1113 | PREPACK struct htt_tx_msdu_desc_ext_t { |
| 1114 | /* DWORD 0: flags */ |
| 1115 | A_UINT32 valid_pwr:1,/* bit 0:if set, tx pwr spec is valid */ |
| 1116 | valid_mcs_mask:1,/* bit 1:if set, tx MCS mask spec is valid */ |
| 1117 | valid_nss_mask:1,/* bit 2:if set, tx Nss mask spec is valid */ |
| 1118 | valid_guard_interval:1,/* bit 3:if set, tx guard intv spec is valid */ |
| 1119 | valid_preamble_type_mask:1,/* 4:if set, tx preamble mask is valid */ |
| 1120 | valid_chainmask:1,/* bit 5:if set, tx chainmask spec is valid */ |
| 1121 | valid_retries:1,/* bit 6:if set, tx retries spec is valid */ |
| 1122 | valid_bandwidth:1,/* bit 7:if set, tx bandwidth spec is valid */ |
| 1123 | valid_expire_tsf:1,/* bit 8:if set, tx expire TSF spec is valid */ |
| 1124 | is_dsrc:1, /* bit 9:if set, MSDU is a DSRC frame */ |
| 1125 | reserved0_31_7:22; /* bits 31:10 - unused, set to 0x0 */ |
| 1126 | |
| 1127 | /* DWORD 1:tx power, tx rate, tx BW */ |
| 1128 | A_UINT32 |
| 1129 | /* pwr - |
| 1130 | * Specify what power the tx frame needs to be transmitted at. |
| 1131 | * The power a signed (two's complement) value is in units of 0.5 dBm. |
| 1132 | * The value needs to be appropriately sign-extended when extracting |
| 1133 | * the value from the message and storing it in a variable that is |
| 1134 | * larger than A_INT8. (The HTT_TX_MSDU_EXT_DESC_FLAG_PWR_GET macro |
| 1135 | * automatically handles this sign-extension.) |
| 1136 | * If the transmission uses multiple tx chains, this power spec is |
| 1137 | * the total transmit power, assuming incoherent combination of |
| 1138 | * per-chain power to produce the total power. |
| 1139 | */ |
| 1140 | pwr:8, |
| 1141 | /* mcs_mask - |
| 1142 | * Specify the allowable values for MCS index (modulation and coding) |
| 1143 | * to use for transmitting the frame. |
| 1144 | * |
| 1145 | * For HT / VHT preamble types, this mask directly corresponds to |
| 1146 | * the HT or VHT MCS indices that are allowed. For each bit N set |
| 1147 | * within the mask, MCS index N is allowed for transmitting the frame. |
| 1148 | * For legacy CCK and OFDM rates, separate bits are provided for CCK |
| 1149 | * rates versus OFDM rates, so the host has the option of specifying |
| 1150 | * that the target must transmit the frame with CCK or OFDM rates |
| 1151 | * (not HT or VHT), but leaving the decision to the target whether |
| 1152 | * to use CCK or OFDM. |
| 1153 | * |
| 1154 | * For CCK and OFDM, the bits within this mask are interpreted as |
| 1155 | * follows: |
| 1156 | * bit 0 -> CCK 1 Mbps rate is allowed |
| 1157 | * bit 1 -> CCK 2 Mbps rate is allowed |
| 1158 | * bit 2 -> CCK 5.5 Mbps rate is allowed |
| 1159 | * bit 3 -> CCK 11 Mbps rate is allowed |
| 1160 | * bit 4 -> OFDM BPSK modulation, 1/2 coding rate is allowed |
| 1161 | * bit 5 -> OFDM BPSK modulation, 3/4 coding rate is allowed |
| 1162 | * bit 6 -> OFDM QPSK modulation, 1/2 coding rate is allowed |
| 1163 | * bit 7 -> OFDM QPSK modulation, 3/4 coding rate is allowed |
| 1164 | * bit 8 -> OFDM 16-QAM modulation, 1/2 coding rate is allowed |
| 1165 | * bit 9 -> OFDM 16-QAM modulation, 3/4 coding rate is allowed |
| 1166 | * bit 10 -> OFDM 64-QAM modulation, 2/3 coding rate is allowed |
| 1167 | * bit 11 -> OFDM 64-QAM modulation, 3/4 coding rate is allowed |
| 1168 | * |
| 1169 | * The MCS index specification needs to be compatible with the |
| 1170 | * bandwidth mask specification. For example, a MCS index == 9 |
| 1171 | * specification is inconsistent with a preamble type == VHT, |
| 1172 | * Nss == 1, and channel bandwidth == 20 MHz. |
| 1173 | * |
| 1174 | * Furthermore, the host has only a limited ability to specify to |
| 1175 | * the target to select from HT + legacy rates, or VHT + legacy rates, |
| 1176 | * since this mcs_mask can specify either HT/VHT rates or legacy rates. |
| 1177 | */ |
| 1178 | mcs_mask:12, |
| 1179 | /* nss_mask - |
| 1180 | * Specify which numbers of spatial streams (MIMO factor) are permitted. |
| 1181 | * Each bit in this mask corresponds to a Nss value: |
| 1182 | * bit 0: if set, Nss = 1 (non-MIMO) is permitted |
| 1183 | * bit 1: if set, Nss = 2 (2x2 MIMO) is permitted |
| 1184 | * bit 2: if set, Nss = 3 (3x3 MIMO) is permitted |
| 1185 | * bit 3: if set, Nss = 4 (4x4 MIMO) is permitted |
| 1186 | * The values in the Nss mask must be suitable for the recipient, e.g. |
| 1187 | * a value of 0x4 (Nss = 3) cannot be specified for a tx frame to a |
| 1188 | * recipient which only supports 2x2 MIMO. |
| 1189 | */ |
| 1190 | nss_mask:4, |
| 1191 | /* guard_interval - |
| 1192 | * Specify a htt_tx_guard_interval enum value to indicate whether |
| 1193 | * the transmission should use a regular guard interval or a |
| 1194 | * short guard interval. |
| 1195 | */ |
| 1196 | guard_interval:1, |
| 1197 | /* preamble_type_mask - |
| 1198 | * Specify which preamble types (CCK, OFDM, HT, VHT) the target |
| 1199 | * may choose from for transmitting this frame. |
| 1200 | * The bits in this mask correspond to the values in the |
| 1201 | * htt_tx_preamble_type enum. For example, to allow the target |
| 1202 | * to transmit the frame as either CCK or OFDM, this field would |
| 1203 | * be set to |
| 1204 | * (1 << htt_tx_preamble_type_ofdm) | |
| 1205 | * (1 << htt_tx_preamble_type_cck) |
| 1206 | */ |
| 1207 | preamble_type_mask:4, |
| 1208 | |
| 1209 | reserved1_31_29:3; /* unused, set to 0x0 */ |
| 1210 | |
| 1211 | /* DWORD 2: tx chain mask, tx retries */ |
| 1212 | A_UINT32 |
| 1213 | /* chain_mask - specify which chains to transmit from */ |
| 1214 | chain_mask:4, |
| 1215 | /* retry_limit - |
| 1216 | * Specify the maximum number of transmissions, including the |
| 1217 | * initial transmission, to attempt before giving up if no ack |
| 1218 | * is received. |
| 1219 | * If the tx rate is specified, then all retries shall use the |
| 1220 | * same rate as the initial transmission. |
| 1221 | * If no tx rate is specified, the target can choose whether to |
| 1222 | * retain the original rate during the retransmissions, or to |
| 1223 | * fall back to a more robust rate. |
| 1224 | */ |
| 1225 | retry_limit:4, |
| 1226 | /* bandwidth_mask - |
| 1227 | * Specify what channel widths may be used for the transmission. |
| 1228 | * A value of zero indicates "don't care" - the target may choose |
| 1229 | * the transmission bandwidth. |
| 1230 | * The bits within this mask correspond to the htt_tx_bandwidth |
| 1231 | * enum values - bit 0 is for 5 MHz, bit 1 is for 10 MHz, etc. |
| 1232 | * The bandwidth_mask must be consistent with the |
| 1233 | * preamble_type_mask * and mcs_mask specs, if they are |
| 1234 | * provided. For example, |
| 1235 | * 80 MHz and 160 MHz can only be enabled in the mask |
| 1236 | * if preamble_type == VHT. |
| 1237 | */ |
| 1238 | bandwidth_mask:6, |
| 1239 | |
| 1240 | reserved2_31_14:18; /* unused, set to 0x0 */ |
| 1241 | |
| 1242 | /* DWORD 3: tx expiry time (TSF) LSBs */ |
| 1243 | A_UINT32 expire_tsf_lo; |
| 1244 | |
| 1245 | /* DWORD 4: tx expiry time (TSF) MSBs */ |
| 1246 | A_UINT32 expire_tsf_hi; |
| 1247 | |
| 1248 | A_UINT32 reserved_for_future_expansion_set_to_zero[3]; |
| 1249 | } POSTPACK; |
| 1250 | |
| 1251 | /* DWORD 0 */ |
| 1252 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M 0x00000001 |
| 1253 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S 0 |
| 1254 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M 0x00000002 |
| 1255 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S 1 |
| 1256 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_M 0x00000004 |
| 1257 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_NSS_MASK_S 2 |
| 1258 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M 0x00000008 |
| 1259 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S 3 |
| 1260 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M 0x00000010 |
| 1261 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S 4 |
| 1262 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M 0x00000020 |
| 1263 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S 5 |
| 1264 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M 0x00000040 |
| 1265 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S 6 |
| 1266 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M 0x00000080 |
| 1267 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S 7 |
| 1268 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M 0x00000100 |
| 1269 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S 8 |
| 1270 | #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M 0x00000200 |
| 1271 | #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S 9 |
| 1272 | |
| 1273 | /* DWORD 1 */ |
| 1274 | #define HTT_TX_MSDU_EXT_DESC_PWR_M 0x000000ff |
| 1275 | #define HTT_TX_MSDU_EXT_DESC_PWR_S 0 |
| 1276 | #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_M 0x000fff00 |
| 1277 | #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_S 8 |
| 1278 | #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_M 0x00f00000 |
| 1279 | #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_S 20 |
| 1280 | #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M 0x01000000 |
| 1281 | #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S 24 |
| 1282 | #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M 0x1c000000 |
| 1283 | #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S 25 |
| 1284 | |
| 1285 | /* DWORD 2 */ |
| 1286 | #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M 0x0000000f |
| 1287 | #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S 0 |
| 1288 | #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M 0x000000f0 |
| 1289 | #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S 4 |
| 1290 | #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M 0x00003f00 |
| 1291 | #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S 8 |
| 1292 | |
| 1293 | |
| 1294 | /* DWORD 0 */ |
| 1295 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_GET(_var) \ |
| 1296 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_M) >> \ |
| 1297 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S) |
| 1298 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_SET(_var, _val) \ |
| 1299 | do { \ |
| 1300 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR, _val); \ |
| 1301 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PWR_S)); \ |
| 1302 | } while (0) |
| 1303 | |
| 1304 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_GET(_var) \ |
| 1305 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_M) >> \ |
| 1306 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S) |
| 1307 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_SET(_var, _val) \ |
| 1308 | do { \ |
| 1309 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK, _val); \ |
| 1310 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_MCS_MASK_S)); \ |
| 1311 | } while (0) |
| 1312 | |
| 1313 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_GET(_var) \ |
| 1314 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_M) >> \ |
| 1315 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S) |
| 1316 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_SET(_var, _val) \ |
| 1317 | do { \ |
| 1318 | HTT_CHECK_SET_VAL( \ |
| 1319 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL, _val); \ |
| 1320 | ((_var) |= ((_val) \ |
| 1321 | << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_GUARD_INTERVAL_S)); \ |
| 1322 | } while (0) |
| 1323 | |
| 1324 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_GET(_var) \ |
| 1325 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_M) >>\ |
| 1326 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S) |
| 1327 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_SET(_var, _val) \ |
| 1328 | do { \ |
| 1329 | HTT_CHECK_SET_VAL( \ |
| 1330 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK, _val); \ |
| 1331 | ((_var) |= ((_val) \ |
| 1332 | << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_PREAMBLE_TYPE_MASK_S)); \ |
| 1333 | } while (0) |
| 1334 | |
| 1335 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_GET(_var) \ |
| 1336 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_M) >> \ |
| 1337 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S) |
| 1338 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_SET(_var, _val) \ |
| 1339 | do { \ |
| 1340 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK, _val); \ |
| 1341 | ((_var) |= ((_val) << \ |
| 1342 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_CHAIN_MASK_S)); \ |
| 1343 | } while (0) |
| 1344 | |
| 1345 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_GET(_var) \ |
| 1346 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_M) >> \ |
| 1347 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S) |
| 1348 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_SET(_var, _val) \ |
| 1349 | do { \ |
| 1350 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES, _val); \ |
| 1351 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_RETRIES_S)); \ |
| 1352 | } while (0) |
| 1353 | |
| 1354 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_GET(_var) \ |
| 1355 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_M) >> \ |
| 1356 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S) |
| 1357 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_SET(_var, _val) \ |
| 1358 | do { \ |
| 1359 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH, _val); \ |
| 1360 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_BANDWIDTH_S)); \ |
| 1361 | } while (0) |
| 1362 | |
| 1363 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_GET(_var) \ |
| 1364 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_M) >> \ |
| 1365 | HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S) |
| 1366 | #define HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_SET(_var, _val) \ |
| 1367 | do { \ |
| 1368 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME, _val); \ |
| 1369 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_VALID_EXPIRE_TIME_S));\ |
| 1370 | } while (0) |
| 1371 | |
| 1372 | #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_GET(_var) \ |
| 1373 | (((_var) & HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_M) >> \ |
| 1374 | HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S) |
| 1375 | #define HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_SET(_var, _val) \ |
| 1376 | do { \ |
| 1377 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC, _val); \ |
| 1378 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_FLAG_IS_DSRC_S)); \ |
| 1379 | } while (0) |
| 1380 | |
| 1381 | |
| 1382 | /* DWORD 1 */ |
| 1383 | #define HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) \ |
| 1384 | (((_var) & HTT_TX_MSDU_EXT_DESC_PWR_M) >> \ |
| 1385 | HTT_TX_MSDU_EXT_DESC_PWR_S) |
| 1386 | #define HTT_TX_MSDU_EXT_DESC_PWR_GET(_var) \ |
| 1387 | (HTT_TX_MSDU_EXT_DESC_PWR_GET_BASE(_var) | \ |
| 1388 | HTT_SIGN_BIT_EXTENSION_MASK(_var, HTT_TX_MSDU_EXT_DESC_PWR)) |
| 1389 | #define HTT_TX_MSDU_EXT_DESC_PWR_SET(_var, _val) \ |
| 1390 | ((_var) |= (((_val) << HTT_TX_MSDU_EXT_DESC_PWR_S)) & \ |
| 1391 | HTT_TX_MSDU_EXT_DESC_PWR_M) |
| 1392 | |
| 1393 | #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_GET(_var) \ |
| 1394 | (((_var) & HTT_TX_MSDU_EXT_DESC_MCS_MASK_M) >> \ |
| 1395 | HTT_TX_MSDU_EXT_DESC_MCS_MASK_S) |
| 1396 | #define HTT_TX_MSDU_EXT_DESC_MCS_MASK_SET(_var, _val) \ |
| 1397 | do { \ |
| 1398 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_MCS_MASK, _val); \ |
| 1399 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_MCS_MASK_S)); \ |
| 1400 | } while (0) |
| 1401 | |
| 1402 | #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_GET(_var) \ |
| 1403 | (((_var) & HTT_TX_MSDU_EXT_DESC_NSS_MASK_M) >> \ |
| 1404 | HTT_TX_MSDU_EXT_DESC_NSS_MASK_S) |
| 1405 | #define HTT_TX_MSDU_EXT_DESC_NSS_MASK_SET(_var, _val) \ |
| 1406 | do { \ |
| 1407 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_NSS_MASK, _val); \ |
| 1408 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_NSS_MASK_S)); \ |
| 1409 | } while (0) |
| 1410 | |
| 1411 | #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_GET(_var) \ |
| 1412 | (((_var) & HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_M) >> \ |
| 1413 | HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S) |
| 1414 | #define HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_SET(_var, _val) \ |
| 1415 | do { \ |
| 1416 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL, _val); \ |
| 1417 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_GUARD_INTERVAL_S)); \ |
| 1418 | } while (0) |
| 1419 | |
| 1420 | #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_GET(_var) \ |
| 1421 | (((_var) & HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_M) >> \ |
| 1422 | HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S) |
| 1423 | #define HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_SET(_var, _val) \ |
| 1424 | do { \ |
| 1425 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK,\ |
| 1426 | _val); \ |
| 1427 | ((_var) |= ((_val) << \ |
| 1428 | HTT_TX_MSDU_EXT_DESC_PREAMBLE_TYPE_MASK_S)); \ |
| 1429 | } while (0) |
| 1430 | |
| 1431 | |
| 1432 | /* DWORD 2 */ |
| 1433 | #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_GET(_var) \ |
| 1434 | (((_var) & HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_M) >> \ |
| 1435 | HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S) |
| 1436 | #define HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_SET(_var, _val) \ |
| 1437 | do { \ |
| 1438 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_CHAIN_MASK, _val); \ |
| 1439 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_CHAIN_MASK_S)); \ |
| 1440 | } while (0) |
| 1441 | |
| 1442 | #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_GET(_var) \ |
| 1443 | (((_var) & HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_M) >> \ |
| 1444 | HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S) |
| 1445 | #define HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_SET(_var, _val) \ |
| 1446 | do { \ |
| 1447 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT, _val); \ |
| 1448 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_RETRY_LIMIT_S)); \ |
| 1449 | } while (0) |
| 1450 | |
| 1451 | #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_GET(_var) \ |
| 1452 | (((_var) & HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_M) >> \ |
| 1453 | HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S) |
| 1454 | #define HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_SET(_var, _val) \ |
| 1455 | do { \ |
| 1456 | HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK, _val); \ |
| 1457 | ((_var) |= ((_val) << HTT_TX_MSDU_EXT_DESC_BANDWIDTH_MASK_S)); \ |
| 1458 | } while (0) |
| 1459 | |
| 1460 | |
| 1461 | /** |
| 1462 | * @brief MAC DMA rx ring setup specification |
| 1463 | * @details |
| 1464 | * To allow for dynamic rx ring reconfiguration and to avoid race |
| 1465 | * conditions, the host SW never directly programs the MAC DMA rx ring(s) |
| 1466 | * it uses. Instead, it sends this message to the target, indicating how |
| 1467 | * the rx ring used by the host should be set up and maintained. |
| 1468 | * The message consists of a 4-octet header followed by 1 or 2 rx ring setup |
| 1469 | * specifications. |
| 1470 | * |
| 1471 | * |31 16|15 8|7 0| |
| 1472 | * |---------------------------------------------------------------| |
| 1473 | * header: | reserved | num rings | msg type | |
| 1474 | * |---------------------------------------------------------------| |
| 1475 | * payload 1: | FW_IDX shadow register physical address (bits 31:0) | |
| 1476 | #if HTT_PADDR64 |
| 1477 | * | FW_IDX shadow register physical address (bits 63:32) | |
| 1478 | #endif |
| 1479 | * |---------------------------------------------------------------| |
| 1480 | * | rx ring base physical address (bits 31:0) | |
| 1481 | #if HTT_PADDR64 |
| 1482 | * | rx ring base physical address (bits 63:32) | |
| 1483 | #endif |
| 1484 | * |---------------------------------------------------------------| |
| 1485 | * | rx ring buffer size | rx ring length | |
| 1486 | * |---------------------------------------------------------------| |
| 1487 | * | FW_IDX initial value | enabled flags | |
| 1488 | * |---------------------------------------------------------------| |
| 1489 | * | MSDU payload offset | 802.11 header offset | |
| 1490 | * |---------------------------------------------------------------| |
| 1491 | * | PPDU end offset | PPDU start offset | |
| 1492 | * |---------------------------------------------------------------| |
| 1493 | * | MPDU end offset | MPDU start offset | |
| 1494 | * |---------------------------------------------------------------| |
| 1495 | * | MSDU end offset | MSDU start offset | |
| 1496 | * |---------------------------------------------------------------| |
| 1497 | * | frag info offset | rx attention offset | |
| 1498 | * |---------------------------------------------------------------| |
| 1499 | * payload 2, if present, has the same format as payload 1 |
| 1500 | * Header fields: |
| 1501 | * - MSG_TYPE |
| 1502 | * Bits 7:0 |
| 1503 | * Purpose: identifies this as an rx ring configuration message |
| 1504 | * Value: 0x2 |
| 1505 | * - NUM_RINGS |
| 1506 | * Bits 15:8 |
| 1507 | * Purpose: indicates whether the host is setting up one rx ring or two |
| 1508 | * Value: 1 or 2 |
| 1509 | * Payload: |
| 1510 | * for systems using 64-bit format for bus addresses: |
| 1511 | * - IDX_SHADOW_REG_PADDR_LO |
| 1512 | * Bits 31:0 |
| 1513 | * Value: lower 4 bytes of physical address of the host's |
| 1514 | * FW_IDX shadow register |
| 1515 | * - IDX_SHADOW_REG_PADDR_HI |
| 1516 | * Bits 31:0 |
| 1517 | * Value: upper 4 bytes of physical address of the host's |
| 1518 | * FW_IDX shadow register |
| 1519 | * - RING_BASE_PADDR_LO |
| 1520 | * Bits 31:0 |
| 1521 | * Value: lower 4 bytes of physical address of the host's rx ring |
| 1522 | * - RING_BASE_PADDR_HI |
| 1523 | * Bits 31:0 |
| 1524 | * Value: uppper 4 bytes of physical address of the host's rx ring |
| 1525 | * for systems using 32-bit format for bus addresses: |
| 1526 | * - IDX_SHADOW_REG_PADDR |
| 1527 | * Bits 31:0 |
| 1528 | * Value: physical address of the host's FW_IDX shadow register |
| 1529 | * - RING_BASE_PADDR |
| 1530 | * Bits 31:0 |
| 1531 | * Value: physical address of the host's rx ring |
| 1532 | * - RING_LEN |
| 1533 | * Bits 15:0 |
| 1534 | * Value: number of elements in the rx ring |
| 1535 | * - RING_BUF_SZ |
| 1536 | * Bits 31:16 |
| 1537 | * Value: size of the buffers referenced by the rx ring, in byte units |
| 1538 | * - ENABLED_FLAGS |
| 1539 | * Bits 15:0 |
| 1540 | * Value: 1-bit flags to show whether different rx fields are enabled |
| 1541 | * bit 0: 802.11 header enabled (1) or disabled (0) |
| 1542 | * bit 1: MSDU payload enabled (1) or disabled (0) |
| 1543 | * bit 2: PPDU start enabled (1) or disabled (0) |
| 1544 | * bit 3: PPDU end enabled (1) or disabled (0) |
| 1545 | * bit 4: MPDU start enabled (1) or disabled (0) |
| 1546 | * bit 5: MPDU end enabled (1) or disabled (0) |
| 1547 | * bit 6: MSDU start enabled (1) or disabled (0) |
| 1548 | * bit 7: MSDU end enabled (1) or disabled (0) |
| 1549 | * bit 8: rx attention enabled (1) or disabled (0) |
| 1550 | * bit 9: frag info enabled (1) or disabled (0) |
| 1551 | * bit 10: unicast rx enabled (1) or disabled (0) |
| 1552 | * bit 11: multicast rx enabled (1) or disabled (0) |
| 1553 | * bit 12: ctrl rx enabled (1) or disabled (0) |
| 1554 | * bit 13: mgmt rx enabled (1) or disabled (0) |
| 1555 | * bit 14: null rx enabled (1) or disabled (0) |
| 1556 | * bit 15: phy data rx enabled (1) or disabled (0) |
| 1557 | * - IDX_INIT_VAL |
| 1558 | * Bits 31:16 |
| 1559 | * Purpose: Specify the initial value for the FW_IDX. |
| 1560 | * Value: the number of buffers initially present in the host's rx ring |
| 1561 | * - OFFSET_802_11_HDR |
| 1562 | * Bits 15:0 |
| 1563 | * Value: offset in QUAD-bytes of 802.11 header from the buffer start |
| 1564 | * - OFFSET_MSDU_PAYLOAD |
| 1565 | * Bits 31:16 |
| 1566 | * Value: offset in QUAD-bytes of MSDU payload from the buffer start |
| 1567 | * - OFFSET_PPDU_START |
| 1568 | * Bits 15:0 |
| 1569 | * Value: offset in QUAD-bytes of PPDU start rx desc from the buffer start |
| 1570 | * - OFFSET_PPDU_END |
| 1571 | * Bits 31:16 |
| 1572 | * Value: offset in QUAD-bytes of PPDU end rx desc from the buffer start |
| 1573 | * - OFFSET_MPDU_START |
| 1574 | * Bits 15:0 |
| 1575 | * Value: offset in QUAD-bytes of MPDU start rx desc from the buffer start |
| 1576 | * - OFFSET_MPDU_END |
| 1577 | * Bits 31:16 |
| 1578 | * Value: offset in QUAD-bytes of MPDU end rx desc from the buffer start |
| 1579 | * - OFFSET_MSDU_START |
| 1580 | * Bits 15:0 |
| 1581 | * Value: offset in QUAD-bytes of MSDU start rx desc from the buffer start |
| 1582 | * - OFFSET_MSDU_END |
| 1583 | * Bits 31:16 |
| 1584 | * Value: offset in QUAD-bytes of MSDU end rx desc from the buffer start |
| 1585 | * - OFFSET_RX_ATTN |
| 1586 | * Bits 15:0 |
| 1587 | * Value: offset in QUAD-bytes of rx attention word from the buffer start |
| 1588 | * - OFFSET_FRAG_INFO |
| 1589 | * Bits 31:16 |
| 1590 | * Value: offset in QUAD-bytes of frag info table |
| 1591 | */ |
| 1592 | /* header fields */ |
| 1593 | #define HTT_RX_RING_CFG_NUM_RINGS_M 0xff00 |
| 1594 | #define HTT_RX_RING_CFG_NUM_RINGS_S 8 |
| 1595 | |
| 1596 | /* payload fields */ |
| 1597 | /* for systems using a 64-bit format for bus addresses */ |
| 1598 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_M 0xffffffff |
| 1599 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_S 0 |
| 1600 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_M 0xffffffff |
| 1601 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_S 0 |
| 1602 | #define HTT_RX_RING_CFG_BASE_PADDR_HI_M 0xffffffff |
| 1603 | #define HTT_RX_RING_CFG_BASE_PADDR_HI_S 0 |
| 1604 | #define HTT_RX_RING_CFG_BASE_PADDR_LO_M 0xffffffff |
| 1605 | #define HTT_RX_RING_CFG_BASE_PADDR_LO_S 0 |
| 1606 | |
| 1607 | /* for systems using a 32-bit format for bus addresses */ |
| 1608 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_M 0xffffffff |
| 1609 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_S 0 |
| 1610 | #define HTT_RX_RING_CFG_BASE_PADDR_M 0xffffffff |
| 1611 | #define HTT_RX_RING_CFG_BASE_PADDR_S 0 |
| 1612 | |
| 1613 | #define HTT_RX_RING_CFG_LEN_M 0xffff |
| 1614 | #define HTT_RX_RING_CFG_LEN_S 0 |
| 1615 | #define HTT_RX_RING_CFG_BUF_SZ_M 0xffff0000 |
| 1616 | #define HTT_RX_RING_CFG_BUF_SZ_S 16 |
| 1617 | #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_M 0x1 |
| 1618 | #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_S 0 |
| 1619 | #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M 0x2 |
| 1620 | #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S 1 |
| 1621 | #define HTT_RX_RING_CFG_ENABLED_PPDU_START_M 0x4 |
| 1622 | #define HTT_RX_RING_CFG_ENABLED_PPDU_START_S 2 |
| 1623 | #define HTT_RX_RING_CFG_ENABLED_PPDU_END_M 0x8 |
| 1624 | #define HTT_RX_RING_CFG_ENABLED_PPDU_END_S 3 |
| 1625 | #define HTT_RX_RING_CFG_ENABLED_MPDU_START_M 0x10 |
| 1626 | #define HTT_RX_RING_CFG_ENABLED_MPDU_START_S 4 |
| 1627 | #define HTT_RX_RING_CFG_ENABLED_MPDU_END_M 0x20 |
| 1628 | #define HTT_RX_RING_CFG_ENABLED_MPDU_END_S 5 |
| 1629 | #define HTT_RX_RING_CFG_ENABLED_MSDU_START_M 0x40 |
| 1630 | #define HTT_RX_RING_CFG_ENABLED_MSDU_START_S 6 |
| 1631 | #define HTT_RX_RING_CFG_ENABLED_MSDU_END_M 0x80 |
| 1632 | #define HTT_RX_RING_CFG_ENABLED_MSDU_END_S 7 |
| 1633 | #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_M 0x100 |
| 1634 | #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_S 8 |
| 1635 | #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M 0x200 |
| 1636 | #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S 9 |
| 1637 | #define HTT_RX_RING_CFG_ENABLED_UCAST_M 0x400 |
| 1638 | #define HTT_RX_RING_CFG_ENABLED_UCAST_S 10 |
| 1639 | #define HTT_RX_RING_CFG_ENABLED_MCAST_M 0x800 |
| 1640 | #define HTT_RX_RING_CFG_ENABLED_MCAST_S 11 |
| 1641 | #define HTT_RX_RING_CFG_ENABLED_CTRL_M 0x1000 |
| 1642 | #define HTT_RX_RING_CFG_ENABLED_CTRL_S 12 |
| 1643 | #define HTT_RX_RING_CFG_ENABLED_MGMT_M 0x2000 |
| 1644 | #define HTT_RX_RING_CFG_ENABLED_MGMT_S 13 |
| 1645 | #define HTT_RX_RING_CFG_ENABLED_NULL_M 0x4000 |
| 1646 | #define HTT_RX_RING_CFG_ENABLED_NULL_S 14 |
| 1647 | #define HTT_RX_RING_CFG_ENABLED_PHY_M 0x8000 |
| 1648 | #define HTT_RX_RING_CFG_ENABLED_PHY_S 15 |
| 1649 | #define HTT_RX_RING_CFG_IDX_INIT_VAL_M 0xffff0000 |
| 1650 | #define HTT_RX_RING_CFG_IDX_INIT_VAL_S 16 |
| 1651 | #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_M 0xffff |
| 1652 | #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_S 0 |
| 1653 | #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M 0xffff0000 |
| 1654 | #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S 16 |
| 1655 | #define HTT_RX_RING_CFG_OFFSET_PPDU_START_M 0xffff |
| 1656 | #define HTT_RX_RING_CFG_OFFSET_PPDU_START_S 0 |
| 1657 | #define HTT_RX_RING_CFG_OFFSET_PPDU_END_M 0xffff0000 |
| 1658 | #define HTT_RX_RING_CFG_OFFSET_PPDU_END_S 16 |
| 1659 | #define HTT_RX_RING_CFG_OFFSET_MPDU_START_M 0xffff |
| 1660 | #define HTT_RX_RING_CFG_OFFSET_MPDU_START_S 0 |
| 1661 | #define HTT_RX_RING_CFG_OFFSET_MPDU_END_M 0xffff0000 |
| 1662 | #define HTT_RX_RING_CFG_OFFSET_MPDU_END_S 16 |
| 1663 | #define HTT_RX_RING_CFG_OFFSET_MSDU_START_M 0xffff |
| 1664 | #define HTT_RX_RING_CFG_OFFSET_MSDU_START_S 0 |
| 1665 | #define HTT_RX_RING_CFG_OFFSET_MSDU_END_M 0xffff0000 |
| 1666 | #define HTT_RX_RING_CFG_OFFSET_MSDU_END_S 16 |
| 1667 | #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_M 0xffff |
| 1668 | #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_S 0 |
| 1669 | #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M 0xffff0000 |
| 1670 | #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S 16 |
| 1671 | |
| 1672 | #define HTT_RX_RING_CFG_HDR_BYTES 4 |
| 1673 | #define HTT_RX_RING_CFG_PAYLD_BYTES_64 44 |
| 1674 | #define HTT_RX_RING_CFG_PAYLD_BYTES_32 36 |
| 1675 | #if HTT_PADDR64 |
| 1676 | #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_64 |
| 1677 | #else |
| 1678 | #define HTT_RX_RING_CFG_PAYLD_BYTES HTT_RX_RING_CFG_PAYLD_BYTES_32 |
| 1679 | #endif |
| 1680 | #define HTT_RX_RING_CFG_BYTES(num_rings) \ |
| 1681 | (HTT_RX_RING_CFG_HDR_BYTES + (num_rings) * HTT_RX_RING_CFG_PAYLD_BYTES) |
| 1682 | |
| 1683 | |
| 1684 | #define HTT_RX_RING_CFG_NUM_RINGS_GET(_var) \ |
| 1685 | (((_var) & HTT_RX_RING_CFG_NUM_RINGS_M) >> HTT_RX_RING_CFG_NUM_RINGS_S) |
| 1686 | #define HTT_RX_RING_CFG_NUM_RINGS_SET(_var, _val) \ |
| 1687 | do { \ |
| 1688 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_NUM_RINGS, _val); \ |
| 1689 | ((_var) |= ((_val) << HTT_RX_RING_CFG_NUM_RINGS_S)); \ |
| 1690 | } while (0) |
| 1691 | |
| 1692 | /* degenerate case for 32-bit fields */ |
| 1693 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_GET(_var) (_var) |
| 1694 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_HI_SET(_var, _val) \ |
| 1695 | ((_var) = (_val)) |
| 1696 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_GET(_var) (_var) |
| 1697 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_LO_SET(_var, _val) \ |
| 1698 | ((_var) = (_val)) |
| 1699 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_GET(_var) (_var) |
| 1700 | #define HTT_RX_RING_CFG_IDX_SHADOW_REG_PADDR_SET(_var, _val) \ |
| 1701 | ((_var) = (_val)) |
| 1702 | |
| 1703 | /* degenerate case for 32-bit fields */ |
| 1704 | #define HTT_RX_RING_CFG_BASE_PADDR_HI_GET(_var) (_var) |
| 1705 | #define HTT_RX_RING_CFG_BASE_PADDR_HI_SET(_var, _val) ((_var) = (_val)) |
| 1706 | #define HTT_RX_RING_CFG_BASE_PADDR_LO_GET(_var) (_var) |
| 1707 | #define HTT_RX_RING_CFG_BASE_PADDR_LO_SET(_var, _val) ((_var) = (_val)) |
| 1708 | #define HTT_RX_RING_CFG_BASE_PADDR_GET(_var) (_var) |
| 1709 | #define HTT_RX_RING_CFG_BASE_PADDR_SET(_var, _val) ((_var) = (_val)) |
| 1710 | |
| 1711 | #define HTT_RX_RING_CFG_LEN_GET(_var) \ |
| 1712 | (((_var) & HTT_RX_RING_CFG_LEN_M) >> HTT_RX_RING_CFG_LEN_S) |
| 1713 | #define HTT_RX_RING_CFG_LEN_SET(_var, _val) \ |
| 1714 | do { \ |
| 1715 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_LEN, _val); \ |
| 1716 | ((_var) |= ((_val) << HTT_RX_RING_CFG_LEN_S)); \ |
| 1717 | } while (0) |
| 1718 | |
| 1719 | #define HTT_RX_RING_CFG_BUF_SZ_GET(_var) \ |
| 1720 | (((_var) & HTT_RX_RING_CFG_BUF_SZ_M) >> HTT_RX_RING_CFG_BUF_SZ_S) |
| 1721 | #define HTT_RX_RING_CFG_BUF_SZ_SET(_var, _val) \ |
| 1722 | do { \ |
| 1723 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_BUF_SZ, _val); \ |
| 1724 | ((_var) |= ((_val) << HTT_RX_RING_CFG_BUF_SZ_S)); \ |
| 1725 | } while (0) |
| 1726 | |
| 1727 | #define HTT_RX_RING_CFG_IDX_INIT_VAL_GET(_var) \ |
| 1728 | (((_var) & HTT_RX_RING_CFG_IDX_INIT_VAL_M) >> \ |
| 1729 | HTT_RX_RING_CFG_IDX_INIT_VAL_S) |
| 1730 | #define HTT_RX_RING_CFG_IDX_INIT_VAL_SET(_var, _val) \ |
| 1731 | do { \ |
| 1732 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_IDX_INIT_VAL, _val); \ |
| 1733 | ((_var) |= ((_val) << HTT_RX_RING_CFG_IDX_INIT_VAL_S)); \ |
| 1734 | } while (0) |
| 1735 | |
| 1736 | #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_GET(_var) \ |
| 1737 | (((_var) & HTT_RX_RING_CFG_ENABLED_802_11_HDR_M) >> \ |
| 1738 | HTT_RX_RING_CFG_ENABLED_802_11_HDR_S) |
| 1739 | #define HTT_RX_RING_CFG_ENABLED_802_11_HDR_SET(_var, _val) \ |
| 1740 | do { \ |
| 1741 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_802_11_HDR, _val); \ |
| 1742 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_802_11_HDR_S)); \ |
| 1743 | } while (0) |
| 1744 | |
| 1745 | #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_GET(_var) \ |
| 1746 | (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_M) >> \ |
| 1747 | HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S) |
| 1748 | #define HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_SET(_var, _val) \ |
| 1749 | do { \ |
| 1750 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD, _val); \ |
| 1751 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_PAYLD_S)); \ |
| 1752 | } while (0) |
| 1753 | |
| 1754 | #define HTT_RX_RING_CFG_ENABLED_PPDU_START_GET(_var) \ |
| 1755 | (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_START_M) >> \ |
| 1756 | HTT_RX_RING_CFG_ENABLED_PPDU_START_S) |
| 1757 | #define HTT_RX_RING_CFG_ENABLED_PPDU_START_SET(_var, _val) \ |
| 1758 | do { \ |
| 1759 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_START, _val); \ |
| 1760 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_START_S)); \ |
| 1761 | } while (0) |
| 1762 | |
| 1763 | #define HTT_RX_RING_CFG_ENABLED_PPDU_END_GET(_var) \ |
| 1764 | (((_var) & HTT_RX_RING_CFG_ENABLED_PPDU_END_M) >> \ |
| 1765 | HTT_RX_RING_CFG_ENABLED_PPDU_END_S) |
| 1766 | #define HTT_RX_RING_CFG_ENABLED_PPDU_END_SET(_var, _val) \ |
| 1767 | do { \ |
| 1768 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PPDU_END, _val); \ |
| 1769 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PPDU_END_S)); \ |
| 1770 | } while (0) |
| 1771 | |
| 1772 | #define HTT_RX_RING_CFG_ENABLED_MPDU_START_GET(_var) \ |
| 1773 | (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_START_M) >> \ |
| 1774 | HTT_RX_RING_CFG_ENABLED_MPDU_START_S) |
| 1775 | #define HTT_RX_RING_CFG_ENABLED_MPDU_START_SET(_var, _val) \ |
| 1776 | do { \ |
| 1777 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_START, _val); \ |
| 1778 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_START_S)); \ |
| 1779 | } while (0) |
| 1780 | |
| 1781 | #define HTT_RX_RING_CFG_ENABLED_MPDU_END_GET(_var) \ |
| 1782 | (((_var) & HTT_RX_RING_CFG_ENABLED_MPDU_END_M) >> \ |
| 1783 | HTT_RX_RING_CFG_ENABLED_MPDU_END_S) |
| 1784 | #define HTT_RX_RING_CFG_ENABLED_MPDU_END_SET(_var, _val) \ |
| 1785 | do { \ |
| 1786 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MPDU_END, _val); \ |
| 1787 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MPDU_END_S)); \ |
| 1788 | } while (0) |
| 1789 | |
| 1790 | #define HTT_RX_RING_CFG_ENABLED_MSDU_START_GET(_var) \ |
| 1791 | (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_START_M) >> \ |
| 1792 | HTT_RX_RING_CFG_ENABLED_MSDU_START_S) |
| 1793 | #define HTT_RX_RING_CFG_ENABLED_MSDU_START_SET(_var, _val) \ |
| 1794 | do { \ |
| 1795 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_START, _val); \ |
| 1796 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_START_S)); \ |
| 1797 | } while (0) |
| 1798 | |
| 1799 | #define HTT_RX_RING_CFG_ENABLED_MSDU_END_GET(_var) \ |
| 1800 | (((_var) & HTT_RX_RING_CFG_ENABLED_MSDU_END_M) >> \ |
| 1801 | HTT_RX_RING_CFG_ENABLED_MSDU_END_S) |
| 1802 | #define HTT_RX_RING_CFG_ENABLED_MSDU_END_SET(_var, _val) \ |
| 1803 | do { \ |
| 1804 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MSDU_END, _val); \ |
| 1805 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MSDU_END_S)); \ |
| 1806 | } while (0) |
| 1807 | |
| 1808 | #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_GET(_var) \ |
| 1809 | (((_var) & HTT_RX_RING_CFG_ENABLED_RX_ATTN_M) >> \ |
| 1810 | HTT_RX_RING_CFG_ENABLED_RX_ATTN_S) |
| 1811 | #define HTT_RX_RING_CFG_ENABLED_RX_ATTN_SET(_var, _val) \ |
| 1812 | do { \ |
| 1813 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_RX_ATTN, _val); \ |
| 1814 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_RX_ATTN_S)); \ |
| 1815 | } while (0) |
| 1816 | |
| 1817 | #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_GET(_var) \ |
| 1818 | (((_var) & HTT_RX_RING_CFG_ENABLED_FRAG_INFO_M) >> \ |
| 1819 | HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S) |
| 1820 | #define HTT_RX_RING_CFG_ENABLED_FRAG_INFO_SET(_var, _val) \ |
| 1821 | do { \ |
| 1822 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_FRAG_INFO, _val); \ |
| 1823 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_FRAG_INFO_S)); \ |
| 1824 | } while (0) |
| 1825 | |
| 1826 | #define HTT_RX_RING_CFG_ENABLED_UCAST_GET(_var) \ |
| 1827 | (((_var) & HTT_RX_RING_CFG_ENABLED_UCAST_M) >> \ |
| 1828 | HTT_RX_RING_CFG_ENABLED_UCAST_S) |
| 1829 | #define HTT_RX_RING_CFG_ENABLED_UCAST_SET(_var, _val) \ |
| 1830 | do { \ |
| 1831 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_UCAST, _val); \ |
| 1832 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_UCAST_S)); \ |
| 1833 | } while (0) |
| 1834 | |
| 1835 | #define HTT_RX_RING_CFG_ENABLED_MCAST_GET(_var) \ |
| 1836 | (((_var) & HTT_RX_RING_CFG_ENABLED_MCAST_M) >> \ |
| 1837 | HTT_RX_RING_CFG_ENABLED_MCAST_S) |
| 1838 | #define HTT_RX_RING_CFG_ENABLED_MCAST_SET(_var, _val) \ |
| 1839 | do { \ |
| 1840 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MCAST, _val); \ |
| 1841 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MCAST_S)); \ |
| 1842 | } while (0) |
| 1843 | #define HTT_RX_RING_CFG_ENABLED_CTRL_GET(_var) \ |
| 1844 | (((_var) & HTT_RX_RING_CFG_ENABLED_CTRL_M) >> \ |
| 1845 | HTT_RX_RING_CFG_ENABLED_CTRL_S) |
| 1846 | #define HTT_RX_RING_CFG_ENABLED_CTRL_SET(_var, _val) \ |
| 1847 | do { \ |
| 1848 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_CTRL, _val); \ |
| 1849 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_CTRL_S)); \ |
| 1850 | } while (0) |
| 1851 | #define HTT_RX_RING_CFG_ENABLED_MGMT_GET(_var) \ |
| 1852 | (((_var) & HTT_RX_RING_CFG_ENABLED_MGMT_M) >> \ |
| 1853 | HTT_RX_RING_CFG_ENABLED_MGMT_S) |
| 1854 | #define HTT_RX_RING_CFG_ENABLED_MGMT_SET(_var, _val) \ |
| 1855 | do { \ |
| 1856 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_MGMT, _val); \ |
| 1857 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_MGMT_S)); \ |
| 1858 | } while (0) |
| 1859 | #define HTT_RX_RING_CFG_ENABLED_NULL_GET(_var) \ |
| 1860 | (((_var) & HTT_RX_RING_CFG_ENABLED_NULL_M) >> \ |
| 1861 | HTT_RX_RING_CFG_ENABLED_NULL_S) |
| 1862 | #define HTT_RX_RING_CFG_ENABLED_NULL_SET(_var, _val) \ |
| 1863 | do { \ |
| 1864 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_NULL, _val); \ |
| 1865 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_NULL_S)); \ |
| 1866 | } while (0) |
| 1867 | #define HTT_RX_RING_CFG_ENABLED_PHY_GET(_var) \ |
| 1868 | (((_var) & HTT_RX_RING_CFG_ENABLED_PHY_M) >> \ |
| 1869 | HTT_RX_RING_CFG_ENABLED_PHY_S) |
| 1870 | #define HTT_RX_RING_CFG_ENABLED_PHY_SET(_var, _val) \ |
| 1871 | do { \ |
| 1872 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_ENABLED_PHY, _val); \ |
| 1873 | ((_var) |= ((_val) << HTT_RX_RING_CFG_ENABLED_PHY_S)); \ |
| 1874 | } while (0) |
| 1875 | |
| 1876 | #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_GET(_var) \ |
| 1877 | (((_var) & HTT_RX_RING_CFG_OFFSET_802_11_HDR_M) >> \ |
| 1878 | HTT_RX_RING_CFG_OFFSET_802_11_HDR_S) |
| 1879 | #define HTT_RX_RING_CFG_OFFSET_802_11_HDR_SET(_var, _val) \ |
| 1880 | do { \ |
| 1881 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_802_11_HDR, _val); \ |
| 1882 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_802_11_HDR_S)); \ |
| 1883 | } while (0) |
| 1884 | |
| 1885 | #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_GET(_var) \ |
| 1886 | (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_M) >> \ |
| 1887 | HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S) |
| 1888 | #define HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_SET(_var, _val) \ |
| 1889 | do { \ |
| 1890 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD, _val); \ |
| 1891 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_PAYLD_S)); \ |
| 1892 | } while (0) |
| 1893 | |
| 1894 | #define HTT_RX_RING_CFG_OFFSET_PPDU_START_GET(_var) \ |
| 1895 | (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_START_M) >> \ |
| 1896 | HTT_RX_RING_CFG_OFFSET_PPDU_START_S) |
| 1897 | #define HTT_RX_RING_CFG_OFFSET_PPDU_START_SET(_var, _val) \ |
| 1898 | do { \ |
| 1899 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_START, _val); \ |
| 1900 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_START_S)); \ |
| 1901 | } while (0) |
| 1902 | |
| 1903 | #define HTT_RX_RING_CFG_OFFSET_PPDU_END_GET(_var) \ |
| 1904 | (((_var) & HTT_RX_RING_CFG_OFFSET_PPDU_END_M) >> \ |
| 1905 | HTT_RX_RING_CFG_OFFSET_PPDU_END_S) |
| 1906 | #define HTT_RX_RING_CFG_OFFSET_PPDU_END_SET(_var, _val) \ |
| 1907 | do { \ |
| 1908 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_PPDU_END, _val); \ |
| 1909 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_PPDU_END_S)); \ |
| 1910 | } while (0) |
| 1911 | |
| 1912 | #define HTT_RX_RING_CFG_OFFSET_MPDU_START_GET(_var) \ |
| 1913 | (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_START_M) >> \ |
| 1914 | HTT_RX_RING_CFG_OFFSET_MPDU_START_S) |
| 1915 | #define HTT_RX_RING_CFG_OFFSET_MPDU_START_SET(_var, _val) \ |
| 1916 | do { \ |
| 1917 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_START, _val); \ |
| 1918 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_START_S)); \ |
| 1919 | } while (0) |
| 1920 | |
| 1921 | #define HTT_RX_RING_CFG_OFFSET_MPDU_END_GET(_var) \ |
| 1922 | (((_var) & HTT_RX_RING_CFG_OFFSET_MPDU_END_M) >> \ |
| 1923 | HTT_RX_RING_CFG_OFFSET_MPDU_END_S) |
| 1924 | #define HTT_RX_RING_CFG_OFFSET_MPDU_END_SET(_var, _val) \ |
| 1925 | do { \ |
| 1926 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MPDU_END, _val); \ |
| 1927 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MPDU_END_S)); \ |
| 1928 | } while (0) |
| 1929 | |
| 1930 | #define HTT_RX_RING_CFG_OFFSET_MSDU_START_GET(_var) \ |
| 1931 | (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_START_M) >> \ |
| 1932 | HTT_RX_RING_CFG_OFFSET_MSDU_START_S) |
| 1933 | #define HTT_RX_RING_CFG_OFFSET_MSDU_START_SET(_var, _val) \ |
| 1934 | do { \ |
| 1935 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_START, _val); \ |
| 1936 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_START_S)); \ |
| 1937 | } while (0) |
| 1938 | |
| 1939 | #define HTT_RX_RING_CFG_OFFSET_MSDU_END_GET(_var) \ |
| 1940 | (((_var) & HTT_RX_RING_CFG_OFFSET_MSDU_END_M) >> \ |
| 1941 | HTT_RX_RING_CFG_OFFSET_MSDU_END_S) |
| 1942 | #define HTT_RX_RING_CFG_OFFSET_MSDU_END_SET(_var, _val) \ |
| 1943 | do { \ |
| 1944 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_MSDU_END, _val); \ |
| 1945 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_MSDU_END_S)); \ |
| 1946 | } while (0) |
| 1947 | |
| 1948 | #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_GET(_var) \ |
| 1949 | (((_var) & HTT_RX_RING_CFG_OFFSET_RX_ATTN_M) >> \ |
| 1950 | HTT_RX_RING_CFG_OFFSET_RX_ATTN_S) |
| 1951 | #define HTT_RX_RING_CFG_OFFSET_RX_ATTN_SET(_var, _val) \ |
| 1952 | do { \ |
| 1953 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_RX_ATTN, _val); \ |
| 1954 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_RX_ATTN_S)); \ |
| 1955 | } while (0) |
| 1956 | |
| 1957 | #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_GET(_var) \ |
| 1958 | (((_var) & HTT_RX_RING_CFG_OFFSET_FRAG_INFO_M) >> \ |
| 1959 | HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S) |
| 1960 | #define HTT_RX_RING_CFG_OFFSET_FRAG_INFO_SET(_var, _val) \ |
| 1961 | do { \ |
| 1962 | HTT_CHECK_SET_VAL(HTT_RX_RING_CFG_OFFSET_FRAG_INFO, _val); \ |
| 1963 | ((_var) |= ((_val) << HTT_RX_RING_CFG_OFFSET_FRAG_INFO_S)); \ |
| 1964 | } while (0) |
| 1965 | |
| 1966 | /** |
| 1967 | * @brief host -> target FW statistics retrieve |
| 1968 | * |
| 1969 | * @details |
| 1970 | * The following field definitions describe the format of the HTT host |
| 1971 | * to target FW stats retrieve message. The message specifies the type of |
| 1972 | * stats host wants to retrieve. |
| 1973 | * |
| 1974 | * |31 24|23 16|15 8|7 0| |
| 1975 | * |-----------------------------------------------------------| |
| 1976 | * | stats types request bitmask | msg type | |
| 1977 | * |-----------------------------------------------------------| |
| 1978 | * | stats types reset bitmask | reserved | |
| 1979 | * |-----------------------------------------------------------| |
| 1980 | * | stats type | config value | |
| 1981 | * |-----------------------------------------------------------| |
| 1982 | * | cookie LSBs | |
| 1983 | * |-----------------------------------------------------------| |
| 1984 | * | cookie MSBs | |
| 1985 | * |-----------------------------------------------------------| |
| 1986 | * Header fields: |
| 1987 | * - MSG_TYPE |
| 1988 | * Bits 7:0 |
| 1989 | * Purpose: identifies this is a stats upload request message |
| 1990 | * Value: 0x3 |
| 1991 | * - UPLOAD_TYPES |
| 1992 | * Bits 31:8 |
| 1993 | * Purpose: identifies which types of FW statistics to upload |
| 1994 | * Value: mask with bits set in positions defined by htt_dbg_stats_type |
| 1995 | * - RESET_TYPES |
| 1996 | * Bits 31:8 |
| 1997 | * Purpose: identifies which types of FW statistics to reset |
| 1998 | * Value: mask with bits set in positions defined by htt_dbg_stats_type |
| 1999 | * - CFG_VAL |
| 2000 | * Bits 23:0 |
| 2001 | * Purpose: give an opaque configuration value to the specified stats type |
| 2002 | * Value: stats-type specific configuration value |
| 2003 | * if stats type == tx PPDU log, then CONFIG_VAL has the format: |
| 2004 | * bits 7:0 - how many per-MPDU byte counts to include in a record |
| 2005 | * bits 15:8 - how many per-MPDU MSDU counts to include in a record |
| 2006 | * bits 23:16 - how many per-MSDU byte counts to include in a record |
| 2007 | * - CFG_STAT_TYPE |
| 2008 | * Bits 31:24 |
| 2009 | * Purpose: specify which stats type (if any) the config value applies to |
| 2010 | * Value: htt_dbg_stats_type value, or 0xff if the message doesn't have |
| 2011 | * a valid configuration specification |
| 2012 | * - COOKIE_LSBS |
| 2013 | * Bits 31:0 |
| 2014 | * Purpose: Provide a mechanism to match a target->host stats confirmation |
| 2015 | * message with its preceding host->target stats request message. |
| 2016 | * Value: LSBs of the opaque cookie specified by the host-side requestor |
| 2017 | * - COOKIE_MSBS |
| 2018 | * Bits 31:0 |
| 2019 | * Purpose: Provide a mechanism to match a target->host stats confirmation |
| 2020 | * message with its preceding host->target stats request message. |
| 2021 | * Value: MSBs of the opaque cookie specified by the host-side requestor |
| 2022 | */ |
| 2023 | |
| 2024 | #define HTT_H2T_STATS_REQ_MSG_SZ 20 /* bytes */ |
| 2025 | |
| 2026 | #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff |
| 2027 | |
| 2028 | #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_M 0xffffff00 |
| 2029 | #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_S 8 |
| 2030 | |
| 2031 | #define HTT_H2T_STATS_REQ_RESET_TYPES_M 0xffffff00 |
| 2032 | #define HTT_H2T_STATS_REQ_RESET_TYPES_S 8 |
| 2033 | |
| 2034 | #define HTT_H2T_STATS_REQ_CFG_VAL_M 0x00ffffff |
| 2035 | #define HTT_H2T_STATS_REQ_CFG_VAL_S 0 |
| 2036 | |
| 2037 | #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M 0xff000000 |
| 2038 | #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S 24 |
| 2039 | |
| 2040 | #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_GET(_var) \ |
| 2041 | (((_var) & HTT_H2T_STATS_REQ_UPLOAD_TYPES_M) >> \ |
| 2042 | HTT_H2T_STATS_REQ_UPLOAD_TYPES_S) |
| 2043 | #define HTT_H2T_STATS_REQ_UPLOAD_TYPES_SET(_var, _val) \ |
| 2044 | do { \ |
| 2045 | HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_UPLOAD_TYPES, _val); \ |
| 2046 | ((_var) |= ((_val) << HTT_H2T_STATS_REQ_UPLOAD_TYPES_S)); \ |
| 2047 | } while (0) |
| 2048 | |
| 2049 | #define HTT_H2T_STATS_REQ_RESET_TYPES_GET(_var) \ |
| 2050 | (((_var) & HTT_H2T_STATS_REQ_RESET_TYPES_M) >> \ |
| 2051 | HTT_H2T_STATS_REQ_RESET_TYPES_S) |
| 2052 | #define HTT_H2T_STATS_REQ_RESET_TYPES_SET(_var, _val) \ |
| 2053 | do { \ |
| 2054 | HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_RESET_TYPES, _val); \ |
| 2055 | ((_var) |= ((_val) << HTT_H2T_STATS_REQ_RESET_TYPES_S)); \ |
| 2056 | } while (0) |
| 2057 | |
| 2058 | #define HTT_H2T_STATS_REQ_CFG_VAL_GET(_var) \ |
| 2059 | (((_var) & HTT_H2T_STATS_REQ_CFG_VAL_M) >> \ |
| 2060 | HTT_H2T_STATS_REQ_CFG_VAL_S) |
| 2061 | #define HTT_H2T_STATS_REQ_CFG_VAL_SET(_var, _val) \ |
| 2062 | do { \ |
| 2063 | HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_VAL, _val); \ |
| 2064 | ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_VAL_S)); \ |
| 2065 | } while (0) |
| 2066 | |
| 2067 | #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_GET(_var) \ |
| 2068 | (((_var) & HTT_H2T_STATS_REQ_CFG_STAT_TYPE_M) >> \ |
| 2069 | HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S) |
| 2070 | #define HTT_H2T_STATS_REQ_CFG_STAT_TYPE_SET(_var, _val) \ |
| 2071 | do { \ |
| 2072 | HTT_CHECK_SET_VAL(HTT_H2T_STATS_REQ_CFG_STAT_TYPE, _val); \ |
| 2073 | ((_var) |= ((_val) << HTT_H2T_STATS_REQ_CFG_STAT_TYPE_S)); \ |
| 2074 | } while (0) |
| 2075 | |
| 2076 | /** |
| 2077 | * @brief host -> target HTT out-of-band sync request |
| 2078 | * |
| 2079 | * @details |
| 2080 | * The HTT SYNC tells the target to suspend processing of subsequent |
| 2081 | * HTT host-to-target messages until some other target agent locally |
| 2082 | * informs the target HTT FW that the current sync counter is equal to |
| 2083 | * or greater than (in a modulo sense) the sync counter specified in |
| 2084 | * the SYNC message. |
| 2085 | * This allows other host-target components to synchronize their operation |
| 2086 | * with HTT, e.g. to ensure that tx frames don't get transmitted until a |
| 2087 | * security key has been downloaded to and activated by the target. |
| 2088 | * In the absence of any explicit synchronization counter value |
| 2089 | * specification, the target HTT FW will use zero as the default current |
| 2090 | * sync value. |
| 2091 | * |
| 2092 | * |31 24|23 16|15 8|7 0| |
| 2093 | * |-----------------------------------------------------------| |
| 2094 | * | reserved | sync count | msg type | |
| 2095 | * |-----------------------------------------------------------| |
| 2096 | * Header fields: |
| 2097 | * - MSG_TYPE |
| 2098 | * Bits 7:0 |
| 2099 | * Purpose: identifies this as a sync message |
| 2100 | * Value: 0x4 |
| 2101 | * - SYNC_COUNT |
| 2102 | * Bits 15:8 |
| 2103 | * Purpose: specifies what sync value the HTT FW will wait for from |
| 2104 | * an out-of-band specification to resume its operation |
| 2105 | * Value: in-band sync counter value to compare against the out-of-band |
| 2106 | * counter spec. |
| 2107 | * The HTT target FW will suspend its host->target message processing |
| 2108 | * as long as |
| 2109 | * 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128 |
| 2110 | */ |
| 2111 | |
| 2112 | #define HTT_H2T_SYNC_MSG_SZ 4 |
| 2113 | |
| 2114 | #define HTT_H2T_SYNC_COUNT_M 0x0000ff00 |
| 2115 | #define HTT_H2T_SYNC_COUNT_S 8 |
| 2116 | |
| 2117 | #define HTT_H2T_SYNC_COUNT_GET(_var) \ |
| 2118 | (((_var) & HTT_H2T_SYNC_COUNT_M) >> \ |
| 2119 | HTT_H2T_SYNC_COUNT_S) |
| 2120 | #define HTT_H2T_SYNC_COUNT_SET(_var, _val) \ |
| 2121 | do { \ |
| 2122 | HTT_CHECK_SET_VAL(HTT_H2T_SYNC_COUNT, _val); \ |
| 2123 | ((_var) |= ((_val) << HTT_H2T_SYNC_COUNT_S)); \ |
| 2124 | } while (0) |
| 2125 | |
| 2126 | |
| 2127 | /** |
| 2128 | * @brief HTT aggregation configuration |
| 2129 | */ |
| 2130 | #define HTT_AGGR_CFG_MSG_SZ 4 |
| 2131 | |
| 2132 | #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M 0xff00 |
| 2133 | #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S 8 |
| 2134 | #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M 0x1f0000 |
| 2135 | #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S 16 |
| 2136 | |
| 2137 | #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_GET(_var) \ |
| 2138 | (((_var) & HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_M) >> \ |
| 2139 | HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S) |
| 2140 | #define HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_SET(_var, _val) \ |
| 2141 | do { \ |
| 2142 | HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM, _val); \ |
| 2143 | ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMPDU_SUBFRM_S)); \ |
| 2144 | } while (0) |
| 2145 | |
| 2146 | #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ |
| 2147 | (((_var) & HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_M) >> \ |
| 2148 | HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S) |
| 2149 | #define HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ |
| 2150 | do { \ |
| 2151 | HTT_CHECK_SET_VAL(HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM, _val); \ |
| 2152 | ((_var) |= ((_val) << HTT_AGGR_CFG_MAX_NUM_AMSDU_SUBFRM_S)); \ |
| 2153 | } while (0) |
| 2154 | |
| 2155 | |
| 2156 | /** |
| 2157 | * @brief host -> target HTT configure max amsdu info per vdev |
| 2158 | * |
| 2159 | * @details |
| 2160 | * The HTT AGGR CFG EX tells the target to configure max_amsdu info per vdev |
| 2161 | * |
| 2162 | * |31 21|20 16|15 8|7 0| |
| 2163 | * |-----------------------------------------------------------| |
| 2164 | * | reserved | vdev id | max amsdu | msg type | |
| 2165 | * |-----------------------------------------------------------| |
| 2166 | * Header fields: |
| 2167 | * - MSG_TYPE |
| 2168 | * Bits 7:0 |
| 2169 | * Purpose: identifies this as a aggr cfg ex message |
| 2170 | * Value: 0xa |
| 2171 | * - MAX_NUM_AMSDU_SUBFRM |
| 2172 | * Bits 15:8 |
| 2173 | * Purpose: max MSDUs per A-MSDU |
| 2174 | * - VDEV_ID |
| 2175 | * Bits 20:16 |
| 2176 | * Purpose: ID of the vdev to which this limit is applied |
| 2177 | */ |
| 2178 | #define HTT_AGGR_CFG_EX_MSG_SZ 4 |
| 2179 | |
| 2180 | #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M 0xff00 |
| 2181 | #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S 8 |
| 2182 | #define HTT_AGGR_CFG_EX_VDEV_ID_M 0x1f0000 |
| 2183 | #define HTT_AGGR_CFG_EX_VDEV_ID_S 16 |
| 2184 | |
| 2185 | #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_GET(_var) \ |
| 2186 | (((_var) & HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_M) >> \ |
| 2187 | HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S) |
| 2188 | #define HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_SET(_var, _val) \ |
| 2189 | do { \ |
| 2190 | HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM, _val); \ |
| 2191 | ((_var) |= ((_val) << HTT_AGGR_CFG_EX_MAX_NUM_AMSDU_SUBFRM_S)); \ |
| 2192 | } while (0) |
| 2193 | |
| 2194 | #define HTT_AGGR_CFG_EX_VDEV_ID_GET(_var) \ |
| 2195 | (((_var) & HTT_AGGR_CFG_EX_VDEV_ID_M) >> \ |
| 2196 | HTT_AGGR_CFG_EX_VDEV_ID_S) |
| 2197 | #define HTT_AGGR_CFG_EX_VDEV_ID_SET(_var, _val) \ |
| 2198 | do { \ |
| 2199 | HTT_CHECK_SET_VAL(HTT_AGGR_CFG_EX_VDEV_ID, _val); \ |
| 2200 | ((_var) |= ((_val) << HTT_AGGR_CFG_EX_VDEV_ID_S)); \ |
| 2201 | } while (0) |
| 2202 | |
| 2203 | /** |
| 2204 | * @brief HTT WDI_IPA Config Message |
| 2205 | * |
| 2206 | * @details |
| 2207 | * The HTT WDI_IPA config message is created/sent by host at driver |
| 2208 | * init time. It contains information about data structures used on |
| 2209 | * WDI_IPA TX and RX path. |
| 2210 | * TX CE ring is used for pushing packet metadata from IPA uC |
| 2211 | * to WLAN FW |
| 2212 | * TX Completion ring is used for generating TX completions from |
| 2213 | * WLAN FW to IPA uC |
| 2214 | * RX Indication ring is used for indicating RX packets from FW |
| 2215 | * to IPA uC |
| 2216 | * RX Ring2 is used as either completion ring or as second |
| 2217 | * indication ring. when Ring2 is used as completion ring, IPA uC |
| 2218 | * puts completed RX packet meta data to Ring2. when Ring2 is used |
| 2219 | * as second indication ring, RX packets for LTE-WLAN aggregation are |
| 2220 | * indicated in Ring2, other RX packets (e.g. hotspot related) are |
| 2221 | * indicated in RX Indication ring. Please see WDI_IPA specification |
| 2222 | * for more details. |
| 2223 | * |31 24|23 16|15 8|7 0| |
| 2224 | * |----------------+----------------+----------------+----------------| |
| 2225 | * | tx pkt pool size | Rsvd | msg_type | |
| 2226 | * |-------------------------------------------------------------------| |
| 2227 | * | tx comp ring base (bits 31:0) | |
| 2228 | #if HTT_PADDR64 |
| 2229 | * | tx comp ring base (bits 63:32) | |
| 2230 | #endif |
| 2231 | * |-------------------------------------------------------------------| |
| 2232 | * | tx comp ring size | |
| 2233 | * |-------------------------------------------------------------------| |
| 2234 | * | tx comp WR_IDX physical address (bits 31:0) | |
| 2235 | #if HTT_PADDR64 |
| 2236 | * | tx comp WR_IDX physical address (bits 63:32) | |
| 2237 | #endif |
| 2238 | * |-------------------------------------------------------------------| |
| 2239 | * | tx CE WR_IDX physical address (bits 31:0) | |
| 2240 | #if HTT_PADDR64 |
| 2241 | * | tx CE WR_IDX physical address (bits 63:32) | |
| 2242 | #endif |
| 2243 | * |-------------------------------------------------------------------| |
| 2244 | * | rx indication ring base (bits 31:0) | |
| 2245 | #if HTT_PADDR64 |
| 2246 | * | rx indication ring base (bits 63:32) | |
| 2247 | #endif |
| 2248 | * |-------------------------------------------------------------------| |
| 2249 | * | rx indication ring size | |
| 2250 | * |-------------------------------------------------------------------| |
| 2251 | * | rx ind RD_IDX physical address (bits 31:0) | |
| 2252 | #if HTT_PADDR64 |
| 2253 | * | rx ind RD_IDX physical address (bits 63:32) | |
| 2254 | #endif |
| 2255 | * |-------------------------------------------------------------------| |
| 2256 | * | rx ind WR_IDX physical address (bits 31:0) | |
| 2257 | #if HTT_PADDR64 |
| 2258 | * | rx ind WR_IDX physical address (bits 63:32) | |
| 2259 | #endif |
| 2260 | * |-------------------------------------------------------------------| |
| 2261 | * |-------------------------------------------------------------------| |
| 2262 | * | rx ring2 base (bits 31:0) | |
| 2263 | #if HTT_PADDR64 |
| 2264 | * | rx ring2 base (bits 63:32) | |
| 2265 | #endif |
| 2266 | * |-------------------------------------------------------------------| |
| 2267 | * | rx ring2 size | |
| 2268 | * |-------------------------------------------------------------------| |
| 2269 | * | rx ring2 RD_IDX physical address (bits 31:0) | |
| 2270 | #if HTT_PADDR64 |
| 2271 | * | rx ring2 RD_IDX physical address (bits 63:32) | |
| 2272 | #endif |
| 2273 | * |-------------------------------------------------------------------| |
| 2274 | * | rx ring2 WR_IDX physical address (bits 31:0) | |
| 2275 | #if HTT_PADDR64 |
| 2276 | * | rx ring2 WR_IDX physical address (bits 63:32) | |
| 2277 | #endif |
| 2278 | * |-------------------------------------------------------------------| |
| 2279 | * |
| 2280 | * Header fields: |
| 2281 | * Header fields: |
| 2282 | * - MSG_TYPE |
| 2283 | * Bits 7:0 |
| 2284 | * Purpose: Identifies this as WDI_IPA config message |
| 2285 | * value: = 0x8 |
| 2286 | * - TX_PKT_POOL_SIZE |
| 2287 | * Bits 15:0 |
| 2288 | * Purpose: Total number of TX packet buffer pool allocated by Host for |
| 2289 | * WDI_IPA TX path |
| 2290 | * For systems using 32-bit format for bus addresses: |
| 2291 | * - TX_COMP_RING_BASE_ADDR |
| 2292 | * Bits 31:0 |
| 2293 | * Purpose: TX Completion Ring base address in DDR |
| 2294 | * - TX_COMP_RING_SIZE |
| 2295 | * Bits 31:0 |
| 2296 | * Purpose: TX Completion Ring size (must be power of 2) |
| 2297 | * - TX_COMP_WR_IDX_ADDR |
| 2298 | * Bits 31:0 |
| 2299 | * Purpose: IPA doorbell register address OR DDR address where WIFI FW |
| 2300 | * updates the Write Index for WDI_IPA TX completion ring |
| 2301 | * - TX_CE_WR_IDX_ADDR |
| 2302 | * Bits 31:0 |
| 2303 | * Purpose: DDR address where IPA uC |
| 2304 | * updates the WR Index for TX CE ring |
| 2305 | * (needed for fusion platforms) |
| 2306 | * - RX_IND_RING_BASE_ADDR |
| 2307 | * Bits 31:0 |
| 2308 | * Purpose: RX Indication Ring base address in DDR |
| 2309 | * - RX_IND_RING_SIZE |
| 2310 | * Bits 31:0 |
| 2311 | * Purpose: RX Indication Ring size |
| 2312 | * - RX_IND_RD_IDX_ADDR |
| 2313 | * Bits 31:0 |
| 2314 | * Purpose: DDR address where IPA uC updates the Read Index for WDI_IPA |
| 2315 | * RX indication ring |
| 2316 | * - RX_IND_WR_IDX_ADDR |
| 2317 | * Bits 31:0 |
| 2318 | * Purpose: IPA doorbell register address OR DDR address where WIFI FW |
| 2319 | * updates the Write Index for WDI_IPA RX indication ring |
| 2320 | * - RX_RING2_BASE_ADDR |
| 2321 | * Bits 31:0 |
| 2322 | * Purpose: Second RX Ring(Indication or completion)base address in DDR |
| 2323 | * - RX_RING2_SIZE |
| 2324 | * Bits 31:0 |
| 2325 | * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) |
| 2326 | * - RX_RING2_RD_IDX_ADDR |
| 2327 | * Bits 31:0 |
| 2328 | * Purpose: If Second RX ring is Indication ring, DDR address where |
| 2329 | * IPA uC updates the Read Index for Ring2. |
| 2330 | * If Second RX ring is completion ring, this is NOT used |
| 2331 | * - RX_RING2_WR_IDX_ADDR |
| 2332 | * Bits 31:0 |
| 2333 | * Purpose: If Second RX ring is Indication ring, DDR address where |
| 2334 | * WIFI FW updates the Write Index for WDI_IPA RX ring2 |
| 2335 | * If second RX ring is completion ring, DDR address where |
| 2336 | * IPA uC updates the Write Index for Ring 2. |
| 2337 | * For systems using 64-bit format for bus addresses: |
| 2338 | * - TX_COMP_RING_BASE_ADDR_LO |
| 2339 | * Bits 31:0 |
| 2340 | * Purpose: Lower 4 bytes of TX Completion Ring base physical |
| 2341 | * address in DDR |
| 2342 | * - TX_COMP_RING_BASE_ADDR_HI |
| 2343 | * Bits 31:0 |
| 2344 | * Purpose: Higher 4 bytes of TX Completion Ring base physical |
| 2345 | * address in DDR |
| 2346 | * - TX_COMP_RING_SIZE |
| 2347 | * Bits 31:0 |
| 2348 | * Purpose: TX Completion Ring size (must be power of 2) |
| 2349 | * - TX_COMP_WR_IDX_ADDR_LO |
| 2350 | * Bits 31:0 |
| 2351 | * Purpose: Lower 4 bytes of IPA doorbell register address OR |
| 2352 | * Lower 4 bytes of DDR address where WIFI FW |
| 2353 | * updates the Write Index for WDI_IPA TX completion ring |
| 2354 | * - TX_COMP_WR_IDX_ADDR_HI |
| 2355 | * Bits 31:0 |
| 2356 | * Purpose: Higher 4 bytes of IPA doorbell register address OR |
| 2357 | * Higher 4 bytes of DDR address where WIFI FW |
| 2358 | * updates the Write Index for WDI_IPA TX completion ring |
| 2359 | * - TX_CE_WR_IDX_ADDR_LO |
| 2360 | * Bits 31:0 |
| 2361 | * Purpose: Lower 4 bytes of DDR address where IPA uC |
| 2362 | * updates the WR Index for TX CE ring |
| 2363 | * (needed for fusion platforms) |
| 2364 | * - TX_CE_WR_IDX_ADDR_HI |
| 2365 | * Bits 31:0 |
| 2366 | * Purpose: Higher 4 bytes of DDR address where IPA uC |
| 2367 | * updates the WR Index for TX CE ring |
| 2368 | * (needed for fusion platforms) |
| 2369 | * - RX_IND_RING_BASE_ADDR_LO |
| 2370 | * Bits 31:0 |
| 2371 | * Purpose: Lower 4 bytes of RX Indication Ring base address in DDR |
| 2372 | * - RX_IND_RING_BASE_ADDR_HI |
| 2373 | * Bits 31:0 |
| 2374 | * Purpose: Higher 4 bytes of RX Indication Ring base address in DDR |
| 2375 | * - RX_IND_RING_SIZE |
| 2376 | * Bits 31:0 |
| 2377 | * Purpose: RX Indication Ring size |
| 2378 | * - RX_IND_RD_IDX_ADDR_LO |
| 2379 | * Bits 31:0 |
| 2380 | * Purpose: Lower 4 bytes of DDR address where IPA uC updates the |
| 2381 | * Read Index for WDI_IPA RX indication ring |
| 2382 | * - RX_IND_RD_IDX_ADDR_HI |
| 2383 | * Bits 31:0 |
| 2384 | * Purpose: Higher 4 bytes of DDR address where IPA uC updates the |
| 2385 | * Read Index for WDI_IPA RX indication ring |
| 2386 | * - RX_IND_WR_IDX_ADDR_LO |
| 2387 | * Bits 31:0 |
| 2388 | * Purpose: Lower 4 bytes of IPA doorbell register address OR |
| 2389 | * Lower 4 bytes of DDR address where WIFI FW |
| 2390 | * updates the Write Index for WDI_IPA RX indication ring |
| 2391 | * - RX_IND_WR_IDX_ADDR_HI |
| 2392 | * Bits 31:0 |
| 2393 | * Purpose: Higher 4 bytes of IPA doorbell register address OR |
| 2394 | * Higher 4 bytes of DDR address where WIFI FW |
| 2395 | * updates the Write Index for WDI_IPA RX indication ring |
| 2396 | * - RX_RING2_BASE_ADDR_LO |
| 2397 | * Bits 31:0 |
| 2398 | * Purpose: Lower 4 bytes of Second RX Ring(Indication OR completion) |
| 2399 | * base address in DDR |
| 2400 | * - RX_RING2_BASE_ADDR_HI |
| 2401 | * Bits 31:0 |
| 2402 | * Purpose: Higher 4 bytes of Second RX Ring(Indication OR completion) |
| 2403 | * base address in DDR |
| 2404 | * - RX_RING2_SIZE |
| 2405 | * Bits 31:0 |
| 2406 | * Purpose: Second RX Ring size (must be >= RX_IND_RING_SIZE) |
| 2407 | * - RX_RING2_RD_IDX_ADDR_LO |
| 2408 | * Bits 31:0 |
| 2409 | * Purpose: If Second RX ring is Indication ring, lower 4 bytes of |
| 2410 | * DDR address where IPA uC updates the Read Index for Ring2. |
| 2411 | * If Second RX ring is completion ring, this is NOT used |
| 2412 | * - RX_RING2_RD_IDX_ADDR_HI |
| 2413 | * Bits 31:0 |
| 2414 | * Purpose: If Second RX ring is Indication ring, higher 4 bytes of |
| 2415 | * DDR address where IPA uC updates the Read Index for Ring2. |
| 2416 | * If Second RX ring is completion ring, this is NOT used |
| 2417 | * - RX_RING2_WR_IDX_ADDR_LO |
| 2418 | * Bits 31:0 |
| 2419 | * Purpose: If Second RX ring is Indication ring, lower 4 bytes of |
| 2420 | * DDR address where WIFI FW updates the Write Index |
| 2421 | * for WDI_IPA RX ring2 |
| 2422 | * If second RX ring is completion ring, lower 4 bytes of |
| 2423 | * DDR address where IPA uC updates the Write Index for Ring 2. |
| 2424 | * - RX_RING2_WR_IDX_ADDR_HI |
| 2425 | * Bits 31:0 |
| 2426 | * Purpose: If Second RX ring is Indication ring, higher 4 bytes of |
| 2427 | * DDR address where WIFI FW updates the Write Index |
| 2428 | * for WDI_IPA RX ring2 |
| 2429 | * If second RX ring is completion ring, higher 4 bytes of |
| 2430 | * DDR address where IPA uC updates the Write Index for Ring 2. |
| 2431 | */ |
| 2432 | |
| 2433 | #if HTT_PADDR64 |
| 2434 | #define HTT_WDI_IPA_CFG_SZ 88 /* bytes */ |
| 2435 | #else |
| 2436 | #define HTT_WDI_IPA_CFG_SZ 52 /* bytes */ |
| 2437 | #endif |
| 2438 | |
| 2439 | #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M 0xffff0000 |
| 2440 | #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S 16 |
| 2441 | |
| 2442 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M 0xffffffff |
| 2443 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S 0 |
| 2444 | |
| 2445 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M 0xffffffff |
| 2446 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S 0 |
| 2447 | |
| 2448 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M 0xffffffff |
| 2449 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S 0 |
| 2450 | |
| 2451 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M 0xffffffff |
| 2452 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S 0 |
| 2453 | |
| 2454 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M 0xffffffff |
| 2455 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S 0 |
| 2456 | |
| 2457 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M 0xffffffff |
| 2458 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S 0 |
| 2459 | |
| 2460 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M 0xffffffff |
| 2461 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S 0 |
| 2462 | |
| 2463 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M 0xffffffff |
| 2464 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S 0 |
| 2465 | |
| 2466 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M 0xffffffff |
| 2467 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S 0 |
| 2468 | |
| 2469 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M 0xffffffff |
| 2470 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S 0 |
| 2471 | |
| 2472 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M 0xffffffff |
| 2473 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S 0 |
| 2474 | |
| 2475 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M 0xffffffff |
| 2476 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S 0 |
| 2477 | |
| 2478 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M 0xffffffff |
| 2479 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S 0 |
| 2480 | |
| 2481 | #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M 0xffffffff |
| 2482 | #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S 0 |
| 2483 | |
| 2484 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M 0xffffffff |
| 2485 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S 0 |
| 2486 | |
| 2487 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M 0xffffffff |
| 2488 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S 0 |
| 2489 | |
| 2490 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M 0xffffffff |
| 2491 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S 0 |
| 2492 | |
| 2493 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M 0xffffffff |
| 2494 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S 0 |
| 2495 | |
| 2496 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M 0xffffffff |
| 2497 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S 0 |
| 2498 | |
| 2499 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M 0xffffffff |
| 2500 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S 0 |
| 2501 | |
| 2502 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M 0xffffffff |
| 2503 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S 0 |
| 2504 | |
| 2505 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M 0xffffffff |
| 2506 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S 0 |
| 2507 | |
| 2508 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M 0xffffffff |
| 2509 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S 0 |
| 2510 | |
| 2511 | #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_M 0xffffffff |
| 2512 | #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_S 0 |
| 2513 | |
| 2514 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M 0xffffffff |
| 2515 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S 0 |
| 2516 | |
| 2517 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M 0xffffffff |
| 2518 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S 0 |
| 2519 | |
| 2520 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M 0xffffffff |
| 2521 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S 0 |
| 2522 | |
| 2523 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M 0xffffffff |
| 2524 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S 0 |
| 2525 | |
| 2526 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M 0xffffffff |
| 2527 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S 0 |
| 2528 | |
| 2529 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M 0xffffffff |
| 2530 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S 0 |
| 2531 | |
| 2532 | #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_GET(_var) \ |
| 2533 | (((_var) & HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_M) >> \ |
| 2534 | HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S) |
| 2535 | #define HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_SET(_var, _val) \ |
| 2536 | do { \ |
| 2537 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE, _val); \ |
| 2538 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_PKT_POOL_SIZE_S)); \ |
| 2539 | } while (0) |
| 2540 | |
| 2541 | /* for systems using 32-bit format for bus addr */ |
| 2542 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_GET(_var) \ |
| 2543 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_M) >> \ |
| 2544 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S) |
| 2545 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_SET(_var, _val) \ |
| 2546 | do { \ |
| 2547 | HTT_CHECK_SET_VAL( \ |
| 2548 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR, _val);\ |
| 2549 | ((_var) |= \ |
| 2550 | ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_S)); \ |
| 2551 | } while (0) |
| 2552 | |
| 2553 | /* for systems using 64-bit format for bus addr */ |
| 2554 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_GET(_var) \ |
| 2555 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_M) >> \ |
| 2556 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S) |
| 2557 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_SET(_var, _val) \ |
| 2558 | do { \ |
| 2559 | HTT_CHECK_SET_VAL( \ |
| 2560 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI, _val);\ |
| 2561 | ((_var) |= \ |
| 2562 | ((_val) << \ |
| 2563 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_HI_S)); \ |
| 2564 | } while (0) |
| 2565 | |
| 2566 | /* for systems using 64-bit format for bus addr */ |
| 2567 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_GET(_var) \ |
| 2568 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_M) >> \ |
| 2569 | HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S) |
| 2570 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_SET(_var, _val) \ |
| 2571 | do { \ |
| 2572 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO, _val); \ |
| 2573 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_BASE_ADDR_LO_S)); \ |
| 2574 | } while (0) |
| 2575 | |
| 2576 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_GET(_var) \ |
| 2577 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_M) >> \ |
| 2578 | HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S) |
| 2579 | #define HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_SET(_var, _val) \ |
| 2580 | do { \ |
| 2581 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE, _val); \ |
| 2582 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_RING_SIZE_S)); \ |
| 2583 | } while (0) |
| 2584 | |
| 2585 | /* for systems using 32-bit format for bus addr */ |
| 2586 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_GET(_var) \ |
| 2587 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_M) >> \ |
| 2588 | HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S) |
| 2589 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_SET(_var, _val) \ |
| 2590 | do { \ |
| 2591 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR, _val); \ |
| 2592 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_S)); \ |
| 2593 | } while (0) |
| 2594 | |
| 2595 | /* for systems using 64-bit format for bus addr */ |
| 2596 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_GET(_var) \ |
| 2597 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_M) >> \ |
| 2598 | HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S) |
| 2599 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| 2600 | do { \ |
| 2601 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI, _val); \ |
| 2602 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_HI_S)); \ |
| 2603 | } while (0) |
| 2604 | |
| 2605 | /* for systems using 64-bit format for bus addr */ |
| 2606 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_GET(_var) \ |
| 2607 | (((_var) & HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_M) >> \ |
| 2608 | HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S) |
| 2609 | #define HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| 2610 | do { \ |
| 2611 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO, _val); \ |
| 2612 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_COMP_WR_IDX_ADDR_LO_S)); \ |
| 2613 | } while (0) |
| 2614 | |
| 2615 | |
| 2616 | /* for systems using 32-bit format for bus addr */ |
| 2617 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_GET(_var) \ |
| 2618 | (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_M) >> \ |
| 2619 | HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S) |
| 2620 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_SET(_var, _val) \ |
| 2621 | do { \ |
| 2622 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR, _val); \ |
| 2623 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_S)); \ |
| 2624 | } while (0) |
| 2625 | |
| 2626 | /* for systems using 64-bit format for bus addr */ |
| 2627 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_GET(_var) \ |
| 2628 | (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_M) >>\ |
| 2629 | HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S) |
| 2630 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| 2631 | do { \ |
| 2632 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI, _val); \ |
| 2633 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_HI_S)); \ |
| 2634 | } while (0) |
| 2635 | |
| 2636 | /* for systems using 64-bit format for bus addr */ |
| 2637 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_GET(_var) \ |
| 2638 | (((_var) & HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_M) >> \ |
| 2639 | HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S) |
| 2640 | #define HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| 2641 | do { \ |
| 2642 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO, _val); \ |
| 2643 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_TX_CE_WR_IDX_ADDR_LO_S)); \ |
| 2644 | } while (0) |
| 2645 | |
| 2646 | /* for systems using 32-bit format for bus addr */ |
| 2647 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_GET(_var) \ |
| 2648 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_M) >> \ |
| 2649 | HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S) |
| 2650 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_SET(_var, _val) \ |
| 2651 | do { \ |
| 2652 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR, _val); \ |
| 2653 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_S)); \ |
| 2654 | } while (0) |
| 2655 | |
| 2656 | /* for systems using 64-bit format for bus addr */ |
| 2657 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_GET(_var) \ |
| 2658 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_M) >> \ |
| 2659 | HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S) |
| 2660 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_SET(_var, _val) \ |
| 2661 | do { \ |
| 2662 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI, _val); \ |
| 2663 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_HI_S)); \ |
| 2664 | } while (0) |
| 2665 | |
| 2666 | /* for systems using 64-bit format for bus addr */ |
| 2667 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_GET(_var) \ |
| 2668 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_M) >> \ |
| 2669 | HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S) |
| 2670 | #define HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_SET(_var, _val) \ |
| 2671 | do { \ |
| 2672 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO, _val); \ |
| 2673 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_BASE_ADDR_LO_S)); \ |
| 2674 | } while (0) |
| 2675 | |
| 2676 | #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_GET(_var) \ |
| 2677 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_M) >> \ |
| 2678 | HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S) |
| 2679 | #define HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_SET(_var, _val) \ |
| 2680 | do { \ |
| 2681 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RING_SIZE, _val); \ |
| 2682 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RING_SIZE_S)); \ |
| 2683 | } while (0) |
| 2684 | |
| 2685 | /* for systems using 32-bit format for bus addr */ |
| 2686 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_GET(_var) \ |
| 2687 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_M) >> \ |
| 2688 | HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S) |
| 2689 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_SET(_var, _val) \ |
| 2690 | do { \ |
| 2691 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR, _val); \ |
| 2692 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_S)); \ |
| 2693 | } while (0) |
| 2694 | |
| 2695 | /* for systems using 64-bit format for bus addr */ |
| 2696 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_GET(_var) \ |
| 2697 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_M) >> \ |
| 2698 | HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S) |
| 2699 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_SET(_var, _val) \ |
| 2700 | do { \ |
| 2701 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI, _val); \ |
| 2702 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_HI_S)); \ |
| 2703 | } while (0) |
| 2704 | |
| 2705 | /* for systems using 64-bit format for bus addr */ |
| 2706 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_GET(_var) \ |
| 2707 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_M) >> \ |
| 2708 | HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S) |
| 2709 | #define HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_SET(_var, _val) \ |
| 2710 | do { \ |
| 2711 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO, _val); \ |
| 2712 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_RD_IDX_ADDR_LO_S)); \ |
| 2713 | } while (0) |
| 2714 | |
| 2715 | /* for systems using 32-bit format for bus addr */ |
| 2716 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_GET(_var) \ |
| 2717 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_M) >> \ |
| 2718 | HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S) |
| 2719 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_SET(_var, _val) \ |
| 2720 | do { \ |
| 2721 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR, _val); \ |
| 2722 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_S)); \ |
| 2723 | } while (0) |
| 2724 | |
| 2725 | /* for systems using 64-bit format for bus addr */ |
| 2726 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_GET(_var) \ |
| 2727 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_M) >> \ |
| 2728 | HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S) |
| 2729 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| 2730 | do { \ |
| 2731 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI, _val); \ |
| 2732 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_HI_S)); \ |
| 2733 | } while (0) |
| 2734 | |
| 2735 | /* for systems using 64-bit format for bus addr */ |
| 2736 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_GET(_var) \ |
| 2737 | (((_var) & HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_M) >> \ |
| 2738 | HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S) |
| 2739 | #define HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| 2740 | do { \ |
| 2741 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO, _val); \ |
| 2742 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_IND_WR_IDX_ADDR_LO_S)); \ |
| 2743 | } while (0) |
| 2744 | |
| 2745 | /* for systems using 32-bit format for bus addr */ |
| 2746 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_GET(_var) \ |
| 2747 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_M) >> \ |
| 2748 | HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S) |
| 2749 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_SET(_var, _val) \ |
| 2750 | do { \ |
| 2751 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR, _val); \ |
| 2752 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_S)); \ |
| 2753 | } while (0) |
| 2754 | |
| 2755 | /* for systems using 64-bit format for bus addr */ |
| 2756 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_GET(_var) \ |
| 2757 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_M) >> \ |
| 2758 | HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S) |
| 2759 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_SET(_var, _val) \ |
| 2760 | do { \ |
| 2761 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI, _val); \ |
| 2762 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_HI_S)); \ |
| 2763 | } while (0) |
| 2764 | |
| 2765 | /* for systems using 64-bit format for bus addr */ |
| 2766 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_GET(_var) \ |
| 2767 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_M) >> \ |
| 2768 | HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S) |
| 2769 | #define HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_SET(_var, _val) \ |
| 2770 | do { \ |
| 2771 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO, _val); \ |
| 2772 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_BASE_ADDR_LO_S)); \ |
| 2773 | } while (0) |
| 2774 | |
| 2775 | #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_GET(_var) \ |
| 2776 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_SIZE_M) >> \ |
| 2777 | HTT_WDI_IPA_CFG_RX_RING2_SIZE_S) |
| 2778 | #define HTT_WDI_IPA_CFG_RX_RING2_SIZE_SET(_var, _val) \ |
| 2779 | do { \ |
| 2780 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_SIZE, _val); \ |
| 2781 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_SIZE_S)); \ |
| 2782 | } while (0) |
| 2783 | |
| 2784 | /* for systems using 32-bit format for bus addr */ |
| 2785 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_GET(_var) \ |
| 2786 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_M) >> \ |
| 2787 | HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S) |
| 2788 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_SET(_var, _val) \ |
| 2789 | do { \ |
| 2790 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR, _val); \ |
| 2791 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_S)); \ |
| 2792 | } while (0) |
| 2793 | |
| 2794 | /* for systems using 64-bit format for bus addr */ |
| 2795 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_GET(_var) \ |
| 2796 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_M) >> \ |
| 2797 | HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S) |
| 2798 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_SET(_var, _val) \ |
| 2799 | do { \ |
| 2800 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI, _val); \ |
| 2801 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_HI_S)); \ |
| 2802 | } while (0) |
| 2803 | |
| 2804 | /* for systems using 64-bit format for bus addr */ |
| 2805 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_GET(_var) \ |
| 2806 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_M) >> \ |
| 2807 | HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S) |
| 2808 | #define HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_SET(_var, _val) \ |
| 2809 | do { \ |
| 2810 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO, _val); \ |
| 2811 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_RD_IDX_ADDR_LO_S)); \ |
| 2812 | } while (0) |
| 2813 | |
| 2814 | /* for systems using 32-bit format for bus addr */ |
| 2815 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_GET(_var) \ |
| 2816 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_M) >> \ |
| 2817 | HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S) |
| 2818 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_SET(_var, _val) \ |
| 2819 | do { \ |
| 2820 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR, _val); \ |
| 2821 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_S)); \ |
| 2822 | } while (0) |
| 2823 | |
| 2824 | /* for systems using 64-bit format for bus addr */ |
| 2825 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_GET(_var) \ |
| 2826 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_M) >> \ |
| 2827 | HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S) |
| 2828 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_SET(_var, _val) \ |
| 2829 | do { \ |
| 2830 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI, _val); \ |
| 2831 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_HI_S)); \ |
| 2832 | } while (0) |
| 2833 | |
| 2834 | /* for systems using 64-bit format for bus addr */ |
| 2835 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_GET(_var) \ |
| 2836 | (((_var) & HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_M) >> \ |
| 2837 | HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S) |
| 2838 | #define HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_SET(_var, _val) \ |
| 2839 | do { \ |
| 2840 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO, _val); \ |
| 2841 | ((_var) |= ((_val) << HTT_WDI_IPA_CFG_RX_RING2_WR_IDX_ADDR_LO_S)); \ |
| 2842 | } while (0) |
| 2843 | |
| 2844 | /* |
| 2845 | * TEMPLATE_HTT_WDI_IPA_CONFIG_T: |
| 2846 | * This macro defines a htt_wdi_ipa_configXXX_t in which any physical |
| 2847 | * addresses are stored in a XXX-bit field. |
| 2848 | * This macro is used to define both htt_wdi_ipa_config32_t and |
| 2849 | * htt_wdi_ipa_config64_t structs. |
| 2850 | */ |
| 2851 | #define TEMPLATE_HTT_WDI_IPA_CONFIG_T(_paddr_bits_, \ |
| 2852 | _paddr__tx_comp_ring_base_addr_, \ |
| 2853 | _paddr__tx_comp_wr_idx_addr_, \ |
| 2854 | _paddr__tx_ce_wr_idx_addr_, \ |
| 2855 | _paddr__rx_ind_ring_base_addr_, \ |
| 2856 | _paddr__rx_ind_rd_idx_addr_, \ |
| 2857 | _paddr__rx_ind_wr_idx_addr_, \ |
| 2858 | _paddr__rx_ring2_base_addr_,\ |
| 2859 | _paddr__rx_ring2_rd_idx_addr_,\ |
| 2860 | _paddr__rx_ring2_wr_idx_addr_) \ |
| 2861 | PREPACK struct htt_wdi_ipa_cfg ## _paddr_bits_ ## _t \ |
| 2862 | { \ |
| 2863 | /* DWORD 0: flags and meta-data */ \ |
| 2864 | A_UINT32 \ |
| 2865 | msg_type:8, /* HTT_H2T_MSG_TYPE_WDI_IPA_CFG */ \ |
| 2866 | reserved:8, \ |
| 2867 | tx_pkt_pool_size:16;\ |
| 2868 | /* DWORD 1 */\ |
| 2869 | _paddr__tx_comp_ring_base_addr_;\ |
| 2870 | /* DWORD 2 (or 3)*/\ |
| 2871 | A_UINT32 tx_comp_ring_size;\ |
| 2872 | /* DWORD 3 (or 4)*/\ |
| 2873 | _paddr__tx_comp_wr_idx_addr_;\ |
| 2874 | /* DWORD 4 (or 6)*/\ |
| 2875 | _paddr__tx_ce_wr_idx_addr_;\ |
| 2876 | /* DWORD 5 (or 8)*/\ |
| 2877 | _paddr__rx_ind_ring_base_addr_;\ |
| 2878 | /* DWORD 6 (or 10)*/\ |
| 2879 | A_UINT32 rx_ind_ring_size;\ |
| 2880 | /* DWORD 7 (or 11)*/\ |
| 2881 | _paddr__rx_ind_rd_idx_addr_;\ |
| 2882 | /* DWORD 8 (or 13)*/\ |
| 2883 | _paddr__rx_ind_wr_idx_addr_;\ |
| 2884 | /* DWORD 9 (or 15)*/\ |
| 2885 | _paddr__rx_ring2_base_addr_;\ |
| 2886 | /* DWORD 10 (or 17) */\ |
| 2887 | A_UINT32 rx_ring2_size;\ |
| 2888 | /* DWORD 11 (or 18) */\ |
| 2889 | _paddr__rx_ring2_rd_idx_addr_;\ |
| 2890 | /* DWORD 12 (or 20) */\ |
| 2891 | _paddr__rx_ring2_wr_idx_addr_;\ |
| 2892 | } POSTPACK |
| 2893 | |
| 2894 | /* define a htt_wdi_ipa_config32_t type */ |
| 2895 | TEMPLATE_HTT_WDI_IPA_CONFIG_T(32, HTT_VAR_PADDR32(tx_comp_ring_base_addr), |
| 2896 | HTT_VAR_PADDR32(tx_comp_wr_idx_addr), |
| 2897 | HTT_VAR_PADDR32(tx_ce_wr_idx_addr), |
| 2898 | HTT_VAR_PADDR32(rx_ind_ring_base_addr), |
| 2899 | HTT_VAR_PADDR32(rx_ind_rd_idx_addr), |
| 2900 | HTT_VAR_PADDR32(rx_ind_wr_idx_addr), |
| 2901 | HTT_VAR_PADDR32(rx_ring2_base_addr), |
| 2902 | HTT_VAR_PADDR32(rx_ring2_rd_idx_addr), |
| 2903 | HTT_VAR_PADDR32(rx_ring2_wr_idx_addr)); |
| 2904 | |
| 2905 | /* define a htt_wdi_ipa_config64_t type */ |
| 2906 | TEMPLATE_HTT_WDI_IPA_CONFIG_T(64, HTT_VAR_PADDR64_LE(tx_comp_ring_base_addr), |
| 2907 | HTT_VAR_PADDR64_LE(tx_comp_wr_idx_addr), |
| 2908 | HTT_VAR_PADDR64_LE(tx_ce_wr_idx_addr), |
| 2909 | HTT_VAR_PADDR64_LE(rx_ind_ring_base_addr), |
| 2910 | HTT_VAR_PADDR64_LE(rx_ind_rd_idx_addr), |
| 2911 | HTT_VAR_PADDR64_LE(rx_ind_wr_idx_addr), |
| 2912 | HTT_VAR_PADDR64_LE(rx_ring2_base_addr), |
| 2913 | HTT_VAR_PADDR64_LE(rx_ring2_rd_idx_addr), |
| 2914 | HTT_VAR_PADDR64_LE(rx_ring2_wr_idx_addr)); |
| 2915 | |
| 2916 | #if HTT_PADDR64 |
| 2917 | #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg64_t |
| 2918 | #else |
| 2919 | #define htt_wdi_ipa_cfg_t htt_wdi_ipa_cfg32_t |
| 2920 | #endif |
| 2921 | |
| 2922 | enum htt_wdi_ipa_op_code { |
| 2923 | HTT_WDI_IPA_OPCODE_TX_SUSPEND = 0, |
| 2924 | HTT_WDI_IPA_OPCODE_TX_RESUME = 1, |
| 2925 | HTT_WDI_IPA_OPCODE_RX_SUSPEND = 2, |
| 2926 | HTT_WDI_IPA_OPCODE_RX_RESUME = 3, |
| 2927 | HTT_WDI_IPA_OPCODE_DBG_STATS = 4, |
| 2928 | /* keep this last */ |
| 2929 | HTT_WDI_IPA_OPCODE_MAX |
| 2930 | }; |
| 2931 | |
| 2932 | /** |
| 2933 | * @brief HTT WDI_IPA Operation Request Message |
| 2934 | * |
| 2935 | * @details |
| 2936 | * HTT WDI_IPA Operation Request message is sent by host |
| 2937 | * to either suspend or resume WDI_IPA TX or RX path. |
| 2938 | * |31 24|23 16|15 8|7 0| |
| 2939 | * |----------------+----------------+----------------+----------------| |
| 2940 | * | op_code | Rsvd | msg_type | |
| 2941 | * |-------------------------------------------------------------------| |
| 2942 | * |
| 2943 | * Header fields: |
| 2944 | * - MSG_TYPE |
| 2945 | * Bits 7:0 |
| 2946 | * Purpose: Identifies this as WDI_IPA Operation Request message |
| 2947 | * value: = 0x9 |
| 2948 | * - OP_CODE |
| 2949 | * Bits 31:16 |
| 2950 | * Purpose: Identifies operation host is requesting (e.g. TX suspend) |
| 2951 | * value: = enum htt_wdi_ipa_op_code |
| 2952 | */ |
| 2953 | |
| 2954 | PREPACK struct htt_wdi_ipa_op_request_t { |
| 2955 | /* DWORD 0: flags and meta-data */ |
| 2956 | A_UINT32 |
| 2957 | msg_type:8, /* HTT_H2T_MSG_TYPE_WDI_IPA_OP_REQUEST */ |
| 2958 | reserved:8, |
| 2959 | op_code:16; |
| 2960 | } POSTPACK; |
| 2961 | |
| 2962 | #define HTT_WDI_IPA_OP_REQUEST_SZ 4 /* bytes */ |
| 2963 | |
| 2964 | #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_M 0xffff0000 |
| 2965 | #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_S 16 |
| 2966 | |
| 2967 | #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_GET(_var) \ |
| 2968 | (((_var) & HTT_WDI_IPA_OP_REQUEST_OP_CODE_M) >> \ |
| 2969 | HTT_WDI_IPA_OP_REQUEST_OP_CODE_S) |
| 2970 | #define HTT_WDI_IPA_OP_REQUEST_OP_CODE_SET(_var, _val) \ |
| 2971 | do { \ |
| 2972 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_REQUEST_OP_CODE, _val); \ |
| 2973 | ((_var) |= ((_val) << HTT_WDI_IPA_OP_REQUEST_OP_CODE_S)); \ |
| 2974 | } while (0) |
| 2975 | |
| 2976 | |
| 2977 | |
| 2978 | |
| 2979 | /*=== target -> host messages ===============================================*/ |
| 2980 | |
| 2981 | |
| 2982 | enum htt_t2h_msg_type { |
| 2983 | HTT_T2H_MSG_TYPE_VERSION_CONF = 0x0, |
| 2984 | HTT_T2H_MSG_TYPE_RX_IND = 0x1, |
| 2985 | HTT_T2H_MSG_TYPE_RX_FLUSH = 0x2, |
| 2986 | HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, |
| 2987 | HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, |
| 2988 | HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, |
| 2989 | HTT_T2H_MSG_TYPE_RX_DELBA = 0x6, |
| 2990 | HTT_T2H_MSG_TYPE_TX_COMPL_IND = 0x7, |
| 2991 | HTT_T2H_MSG_TYPE_PKTLOG = 0x8, |
| 2992 | HTT_T2H_MSG_TYPE_STATS_CONF = 0x9, |
| 2993 | HTT_T2H_MSG_TYPE_RX_FRAG_IND = 0xa, |
| 2994 | HTT_T2H_MSG_TYPE_SEC_IND = 0xb, |
| 2995 | DEPRECATED_HTT_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,/* no longer used */ |
| 2996 | HTT_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd, |
| 2997 | HTT_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe, |
| 2998 | /* only used for HL, add HTT MSG for HTT CREDIT update */ |
| 2999 | HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf, |
| 3000 | HTT_T2H_MSG_TYPE_RX_PN_IND = 0x10, |
| 3001 | HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11, |
| 3002 | HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12, |
| 3003 | /* 0x13 is reserved for RX_RING_LOW_IND (RX Full reordering related) */ |
| 3004 | HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14, |
| 3005 | HTT_T2H_MSG_TYPE_CHAN_CHANGE = 0x15, |
| 3006 | HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16, |
| 3007 | HTT_T2H_MSG_TYPE_RATE_REPORT = 0x17, |
| 3008 | HTT_T2H_MSG_TYPE_FLOW_POOL_MAP = 0x18, |
| 3009 | HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP = 0x19, |
| 3010 | |
| 3011 | HTT_T2H_MSG_TYPE_TEST, |
| 3012 | /* keep this last */ |
| 3013 | HTT_T2H_NUM_MSGS |
| 3014 | }; |
| 3015 | |
| 3016 | /* |
| 3017 | * HTT target to host message type - |
| 3018 | * stored in bits 7:0 of the first word of the message |
| 3019 | */ |
| 3020 | #define HTT_T2H_MSG_TYPE_M 0xff |
| 3021 | #define HTT_T2H_MSG_TYPE_S 0 |
| 3022 | |
| 3023 | #define HTT_T2H_MSG_TYPE_SET(word, msg_type) \ |
| 3024 | do { \ |
| 3025 | HTT_CHECK_SET_VAL(HTT_T2H_MSG_TYPE, msg_type); \ |
| 3026 | (word) |= ((msg_type) << HTT_T2H_MSG_TYPE_S); \ |
| 3027 | } while (0) |
| 3028 | #define HTT_T2H_MSG_TYPE_GET(word) \ |
| 3029 | (((word) & HTT_T2H_MSG_TYPE_M) >> HTT_T2H_MSG_TYPE_S) |
| 3030 | |
| 3031 | /** |
| 3032 | * @brief target -> host version number confirmation message definition |
| 3033 | * |
| 3034 | * |31 24|23 16|15 8|7 0| |
| 3035 | * |----------------+----------------+----------------+----------------| |
| 3036 | * | reserved | major number | minor number | msg type | |
| 3037 | * |-------------------------------------------------------------------| |
| 3038 | * : option request TLV (optional) | |
| 3039 | * :...................................................................: |
| 3040 | * |
| 3041 | * The VER_CONF message may consist of a single 4-byte word, or may be |
| 3042 | * extended with TLVs that specify HTT options selected by the target. |
| 3043 | * The following option TLVs may be appended to the VER_CONF message: |
| 3044 | * - LL_BUS_ADDR_SIZE |
| 3045 | * - HL_SUPPRESS_TX_COMPL_IND |
| 3046 | * - MAX_TX_QUEUE_GROUPS |
| 3047 | * These TLVs may appear in an arbitrary order. Any number of these TLVs |
| 3048 | * may be appended to the VER_CONF message (but only one TLV of each type). |
| 3049 | * |
| 3050 | * Header fields: |
| 3051 | * - MSG_TYPE |
| 3052 | * Bits 7:0 |
| 3053 | * Purpose: identifies this as a version number confirmation message |
| 3054 | * Value: 0x0 |
| 3055 | * - VER_MINOR |
| 3056 | * Bits 15:8 |
| 3057 | * Purpose: Specify the minor number of the HTT message library version |
| 3058 | * in use by the target firmware. |
| 3059 | * The minor number specifies the specific revision within a range |
| 3060 | * of fundamentally compatible HTT message definition revisions. |
| 3061 | * Compatible revisions involve adding new messages or perhaps |
| 3062 | * adding new fields to existing messages, in a backwards-compatible |
| 3063 | * manner. |
| 3064 | * Incompatible revisions involve changing the message type values, |
| 3065 | * or redefining existing messages. |
| 3066 | * Value: minor number |
| 3067 | * - VER_MAJOR |
| 3068 | * Bits 15:8 |
| 3069 | * Purpose: Specify the major number of the HTT message library version |
| 3070 | * in use by the target firmware. |
| 3071 | * The major number specifies the family of minor revisions that are |
| 3072 | * fundamentally compatible with each other, but not with prior or |
| 3073 | * later families. |
| 3074 | * Value: major number |
| 3075 | */ |
| 3076 | |
| 3077 | #define HTT_VER_CONF_MINOR_M 0x0000ff00 |
| 3078 | #define HTT_VER_CONF_MINOR_S 8 |
| 3079 | #define HTT_VER_CONF_MAJOR_M 0x00ff0000 |
| 3080 | #define HTT_VER_CONF_MAJOR_S 16 |
| 3081 | |
| 3082 | |
| 3083 | #define HTT_VER_CONF_MINOR_SET(word, value) \ |
| 3084 | do { \ |
| 3085 | HTT_CHECK_SET_VAL(HTT_VER_CONF_MINOR, value); \ |
| 3086 | (word) |= (value) << HTT_VER_CONF_MINOR_S; \ |
| 3087 | } while (0) |
| 3088 | #define HTT_VER_CONF_MINOR_GET(word) \ |
| 3089 | (((word) & HTT_VER_CONF_MINOR_M) >> HTT_VER_CONF_MINOR_S) |
| 3090 | |
| 3091 | #define HTT_VER_CONF_MAJOR_SET(word, value) \ |
| 3092 | do { \ |
| 3093 | HTT_CHECK_SET_VAL(HTT_VER_CONF_MAJOR, value); \ |
| 3094 | (word) |= (value) << HTT_VER_CONF_MAJOR_S; \ |
| 3095 | } while (0) |
| 3096 | #define HTT_VER_CONF_MAJOR_GET(word) \ |
| 3097 | (((word) & HTT_VER_CONF_MAJOR_M) >> HTT_VER_CONF_MAJOR_S) |
| 3098 | |
| 3099 | |
| 3100 | #define HTT_VER_CONF_BYTES 4 |
| 3101 | |
| 3102 | |
| 3103 | /** |
| 3104 | * @brief - target -> host HTT Rx In order indication message |
| 3105 | * |
| 3106 | * @details |
| 3107 | * |
| 3108 | * |31 24|23 |15|14|13|12|11|10|9|8|7|6|5|4 0| |
| 3109 | * |----------------+-------------------+---------------------+---------------| |
| 3110 | * | peer ID | | F| O| ext TID | msg type | |
| 3111 | * |--------------------------------------------------------------------------| |
| 3112 | * | MSDU count | Reserved | vdev id | |
| 3113 | * |--------------------------------------------------------------------------| |
| 3114 | * | MSDU 0 bus address (bits 31:0) | |
| 3115 | #if HTT_PADDR64 |
| 3116 | * | MSDU 0 bus address (bits 63:32) | |
| 3117 | #endif |
| 3118 | * |--------------------------------------------------------------------------| |
| 3119 | * | MSDU info | MSDU 0 FW Desc | MSDU 0 Length | |
| 3120 | * |--------------------------------------------------------------------------| |
| 3121 | * | MSDU 1 bus address (bits 31:0) | |
| 3122 | #if HTT_PADDR64 |
| 3123 | * | MSDU 1 bus address (bits 63:32) | |
| 3124 | #endif |
| 3125 | * |--------------------------------------------------------------------------| |
| 3126 | * | MSDU info | MSDU 1 FW Desc | MSDU 1 Length | |
| 3127 | * |--------------------------------------------------------------------------| |
| 3128 | */ |
| 3129 | |
| 3130 | |
| 3131 | /** @brief - MSDU info byte for TCP_CHECKSUM_OFFLOAD use |
| 3132 | * |
| 3133 | * @details |
| 3134 | * bits |
| 3135 | * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| 3136 | * |-----+----+-------+--------+--------+---------+---------+-----------| |
| 3137 | * | reserved | is IP | is UDP | is TCP | is IPv6 |IP chksum| TCP/UDP | |
| 3138 | * | | frag | | | | fail |chksum fail| |
| 3139 | * |-----+----+-------+--------+--------+---------+---------+-----------| |
| 3140 | * (see fw_rx_msdu_info def in wal_rx_desc.h) |
| 3141 | */ |
| 3142 | |
| 3143 | struct htt_rx_in_ord_paddr_ind_hdr_t { |
| 3144 | A_UINT32 /* word 0 */ |
| 3145 | msg_type:8, |
| 3146 | ext_tid:5, |
| 3147 | offload:1, |
| 3148 | frag:1, |
| 3149 | reserved_0:1, |
| 3150 | peer_id:16; |
| 3151 | |
| 3152 | A_UINT32 /* word 1 */ |
| 3153 | vap_id:8, |
| 3154 | reserved_1:8, |
| 3155 | msdu_cnt:16; |
| 3156 | }; |
| 3157 | |
| 3158 | struct htt_rx_in_ord_paddr_ind_msdu32_t { |
| 3159 | A_UINT32 dma_addr; |
| 3160 | A_UINT32 |
| 3161 | length:16, |
| 3162 | fw_desc:8, |
| 3163 | msdu_info:8; |
| 3164 | }; |
| 3165 | struct htt_rx_in_ord_paddr_ind_msdu64_t { |
| 3166 | A_UINT32 dma_addr_lo; |
| 3167 | A_UINT32 dma_addr_hi; |
| 3168 | A_UINT32 |
| 3169 | length:16, |
| 3170 | fw_desc:8, |
| 3171 | msdu_info:8; |
| 3172 | }; |
| 3173 | #if HTT_PADDR64 |
| 3174 | #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu64_t |
| 3175 | #else |
| 3176 | #define htt_rx_in_ord_paddr_ind_msdu_t htt_rx_in_ord_paddr_ind_msdu32_t |
| 3177 | #endif |
| 3178 | |
| 3179 | |
| 3180 | #define HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES \ |
| 3181 | (sizeof(struct htt_rx_in_ord_paddr_ind_hdr_t)) |
| 3182 | #define HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS \ |
| 3183 | (HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES >> 2) |
| 3184 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTE_OFFSET \ |
| 3185 | HTT_RX_IN_ORD_PADDR_IND_HDR_BYTES |
| 3186 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORD_OFFSET \ |
| 3187 | HTT_RX_IN_ORD_PADDR_IND_HDR_DWORDS |
| 3188 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 \ |
| 3189 | (sizeof(struct htt_rx_in_ord_paddr_ind_msdu64_t)) |
| 3190 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_64 \ |
| 3191 | (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_64 >> 2) |
| 3192 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 \ |
| 3193 | (sizeof(struct htt_rx_in_ord_paddr_ind_msdu32_t)) |
| 3194 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS_32 \ |
| 3195 | (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES_32 >> 2) |
| 3196 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES \ |
| 3197 | (sizeof(struct htt_rx_in_ord_paddr_ind_msdu_t)) |
| 3198 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_DWORDS \ |
| 3199 | (HTT_RX_IN_ORD_PADDR_IND_MSDU_BYTES >> 2) |
| 3200 | |
| 3201 | #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M 0x00001f00 |
| 3202 | #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S 8 |
| 3203 | #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M 0x00002000 |
| 3204 | #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S 13 |
| 3205 | #define HTT_RX_IN_ORD_PADDR_IND_FRAG_M 0x00004000 |
| 3206 | #define HTT_RX_IN_ORD_PADDR_IND_FRAG_S 14 |
| 3207 | #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M 0xffff0000 |
| 3208 | #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16 |
| 3209 | #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff |
| 3210 | #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0 |
| 3211 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000 |
| 3212 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16 |
| 3213 | /* for systems using 64-bit format for bus addresses */ |
| 3214 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M 0xffffffff |
| 3215 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S 0 |
| 3216 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M 0xffffffff |
| 3217 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S 0 |
| 3218 | /* for systems using 32-bit format for bus addresses */ |
| 3219 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_M 0xffffffff |
| 3220 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_S 0 |
| 3221 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M 0x0000ffff |
| 3222 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S 0 |
| 3223 | #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M 0x00ff0000 |
| 3224 | #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S 16 |
| 3225 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M 0xff000000 |
| 3226 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S 24 |
| 3227 | |
| 3228 | |
| 3229 | #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_SET(word, value) \ |
| 3230 | do { \ |
| 3231 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_EXT_TID, value); \ |
| 3232 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S; \ |
| 3233 | } while (0) |
| 3234 | #define HTT_RX_IN_ORD_PADDR_IND_EXT_TID_GET(word) \ |
| 3235 | (((word) & HTT_RX_IN_ORD_PADDR_IND_EXT_TID_M) >> \ |
| 3236 | HTT_RX_IN_ORD_PADDR_IND_EXT_TID_S) |
| 3237 | |
| 3238 | #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_SET(word, value) \ |
| 3239 | do { \ |
| 3240 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PEER_ID, value); \ |
| 3241 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S; \ |
| 3242 | } while (0) |
| 3243 | #define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_GET(word) \ |
| 3244 | (((word) & HTT_RX_IN_ORD_PADDR_IND_PEER_ID_M) >> \ |
| 3245 | HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S) |
| 3246 | |
| 3247 | #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_SET(word, value) \ |
| 3248 | do { \ |
| 3249 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_VAP_ID, value); \ |
| 3250 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S; \ |
| 3251 | } while (0) |
| 3252 | #define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \ |
| 3253 | (((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> \ |
| 3254 | HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S) |
| 3255 | |
| 3256 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \ |
| 3257 | do { \ |
| 3258 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \ |
| 3259 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S; \ |
| 3260 | } while (0) |
| 3261 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_GET(word) \ |
| 3262 | (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M) >> \ |
| 3263 | HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S) |
| 3264 | |
| 3265 | /* for systems using 64-bit format for bus addresses */ |
| 3266 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_SET(word, value) \ |
| 3267 | do { \ |
| 3268 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_HI, value); \ |
| 3269 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S; \ |
| 3270 | } while (0) |
| 3271 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_GET(word) \ |
| 3272 | (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_M) >> \ |
| 3273 | HTT_RX_IN_ORD_PADDR_IND_PADDR_HI_S) |
| 3274 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_SET(word, value) \ |
| 3275 | do { \ |
| 3276 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR_LO, value); \ |
| 3277 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S; \ |
| 3278 | } while (0) |
| 3279 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_GET(word) \ |
| 3280 | (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_M) >> \ |
| 3281 | HTT_RX_IN_ORD_PADDR_IND_PADDR_LO_S) |
| 3282 | |
| 3283 | /* for systems using 32-bit format for bus addresses */ |
| 3284 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_SET(word, value) \ |
| 3285 | do { \ |
| 3286 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PADDR, value); \ |
| 3287 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PADDR_S; \ |
| 3288 | } while (0) |
| 3289 | #define HTT_RX_IN_ORD_PADDR_IND_PADDR_GET(word) \ |
| 3290 | (((word) & HTT_RX_IN_ORD_PADDR_IND_PADDR_M) >> \ |
| 3291 | HTT_RX_IN_ORD_PADDR_IND_PADDR_S) |
| 3292 | |
| 3293 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_SET(word, value) \ |
| 3294 | do { \ |
| 3295 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN, value);\ |
| 3296 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S; \ |
| 3297 | } while (0) |
| 3298 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_GET(word) \ |
| 3299 | (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_M) >> \ |
| 3300 | HTT_RX_IN_ORD_PADDR_IND_MSDU_LEN_S) |
| 3301 | |
| 3302 | #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_SET(word, value) \ |
| 3303 | do { \ |
| 3304 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_FW_DESC, value); \ |
| 3305 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S; \ |
| 3306 | } while (0) |
| 3307 | #define HTT_RX_IN_ORD_PADDR_IND_FW_DESC_GET(word) \ |
| 3308 | (((word) & HTT_RX_IN_ORD_PADDR_IND_FW_DESC_M) >> \ |
| 3309 | HTT_RX_IN_ORD_PADDR_IND_FW_DESC_S) |
| 3310 | |
| 3311 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_SET(word, value) \ |
| 3312 | do { \ |
| 3313 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO, value);\ |
| 3314 | (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S;\ |
| 3315 | } while (0) |
| 3316 | #define HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_GET(word) \ |
| 3317 | (((word) & HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_M) >> \ |
| 3318 | HTT_RX_IN_ORD_PADDR_IND_MSDU_INFO_S) |
| 3319 | |
| 3320 | #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_SET(word, value) \ |
| 3321 | do { \ |
| 3322 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_OFFLOAD, value);\ |
| 3323 | (word) |= (value) << HTT_RX_IN_ORD_IND_OFFLOAD_S; \ |
| 3324 | } while (0) |
| 3325 | #define HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_GET(word) \ |
| 3326 | (((word) & HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_M) >> \ |
| 3327 | HTT_RX_IN_ORD_PADDR_IND_OFFLOAD_S) |
| 3328 | |
| 3329 | #define HTT_RX_IN_ORD_PADDR_IND_FRAG_SET(word, value) \ |
| 3330 | do { \ |
| 3331 | HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_IND_FRAG, value); \ |
| 3332 | (word) |= (value) << HTT_RX_IN_ORD_IND_FRAG_S; \ |
| 3333 | } while (0) |
| 3334 | #define HTT_RX_IN_ORD_PADDR_IND_FRAG_GET(word) \ |
| 3335 | (((word) & HTT_RX_IN_ORD_PADDR_IND_FRAG_M) >> \ |
| 3336 | HTT_RX_IN_ORD_PADDR_IND_FRAG_S) |
| 3337 | |
| 3338 | /* definitions used within target -> host rx indication message */ |
| 3339 | |
| 3340 | PREPACK struct htt_rx_ind_hdr_prefix_t { |
| 3341 | A_UINT32 /* word 0 */ |
| 3342 | msg_type:8, |
| 3343 | ext_tid:5, |
| 3344 | release_valid:1, |
| 3345 | flush_valid:1, |
| 3346 | reserved0:1, |
| 3347 | peer_id:16; |
| 3348 | |
| 3349 | A_UINT32 /* word 1 */ |
| 3350 | flush_start_seq_num:6, |
| 3351 | flush_end_seq_num:6, |
| 3352 | release_start_seq_num:6, |
| 3353 | release_end_seq_num:6, |
| 3354 | num_mpdu_ranges:8; |
| 3355 | } POSTPACK; |
| 3356 | |
| 3357 | #define HTT_RX_IND_HDR_PREFIX_BYTES (sizeof(struct htt_rx_ind_hdr_prefix_t)) |
| 3358 | #define HTT_RX_IND_HDR_PREFIX_SIZE32 (HTT_RX_IND_HDR_PREFIX_BYTES >> 2) |
| 3359 | |
| 3360 | #define HTT_TGT_RSSI_INVALID 0x80 |
| 3361 | |
| 3362 | PREPACK struct htt_rx_ppdu_desc_t { |
| 3363 | #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI_CMB 0 |
| 3364 | #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_SUBMICROSEC 0 |
| 3365 | #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR_CODE 0 |
| 3366 | #define HTT_RX_IND_PPDU_OFFSET_WORD_PHY_ERR 0 |
| 3367 | #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE 0 |
| 3368 | #define HTT_RX_IND_PPDU_OFFSET_WORD_LEGACY_RATE_SEL 0 |
| 3369 | #define HTT_RX_IND_PPDU_OFFSET_WORD_END_VALID 0 |
| 3370 | #define HTT_RX_IND_PPDU_OFFSET_WORD_START_VALID 0 |
| 3371 | A_UINT32 /* word 0 */ |
| 3372 | rssi_cmb:8, |
| 3373 | timestamp_submicrosec:8, |
| 3374 | phy_err_code:8, |
| 3375 | phy_err:1, |
| 3376 | legacy_rate:4, |
| 3377 | legacy_rate_sel:1, |
| 3378 | end_valid:1, |
| 3379 | start_valid:1; |
| 3380 | |
| 3381 | #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI0 1 |
| 3382 | union { |
| 3383 | A_UINT32 /* word 1 */ |
| 3384 | rssi0_pri20:8, |
| 3385 | rssi0_ext20:8, |
| 3386 | rssi0_ext40:8, |
| 3387 | rssi0_ext80:8; |
| 3388 | A_UINT32 rssi0; /* access all 20/40/80 per-b/w RSSIs together */ |
| 3389 | } u0; |
| 3390 | |
| 3391 | #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI1 2 |
| 3392 | union { |
| 3393 | A_UINT32 /* word 2 */ |
| 3394 | rssi1_pri20:8, |
| 3395 | rssi1_ext20:8, |
| 3396 | rssi1_ext40:8, |
| 3397 | rssi1_ext80:8; |
| 3398 | A_UINT32 rssi1; /* access all 20/40/80 per-b/w RSSIs together */ |
| 3399 | } u1; |
| 3400 | |
| 3401 | #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI2 3 |
| 3402 | union { |
| 3403 | A_UINT32 /* word 3 */ |
| 3404 | rssi2_pri20:8, |
| 3405 | rssi2_ext20:8, |
| 3406 | rssi2_ext40:8, |
| 3407 | rssi2_ext80:8; |
| 3408 | A_UINT32 rssi2; /* access all 20/40/80 per-b/w RSSIs together */ |
| 3409 | } u2; |
| 3410 | |
| 3411 | #define HTT_RX_IND_PPDU_OFFSET_WORD_RSSI3 4 |
| 3412 | union { |
| 3413 | A_UINT32 /* word 4 */ |
| 3414 | rssi3_pri20:8, |
| 3415 | rssi3_ext20:8, |
| 3416 | rssi3_ext40:8, |
| 3417 | rssi3_ext80:8; |
| 3418 | A_UINT32 rssi3; /* access all 20/40/80 per-b/w RSSIs together */ |
| 3419 | } u3; |
| 3420 | |
| 3421 | #define HTT_RX_IND_PPDU_OFFSET_WORD_TSF32 5 |
| 3422 | A_UINT32 tsf32; /* word 5 */ |
| 3423 | |
| 3424 | #define HTT_RX_IND_PPDU_OFFSET_WORD_TIMESTAMP_MICROSEC 6 |
| 3425 | A_UINT32 timestamp_microsec; /* word 6 */ |
| 3426 | |
| 3427 | #define HTT_RX_IND_PPDU_OFFSET_WORD_PREAMBLE_TYPE 7 |
| 3428 | #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A1 7 |
| 3429 | A_UINT32 /* word 7 */ |
| 3430 | vht_sig_a1:24, |
| 3431 | preamble_type:8; |
| 3432 | |
| 3433 | #define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8 |
| 3434 | A_UINT32 /* word 8 */ |
| 3435 | vht_sig_a2:24, |
| 3436 | reserved0:8; |
| 3437 | } POSTPACK; |
| 3438 | |
| 3439 | #define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t)) |
| 3440 | #define HTT_RX_PPDU_DESC_SIZE32 (HTT_RX_PPDU_DESC_BYTES >> 2) |
| 3441 | |
| 3442 | PREPACK struct htt_rx_ind_hdr_suffix_t { |
| 3443 | A_UINT32 /* word 0 */ |
| 3444 | fw_rx_desc_bytes:16, |
| 3445 | reserved0:16; |
| 3446 | } POSTPACK; |
| 3447 | |
| 3448 | #define HTT_RX_IND_HDR_SUFFIX_BYTES (sizeof(struct htt_rx_ind_hdr_suffix_t)) |
| 3449 | #define HTT_RX_IND_HDR_SUFFIX_SIZE32 (HTT_RX_IND_HDR_SUFFIX_BYTES >> 2) |
| 3450 | |
| 3451 | PREPACK struct htt_rx_ind_hdr_t { |
| 3452 | struct htt_rx_ind_hdr_prefix_t prefix; |
| 3453 | struct htt_rx_ppdu_desc_t rx_ppdu_desc; |
| 3454 | struct htt_rx_ind_hdr_suffix_t suffix; |
| 3455 | } POSTPACK; |
| 3456 | |
| 3457 | #define HTT_RX_IND_HDR_BYTES (sizeof(struct htt_rx_ind_hdr_t)) |
| 3458 | #define HTT_RX_IND_HDR_SIZE32 (HTT_RX_IND_HDR_BYTES >> 2) |
| 3459 | |
| 3460 | /* confirm that HTT_RX_IND_HDR_BYTES is a multiple of 4 */ |
| 3461 | A_COMPILE_TIME_ASSERT(HTT_RX_IND_hdr_size_quantum, |
| 3462 | (HTT_RX_IND_HDR_BYTES & 0x3) == 0); |
| 3463 | |
| 3464 | /* |
| 3465 | * HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET: |
| 3466 | * the offset into the HTT rx indication message at which the |
| 3467 | * FW rx PPDU descriptor resides |
| 3468 | */ |
| 3469 | #define HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET HTT_RX_IND_HDR_PREFIX_BYTES |
| 3470 | |
| 3471 | /* |
| 3472 | * HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET: |
| 3473 | * the offset into the HTT rx indication message at which the |
| 3474 | * header suffix (FW rx MSDU byte count) resides |
| 3475 | */ |
| 3476 | #define HTT_RX_IND_HDR_SUFFIX_BYTE_OFFSET \ |
| 3477 | (HTT_RX_IND_FW_RX_PPDU_DESC_BYTE_OFFSET + HTT_RX_PPDU_DESC_BYTES) |
| 3478 | |
| 3479 | /* |
| 3480 | * HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET: |
| 3481 | * the offset into the HTT rx indication message at which the per-MSDU |
| 3482 | * information starts |
| 3483 | * Bytes 0-7 are the message header; bytes 8-11 contain the length of the |
| 3484 | * per-MSDU information portion of the message. The per-MSDU info itself |
| 3485 | * starts at byte 12. |
| 3486 | */ |
| 3487 | #define HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET HTT_RX_IND_HDR_BYTES |
| 3488 | |
| 3489 | |
| 3490 | /** |
| 3491 | * @brief target -> host rx indication message definition |
| 3492 | * |
| 3493 | * @details |
| 3494 | * The following field definitions describe the format of the rx indication |
| 3495 | * message sent from the target to the host. |
| 3496 | * The message consists of three major sections: |
| 3497 | * 1. a fixed-length header |
| 3498 | * 2. a variable-length list of firmware rx MSDU descriptors |
| 3499 | * 3. one or more 4-octet MPDU range information elements |
| 3500 | * The fixed length header itself has two sub-sections |
| 3501 | * 1. the message meta-information, including identification of the |
| 3502 | * sender and type of the received data, and a 4-octet flush/release IE |
| 3503 | * 2. the firmware rx PPDU descriptor |
| 3504 | * |
| 3505 | * The format of the message is depicted below. |
| 3506 | * in this depiction, the following abbreviations are used for information |
| 3507 | * elements within the message: |
| 3508 | * - SV - start valid: this flag is set if the FW rx PPDU descriptor |
| 3509 | * elements associated with the PPDU start are valid. |
| 3510 | * Specifically, the following fields are valid only if SV is set: |
| 3511 | * RSSI (all variants), L, legacy rate, preamble type, service, |
| 3512 | * VHT-SIG-A |
| 3513 | * - EV - end valid: this flag is set if the FW rx PPDU descriptor |
| 3514 | * elements associated with the PPDU end are valid. |
| 3515 | * Specifically, the following fields are valid only if EV is set: |
| 3516 | * P, PHY err code, TSF, microsec / sub-microsec timestamp |
| 3517 | * - L - Legacy rate selector - if legacy rates are used, this flag |
| 3518 | * indicates whether the rate is from a CCK (L == 1) or OFDM |
| 3519 | * (L == 0) PHY. |
| 3520 | * - P - PHY error flag - boolean indication of whether the rx frame had |
| 3521 | * a PHY error |
| 3522 | * |
| 3523 | * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| |
| 3524 | * |----------------+-------------------+---------------------+---------------| |
| 3525 | * | peer ID | |RV|FV| ext TID | msg type | |
| 3526 | * |--------------------------------------------------------------------------| |
| 3527 | * | num | release | release | flush | flush | |
| 3528 | * | MPDU | end | start | end | start | |
| 3529 | * | ranges | seq num | seq num | seq num | seq num | |
| 3530 | * |==========================================================================| |
| 3531 | * |S|E|L| legacy |P| PHY err code | sub-microsec | combined | |
| 3532 | * |V|V| | rate | | | timestamp | RSSI | |
| 3533 | * |--------------------------------------------------------------------------| |
| 3534 | * | RSSI rx0 ext80 | RSSI rx0 ext40 | RSSI rx0 ext20 | RSSI rx0 pri20| |
| 3535 | * |--------------------------------------------------------------------------| |
| 3536 | * | RSSI rx1 ext80 | RSSI rx1 ext40 | RSSI rx1 ext20 | RSSI rx1 pri20| |
| 3537 | * |--------------------------------------------------------------------------| |
| 3538 | * | RSSI rx2 ext80 | RSSI rx2 ext40 | RSSI rx2 ext20 | RSSI rx2 pri20| |
| 3539 | * |--------------------------------------------------------------------------| |
| 3540 | * | RSSI rx3 ext80 | RSSI rx3 ext40 | RSSI rx3 ext20 | RSSI rx3 pri20| |
| 3541 | * |--------------------------------------------------------------------------| |
| 3542 | * | TSF LSBs | |
| 3543 | * |--------------------------------------------------------------------------| |
| 3544 | * | microsec timestamp | |
| 3545 | * |--------------------------------------------------------------------------| |
| 3546 | * | preamble type | HT-SIG / VHT-SIG-A1 | |
| 3547 | * |--------------------------------------------------------------------------| |
| 3548 | * | service | HT-SIG / VHT-SIG-A2 | |
| 3549 | * |==========================================================================| |
| 3550 | * | reserved | FW rx desc bytes | |
| 3551 | * |--------------------------------------------------------------------------| |
| 3552 | * | MSDU Rx | MSDU Rx | MSDU Rx | MSDU Rx | |
| 3553 | * | desc B3 | desc B2 | desc B1 | desc B0 | |
| 3554 | * |--------------------------------------------------------------------------| |
| 3555 | * : : : |
| 3556 | * |--------------------------------------------------------------------------| |
| 3557 | * | alignment | MSDU Rx | |
| 3558 | * | padding | desc Bn | |
| 3559 | * |--------------------------------------------------------------------------| |
| 3560 | * | reserved | MPDU range status | MPDU count | |
| 3561 | * |--------------------------------------------------------------------------| |
| 3562 | * : reserved : MPDU range status : MPDU count : |
| 3563 | * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - : |
| 3564 | * |
| 3565 | * Header fields: |
| 3566 | * - MSG_TYPE |
| 3567 | * Bits 7:0 |
| 3568 | * Purpose: identifies this as an rx indication message |
| 3569 | * Value: 0x1 |
| 3570 | * - EXT_TID |
| 3571 | * Bits 12:8 |
| 3572 | * Purpose: identify the traffic ID of the rx data, including |
| 3573 | * special "extended" TID values for multicast, broadcast, and |
| 3574 | * non-QoS data frames |
| 3575 | * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS |
| 3576 | * - FLUSH_VALID (FV) |
| 3577 | * Bit 13 |
| 3578 | * Purpose: indicate whether the flush IE (start/end sequence numbers) |
| 3579 | * is valid |
| 3580 | * Value: |
| 3581 | * 1 -> flush IE is valid and needs to be processed |
| 3582 | * 0 -> flush IE is not valid and should be ignored |
| 3583 | * - REL_VALID (RV) |
| 3584 | * Bit 13 |
| 3585 | * Purpose: indicate whether the release IE (start/end sequence numbers) |
| 3586 | * is valid |
| 3587 | * Value: |
| 3588 | * 1 -> release IE is valid and needs to be processed |
| 3589 | * 0 -> release IE is not valid and should be ignored |
| 3590 | * - PEER_ID |
| 3591 | * Bits 31:16 |
| 3592 | * Purpose: Identify, by ID, which peer sent the rx data |
| 3593 | * Value: ID of the peer who sent the rx data |
| 3594 | * - FLUSH_SEQ_NUM_START |
| 3595 | * Bits 5:0 |
| 3596 | * Purpose: Indicate the start of a series of MPDUs to flush |
| 3597 | * Not all MPDUs within this series are necessarily valid - the host |
| 3598 | * must check each sequence number within this range to see if the |
| 3599 | * corresponding MPDU is actually present. |
| 3600 | * This field is only valid if the FV bit is set. |
| 3601 | * Value: |
| 3602 | * The sequence number for the first MPDUs to check to flush. |
| 3603 | * The sequence number is masked by 0x3f. |
| 3604 | * - FLUSH_SEQ_NUM_END |
| 3605 | * Bits 11:6 |
| 3606 | * Purpose: Indicate the end of a series of MPDUs to flush |
| 3607 | * Value: |
| 3608 | * The sequence number one larger than the sequence number of the |
| 3609 | * last MPDU to check to flush. |
| 3610 | * The sequence number is masked by 0x3f. |
| 3611 | * Not all MPDUs within this series are necessarily valid - the host |
| 3612 | * must check each sequence number within this range to see if the |
| 3613 | * corresponding MPDU is actually present. |
| 3614 | * This field is only valid if the FV bit is set. |
| 3615 | * - REL_SEQ_NUM_START |
| 3616 | * Bits 17:12 |
| 3617 | * Purpose: Indicate the start of a series of MPDUs to release. |
| 3618 | * All MPDUs within this series are present and valid - the host |
| 3619 | * need not check each sequence number within this range to see if |
| 3620 | * the corresponding MPDU is actually present. |
| 3621 | * This field is only valid if the RV bit is set. |
| 3622 | * Value: |
| 3623 | * The sequence number for the first MPDUs to check to release. |
| 3624 | * The sequence number is masked by 0x3f. |
| 3625 | * - REL_SEQ_NUM_END |
| 3626 | * Bits 23:18 |
| 3627 | * Purpose: Indicate the end of a series of MPDUs to release. |
| 3628 | * Value: |
| 3629 | * The sequence number one larger than the sequence number of the |
| 3630 | * last MPDU to check to release. |
| 3631 | * The sequence number is masked by 0x3f. |
| 3632 | * All MPDUs within this series are present and valid - the host |
| 3633 | * need not check each sequence number within this range to see if |
| 3634 | * the corresponding MPDU is actually present. |
| 3635 | * This field is only valid if the RV bit is set. |
| 3636 | * - NUM_MPDU_RANGES |
| 3637 | * Bits 31:24 |
| 3638 | * Purpose: Indicate how many ranges of MPDUs are present. |
| 3639 | * Each MPDU range consists of a series of contiguous MPDUs within the |
| 3640 | * rx frame sequence which all have the same MPDU status. |
| 3641 | * Value: 1-63 (typically a small number, like 1-3) |
| 3642 | * |
| 3643 | * Rx PPDU descriptor fields: |
| 3644 | * - RSSI_CMB |
| 3645 | * Bits 7:0 |
| 3646 | * Purpose: Combined RSSI from all active rx chains, across the active |
| 3647 | * bandwidth. |
| 3648 | * Value: RSSI dB units w.r.t. noise floor |
| 3649 | * - TIMESTAMP_SUBMICROSEC |
| 3650 | * Bits 15:8 |
| 3651 | * Purpose: high-resolution timestamp |
| 3652 | * Value: |
| 3653 | * Sub-microsecond time of PPDU reception. |
| 3654 | * This timestamp ranges from [0,MAC clock MHz). |
| 3655 | * This timestamp can be used in conjunction with TIMESTAMP_MICROSEC |
| 3656 | * to form a high-resolution, large range rx timestamp. |
| 3657 | * - PHY_ERR_CODE |
| 3658 | * Bits 23:16 |
| 3659 | * Purpose: |
| 3660 | * If the rx frame processing resulted in a PHY error, indicate what |
| 3661 | * type of rx PHY error occurred. |
| 3662 | * Value: |
| 3663 | * This field is valid if the "P" (PHY_ERR) flag is set. |
| 3664 | * TBD: document/specify the values for this field |
| 3665 | * - PHY_ERR |
| 3666 | * Bit 24 |
| 3667 | * Purpose: indicate whether the rx PPDU had a PHY error |
| 3668 | * Value: 0 -> no rx PHY error, 1 -> rx PHY error encountered |
| 3669 | * - LEGACY_RATE |
| 3670 | * Bits 28:25 |
| 3671 | * Purpose: |
| 3672 | * If the rx frame used a legacy rate rather than a HT or VHT rate, |
| 3673 | * specify which rate was used. |
| 3674 | * Value: |
| 3675 | * The LEGACY_RATE field's value depends on the "L" (LEGACY_RATE_SEL) |
| 3676 | * flag. |
| 3677 | * If LEGACY_RATE_SEL is 0: |
| 3678 | * 0x8: OFDM 48 Mbps |
| 3679 | * 0x9: OFDM 24 Mbps |
| 3680 | * 0xA: OFDM 12 Mbps |
| 3681 | * 0xB: OFDM 6 Mbps |
| 3682 | * 0xC: OFDM 54 Mbps |
| 3683 | * 0xD: OFDM 36 Mbps |
| 3684 | * 0xE: OFDM 18 Mbps |
| 3685 | * 0xF: OFDM 9 Mbps |
| 3686 | * If LEGACY_RATE_SEL is 1: |
| 3687 | * 0x8: CCK 11 Mbps long preamble |
| 3688 | * 0x9: CCK 5.5 Mbps long preamble |
| 3689 | * 0xA: CCK 2 Mbps long preamble |
| 3690 | * 0xB: CCK 1 Mbps long preamble |
| 3691 | * 0xC: CCK 11 Mbps short preamble |
| 3692 | * 0xD: CCK 5.5 Mbps short preamble |
| 3693 | * 0xE: CCK 2 Mbps short preamble |
| 3694 | * - LEGACY_RATE_SEL |
| 3695 | * Bit 29 |
| 3696 | * Purpose: if rx used a legacy rate, specify whether it was OFDM or CCK |
| 3697 | * Value: |
| 3698 | * This field is valid if the PREAMBLE_TYPE field indicates the rx |
| 3699 | * used a legacy rate. |
| 3700 | * 0 -> OFDM, 1 -> CCK |
| 3701 | * - END_VALID |
| 3702 | * Bit 30 |
| 3703 | * Purpose: Indicate whether the FW rx PPDU desc fields associated with |
| 3704 | * the start of the PPDU are valid. Specifically, the following |
| 3705 | * fields are only valid if END_VALID is set: |
| 3706 | * PHY_ERR, PHY_ERR_CODE, TSF32, TIMESTAMP_MICROSEC, |
| 3707 | * TIMESTAMP_SUBMICROSEC |
| 3708 | * Value: |
| 3709 | * 0 -> rx PPDU desc end fields are not valid |
| 3710 | * 1 -> rx PPDU desc end fields are valid |
| 3711 | * - START_VALID |
| 3712 | * Bit 31 |
| 3713 | * Purpose: Indicate whether the FW rx PPDU desc fields associated with |
| 3714 | * the end of the PPDU are valid. Specifically, the following |
| 3715 | * fields are only valid if START_VALID is set: |
| 3716 | * RSSI, LEGACY_RATE_SEL, LEGACY_RATE, PREAMBLE_TYPE, SERVICE, |
| 3717 | * VHT-SIG-A |
| 3718 | * Value: |
| 3719 | * 0 -> rx PPDU desc start fields are not valid |
| 3720 | * 1 -> rx PPDU desc start fields are valid |
| 3721 | * - RSSI0_PRI20 |
| 3722 | * Bits 7:0 |
| 3723 | * Purpose: RSSI from chain 0 on the primary 20 MHz channel |
| 3724 | * Value: RSSI dB units w.r.t. noise floor |
| 3725 | * |
| 3726 | * - RSSI0_EXT20 |
| 3727 | * Bits 7:0 |
| 3728 | * Purpose: RSSI from chain 0 on the bonded extension 20 MHz channel |
| 3729 | * (if the rx bandwidth was >= 40 MHz) |
| 3730 | * Value: RSSI dB units w.r.t. noise floor |
| 3731 | * - RSSI0_EXT40 |
| 3732 | * Bits 7:0 |
| 3733 | * Purpose: RSSI from chain 0 on the bonded extension 40 MHz channel |
| 3734 | * (if the rx bandwidth was >= 80 MHz) |
| 3735 | * Value: RSSI dB units w.r.t. noise floor |
| 3736 | * - RSSI0_EXT80 |
| 3737 | * Bits 7:0 |
| 3738 | * Purpose: RSSI from chain 0 on the bonded extension 80 MHz channel |
| 3739 | * (if the rx bandwidth was >= 160 MHz) |
| 3740 | * Value: RSSI dB units w.r.t. noise floor |
| 3741 | * |
| 3742 | * - RSSI1_PRI20 |
| 3743 | * Bits 7:0 |
| 3744 | * Purpose: RSSI from chain 1 on the primary 20 MHz channel |
| 3745 | * Value: RSSI dB units w.r.t. noise floor |
| 3746 | * - RSSI1_EXT20 |
| 3747 | * Bits 7:0 |
| 3748 | * Purpose: RSSI from chain 1 on the bonded extension 20 MHz channel |
| 3749 | * (if the rx bandwidth was >= 40 MHz) |
| 3750 | * Value: RSSI dB units w.r.t. noise floor |
| 3751 | * - RSSI1_EXT40 |
| 3752 | * Bits 7:0 |
| 3753 | * Purpose: RSSI from chain 1 on the bonded extension 40 MHz channel |
| 3754 | * (if the rx bandwidth was >= 80 MHz) |
| 3755 | * Value: RSSI dB units w.r.t. noise floor |
| 3756 | * - RSSI1_EXT80 |
| 3757 | * Bits 7:0 |
| 3758 | * Purpose: RSSI from chain 1 on the bonded extension 80 MHz channel |
| 3759 | * (if the rx bandwidth was >= 160 MHz) |
| 3760 | * Value: RSSI dB units w.r.t. noise floor |
| 3761 | * |
| 3762 | * - RSSI2_PRI20 |
| 3763 | * Bits 7:0 |
| 3764 | * Purpose: RSSI from chain 2 on the primary 20 MHz channel |
| 3765 | * Value: RSSI dB units w.r.t. noise floor |
| 3766 | * - RSSI2_EXT20 |
| 3767 | * Bits 7:0 |
| 3768 | * Purpose: RSSI from chain 2 on the bonded extension 20 MHz channel |
| 3769 | * (if the rx bandwidth was >= 40 MHz) |
| 3770 | * Value: RSSI dB units w.r.t. noise floor |
| 3771 | * - RSSI2_EXT40 |
| 3772 | * Bits 7:0 |
| 3773 | * Purpose: RSSI from chain 2 on the bonded extension 40 MHz channel |
| 3774 | * (if the rx bandwidth was >= 80 MHz) |
| 3775 | * Value: RSSI dB units w.r.t. noise floor |
| 3776 | * - RSSI2_EXT80 |
| 3777 | * Bits 7:0 |
| 3778 | * Purpose: RSSI from chain 2 on the bonded extension 80 MHz channel |
| 3779 | * (if the rx bandwidth was >= 160 MHz) |
| 3780 | * Value: RSSI dB units w.r.t. noise floor |
| 3781 | * |
| 3782 | * - RSSI3_PRI20 |
| 3783 | * Bits 7:0 |
| 3784 | * Purpose: RSSI from chain 3 on the primary 20 MHz channel |
| 3785 | * Value: RSSI dB units w.r.t. noise floor |
| 3786 | * - RSSI3_EXT20 |
| 3787 | * Bits 7:0 |
| 3788 | * Purpose: RSSI from chain 3 on the bonded extension 20 MHz channel |
| 3789 | * (if the rx bandwidth was >= 40 MHz) |
| 3790 | * Value: RSSI dB units w.r.t. noise floor |
| 3791 | * - RSSI3_EXT40 |
| 3792 | * Bits 7:0 |
| 3793 | * Purpose: RSSI from chain 3 on the bonded extension 40 MHz channel |
| 3794 | * (if the rx bandwidth was >= 80 MHz) |
| 3795 | * Value: RSSI dB units w.r.t. noise floor |
| 3796 | * - RSSI3_EXT80 |
| 3797 | * Bits 7:0 |
| 3798 | * Purpose: RSSI from chain 3 on the bonded extension 80 MHz channel |
| 3799 | * (if the rx bandwidth was >= 160 MHz) |
| 3800 | * Value: RSSI dB units w.r.t. noise floor |
| 3801 | * |
| 3802 | * - TSF32 |
| 3803 | * Bits 31:0 |
| 3804 | * Purpose: specify the time the rx PPDU was received, in TSF units |
| 3805 | * Value: 32 LSBs of the TSF |
| 3806 | * - TIMESTAMP_MICROSEC |
| 3807 | * Bits 31:0 |
| 3808 | * Purpose: specify the time the rx PPDU was received, in microsecond units |
| 3809 | * Value: PPDU rx time, in microseconds |
| 3810 | * - VHT_SIG_A1 |
| 3811 | * Bits 23:0 |
| 3812 | * Purpose: Provide the HT-SIG (initial 24 bits) or VHT-SIG-A1 field |
| 3813 | * from the rx PPDU |
| 3814 | * Value: |
| 3815 | * If PREAMBLE_TYPE specifies VHT, then this field contains the |
| 3816 | * VHT-SIG-A1 data. |
| 3817 | * If PREAMBLE_TYPE specifies HT, then this field contains the |
| 3818 | * first 24 bits of the HT-SIG data. |
| 3819 | * Otherwise, this field is invalid. |
| 3820 | * Refer to the the 802.11 protocol for the definition of the |
| 3821 | * HT-SIG and VHT-SIG-A1 fields |
| 3822 | * - VHT_SIG_A2 |
| 3823 | * Bits 23:0 |
| 3824 | * Purpose: Provide the HT-SIG (final 24 bits) or VHT-SIG-A2 field |
| 3825 | * from the rx PPDU |
| 3826 | * Value: |
| 3827 | * If PREAMBLE_TYPE specifies VHT, then this field contains the |
| 3828 | * VHT-SIG-A2 data. |
| 3829 | * If PREAMBLE_TYPE specifies HT, then this field contains the |
| 3830 | * last 24 bits of the HT-SIG data. |
| 3831 | * Otherwise, this field is invalid. |
| 3832 | * Refer to the the 802.11 protocol for the definition of the |
| 3833 | * HT-SIG and VHT-SIG-A2 fields |
| 3834 | * - PREAMBLE_TYPE |
| 3835 | * Bits 31:24 |
| 3836 | * Purpose: indicate the PHY format of the received burst |
| 3837 | * Value: |
| 3838 | * 0x4: Legacy (OFDM/CCK) |
| 3839 | * 0x8: HT |
| 3840 | * 0x9: HT with TxBF |
| 3841 | * 0xC: VHT |
| 3842 | * 0xD: VHT with TxBF |
| 3843 | * - SERVICE |
| 3844 | * Bits 31:24 |
| 3845 | * Purpose: TBD |
| 3846 | * Value: TBD |
| 3847 | * |
| 3848 | * Rx MSDU descriptor fields: |
| 3849 | * - FW_RX_DESC_BYTES |
| 3850 | * Bits 15:0 |
| 3851 | * Purpose: Indicate how many bytes in the Rx indication are used for |
| 3852 | * FW Rx descriptors |
| 3853 | * |
| 3854 | * Payload fields: |
| 3855 | * - MPDU_COUNT |
| 3856 | * Bits 7:0 |
| 3857 | * Purpose: Indicate how many sequential MPDUs share the same status. |
| 3858 | * All MPDUs within the indicated list are from the same RA-TA-TID. |
| 3859 | * - MPDU_STATUS |
| 3860 | * Bits 15:8 |
| 3861 | * Purpose: Indicate whether the (group of sequential) MPDU(s) were |
| 3862 | * received successfully. |
| 3863 | * Value: |
| 3864 | * 0x1: success |
| 3865 | * 0x2: FCS error |
| 3866 | * 0x3: duplicate error |
| 3867 | * 0x4: replay error |
| 3868 | * 0x5: invalid peer |
| 3869 | */ |
| 3870 | /* header fields */ |
| 3871 | #define HTT_RX_IND_EXT_TID_M 0x1f00 |
| 3872 | #define HTT_RX_IND_EXT_TID_S 8 |
| 3873 | #define HTT_RX_IND_FLUSH_VALID_M 0x2000 |
| 3874 | #define HTT_RX_IND_FLUSH_VALID_S 13 |
| 3875 | #define HTT_RX_IND_REL_VALID_M 0x4000 |
| 3876 | #define HTT_RX_IND_REL_VALID_S 14 |
| 3877 | #define HTT_RX_IND_PEER_ID_M 0xffff0000 |
| 3878 | #define HTT_RX_IND_PEER_ID_S 16 |
| 3879 | |
| 3880 | #define HTT_RX_IND_FLUSH_SEQ_NUM_START_M 0x3f |
| 3881 | #define HTT_RX_IND_FLUSH_SEQ_NUM_START_S 0 |
| 3882 | #define HTT_RX_IND_FLUSH_SEQ_NUM_END_M 0xfc0 |
| 3883 | #define HTT_RX_IND_FLUSH_SEQ_NUM_END_S 6 |
| 3884 | #define HTT_RX_IND_REL_SEQ_NUM_START_M 0x3f000 |
| 3885 | #define HTT_RX_IND_REL_SEQ_NUM_START_S 12 |
| 3886 | #define HTT_RX_IND_REL_SEQ_NUM_END_M 0xfc0000 |
| 3887 | #define HTT_RX_IND_REL_SEQ_NUM_END_S 18 |
| 3888 | #define HTT_RX_IND_NUM_MPDU_RANGES_M 0xff000000 |
| 3889 | #define HTT_RX_IND_NUM_MPDU_RANGES_S 24 |
| 3890 | |
| 3891 | /* rx PPDU descriptor fields */ |
| 3892 | #define HTT_RX_IND_RSSI_CMB_M 0x000000ff |
| 3893 | #define HTT_RX_IND_RSSI_CMB_S 0 |
| 3894 | #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M 0x0000ff00 |
| 3895 | #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S 8 |
| 3896 | #define HTT_RX_IND_PHY_ERR_CODE_M 0x00ff0000 |
| 3897 | #define HTT_RX_IND_PHY_ERR_CODE_S 16 |
| 3898 | #define HTT_RX_IND_PHY_ERR_M 0x01000000 |
| 3899 | #define HTT_RX_IND_PHY_ERR_S 24 |
| 3900 | #define HTT_RX_IND_LEGACY_RATE_M 0x1e000000 |
| 3901 | #define HTT_RX_IND_LEGACY_RATE_S 25 |
| 3902 | #define HTT_RX_IND_LEGACY_RATE_SEL_M 0x20000000 |
| 3903 | #define HTT_RX_IND_LEGACY_RATE_SEL_S 29 |
| 3904 | #define HTT_RX_IND_END_VALID_M 0x40000000 |
| 3905 | #define HTT_RX_IND_END_VALID_S 30 |
| 3906 | #define HTT_RX_IND_START_VALID_M 0x80000000 |
| 3907 | #define HTT_RX_IND_START_VALID_S 31 |
| 3908 | |
| 3909 | #define HTT_RX_IND_RSSI_PRI20_M 0x000000ff |
| 3910 | #define HTT_RX_IND_RSSI_PRI20_S 0 |
| 3911 | #define HTT_RX_IND_RSSI_EXT20_M 0x0000ff00 |
| 3912 | #define HTT_RX_IND_RSSI_EXT20_S 8 |
| 3913 | #define HTT_RX_IND_RSSI_EXT40_M 0x00ff0000 |
| 3914 | #define HTT_RX_IND_RSSI_EXT40_S 16 |
| 3915 | #define HTT_RX_IND_RSSI_EXT80_M 0xff000000 |
| 3916 | #define HTT_RX_IND_RSSI_EXT80_S 24 |
| 3917 | |
| 3918 | #define HTT_RX_IND_VHT_SIG_A1_M 0x00ffffff |
| 3919 | #define HTT_RX_IND_VHT_SIG_A1_S 0 |
| 3920 | #define HTT_RX_IND_VHT_SIG_A2_M 0x00ffffff |
| 3921 | #define HTT_RX_IND_VHT_SIG_A2_S 0 |
| 3922 | #define HTT_RX_IND_PREAMBLE_TYPE_M 0xff000000 |
| 3923 | #define HTT_RX_IND_PREAMBLE_TYPE_S 24 |
| 3924 | #define HTT_RX_IND_SERVICE_M 0xff000000 |
| 3925 | #define HTT_RX_IND_SERVICE_S 24 |
| 3926 | |
| 3927 | /* rx MSDU descriptor fields */ |
| 3928 | #define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff |
| 3929 | #define HTT_RX_IND_FW_RX_DESC_BYTES_S 0 |
| 3930 | |
| 3931 | /* payload fields */ |
| 3932 | #define HTT_RX_IND_MPDU_COUNT_M 0xff |
| 3933 | #define HTT_RX_IND_MPDU_COUNT_S 0 |
| 3934 | #define HTT_RX_IND_MPDU_STATUS_M 0xff00 |
| 3935 | #define HTT_RX_IND_MPDU_STATUS_S 8 |
| 3936 | |
| 3937 | |
| 3938 | #define HTT_RX_IND_EXT_TID_SET(word, value) \ |
| 3939 | do { \ |
| 3940 | HTT_CHECK_SET_VAL(HTT_RX_IND_EXT_TID, value); \ |
| 3941 | (word) |= (value) << HTT_RX_IND_EXT_TID_S; \ |
| 3942 | } while (0) |
| 3943 | #define HTT_RX_IND_EXT_TID_GET(word) \ |
| 3944 | (((word) & HTT_RX_IND_EXT_TID_M) >> HTT_RX_IND_EXT_TID_S) |
| 3945 | |
| 3946 | #define HTT_RX_IND_FLUSH_VALID_SET(word, value) \ |
| 3947 | do { \ |
| 3948 | HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_VALID, value); \ |
| 3949 | (word) |= (value) << HTT_RX_IND_FLUSH_VALID_S; \ |
| 3950 | } while (0) |
| 3951 | #define HTT_RX_IND_FLUSH_VALID_GET(word) \ |
| 3952 | (((word) & HTT_RX_IND_FLUSH_VALID_M) >> HTT_RX_IND_FLUSH_VALID_S) |
| 3953 | |
| 3954 | #define HTT_RX_IND_REL_VALID_SET(word, value) \ |
| 3955 | do { \ |
| 3956 | HTT_CHECK_SET_VAL(HTT_RX_IND_REL_VALID, value); \ |
| 3957 | (word) |= (value) << HTT_RX_IND_REL_VALID_S; \ |
| 3958 | } while (0) |
| 3959 | #define HTT_RX_IND_REL_VALID_GET(word) \ |
| 3960 | (((word) & HTT_RX_IND_REL_VALID_M) >> HTT_RX_IND_REL_VALID_S) |
| 3961 | |
| 3962 | #define HTT_RX_IND_PEER_ID_SET(word, value) \ |
| 3963 | do { \ |
| 3964 | HTT_CHECK_SET_VAL(HTT_RX_IND_PEER_ID, value); \ |
| 3965 | (word) |= (value) << HTT_RX_IND_PEER_ID_S; \ |
| 3966 | } while (0) |
| 3967 | #define HTT_RX_IND_PEER_ID_GET(word) \ |
| 3968 | (((word) & HTT_RX_IND_PEER_ID_M) >> HTT_RX_IND_PEER_ID_S) |
| 3969 | |
| 3970 | |
| 3971 | #define HTT_RX_IND_FW_RX_DESC_BYTES_SET(word, value) \ |
| 3972 | do { \ |
| 3973 | HTT_CHECK_SET_VAL(HTT_RX_IND_FW_RX_DESC_BYTES, value); \ |
| 3974 | (word) |= (value) << HTT_RX_IND_FW_RX_DESC_BYTES_S; \ |
| 3975 | } while (0) |
| 3976 | #define HTT_RX_IND_FW_RX_DESC_BYTES_GET(word) \ |
| 3977 | (((word) & HTT_RX_IND_FW_RX_DESC_BYTES_M) >> \ |
| 3978 | HTT_RX_IND_FW_RX_DESC_BYTES_S) |
| 3979 | |
| 3980 | |
| 3981 | #define HTT_RX_IND_FLUSH_SEQ_NUM_START_SET(word, value) \ |
| 3982 | do { \ |
| 3983 | HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_START, value); \ |
| 3984 | (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_START_S; \ |
| 3985 | } while (0) |
| 3986 | #define HTT_RX_IND_FLUSH_SEQ_NUM_START_GET(word) \ |
| 3987 | (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_START_M) >> \ |
| 3988 | HTT_RX_IND_FLUSH_SEQ_NUM_START_S) |
| 3989 | |
| 3990 | #define HTT_RX_IND_FLUSH_SEQ_NUM_END_SET(word, value) \ |
| 3991 | do { \ |
| 3992 | HTT_CHECK_SET_VAL(HTT_RX_IND_FLUSH_SEQ_NUM_END, value); \ |
| 3993 | (word) |= (value) << HTT_RX_IND_FLUSH_SEQ_NUM_END_S; \ |
| 3994 | } while (0) |
| 3995 | #define HTT_RX_IND_FLUSH_SEQ_NUM_END_GET(word) \ |
| 3996 | (((word) & HTT_RX_IND_FLUSH_SEQ_NUM_END_M) >> \ |
| 3997 | HTT_RX_IND_FLUSH_SEQ_NUM_END_S) |
| 3998 | |
| 3999 | #define HTT_RX_IND_REL_SEQ_NUM_START_SET(word, value) \ |
| 4000 | do { \ |
| 4001 | HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_START, value); \ |
| 4002 | (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_START_S; \ |
| 4003 | } while (0) |
| 4004 | #define HTT_RX_IND_REL_SEQ_NUM_START_GET(word) \ |
| 4005 | (((word) & HTT_RX_IND_REL_SEQ_NUM_START_M) >> \ |
| 4006 | HTT_RX_IND_REL_SEQ_NUM_START_S) |
| 4007 | |
| 4008 | #define HTT_RX_IND_REL_SEQ_NUM_END_SET(word, value) \ |
| 4009 | do { \ |
| 4010 | HTT_CHECK_SET_VAL(HTT_RX_IND_REL_SEQ_NUM_END, value); \ |
| 4011 | (word) |= (value) << HTT_RX_IND_REL_SEQ_NUM_END_S; \ |
| 4012 | } while (0) |
| 4013 | #define HTT_RX_IND_REL_SEQ_NUM_END_GET(word) \ |
| 4014 | (((word) & HTT_RX_IND_REL_SEQ_NUM_END_M) >> \ |
| 4015 | HTT_RX_IND_REL_SEQ_NUM_END_S) |
| 4016 | |
| 4017 | #define HTT_RX_IND_NUM_MPDU_RANGES_SET(word, value) \ |
| 4018 | do { \ |
| 4019 | HTT_CHECK_SET_VAL(HTT_RX_IND_NUM_MPDU_RANGES, value); \ |
| 4020 | (word) |= (value) << HTT_RX_IND_NUM_MPDU_RANGES_S; \ |
| 4021 | } while (0) |
| 4022 | #define HTT_RX_IND_NUM_MPDU_RANGES_GET(word) \ |
| 4023 | (((word) & HTT_RX_IND_NUM_MPDU_RANGES_M) >> \ |
| 4024 | HTT_RX_IND_NUM_MPDU_RANGES_S) |
| 4025 | |
| 4026 | /* FW rx PPDU descriptor fields */ |
| 4027 | #define HTT_RX_IND_RSSI_CMB_SET(word, value) \ |
| 4028 | do { \ |
| 4029 | HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_CMB, value); \ |
| 4030 | (word) |= (value) << HTT_RX_IND_RSSI_CMB_S; \ |
| 4031 | } while (0) |
| 4032 | #define HTT_RX_IND_RSSI_CMB_GET(word) \ |
| 4033 | (((word) & HTT_RX_IND_RSSI_CMB_M) >> \ |
| 4034 | HTT_RX_IND_RSSI_CMB_S) |
| 4035 | |
| 4036 | #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_SET(word, value) \ |
| 4037 | do { \ |
| 4038 | HTT_CHECK_SET_VAL(HTT_RX_IND_TIMESTAMP_SUBMICROSEC, value); \ |
| 4039 | (word) |= (value) << HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S; \ |
| 4040 | } while (0) |
| 4041 | #define HTT_RX_IND_TIMESTAMP_SUBMICROSEC_GET(word) \ |
| 4042 | (((word) & HTT_RX_IND_TIMESTAMP_SUBMICROSEC_M) >> \ |
| 4043 | HTT_RX_IND_TIMESTAMP_SUBMICROSEC_S) |
| 4044 | |
| 4045 | #define HTT_RX_IND_PHY_ERR_CODE_SET(word, value) \ |
| 4046 | do { \ |
| 4047 | HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR_CODE, value); \ |
| 4048 | (word) |= (value) << HTT_RX_IND_PHY_ERR_CODE_S; \ |
| 4049 | } while (0) |
| 4050 | #define HTT_RX_IND_PHY_ERR_CODE_GET(word) \ |
| 4051 | (((word) & HTT_RX_IND_PHY_ERR_CODE_M) >> \ |
| 4052 | HTT_RX_IND_PHY_ERR_CODE_S) |
| 4053 | |
| 4054 | #define HTT_RX_IND_PHY_ERR_SET(word, value) \ |
| 4055 | do { \ |
| 4056 | HTT_CHECK_SET_VAL(HTT_RX_IND_PHY_ERR, value); \ |
| 4057 | (word) |= (value) << HTT_RX_IND_PHY_ERR_S; \ |
| 4058 | } while (0) |
| 4059 | #define HTT_RX_IND_PHY_ERR_GET(word) \ |
| 4060 | (((word) & HTT_RX_IND_PHY_ERR_M) >> \ |
| 4061 | HTT_RX_IND_PHY_ERR_S) |
| 4062 | |
| 4063 | #define HTT_RX_IND_LEGACY_RATE_SET(word, value) \ |
| 4064 | do { \ |
| 4065 | HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE, value); \ |
| 4066 | (word) |= (value) << HTT_RX_IND_LEGACY_RATE_S; \ |
| 4067 | } while (0) |
| 4068 | #define HTT_RX_IND_LEGACY_RATE_GET(word) \ |
| 4069 | (((word) & HTT_RX_IND_LEGACY_RATE_M) >> \ |
| 4070 | HTT_RX_IND_LEGACY_RATE_S) |
| 4071 | |
| 4072 | #define HTT_RX_IND_LEGACY_RATE_SEL_SET(word, value) \ |
| 4073 | do { \ |
| 4074 | HTT_CHECK_SET_VAL(HTT_RX_IND_LEGACY_RATE_SEL, value); \ |
| 4075 | (word) |= (value) << HTT_RX_IND_LEGACY_RATE_SEL_S; \ |
| 4076 | } while (0) |
| 4077 | #define HTT_RX_IND_LEGACY_RATE_SEL_GET(word) \ |
| 4078 | (((word) & HTT_RX_IND_LEGACY_RATE_SEL_M) >> \ |
| 4079 | HTT_RX_IND_LEGACY_RATE_SEL_S) |
| 4080 | |
| 4081 | #define HTT_RX_IND_END_VALID_SET(word, value) \ |
| 4082 | do { \ |
| 4083 | HTT_CHECK_SET_VAL(HTT_RX_IND_END_VALID, value); \ |
| 4084 | (word) |= (value) << HTT_RX_IND_END_VALID_S; \ |
| 4085 | } while (0) |
| 4086 | #define HTT_RX_IND_END_VALID_GET(word) \ |
| 4087 | (((word) & HTT_RX_IND_END_VALID_M) >> \ |
| 4088 | HTT_RX_IND_END_VALID_S) |
| 4089 | |
| 4090 | #define HTT_RX_IND_START_VALID_SET(word, value) \ |
| 4091 | do { \ |
| 4092 | HTT_CHECK_SET_VAL(HTT_RX_IND_START_VALID, value); \ |
| 4093 | (word) |= (value) << HTT_RX_IND_START_VALID_S; \ |
| 4094 | } while (0) |
| 4095 | #define HTT_RX_IND_START_VALID_GET(word) \ |
| 4096 | (((word) & HTT_RX_IND_START_VALID_M) >> \ |
| 4097 | HTT_RX_IND_START_VALID_S) |
| 4098 | |
| 4099 | #define HTT_RX_IND_RSSI_PRI20_SET(word, value) \ |
| 4100 | do { \ |
| 4101 | HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_PRI20, value); \ |
| 4102 | (word) |= (value) << HTT_RX_IND_RSSI_PRI20_S; \ |
| 4103 | } while (0) |
| 4104 | #define HTT_RX_IND_RSSI_PRI20_GET(word) \ |
| 4105 | (((word) & HTT_RX_IND_RSSI_PRI20_M) >> \ |
| 4106 | HTT_RX_IND_RSSI_PRI20_S) |
| 4107 | |
| 4108 | #define HTT_RX_IND_RSSI_EXT20_SET(word, value) \ |
| 4109 | do { \ |
| 4110 | HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT20, value); \ |
| 4111 | (word) |= (value) << HTT_RX_IND_RSSI_EXT20_S; \ |
| 4112 | } while (0) |
| 4113 | #define HTT_RX_IND_RSSI_EXT20_GET(word) \ |
| 4114 | (((word) & HTT_RX_IND_RSSI_EXT20_M) >> \ |
| 4115 | HTT_RX_IND_RSSI_EXT20_S) |
| 4116 | |
| 4117 | #define HTT_RX_IND_RSSI_EXT40_SET(word, value) \ |
| 4118 | do { \ |
| 4119 | HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT40, value); \ |
| 4120 | (word) |= (value) << HTT_RX_IND_RSSI_EXT40_S; \ |
| 4121 | } while (0) |
| 4122 | #define HTT_RX_IND_RSSI_EXT40_GET(word) \ |
| 4123 | (((word) & HTT_RX_IND_RSSI_EXT40_M) >> \ |
| 4124 | HTT_RX_IND_RSSI_EXT40_S) |
| 4125 | |
| 4126 | #define HTT_RX_IND_RSSI_EXT80_SET(word, value) \ |
| 4127 | do { \ |
| 4128 | HTT_CHECK_SET_VAL(HTT_RX_IND_RSSI_EXT80, value); \ |
| 4129 | (word) |= (value) << HTT_RX_IND_RSSI_EXT80_S; \ |
| 4130 | } while (0) |
| 4131 | #define HTT_RX_IND_RSSI_EXT80_GET(word) \ |
| 4132 | (((word) & HTT_RX_IND_RSSI_EXT80_M) >> \ |
| 4133 | HTT_RX_IND_RSSI_EXT80_S) |
| 4134 | |
| 4135 | #define HTT_RX_IND_VHT_SIG_A1_SET(word, value) \ |
| 4136 | do { \ |
| 4137 | HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A1, value); \ |
| 4138 | (word) |= (value) << HTT_RX_IND_VHT_SIG_A1_S; \ |
| 4139 | } while (0) |
| 4140 | #define HTT_RX_IND_VHT_SIG_A1_GET(word) \ |
| 4141 | (((word) & HTT_RX_IND_VHT_SIG_A1_M) >> \ |
| 4142 | HTT_RX_IND_VHT_SIG_A1_S) |
| 4143 | |
| 4144 | #define HTT_RX_IND_VHT_SIG_A2_SET(word, value) \ |
| 4145 | do { \ |
| 4146 | HTT_CHECK_SET_VAL(HTT_RX_IND_VHT_SIG_A2, value); \ |
| 4147 | (word) |= (value) << HTT_RX_IND_VHT_SIG_A2_S; \ |
| 4148 | } while (0) |
| 4149 | #define HTT_RX_IND_VHT_SIG_A2_GET(word) \ |
| 4150 | (((word) & HTT_RX_IND_VHT_SIG_A2_M) >> \ |
| 4151 | HTT_RX_IND_VHT_SIG_A2_S) |
| 4152 | |
| 4153 | #define HTT_RX_IND_PREAMBLE_TYPE_SET(word, value) \ |
| 4154 | do { \ |
| 4155 | HTT_CHECK_SET_VAL(HTT_RX_IND_PREAMBLE_TYPE, value); \ |
| 4156 | (word) |= (value) << HTT_RX_IND_PREAMBLE_TYPE_S; \ |
| 4157 | } while (0) |
| 4158 | #define HTT_RX_IND_PREAMBLE_TYPE_GET(word) \ |
| 4159 | (((word) & HTT_RX_IND_PREAMBLE_TYPE_M) >> \ |
| 4160 | HTT_RX_IND_PREAMBLE_TYPE_S) |
| 4161 | |
| 4162 | #define HTT_RX_IND_SERVICE_SET(word, value) \ |
| 4163 | do { \ |
| 4164 | HTT_CHECK_SET_VAL(HTT_RX_IND_SERVICE, value); \ |
| 4165 | (word) |= (value) << HTT_RX_IND_SERVICE_S; \ |
| 4166 | } while (0) |
| 4167 | #define HTT_RX_IND_SERVICE_GET(word) \ |
| 4168 | (((word) & HTT_RX_IND_SERVICE_M) >> \ |
| 4169 | HTT_RX_IND_SERVICE_S) |
| 4170 | |
| 4171 | |
| 4172 | #define HTT_RX_IND_MPDU_COUNT_SET(word, value) \ |
| 4173 | do { \ |
| 4174 | HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_COUNT, value); \ |
| 4175 | (word) |= (value) << HTT_RX_IND_MPDU_COUNT_S; \ |
| 4176 | } while (0) |
| 4177 | #define HTT_RX_IND_MPDU_COUNT_GET(word) \ |
| 4178 | (((word) & HTT_RX_IND_MPDU_COUNT_M) >> HTT_RX_IND_MPDU_COUNT_S) |
| 4179 | |
| 4180 | #define HTT_RX_IND_MPDU_STATUS_SET(word, value) \ |
| 4181 | do { \ |
| 4182 | HTT_CHECK_SET_VAL(HTT_RX_IND_MPDU_STATUS, value); \ |
| 4183 | (word) |= (value) << HTT_RX_IND_MPDU_STATUS_S; \ |
| 4184 | } while (0) |
| 4185 | #define HTT_RX_IND_MPDU_STATUS_GET(word) \ |
| 4186 | (((word) & HTT_RX_IND_MPDU_STATUS_M) >> HTT_RX_IND_MPDU_STATUS_S) |
| 4187 | |
| 4188 | |
| 4189 | #define HTT_RX_IND_HL_BYTES \ |
| 4190 | (HTT_RX_IND_HDR_BYTES + \ |
| 4191 | 4 /* single FW rx MSDU descriptor, plus padding */ + \ |
| 4192 | 4 /* single MPDU range information element */) |
| 4193 | #define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2) |
| 4194 | |
| 4195 | /* Could we use one macro entry? */ |
| 4196 | #define HTT_WORD_SET(word, field, value) \ |
| 4197 | do { \ |
| 4198 | HTT_CHECK_SET_VAL(field, value); \ |
| 4199 | (word) |= ((value) << field ## _S); \ |
| 4200 | } while (0) |
| 4201 | #define HTT_WORD_GET(word, field) \ |
| 4202 | (((word) & field ## _M) >> field ## _S) |
| 4203 | |
| 4204 | PREPACK struct hl_htt_rx_ind_base { |
| 4205 | /* |
| 4206 | * align with LL case rx indication message,but |
| 4207 | * reduced to 5 words |
| 4208 | */ |
| 4209 | A_UINT32 rx_ind_msg[HTT_RX_IND_HL_SIZE32]; |
| 4210 | } POSTPACK; |
| 4211 | |
| 4212 | /* |
| 4213 | * HTT_RX_IND_HL_RX_DESC_BASE_OFFSET |
| 4214 | * Currently, we use a resv field in hl_htt_rx_ind_base to store some |
| 4215 | * HL host needed info. The field is just after the msdu fw rx desc. |
| 4216 | */ |
| 4217 | #define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ |
| 4218 | (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1) |
| 4219 | struct htt_rx_ind_hl_rx_desc_t { |
| 4220 | A_UINT8 ver; |
| 4221 | A_UINT8 len; |
| 4222 | struct { |
| 4223 | A_UINT8 |
| 4224 | first_msdu:1, |
| 4225 | last_msdu:1, |
| 4226 | c3_failed:1, |
| 4227 | c4_failed:1, |
| 4228 | ipv6:1, |
| 4229 | tcp:1, |
| 4230 | udp:1, |
| 4231 | reserved:1; |
| 4232 | } flags; |
| 4233 | }; |
| 4234 | |
| 4235 | #define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \ |
| 4236 | (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ |
| 4237 | + offsetof(struct htt_rx_ind_hl_rx_desc_t, ver)) |
| 4238 | #define HTT_RX_IND_HL_RX_DESC_VER 0 |
| 4239 | |
| 4240 | #define HTT_RX_IND_HL_RX_DESC_LEN_OFFSET \ |
| 4241 | (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ |
| 4242 | + offsetof(struct htt_rx_ind_hl_rx_desc_t, len)) |
| 4243 | |
| 4244 | #define HTT_RX_IND_HL_FLAG_OFFSET \ |
| 4245 | (HTT_RX_IND_HL_RX_DESC_BASE_OFFSET \ |
| 4246 | + offsetof(struct htt_rx_ind_hl_rx_desc_t, flags)) |
| 4247 | |
| 4248 | #define HTT_RX_IND_HL_FLAG_FIRST_MSDU (0x01 << 0) |
| 4249 | #define HTT_RX_IND_HL_FLAG_LAST_MSDU (0x01 << 1) |
| 4250 | #define HTT_RX_IND_HL_FLAG_C3_FAILED (0x01 << 2) /* L3 checksum failed */ |
| 4251 | #define HTT_RX_IND_HL_FLAG_C4_FAILED (0x01 << 3) /* L4 checksum failed */ |
| 4252 | #define HTT_RX_IND_HL_FLAG_IPV6 (0x01 << 4) /* is ipv6, or ipv4 */ |
| 4253 | #define HTT_RX_IND_HL_FLAG_TCP (0x01 << 5) /* is tcp */ |
| 4254 | #define HTT_RX_IND_HL_FLAG_UDP (0x01 << 6) /* is udp */ |
| 4255 | /* This structure is used in HL, the basic descriptor information |
| 4256 | * used by host. the structure is translated by FW from HW desc |
| 4257 | * or generated by FW. But in HL monitor mode, the host would use |
| 4258 | * the same structure with LL. |
| 4259 | */ |
| 4260 | PREPACK struct hl_htt_rx_desc_base { |
| 4261 | A_UINT32 |
| 4262 | seq_num:12, |
| 4263 | encrypted:1, |
| 4264 | chan_info_present:1, |
| 4265 | resv0:2, |
| 4266 | mcast_bcast:1, |
| 4267 | fragment:1, |
| 4268 | key_id_oct:8, |
| 4269 | resv1:6; |
| 4270 | A_UINT32 pn_31_0; |
| 4271 | union { |
| 4272 | struct { |
| 4273 | A_UINT16 pn_47_32; |
| 4274 | A_UINT16 pn_63_48; |
| 4275 | } pn16; |
| 4276 | A_UINT32 pn_63_32; |
| 4277 | } u0; |
| 4278 | A_UINT32 pn_95_64; |
| 4279 | A_UINT32 pn_127_96; |
| 4280 | } POSTPACK; |
| 4281 | |
| 4282 | /* |
| 4283 | * Channel information can optionally be appended after hl_htt_rx_desc_base. |
| 4284 | * If so, the len field in htt_rx_ind_hl_rx_desc_t will be updated accordingly, |
| 4285 | * and the chan_info_present flag in hl_htt_rx_desc_base will be set. |
| 4286 | * Please see htt_chan_change_t for description of the fields. |
| 4287 | */ |
| 4288 | PREPACK struct htt_chan_info_t |
| 4289 | { |
| 4290 | A_UINT32 |
| 4291 | primary_chan_center_freq_mhz:16, |
| 4292 | contig_chan1_center_freq_mhz:16; |
| 4293 | A_UINT32 |
| 4294 | contig_chan2_center_freq_mhz:16, |
| 4295 | phy_mode:8, |
| 4296 | reserved:8; |
| 4297 | } POSTPACK; |
| 4298 | |
| 4299 | #define HTT_CHAN_INFO_SIZE sizeof(struct htt_chan_info_t) |
| 4300 | |
| 4301 | #define HL_RX_DESC_SIZE (sizeof(struct hl_htt_rx_desc_base)) |
| 4302 | #define HL_RX_DESC_SIZE_DWORD (HL_RX_STD_DESC_SIZE >> 2) |
| 4303 | |
| 4304 | #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_M 0xfff |
| 4305 | #define HTT_HL_RX_DESC_MPDU_SEQ_NUM_S 0 |
| 4306 | #define HTT_HL_RX_DESC_MPDU_ENC_M 0x1000 |
| 4307 | #define HTT_HL_RX_DESC_MPDU_ENC_S 12 |
| 4308 | #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_M 0x2000 |
| 4309 | #define HTT_HL_RX_DESC_CHAN_INFO_PRESENT_S 13 |
| 4310 | #define HTT_HL_RX_DESC_MCAST_BCAST_M 0x10000 |
| 4311 | #define HTT_HL_RX_DESC_MCAST_BCAST_S 16 |
| 4312 | #define HTT_HL_RX_DESC_FRAGMENT_M 0x20000 |
| 4313 | #define HTT_HL_RX_DESC_FRAGMENT_S 17 |
| 4314 | #define HTT_HL_RX_DESC_KEY_ID_OCT_M 0x3fc0000 |
| 4315 | #define HTT_HL_RX_DESC_KEY_ID_OCT_S 18 |
| 4316 | |
| 4317 | #define HTT_HL_RX_DESC_PN_OFFSET \ |
| 4318 | offsetof(struct hl_htt_rx_desc_base, pn_31_0) |
| 4319 | #define HTT_HL_RX_DESC_PN_WORD_OFFSET \ |
| 4320 | (HTT_HL_RX_DESC_PN_OFFSET >> 2) |
| 4321 | |
| 4322 | /* Channel information */ |
| 4323 | #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M 0x0000ffff |
| 4324 | #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S 0 |
| 4325 | #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M 0xffff0000 |
| 4326 | #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S 16 |
| 4327 | #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M 0x0000ffff |
| 4328 | #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S 0 |
| 4329 | #define HTT_CHAN_INFO_PHY_MODE_M 0x00ff0000 |
| 4330 | #define HTT_CHAN_INFO_PHY_MODE_S 16 |
| 4331 | |
| 4332 | |
| 4333 | #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_SET(word, value) \ |
| 4334 | do { \ |
| 4335 | HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ, value); \ |
| 4336 | (word) |= (value) << HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S; \ |
| 4337 | } while (0) |
| 4338 | #define HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_GET(word) \ |
| 4339 | (((word) & HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_M) \ |
| 4340 | >> HTT_CHAN_INFO_PRIMARY_CHAN_CENTER_FREQ_S) |
| 4341 | |
| 4342 | |
| 4343 | #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_SET(word, value) \ |
| 4344 | do { \ |
| 4345 | HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ, value); \ |
| 4346 | (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S; \ |
| 4347 | } while (0) |
| 4348 | #define HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_GET(word) \ |
| 4349 | (((word) & HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_M) \ |
| 4350 | >> HTT_CHAN_INFO_CONTIG_CHAN1_CENTER_FREQ_S) |
| 4351 | |
| 4352 | |
| 4353 | #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_SET(word, value) \ |
| 4354 | do { \ |
| 4355 | HTT_CHECK_SET_VAL(HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ, value); \ |
| 4356 | (word) |= (value) << HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S; \ |
| 4357 | } while (0) |
| 4358 | #define HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_GET(word) \ |
| 4359 | (((word) & HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_M) \ |
| 4360 | >> HTT_CHAN_INFO_CONTIG_CHAN2_CENTER_FREQ_S) |
| 4361 | |
| 4362 | |
| 4363 | #define HTT_CHAN_INFO_PHY_MODE_SET(word, value) \ |
| 4364 | do { \ |
| 4365 | HTT_CHECK_SET_VAL(HTT_CHAN_INFO_PHY_MODE, value); \ |
| 4366 | (word) |= (value) << HTT_CHAN_INFO_PHY_MODE_S; \ |
| 4367 | } while (0) |
| 4368 | #define HTT_CHAN_INFO_PHY_MODE_GET(word) \ |
| 4369 | (((word) & HTT_CHAN_INFO_PHY_MODE_M) \ |
| 4370 | >> HTT_CHAN_INFO_PHY_MODE_S) |
| 4371 | |
| 4372 | /* |
| 4373 | * @brief target -> host rx reorder flush message definition |
| 4374 | * |
| 4375 | * @details |
| 4376 | * The following field definitions describe the format of the rx flush |
| 4377 | * message sent from the target to the host. |
| 4378 | * The message consists of a 4-octet header, followed by one or more |
| 4379 | * 4-octet payload information elements. |
| 4380 | * |
| 4381 | * |31 24|23 8|7 0| |
| 4382 | * |--------------------------------------------------------------| |
| 4383 | * | TID | peer ID | msg type | |
| 4384 | * |--------------------------------------------------------------| |
| 4385 | * | seq num end | seq num start | MPDU status | reserved | |
| 4386 | * |--------------------------------------------------------------| |
| 4387 | * First DWORD: |
| 4388 | * - MSG_TYPE |
| 4389 | * Bits 7:0 |
| 4390 | * Purpose: identifies this as an rx flush message |
| 4391 | * Value: 0x2 |
| 4392 | * - PEER_ID |
| 4393 | * Bits 23:8 (only bits 18:8 actually used) |
| 4394 | * Purpose: identify which peer's rx data is being flushed |
| 4395 | * Value: (rx) peer ID |
| 4396 | * - TID |
| 4397 | * Bits 31:24 (only bits 27:24 actually used) |
| 4398 | * Purpose: Specifies which traffic identifier's rx data is being flushed |
| 4399 | * Value: traffic identifier |
| 4400 | * Second DWORD: |
| 4401 | * - MPDU_STATUS |
| 4402 | * Bits 15:8 |
| 4403 | * Purpose: |
| 4404 | * Indicate whether the flushed MPDUs should be discarded or processed. |
| 4405 | * Value: |
| 4406 | * 0x1: send the MPDUs from the rx reorder buffer to subsequent |
| 4407 | * stages of rx processing |
| 4408 | * other: discard the MPDUs |
| 4409 | * It is anticipated that flush messages will always have |
| 4410 | * MPDU status == 1, but the status flag is included for |
| 4411 | * flexibility. |
| 4412 | * - SEQ_NUM_START |
| 4413 | * Bits 23:16 |
| 4414 | * Purpose: |
| 4415 | * Indicate the start of a series of consecutive MPDUs being flushed. |
| 4416 | * Not all MPDUs within this range are necessarily valid - the host |
| 4417 | * must check each sequence number within this range to see if the |
| 4418 | * corresponding MPDU is actually present. |
| 4419 | * Value: |
| 4420 | * The sequence number for the first MPDU in the sequence. |
| 4421 | * This sequence number is the 6 LSBs of the 802.11 sequence number. |
| 4422 | * - SEQ_NUM_END |
| 4423 | * Bits 30:24 |
| 4424 | * Purpose: |
| 4425 | * Indicate the end of a series of consecutive MPDUs being flushed. |
| 4426 | * Value: |
| 4427 | * The sequence number one larger than the sequence number of the |
| 4428 | * last MPDU being flushed. |
| 4429 | * This sequence number is the 6 LSBs of the 802.11 sequence number. |
| 4430 | * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] inclusive |
| 4431 | * are to be released for further rx processing. |
| 4432 | * Not all MPDUs within this range are necessarily valid - the host |
| 4433 | * must check each sequence number within this range to see if the |
| 4434 | * corresponding MPDU is actually present. |
| 4435 | */ |
| 4436 | /* first DWORD */ |
| 4437 | #define HTT_RX_FLUSH_PEER_ID_M 0xffff00 |
| 4438 | #define HTT_RX_FLUSH_PEER_ID_S 8 |
| 4439 | #define HTT_RX_FLUSH_TID_M 0xff000000 |
| 4440 | #define HTT_RX_FLUSH_TID_S 24 |
| 4441 | /* second DWORD */ |
| 4442 | #define HTT_RX_FLUSH_MPDU_STATUS_M 0x0000ff00 |
| 4443 | #define HTT_RX_FLUSH_MPDU_STATUS_S 8 |
| 4444 | #define HTT_RX_FLUSH_SEQ_NUM_START_M 0x00ff0000 |
| 4445 | #define HTT_RX_FLUSH_SEQ_NUM_START_S 16 |
| 4446 | #define HTT_RX_FLUSH_SEQ_NUM_END_M 0xff000000 |
| 4447 | #define HTT_RX_FLUSH_SEQ_NUM_END_S 24 |
| 4448 | |
| 4449 | #define HTT_RX_FLUSH_BYTES 8 |
| 4450 | |
| 4451 | #define HTT_RX_FLUSH_PEER_ID_SET(word, value) \ |
| 4452 | do { \ |
| 4453 | HTT_CHECK_SET_VAL(HTT_RX_FLUSH_PEER_ID, value); \ |
| 4454 | (word) |= (value) << HTT_RX_FLUSH_PEER_ID_S; \ |
| 4455 | } while (0) |
| 4456 | #define HTT_RX_FLUSH_PEER_ID_GET(word) \ |
| 4457 | (((word) & HTT_RX_FLUSH_PEER_ID_M) >> HTT_RX_FLUSH_PEER_ID_S) |
| 4458 | |
| 4459 | #define HTT_RX_FLUSH_TID_SET(word, value) \ |
| 4460 | do { \ |
| 4461 | HTT_CHECK_SET_VAL(HTT_RX_FLUSH_TID, value); \ |
| 4462 | (word) |= (value) << HTT_RX_FLUSH_TID_S; \ |
| 4463 | } while (0) |
| 4464 | #define HTT_RX_FLUSH_TID_GET(word) \ |
| 4465 | (((word) & HTT_RX_FLUSH_TID_M) >> HTT_RX_FLUSH_TID_S) |
| 4466 | |
| 4467 | #define HTT_RX_FLUSH_MPDU_STATUS_SET(word, value) \ |
| 4468 | do { \ |
| 4469 | HTT_CHECK_SET_VAL(HTT_RX_FLUSH_MPDU_STATUS, value); \ |
| 4470 | (word) |= (value) << HTT_RX_FLUSH_MPDU_STATUS_S; \ |
| 4471 | } while (0) |
| 4472 | #define HTT_RX_FLUSH_MPDU_STATUS_GET(word) \ |
| 4473 | (((word) & HTT_RX_FLUSH_MPDU_STATUS_M) >> HTT_RX_FLUSH_MPDU_STATUS_S) |
| 4474 | |
| 4475 | #define HTT_RX_FLUSH_SEQ_NUM_START_SET(word, value) \ |
| 4476 | do { \ |
| 4477 | HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_START, value); \ |
| 4478 | (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_START_S; \ |
| 4479 | } while (0) |
| 4480 | #define HTT_RX_FLUSH_SEQ_NUM_START_GET(word) \ |
| 4481 | (((word) & HTT_RX_FLUSH_SEQ_NUM_START_M) >> \ |
| 4482 | HTT_RX_FLUSH_SEQ_NUM_START_S) |
| 4483 | |
| 4484 | #define HTT_RX_FLUSH_SEQ_NUM_END_SET(word, value) \ |
| 4485 | do { \ |
| 4486 | HTT_CHECK_SET_VAL(HTT_RX_FLUSH_SEQ_NUM_END, value); \ |
| 4487 | (word) |= (value) << HTT_RX_FLUSH_SEQ_NUM_END_S; \ |
| 4488 | } while (0) |
| 4489 | #define HTT_RX_FLUSH_SEQ_NUM_END_GET(word) \ |
| 4490 | (((word) & HTT_RX_FLUSH_SEQ_NUM_END_M) >> HTT_RX_FLUSH_SEQ_NUM_END_S) |
| 4491 | |
| 4492 | /* |
| 4493 | * @brief target -> host rx pn check indication message |
| 4494 | * |
| 4495 | * @details |
| 4496 | * The following field definitions describe the format of the Rx PN check |
| 4497 | * indication message sent from the target to the host. |
| 4498 | * The message consists of a 4-octet header, followed by the start and |
| 4499 | * end sequence numbers to be released, followed by the PN IEs. Each PN |
| 4500 | * IE is one octet containing the sequence number that failed the PN |
| 4501 | * check. |
| 4502 | * |
| 4503 | * |31 24|23 8|7 0| |
| 4504 | * |--------------------------------------------------------------| |
| 4505 | * | TID | peer ID | msg type | |
| 4506 | * |--------------------------------------------------------------| |
| 4507 | * | Reserved | PN IE count | seq num end | seq num start| |
| 4508 | * |--------------------------------------------------------------| |
| 4509 | * l : PN IE 2 | PN IE 1 | PN IE 0 | |
| 4510 | * |--------------------------------------------------------------| |
| 4511 | |
| 4512 | * First DWORD: |
| 4513 | * - MSG_TYPE |
| 4514 | * Bits 7:0 |
| 4515 | * Purpose: Identifies this as an rx pn check indication message |
| 4516 | * Value: 0x2 |
| 4517 | * - PEER_ID |
| 4518 | * Bits 23:8 (only bits 18:8 actually used) |
| 4519 | * Purpose: identify which peer |
| 4520 | * Value: (rx) peer ID |
| 4521 | * - TID |
| 4522 | * Bits 31:24 (only bits 27:24 actually used) |
| 4523 | * Purpose: identify traffic identifier |
| 4524 | * Value: traffic identifier |
| 4525 | * Second DWORD: |
| 4526 | * - SEQ_NUM_START |
| 4527 | * Bits 7:0 |
| 4528 | * Purpose: |
| 4529 | * Indicates the starting sequence number of the MPDU in this |
| 4530 | * series of MPDUs that went though PN check. |
| 4531 | * Value: |
| 4532 | * The sequence number for the first MPDU in the sequence. |
| 4533 | * This sequence number is the 6 LSBs of the 802.11 sequence number. |
| 4534 | * - SEQ_NUM_END |
| 4535 | * Bits 15:8 |
| 4536 | * Purpose: |
| 4537 | * Indicates the ending sequence number of the MPDU in this |
| 4538 | * series of MPDUs that went though PN check. |
| 4539 | * Value: |
| 4540 | * The sequence number one larger then the sequence number of the last |
| 4541 | * MPDU being flushed. |
| 4542 | * This sequence number is the 6 LSBs of the 802.11 sequence number. |
| 4543 | * The range of MPDUs from [SEQ_NUM_START,SEQ_NUM_END-1] |
| 4544 | * have been checked for invalid PN numbers and are ready |
| 4545 | * to be released for further processing. |
| 4546 | * Not all MPDUs within this range are necessarily valid - the host |
| 4547 | * must check each sequence number within this range to see if the |
| 4548 | * corresponding MPDU is actually present. |
| 4549 | * - PN_IE_COUNT |
| 4550 | * Bits 23:16 |
| 4551 | * Purpose: |
| 4552 | * Used to determine the variable number of PN information |
| 4553 | * elements in this message |
| 4554 | * |
| 4555 | * PN information elements: |
| 4556 | * - PN_IE_x- |
| 4557 | * Purpose: |
| 4558 | * Each PN information element contains the sequence number |
| 4559 | * of the MPDU that has failed the target PN check. |
| 4560 | * Value: |
| 4561 | * Contains the 6 LSBs of the 802.11 sequence number |
| 4562 | * corresponding to the MPDU that failed the PN check. |
| 4563 | */ |
| 4564 | /* first DWORD */ |
| 4565 | #define HTT_RX_PN_IND_PEER_ID_M 0xffff00 |
| 4566 | #define HTT_RX_PN_IND_PEER_ID_S 8 |
| 4567 | #define HTT_RX_PN_IND_TID_M 0xff000000 |
| 4568 | #define HTT_RX_PN_IND_TID_S 24 |
| 4569 | /* second DWORD */ |
| 4570 | #define HTT_RX_PN_IND_SEQ_NUM_START_M 0x000000ff |
| 4571 | #define HTT_RX_PN_IND_SEQ_NUM_START_S 0 |
| 4572 | #define HTT_RX_PN_IND_SEQ_NUM_END_M 0x0000ff00 |
| 4573 | #define HTT_RX_PN_IND_SEQ_NUM_END_S 8 |
| 4574 | #define HTT_RX_PN_IND_PN_IE_CNT_M 0x00ff0000 |
| 4575 | #define HTT_RX_PN_IND_PN_IE_CNT_S 16 |
| 4576 | |
| 4577 | #define HTT_RX_PN_IND_BYTES 8 |
| 4578 | |
| 4579 | #define HTT_RX_PN_IND_PEER_ID_SET(word, value) \ |
| 4580 | do { \ |
| 4581 | HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PEER_ID, value); \ |
| 4582 | (word) |= (value) << HTT_RX_PN_IND_PEER_ID_S; \ |
| 4583 | } while (0) |
| 4584 | #define HTT_RX_PN_IND_PEER_ID_GET(word) \ |
| 4585 | (((word) & HTT_RX_PN_IND_PEER_ID_M) >> HTT_RX_PN_IND_PEER_ID_S) |
| 4586 | |
| 4587 | #define HTT_RX_PN_IND_EXT_TID_SET(word, value) \ |
| 4588 | do { \ |
| 4589 | HTT_CHECK_SET_VAL(HTT_RX_PN_IND_TID, value); \ |
| 4590 | (word) |= (value) << HTT_RX_PN_IND_TID_S; \ |
| 4591 | } while (0) |
| 4592 | #define HTT_RX_PN_IND_EXT_TID_GET(word) \ |
| 4593 | (((word) & HTT_RX_PN_IND_TID_M) >> HTT_RX_PN_IND_TID_S) |
| 4594 | |
| 4595 | #define HTT_RX_PN_IND_SEQ_NUM_START_SET(word, value) \ |
| 4596 | do { \ |
| 4597 | HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_START, value); \ |
| 4598 | (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_START_S; \ |
| 4599 | } while (0) |
| 4600 | #define HTT_RX_PN_IND_SEQ_NUM_START_GET(word) \ |
| 4601 | (((word) & HTT_RX_PN_IND_SEQ_NUM_START_M) >> \ |
| 4602 | HTT_RX_PN_IND_SEQ_NUM_START_S) |
| 4603 | |
| 4604 | #define HTT_RX_PN_IND_SEQ_NUM_END_SET(word, value) \ |
| 4605 | do { \ |
| 4606 | HTT_CHECK_SET_VAL(HTT_RX_PN_IND_SEQ_NUM_END, value); \ |
| 4607 | (word) |= (value) << HTT_RX_PN_IND_SEQ_NUM_END_S; \ |
| 4608 | } while (0) |
| 4609 | #define HTT_RX_PN_IND_SEQ_NUM_END_GET(word) \ |
| 4610 | (((word) & HTT_RX_PN_IND_SEQ_NUM_END_M) >> HTT_RX_PN_IND_SEQ_NUM_END_S) |
| 4611 | |
| 4612 | #define HTT_RX_PN_IND_PN_IE_CNT_SET(word, value) \ |
| 4613 | do { \ |
| 4614 | HTT_CHECK_SET_VAL(HTT_RX_PN_IND_PN_IE_CNT, value); \ |
| 4615 | (word) |= (value) << HTT_RX_PN_IND_PN_IE_CNT_S; \ |
| 4616 | } while (0) |
| 4617 | #define HTT_RX_PN_IND_PN_IE_CNT_GET(word) \ |
| 4618 | (((word) & HTT_RX_PN_IND_PN_IE_CNT_M) >> HTT_RX_PN_IND_PN_IE_CNT_S) |
| 4619 | |
| 4620 | /* |
| 4621 | * @brief target -> host rx offload deliver message for LL system |
| 4622 | * |
| 4623 | * @details |
| 4624 | * In a low latency system this message is sent whenever the offload |
| 4625 | * manager flushes out the packets it has coalesced in its coalescing buffer. |
| 4626 | * The DMA of the actual packets into host memory is done before sending out |
| 4627 | * this message. This message indicates only how many MSDUs to reap. The |
| 4628 | * peer ID, vdev ID, tid and MSDU length are copied inline into the header |
| 4629 | * portion of the MSDU while DMA'ing into the host memory. Unlike the packets |
| 4630 | * DMA'd by the MAC directly into host memory these packets do not contain |
| 4631 | * the MAC descriptors in the header portion of the packet. Instead they contain |
| 4632 | * the peer ID, vdev ID, tid and MSDU length. Also when the host receives this |
| 4633 | * message, the packets are delivered directly to the NW stack without going |
| 4634 | * through the regular reorder buffering and PN checking path since it has |
| 4635 | * already been done in target. |
| 4636 | * |
| 4637 | * |31 24|23 16|15 8|7 0| |
| 4638 | * |-----------------------------------------------------------------------| |
| 4639 | * | Total MSDU count | reserved | msg type | |
| 4640 | * |-----------------------------------------------------------------------| |
| 4641 | * |
| 4642 | * @brief target -> host rx offload deliver message for HL system |
| 4643 | * |
| 4644 | * @details |
| 4645 | * In a high latency system this message is sent whenever the offload manager |
| 4646 | * flushes out the packets it has coalesced in its coalescing buffer. The |
| 4647 | * actual packets are also carried along with this message. When the host |
| 4648 | * receives this message, it is expected to deliver these packets to the NW |
| 4649 | * stack directly instead of routing them through the reorder buffering and |
| 4650 | * PN checking path since it has already been done in target. |
| 4651 | * |
| 4652 | * |31 24|23 16|15 8|7 0| |
| 4653 | * |-----------------------------------------------------------------------| |
| 4654 | * | Total MSDU count | reserved | msg type | |
| 4655 | * |-----------------------------------------------------------------------| |
| 4656 | * | peer ID | MSDU length | |
| 4657 | * |-----------------------------------------------------------------------| |
| 4658 | * | MSDU payload | FW Desc | tid | vdev ID | |
| 4659 | * |-----------------------------------------------------------------------| |
| 4660 | * | MSDU payload contd. | |
| 4661 | * |-----------------------------------------------------------------------| |
| 4662 | * | peer ID | MSDU length | |
| 4663 | * |-----------------------------------------------------------------------| |
| 4664 | * | MSDU payload | FW Desc | tid | vdev ID | |
| 4665 | * |-----------------------------------------------------------------------| |
| 4666 | * | MSDU payload contd. | |
| 4667 | * |-----------------------------------------------------------------------| |
| 4668 | * |
| 4669 | */ |
| 4670 | /* first DWORD */ |
| 4671 | #define HTT_RX_OFFLOAD_DELIVER_IND_HDR_BYTES 4 |
| 4672 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_HDR_BYTES 7 |
| 4673 | |
| 4674 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M 0xffff0000 |
| 4675 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S 16 |
| 4676 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M 0x0000ffff |
| 4677 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S 0 |
| 4678 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M 0xffff0000 |
| 4679 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S 16 |
| 4680 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M 0x000000ff |
| 4681 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S 0 |
| 4682 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M 0x0000ff00 |
| 4683 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S 8 |
| 4684 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M 0x00ff0000 |
| 4685 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S 16 |
| 4686 | |
| 4687 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_GET(word) \ |
| 4688 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_M) >> \ |
| 4689 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S) |
| 4690 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_SET(word, value) \ |
| 4691 | do { \ |
| 4692 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT, value); \ |
| 4693 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_CNT_S; \ |
| 4694 | } while (0) \ |
| 4695 | |
| 4696 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_GET(word) \ |
| 4697 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_M) >> \ |
| 4698 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S) |
| 4699 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_SET(word, value) \ |
| 4700 | do { \ |
| 4701 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN, value); \ |
| 4702 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_LEN_S; \ |
| 4703 | } while (0) \ |
| 4704 | |
| 4705 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_GET(word) \ |
| 4706 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_M) >> \ |
| 4707 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S) |
| 4708 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_SET(word, value) \ |
| 4709 | do { \ |
| 4710 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID, value); \ |
| 4711 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_PEER_ID_S; \ |
| 4712 | } while (0) \ |
| 4713 | |
| 4714 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_GET(word) \ |
| 4715 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_M) >> \ |
| 4716 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S) |
| 4717 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_SET(word, value) \ |
| 4718 | do { \ |
| 4719 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID, value); \ |
| 4720 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_VDEV_ID_S; \ |
| 4721 | } while (0) \ |
| 4722 | |
| 4723 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_GET(word) \ |
| 4724 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_M) >> \ |
| 4725 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S) |
| 4726 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_SET(word, value) \ |
| 4727 | do { \ |
| 4728 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID, value); \ |
| 4729 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_TID_S; \ |
| 4730 | } while (0) \ |
| 4731 | |
| 4732 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_GET(word) \ |
| 4733 | (((word) & HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_M) >> \ |
| 4734 | HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S) |
| 4735 | #define HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_SET(word, value) \ |
| 4736 | do { \ |
| 4737 | HTT_CHECK_SET_VAL(HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC, value); \ |
| 4738 | (word) |= (value) << HTT_RX_OFFLOAD_DELIVER_IND_MSDU_DESC_S; \ |
| 4739 | } while (0) \ |
| 4740 | |
| 4741 | /** |
| 4742 | * @brief target -> host rx peer map/unmap message definition |
| 4743 | * |
| 4744 | * @details |
| 4745 | * The following diagram shows the format of the rx peer map message sent |
| 4746 | * from the target to the host. This layout assumes the target operates |
| 4747 | * as little-endian. |
| 4748 | * |
| 4749 | * |31 24|23 16|15 8|7 0| |
| 4750 | * |-----------------------------------------------------------------------| |
| 4751 | * | peer ID | VDEV ID | msg type | |
| 4752 | * |-----------------------------------------------------------------------| |
| 4753 | * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | |
| 4754 | * |-----------------------------------------------------------------------| |
| 4755 | * | reserved | MAC addr 5 | MAC addr 4 | |
| 4756 | * |-----------------------------------------------------------------------| |
| 4757 | * |
| 4758 | * |
| 4759 | * The following diagram shows the format of the rx peer unmap message sent |
| 4760 | * from the target to the host. |
| 4761 | * |
| 4762 | * |31 24|23 16|15 8|7 0| |
| 4763 | * |-----------------------------------------------------------------------| |
| 4764 | * | peer ID | VDEV ID | msg type | |
| 4765 | * |-----------------------------------------------------------------------| |
| 4766 | * |
| 4767 | * The following field definitions describe the format of the rx peer map |
| 4768 | * and peer unmap messages sent from the target to the host. |
| 4769 | * - MSG_TYPE |
| 4770 | * Bits 7:0 |
| 4771 | * Purpose: identifies this as an rx peer map or peer unmap message |
| 4772 | * Value: peer map -> 0x3, peer unmap -> 0x4 |
| 4773 | * - VDEV_ID |
| 4774 | * Bits 15:8 |
| 4775 | * Purpose: Indicates which virtual device the peer is associated |
| 4776 | * with. |
| 4777 | * Value: vdev ID (used in the host to look up the vdev object) |
| 4778 | * - PEER_ID |
| 4779 | * Bits 31:16 |
| 4780 | * Purpose: The peer ID (index) that WAL is allocating (map) or |
| 4781 | * freeing (unmap) |
| 4782 | * Value: (rx) peer ID |
| 4783 | * - MAC_ADDR_L32 (peer map only) |
| 4784 | * Bits 31:0 |
| 4785 | * Purpose: Identifies which peer node the peer ID is for. |
| 4786 | * Value: lower 4 bytes of peer node's MAC address |
| 4787 | * - MAC_ADDR_U16 (peer map only) |
| 4788 | * Bits 15:0 |
| 4789 | * Purpose: Identifies which peer node the peer ID is for. |
| 4790 | * Value: upper 2 bytes of peer node's MAC address |
| 4791 | */ |
| 4792 | #define HTT_RX_PEER_MAP_VDEV_ID_M 0xff00 |
| 4793 | #define HTT_RX_PEER_MAP_VDEV_ID_S 8 |
| 4794 | #define HTT_RX_PEER_MAP_PEER_ID_M 0xffff0000 |
| 4795 | #define HTT_RX_PEER_MAP_PEER_ID_S 16 |
| 4796 | #define HTT_RX_PEER_MAP_MAC_ADDR_L32_M 0xffffffff |
| 4797 | #define HTT_RX_PEER_MAP_MAC_ADDR_L32_S 0 |
| 4798 | #define HTT_RX_PEER_MAP_MAC_ADDR_U16_M 0xffff |
| 4799 | #define HTT_RX_PEER_MAP_MAC_ADDR_U16_S 0 |
| 4800 | |
| 4801 | #define HTT_RX_PEER_MAP_VAP_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET /* deprecated */ |
| 4802 | #define HTT_RX_PEER_MAP_VDEV_ID_SET(word, value) \ |
| 4803 | do { \ |
| 4804 | HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_VDEV_ID, value); \ |
| 4805 | (word) |= (value) << HTT_RX_PEER_MAP_VDEV_ID_S; \ |
| 4806 | } while (0) |
| 4807 | #define HTT_RX_PEER_MAP_VAP_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET /* deprecated */ |
| 4808 | #define HTT_RX_PEER_MAP_VDEV_ID_GET(word) \ |
| 4809 | (((word) & HTT_RX_PEER_MAP_VDEV_ID_M) >> HTT_RX_PEER_MAP_VDEV_ID_S) |
| 4810 | |
| 4811 | #define HTT_RX_PEER_MAP_PEER_ID_SET(word, value) \ |
| 4812 | do { \ |
| 4813 | HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ |
| 4814 | (word) |= (value) << HTT_RX_PEER_MAP_PEER_ID_S; \ |
| 4815 | } while (0) |
| 4816 | #define HTT_RX_PEER_MAP_PEER_ID_GET(word) \ |
| 4817 | (((word) & HTT_RX_PEER_MAP_PEER_ID_M) >> HTT_RX_PEER_MAP_PEER_ID_S) |
| 4818 | |
| 4819 | #define HTT_RX_PEER_MAP_MAC_ADDR_OFFSET 4 /* bytes */ |
| 4820 | |
| 4821 | #define HTT_RX_PEER_MAP_BYTES 12 |
| 4822 | |
| 4823 | |
| 4824 | #define HTT_RX_PEER_UNMAP_PEER_ID_M HTT_RX_PEER_MAP_PEER_ID_M |
| 4825 | #define HTT_RX_PEER_UNMAP_PEER_ID_S HTT_RX_PEER_MAP_PEER_ID_S |
| 4826 | |
| 4827 | #define HTT_RX_PEER_UNMAP_PEER_ID_SET HTT_RX_PEER_MAP_PEER_ID_SET |
| 4828 | #define HTT_RX_PEER_UNMAP_PEER_ID_GET HTT_RX_PEER_MAP_PEER_ID_GET |
| 4829 | |
| 4830 | #define HTT_RX_PEER_UNMAP_VDEV_ID_SET HTT_RX_PEER_MAP_VDEV_ID_SET |
| 4831 | #define HTT_RX_PEER_UNMAP_VDEV_ID_GET HTT_RX_PEER_MAP_VDEV_ID_GET |
| 4832 | |
| 4833 | #define HTT_RX_PEER_UNMAP_BYTES 4 |
| 4834 | |
| 4835 | |
| 4836 | /** |
| 4837 | * @brief target -> host message specifying security parameters |
| 4838 | * |
| 4839 | * @details |
| 4840 | * The following diagram shows the format of the security specification |
| 4841 | * message sent from the target to the host. |
| 4842 | * This security specification message tells the host whether a PN check is |
| 4843 | * necessary on rx data frames, and if so, how large the PN counter is. |
| 4844 | * This message also tells the host about the security processing to apply |
| 4845 | * to defragmented rx frames - specifically, whether a Message Integrity |
| 4846 | * Check is required, and the Michael key to use. |
| 4847 | * |
| 4848 | * |31 24|23 16|15|14 8|7 0| |
| 4849 | * |-----------------------------------------------------------------------| |
| 4850 | * | peer ID | U| security type | msg type | |
| 4851 | * |-----------------------------------------------------------------------| |
| 4852 | * | Michael Key K0 | |
| 4853 | * |-----------------------------------------------------------------------| |
| 4854 | * | Michael Key K1 | |
| 4855 | * |-----------------------------------------------------------------------| |
| 4856 | * | WAPI RSC Low0 | |
| 4857 | * |-----------------------------------------------------------------------| |
| 4858 | * | WAPI RSC Low1 | |
| 4859 | * |-----------------------------------------------------------------------| |
| 4860 | * | WAPI RSC Hi0 | |
| 4861 | * |-----------------------------------------------------------------------| |
| 4862 | * | WAPI RSC Hi1 | |
| 4863 | * |-----------------------------------------------------------------------| |
| 4864 | * |
| 4865 | * The following field definitions describe the format of the security |
| 4866 | * indication message sent from the target to the host. |
| 4867 | * - MSG_TYPE |
| 4868 | * Bits 7:0 |
| 4869 | * Purpose: identifies this as a security specification message |
| 4870 | * Value: 0xb |
| 4871 | * - SEC_TYPE |
| 4872 | * Bits 14:8 |
| 4873 | * Purpose: specifies which type of security applies to the peer |
| 4874 | * Value: htt_sec_type enum value |
| 4875 | * - UNICAST |
| 4876 | * Bit 15 |
| 4877 | * Purpose: whether this security is applied to unicast or multicast data |
| 4878 | * Value: 1 -> unicast, 0 -> multicast |
| 4879 | * - PEER_ID |
| 4880 | * Bits 31:16 |
| 4881 | * Purpose: The ID number for the peer the security specification is for |
| 4882 | * Value: peer ID |
| 4883 | * - MICHAEL_KEY_K0 |
| 4884 | * Bits 31:0 |
| 4885 | * Purpose: 4-byte word that forms the 1st half of the TKIP Michael key |
| 4886 | * Value: Michael Key K0 (if security type is TKIP) |
| 4887 | * - MICHAEL_KEY_K1 |
| 4888 | * Bits 31:0 |
| 4889 | * Purpose: 4-byte word that forms the 2nd half of the TKIP Michael key |
| 4890 | * Value: Michael Key K1 (if security type is TKIP) |
| 4891 | * - WAPI_RSC_LOW0 |
| 4892 | * Bits 31:0 |
| 4893 | * Purpose: 4-byte word that forms the 1st quarter of the 16 byte WAPI RSC |
| 4894 | * Value: WAPI RSC Low0 (if security type is WAPI) |
| 4895 | * - WAPI_RSC_LOW1 |
| 4896 | * Bits 31:0 |
| 4897 | * Purpose: 4-byte word that forms the 2nd quarter of the 16 byte WAPI RSC |
| 4898 | * Value: WAPI RSC Low1 (if security type is WAPI) |
| 4899 | * - WAPI_RSC_HI0 |
| 4900 | * Bits 31:0 |
| 4901 | * Purpose: 4-byte word that forms the 3rd quarter of the 16 byte WAPI RSC |
| 4902 | * Value: WAPI RSC Hi0 (if security type is WAPI) |
| 4903 | * - WAPI_RSC_HI1 |
| 4904 | * Bits 31:0 |
| 4905 | * Purpose: 4-byte word that forms the 4th quarter of the 16 byte WAPI RSC |
| 4906 | * Value: WAPI RSC Hi1 (if security type is WAPI) |
| 4907 | */ |
| 4908 | |
| 4909 | #define HTT_SEC_IND_SEC_TYPE_M 0x00007f00 |
| 4910 | #define HTT_SEC_IND_SEC_TYPE_S 8 |
| 4911 | #define HTT_SEC_IND_UNICAST_M 0x00008000 |
| 4912 | #define HTT_SEC_IND_UNICAST_S 15 |
| 4913 | #define HTT_SEC_IND_PEER_ID_M 0xffff0000 |
| 4914 | #define HTT_SEC_IND_PEER_ID_S 16 |
| 4915 | |
| 4916 | #define HTT_SEC_IND_SEC_TYPE_SET(word, value) \ |
| 4917 | do { \ |
| 4918 | HTT_CHECK_SET_VAL(HTT_SEC_IND_SEC_TYPE, value); \ |
| 4919 | (word) |= (value) << HTT_SEC_IND_SEC_TYPE_S; \ |
| 4920 | } while (0) |
| 4921 | #define HTT_SEC_IND_SEC_TYPE_GET(word) \ |
| 4922 | (((word) & HTT_SEC_IND_SEC_TYPE_M) >> HTT_SEC_IND_SEC_TYPE_S) |
| 4923 | |
| 4924 | #define HTT_SEC_IND_UNICAST_SET(word, value) \ |
| 4925 | do { \ |
| 4926 | HTT_CHECK_SET_VAL(HTT_SEC_IND_UNICAST, value); \ |
| 4927 | (word) |= (value) << HTT_SEC_IND_UNICAST_S; \ |
| 4928 | } while (0) |
| 4929 | #define HTT_SEC_IND_UNICAST_GET(word) \ |
| 4930 | (((word) & HTT_SEC_IND_UNICAST_M) >> HTT_SEC_IND_UNICAST_S) |
| 4931 | |
| 4932 | #define HTT_SEC_IND_PEER_ID_SET(word, value) \ |
| 4933 | do { \ |
| 4934 | HTT_CHECK_SET_VAL(HTT_SEC_IND_PEER_ID, value); \ |
| 4935 | (word) |= (value) << HTT_SEC_IND_PEER_ID_S; \ |
| 4936 | } while (0) |
| 4937 | #define HTT_SEC_IND_PEER_ID_GET(word) \ |
| 4938 | (((word) & HTT_SEC_IND_PEER_ID_M) >> HTT_SEC_IND_PEER_ID_S) |
| 4939 | |
| 4940 | |
| 4941 | #define HTT_SEC_IND_BYTES 28 |
| 4942 | |
| 4943 | |
| 4944 | /** |
| 4945 | * @brief target -> host rx ADDBA / DELBA message definitions |
| 4946 | * |
| 4947 | * @details |
| 4948 | * The following diagram shows the format of the rx ADDBA message sent |
| 4949 | * from the target to the host: |
| 4950 | * |
| 4951 | * |31 20|19 16|15 8|7 0| |
| 4952 | * |---------------------------------------------------------------------| |
| 4953 | * | peer ID | TID | window size | msg type | |
| 4954 | * |---------------------------------------------------------------------| |
| 4955 | * |
| 4956 | * The following diagram shows the format of the rx DELBA message sent |
| 4957 | * from the target to the host: |
| 4958 | * |
| 4959 | * |31 20|19 16|15 8|7 0| |
| 4960 | * |---------------------------------------------------------------------| |
| 4961 | * | peer ID | TID | reserved | msg type | |
| 4962 | * |---------------------------------------------------------------------| |
| 4963 | * |
| 4964 | * The following field definitions describe the format of the rx ADDBA |
| 4965 | * and DELBA messages sent from the target to the host. |
| 4966 | * - MSG_TYPE |
| 4967 | * Bits 7:0 |
| 4968 | * Purpose: identifies this as an rx ADDBA or DELBA message |
| 4969 | * Value: ADDBA -> 0x5, DELBA -> 0x6 |
| 4970 | * - WIN_SIZE |
| 4971 | * Bits 15:8 (ADDBA only) |
| 4972 | * Purpose: Specifies the length of the block ack window (max = 64). |
| 4973 | * Value: |
| 4974 | * block ack window length specified by the received ADDBA |
| 4975 | * management message. |
| 4976 | * - TID |
| 4977 | * Bits 19:16 |
| 4978 | * Purpose: Specifies which traffic identifier the ADDBA / DELBA is for. |
| 4979 | * Value: |
| 4980 | * TID specified by the received ADDBA or DELBA management message. |
| 4981 | * - PEER_ID |
| 4982 | * Bits 31:20 |
| 4983 | * Purpose: Identifies which peer sent the ADDBA / DELBA. |
| 4984 | * Value: |
| 4985 | * ID (hash value) used by the host for fast, direct lookup of |
| 4986 | * host SW peer info, including rx reorder states. |
| 4987 | */ |
| 4988 | #define HTT_RX_ADDBA_WIN_SIZE_M 0xff00 |
| 4989 | #define HTT_RX_ADDBA_WIN_SIZE_S 8 |
| 4990 | #define HTT_RX_ADDBA_TID_M 0xf0000 |
| 4991 | #define HTT_RX_ADDBA_TID_S 16 |
| 4992 | #define HTT_RX_ADDBA_PEER_ID_M 0xfff00000 |
| 4993 | #define HTT_RX_ADDBA_PEER_ID_S 20 |
| 4994 | |
| 4995 | #define HTT_RX_ADDBA_WIN_SIZE_SET(word, value) \ |
| 4996 | do { \ |
| 4997 | HTT_CHECK_SET_VAL(HTT_RX_ADDBA_WIN_SIZE, value); \ |
| 4998 | (word) |= (value) << HTT_RX_ADDBA_WIN_SIZE_S; \ |
| 4999 | } while (0) |
| 5000 | #define HTT_RX_ADDBA_WIN_SIZE_GET(word) \ |
| 5001 | (((word) & HTT_RX_ADDBA_WIN_SIZE_M) >> HTT_RX_ADDBA_WIN_SIZE_S) |
| 5002 | |
| 5003 | #define HTT_RX_ADDBA_TID_SET(word, value) \ |
| 5004 | do { \ |
| 5005 | HTT_CHECK_SET_VAL(HTT_RX_ADDBA_TID, value); \ |
| 5006 | (word) |= (value) << HTT_RX_ADDBA_TID_S; \ |
| 5007 | } while (0) |
| 5008 | #define HTT_RX_ADDBA_TID_GET(word) \ |
| 5009 | (((word) & HTT_RX_ADDBA_TID_M) >> HTT_RX_ADDBA_TID_S) |
| 5010 | |
| 5011 | #define HTT_RX_ADDBA_PEER_ID_SET(word, value) \ |
| 5012 | do { \ |
| 5013 | HTT_CHECK_SET_VAL(HTT_RX_ADDBA_PEER_ID, value); \ |
| 5014 | (word) |= (value) << HTT_RX_ADDBA_PEER_ID_S; \ |
| 5015 | } while (0) |
| 5016 | #define HTT_RX_ADDBA_PEER_ID_GET(word) \ |
| 5017 | (((word) & HTT_RX_ADDBA_PEER_ID_M) >> HTT_RX_ADDBA_PEER_ID_S) |
| 5018 | |
| 5019 | #define HTT_RX_ADDBA_BYTES 4 |
| 5020 | |
| 5021 | |
| 5022 | #define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M |
| 5023 | #define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S |
| 5024 | #define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M |
| 5025 | #define HTT_RX_DELBA_PEER_ID_S HTT_RX_ADDBA_PEER_ID_S |
| 5026 | |
| 5027 | #define HTT_RX_DELBA_TID_SET HTT_RX_ADDBA_TID_SET |
| 5028 | #define HTT_RX_DELBA_TID_GET HTT_RX_ADDBA_TID_GET |
| 5029 | #define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET |
| 5030 | #define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET |
| 5031 | |
| 5032 | #define HTT_RX_DELBA_BYTES 4 |
| 5033 | |
| 5034 | /** |
| 5035 | * @brief tx queue group information element definition |
| 5036 | * |
| 5037 | * @details |
| 5038 | * The following diagram shows the format of the tx queue group |
| 5039 | * information element, which can be included in target --> host |
| 5040 | * messages to specify the number of tx "credits" (tx descriptors |
| 5041 | * for LL, or tx buffers for HL) available to a particular group |
| 5042 | * of host-side tx queues, and which host-side tx queues belong to |
| 5043 | * the group. |
| 5044 | * |
| 5045 | * |31|30 24|23 16|15|14|13 0| |
| 5046 | * |------------------------------------------------------------------------| |
| 5047 | * | X| reserved | tx queue grp ID | A| S| credit count | |
| 5048 | * |------------------------------------------------------------------------| |
| 5049 | * | vdev ID mask | AC mask | |
| 5050 | * |------------------------------------------------------------------------| |
| 5051 | * |
| 5052 | * The following definitions describe the fields within the tx queue group |
| 5053 | * information element: |
| 5054 | * - credit_count |
| 5055 | * Bits 13:1 |
| 5056 | * Purpose: specify how many tx credits are available to the tx queue group |
| 5057 | * Value: An absolute or relative, positive or negative credit value |
| 5058 | * The 'A' bit specifies whether the value is absolute or relative. |
| 5059 | * The 'S' bit specifies whether the value is positive or negative. |
| 5060 | * A negative value can only be relative, not absolute. |
| 5061 | * An absolute value replaces any prior credit value the host has for |
| 5062 | * the tx queue group in question. |
| 5063 | * A relative value is added to the prior credit value the host has for |
| 5064 | * the tx queue group in question. |
| 5065 | * - sign |
| 5066 | * Bit 14 |
| 5067 | * Purpose: specify whether the credit count is positive or negative |
| 5068 | * Value: 0 -> positive, 1 -> negative |
| 5069 | * - absolute |
| 5070 | * Bit 15 |
| 5071 | * Purpose: specify whether the credit count is absolute or relative |
| 5072 | * Value: 0 -> relative, 1 -> absolute |
| 5073 | * - txq_group_id |
| 5074 | * Bits 23:16 |
| 5075 | * Purpose: indicate which tx queue group's credit and/or membership are |
| 5076 | * being specified |
| 5077 | * Value: 0 to max_tx_queue_groups-1 |
| 5078 | * - reserved |
| 5079 | * Bits 30:16 |
| 5080 | * Value: 0x0 |
| 5081 | * - eXtension |
| 5082 | * Bit 31 |
| 5083 | * Purpose: specify whether another tx queue group info element follows |
| 5084 | * Value: 0 -> no more tx queue group information elements |
| 5085 | * 1 -> another tx queue group information element immediately follows |
| 5086 | * - ac_mask |
| 5087 | * Bits 15:0 |
| 5088 | * Purpose: specify which Access Categories belong to the tx queue group |
| 5089 | * Value: bit-OR of masks for the ACs (WMM and extension) that belong to |
| 5090 | * the tx queue group. |
| 5091 | * The AC bit-mask values are obtained by left-shifting by the |
| 5092 | * corresponding HTT_AC_WMM enum values, e.g. (1 << HTT_AC_WMM_BE) == 0x1 |
| 5093 | * - vdev_id_mask |
| 5094 | * Bits 31:16 |
| 5095 | * Purpose: specify which vdev's tx queues belong to the tx queue group |
| 5096 | * Value: bit-OR of masks based on the IDs of the vdevs whose tx queues |
| 5097 | * belong to the tx queue group. |
| 5098 | * For example, if vdev IDs 1 and 4 belong to a tx queue group, the |
| 5099 | * vdev_id_mask would be (1 << 1) | (1 << 4) = 0x12 |
| 5100 | */ |
| 5101 | PREPACK struct htt_txq_group { |
| 5102 | A_UINT32 |
| 5103 | credit_count:14, |
| 5104 | sign:1, |
| 5105 | absolute:1, |
| 5106 | tx_queue_group_id:8, |
| 5107 | reserved0:7, |
| 5108 | extension:1; |
| 5109 | A_UINT32 |
| 5110 | ac_mask:16, |
| 5111 | vdev_id_mask:16; |
| 5112 | } POSTPACK; |
| 5113 | |
| 5114 | /* first word */ |
| 5115 | #define HTT_TXQ_GROUP_CREDIT_COUNT_S 0 |
| 5116 | #define HTT_TXQ_GROUP_CREDIT_COUNT_M 0x00003fff |
| 5117 | #define HTT_TXQ_GROUP_SIGN_S 14 |
| 5118 | #define HTT_TXQ_GROUP_SIGN_M 0x00004000 |
| 5119 | #define HTT_TXQ_GROUP_ABS_S 15 |
| 5120 | #define HTT_TXQ_GROUP_ABS_M 0x00008000 |
| 5121 | #define HTT_TXQ_GROUP_ID_S 16 |
| 5122 | #define HTT_TXQ_GROUP_ID_M 0x00ff0000 |
| 5123 | #define HTT_TXQ_GROUP_EXT_S 31 |
| 5124 | #define HTT_TXQ_GROUP_EXT_M 0x80000000 |
| 5125 | /* second word */ |
| 5126 | #define HTT_TXQ_GROUP_AC_MASK_S 0 |
| 5127 | #define HTT_TXQ_GROUP_AC_MASK_M 0x0000ffff |
| 5128 | #define HTT_TXQ_GROUP_VDEV_ID_MASK_S 16 |
| 5129 | #define HTT_TXQ_GROUP_VDEV_ID_MASK_M 0xffff0000 |
| 5130 | |
| 5131 | #define HTT_TXQ_GROUP_CREDIT_COUNT_SET(_info, _val) \ |
| 5132 | do { \ |
| 5133 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_CREDIT_COUNT, _val); \ |
| 5134 | ((_info) |= ((_val) << HTT_TXQ_GROUP_CREDIT_COUNT_S)); \ |
| 5135 | } while (0) |
| 5136 | #define HTT_TXQ_GROUP_CREDIT_COUNT_GET(_info) \ |
| 5137 | (((_info) & HTT_TXQ_GROUP_CREDIT_COUNT_M) >> \ |
| 5138 | HTT_TXQ_GROUP_CREDIT_COUNT_S) |
| 5139 | |
| 5140 | #define HTT_TXQ_GROUP_SIGN_SET(_info, _val) \ |
| 5141 | do { \ |
| 5142 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_SIGN, _val); \ |
| 5143 | ((_info) |= ((_val) << HTT_TXQ_GROUP_SIGN_S)); \ |
| 5144 | } while (0) |
| 5145 | #define HTT_TXQ_GROUP_SIGN_GET(_info) \ |
| 5146 | (((_info) & HTT_TXQ_GROUP_SIGN_M) >> HTT_TXQ_GROUP_SIGN_S) |
| 5147 | |
| 5148 | #define HTT_TXQ_GROUP_ABS_SET(_info, _val) \ |
| 5149 | do { \ |
| 5150 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ABS, _val); \ |
| 5151 | ((_info) |= ((_val) << HTT_TXQ_GROUP_ABS_S)); \ |
| 5152 | } while (0) |
| 5153 | #define HTT_TXQ_GROUP_ABS_GET(_info) \ |
| 5154 | (((_info) & HTT_TXQ_GROUP_ABS_M) >> HTT_TXQ_GROUP_ABS_S) |
| 5155 | |
| 5156 | #define HTT_TXQ_GROUP_ID_SET(_info, _val) \ |
| 5157 | do { \ |
| 5158 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_ID, _val); \ |
| 5159 | ((_info) |= ((_val) << HTT_TXQ_GROUP_ID_S)); \ |
| 5160 | } while (0) |
| 5161 | #define HTT_TXQ_GROUP_ID_GET(_info) \ |
| 5162 | (((_info) & HTT_TXQ_GROUP_ID_M) >> HTT_TXQ_GROUP_ID_S) |
| 5163 | |
| 5164 | #define HTT_TXQ_GROUP_EXT_SET(_info, _val) \ |
| 5165 | do { \ |
| 5166 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_EXT, _val); \ |
| 5167 | ((_info) |= ((_val) << HTT_TXQ_GROUP_EXT_S)); \ |
| 5168 | } while (0) |
| 5169 | #define HTT_TXQ_GROUP_EXT_GET(_info) \ |
| 5170 | (((_info) & HTT_TXQ_GROUP_EXT_M) >> HTT_TXQ_GROUP_EXT_S) |
| 5171 | |
| 5172 | #define HTT_TXQ_GROUP_AC_MASK_SET(_info, _val) \ |
| 5173 | do { \ |
| 5174 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_AC_MASK, _val); \ |
| 5175 | ((_info) |= ((_val) << HTT_TXQ_GROUP_AC_MASK_S)); \ |
| 5176 | } while (0) |
| 5177 | #define HTT_TXQ_GROUP_AC_MASK_GET(_info) \ |
| 5178 | (((_info) & HTT_TXQ_GROUP_AC_MASK_M) >> HTT_TXQ_GROUP_AC_MASK_S) |
| 5179 | |
| 5180 | #define HTT_TXQ_GROUP_VDEV_ID_MASK_SET(_info, _val) \ |
| 5181 | do { \ |
| 5182 | HTT_CHECK_SET_VAL(HTT_TXQ_GROUP_VDEV_ID_MASK, _val); \ |
| 5183 | ((_info) |= ((_val) << HTT_TXQ_GROUP_VDEV_ID_MASK_S)); \ |
| 5184 | } while (0) |
| 5185 | #define HTT_TXQ_GROUP_VDEV_ID_MASK_GET(_info) \ |
| 5186 | (((_info) & HTT_TXQ_GROUP_VDEV_ID_MASK_M) >> \ |
| 5187 | HTT_TXQ_GROUP_VDEV_ID_MASK_S) |
| 5188 | |
| 5189 | /** |
| 5190 | * @brief target -> host TX completion indication message definition |
| 5191 | * |
| 5192 | * @details |
| 5193 | * The following diagram shows the format of the TX completion indication sent |
| 5194 | * from the target to the host |
| 5195 | * |
| 5196 | * |31 25| 24|23 16| 15 |14 11|10 8|7 0| |
| 5197 | * |-------------------------------------------------------------| |
| 5198 | * header: | reserved |append| num | t_i| tid |status| msg_type | |
| 5199 | * |-------------------------------------------------------------| |
| 5200 | * payload: | MSDU1 ID | MSDU0 ID | |
| 5201 | * |-------------------------------------------------------------| |
| 5202 | * : MSDU3 ID : MSDU2 ID : |
| 5203 | * |-------------------------------------------------------------| |
| 5204 | * | struct htt_tx_compl_ind_append_retries | |
| 5205 | * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| 5206 | * |
| 5207 | * The following field definitions describe the format of the TX completion |
| 5208 | * indication sent from the target to the host |
| 5209 | * Header fields: |
| 5210 | * - msg_type |
| 5211 | * Bits 7:0 |
| 5212 | * Purpose: identifies this as HTT TX completion indication |
| 5213 | * Value: 0x7 |
| 5214 | * - status |
| 5215 | * Bits 10:8 |
| 5216 | * Purpose: the TX completion status of payload fragmentations descriptors |
| 5217 | * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD |
| 5218 | * - tid |
| 5219 | * Bits 14:11 |
| 5220 | * Purpose: the tid associated with those fragmentation descriptors. It is |
| 5221 | * valid or not, depending on the tid_invalid bit. |
| 5222 | * Value: 0 to 15 |
| 5223 | * - tid_invalid |
| 5224 | * Bits 15:15 |
| 5225 | * Purpose: this bit indicates whether the tid field is valid or not |
| 5226 | * Value: 0 indicates valid; 1 indicates invalid |
| 5227 | * - num |
| 5228 | * Bits 23:16 |
| 5229 | * Purpose: the number of payload in this indication |
| 5230 | * Value: 1 to 255 |
| 5231 | * - append |
| 5232 | * Bits 24:24 |
| 5233 | * Purpose: append the struct htt_tx_compl_ind_append_retries which contains |
| 5234 | * the number of tx retries for one MSDU at the end of this message |
| 5235 | * Value: 0 indicates no appending; 1 indicates appending |
| 5236 | * Payload fields: |
| 5237 | * - hmsdu_id |
| 5238 | * Bits 15:0 |
| 5239 | * Purpose: this ID is used to track the Tx buffer in host |
| 5240 | * Value: 0 to "size of host MSDU descriptor pool - 1" |
| 5241 | */ |
| 5242 | |
| 5243 | #define HTT_TX_COMPL_IND_STATUS_S 8 |
| 5244 | #define HTT_TX_COMPL_IND_STATUS_M 0x00000700 |
| 5245 | #define HTT_TX_COMPL_IND_TID_S 11 |
| 5246 | #define HTT_TX_COMPL_IND_TID_M 0x00007800 |
| 5247 | #define HTT_TX_COMPL_IND_TID_INV_S 15 |
| 5248 | #define HTT_TX_COMPL_IND_TID_INV_M 0x00008000 |
| 5249 | #define HTT_TX_COMPL_IND_NUM_S 16 |
| 5250 | #define HTT_TX_COMPL_IND_NUM_M 0x00ff0000 |
| 5251 | #define HTT_TX_COMPL_IND_APPEND_S 24 |
| 5252 | #define HTT_TX_COMPL_IND_APPEND_M 0x01000000 |
| 5253 | |
| 5254 | #define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \ |
| 5255 | do { \ |
| 5256 | HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_STATUS, _val); \ |
| 5257 | ((_info) |= ((_val) << HTT_TX_COMPL_IND_STATUS_S)); \ |
| 5258 | } while (0) |
| 5259 | #define HTT_TX_COMPL_IND_STATUS_GET(_info) \ |
| 5260 | (((_info) & HTT_TX_COMPL_IND_STATUS_M) >> HTT_TX_COMPL_IND_STATUS_S) |
| 5261 | #define HTT_TX_COMPL_IND_NUM_SET(_info, _val) \ |
| 5262 | do { \ |
| 5263 | HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_NUM, _val); \ |
| 5264 | ((_info) |= ((_val) << HTT_TX_COMPL_IND_NUM_S)); \ |
| 5265 | } while (0) |
| 5266 | #define HTT_TX_COMPL_IND_NUM_GET(_info) \ |
| 5267 | (((_info) & HTT_TX_COMPL_IND_NUM_M) >> HTT_TX_COMPL_IND_NUM_S) |
| 5268 | #define HTT_TX_COMPL_IND_TID_SET(_info, _val) \ |
| 5269 | do { \ |
| 5270 | HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID, _val); \ |
| 5271 | ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_S)); \ |
| 5272 | } while (0) |
| 5273 | #define HTT_TX_COMPL_IND_TID_GET(_info) \ |
| 5274 | (((_info) & HTT_TX_COMPL_IND_TID_M) >> HTT_TX_COMPL_IND_TID_S) |
| 5275 | #define HTT_TX_COMPL_IND_TID_INV_SET(_info, _val) \ |
| 5276 | do { \ |
| 5277 | HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_TID_INV, _val); \ |
| 5278 | ((_info) |= ((_val) << HTT_TX_COMPL_IND_TID_INV_S)); \ |
| 5279 | } while (0) |
| 5280 | #define HTT_TX_COMPL_IND_TID_INV_GET(_info) \ |
| 5281 | (((_info) & HTT_TX_COMPL_IND_TID_INV_M) >> \ |
| 5282 | HTT_TX_COMPL_IND_TID_INV_S) |
| 5283 | #define HTT_TX_COMPL_IND_APPEND_SET(_info, _val) \ |
| 5284 | do { \ |
| 5285 | HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND, _val); \ |
| 5286 | ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND_S)); \ |
| 5287 | } while (0) |
| 5288 | #define HTT_TX_COMPL_IND_APPEND_GET(_info) \ |
| 5289 | (((_info) & HTT_TX_COMPL_IND_APPEND_M) >> HTT_TX_COMPL_IND_APPEND_S) |
| 5290 | |
| 5291 | #define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16) |
| 5292 | #define HTT_TX_COMPL_CTXT_NUM(_bytes) ((_bytes) >> 1) |
| 5293 | |
| 5294 | #define HTT_TX_COMPL_INV_MSDU_ID 0xffff |
| 5295 | |
| 5296 | #define HTT_TX_COMPL_IND_STAT_OK 0 |
| 5297 | #define HTT_TX_COMPL_IND_STAT_DISCARD 1 |
| 5298 | #define HTT_TX_COMPL_IND_STAT_NO_ACK 2 |
| 5299 | #define HTT_TX_COMPL_IND_STAT_POSTPONE 3 |
| 5300 | /* |
| 5301 | * The PEER_DEL tx completion status is used for HL cases |
| 5302 | * where the peer the frame is for has been deleted. |
| 5303 | * The host has already discarded its copy of the frame, but |
| 5304 | * it still needs the tx completion to restore its credit. |
| 5305 | */ |
| 5306 | #define HTT_TX_COMPL_IND_STAT_PEER_DEL 4 |
| 5307 | |
| 5308 | |
| 5309 | #define HTT_TX_COMPL_IND_APPEND_SET_MORE_RETRY(f) ((f) |= 0x1) |
| 5310 | #define HTT_TX_COMPL_IND_APPEND_CLR_MORE_RETRY(f) ((f) &= (~0x1)) |
| 5311 | |
| 5312 | PREPACK struct htt_tx_compl_ind_base { |
| 5313 | A_UINT32 hdr; |
| 5314 | A_UINT16 payload[1 /*or more */]; |
| 5315 | } POSTPACK; |
| 5316 | |
| 5317 | PREPACK struct htt_tx_compl_ind_append_retries { |
| 5318 | A_UINT16 msdu_id; |
| 5319 | A_UINT8 tx_retries; |
| 5320 | A_UINT8 flag;/* Bit 0, 1: another append_retries struct is appended |
| 5321 | 0: this is the last append_retries struct */ |
| 5322 | } POSTPACK; |
| 5323 | |
| 5324 | /** |
| 5325 | * @brief target -> host rate-control update indication message |
| 5326 | * |
| 5327 | * @details |
| 5328 | * The following diagram shows the format of the RC Update message |
| 5329 | * sent from the target to the host, while processing the tx-completion |
| 5330 | * of a transmitted PPDU. |
| 5331 | * |
| 5332 | * |31 24|23 16|15 8|7 0| |
| 5333 | * |-------------------------------------------------------------| |
| 5334 | * | peer ID | vdev ID | msg_type | |
| 5335 | * |-------------------------------------------------------------| |
| 5336 | * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | |
| 5337 | * |-------------------------------------------------------------| |
| 5338 | * | reserved | num elems | MAC addr 5 | MAC addr 4 | |
| 5339 | * |-------------------------------------------------------------| |
| 5340 | * | : | |
| 5341 | * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : |
| 5342 | * | : | |
| 5343 | * |-------------------------------------------------------------| |
| 5344 | * | : | |
| 5345 | * : HTT_RC_TX_DONE_PARAMS (DWORD-aligned) : |
| 5346 | * | : | |
| 5347 | * |-------------------------------------------------------------| |
| 5348 | * : : |
| 5349 | * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| 5350 | * |
| 5351 | */ |
| 5352 | |
| 5353 | typedef struct { |
| 5354 | A_UINT32 rate_code; /* rate code, bw, chain mask sgi */ |
| 5355 | A_UINT32 rate_code_flags; |
| 5356 | A_UINT32 flags; /* Encodes information such as excessive |
| 5357 | retransmission, aggregate, some info |
| 5358 | from .11 frame control, |
| 5359 | STBC, LDPC, (SGI and Tx Chain Mask |
| 5360 | are encoded in ptx_rc->flags field), |
| 5361 | AMPDU truncation (BT/time based etc.), |
| 5362 | RTS/CTS attempt */ |
| 5363 | |
| 5364 | A_UINT32 num_enqued;/* # of MPDUs (for non-AMPDU 1) for this rate */ |
| 5365 | A_UINT32 num_retries;/* Total # of transmission attempt for this rate */ |
| 5366 | A_UINT32 num_failed;/* # of failed MPDUs in A-MPDU, 0 otherwise */ |
| 5367 | A_UINT32 ack_rssi;/* ACK RSSI: b'7..b'0 avg RSSI across all chain */ |
| 5368 | A_UINT32 time_stamp; /* ACK timestamp (helps determine age) */ |
| 5369 | A_UINT32 is_probe; /* Valid if probing. Else, 0 */ |
| 5370 | } HTT_RC_TX_DONE_PARAMS; |
| 5371 | |
| 5372 | #define HTT_RC_UPDATE_CTXT_SZ (sizeof(HTT_RC_TX_DONE_PARAMS))/* bytes */ |
| 5373 | #define HTT_RC_UPDATE_HDR_SZ (12) /* bytes */ |
| 5374 | |
| 5375 | #define HTT_RC_UPDATE_MAC_ADDR_OFFSET (4) /* bytes */ |
| 5376 | #define HTT_RC_UPDATE_MAC_ADDR_LENGTH IEEE80211_ADDR_LEN /* bytes */ |
| 5377 | |
| 5378 | #define HTT_RC_UPDATE_VDEVID_S 8 |
| 5379 | #define HTT_RC_UPDATE_VDEVID_M 0xff00 |
| 5380 | #define HTT_RC_UPDATE_PEERID_S 16 |
| 5381 | #define HTT_RC_UPDATE_PEERID_M 0xffff0000 |
| 5382 | |
| 5383 | #define HTT_RC_UPDATE_NUM_ELEMS_S 16 |
| 5384 | #define HTT_RC_UPDATE_NUM_ELEMS_M 0x00ff0000 |
| 5385 | |
| 5386 | #define HTT_RC_UPDATE_VDEVID_SET(_info, _val) \ |
| 5387 | do { \ |
| 5388 | HTT_CHECK_SET_VAL(HTT_RC_UPDATE_VDEVID, _val); \ |
| 5389 | ((_info) |= ((_val) << HTT_RC_UPDATE_VDEVID_S)); \ |
| 5390 | } while (0) |
| 5391 | |
| 5392 | #define HTT_RC_UPDATE_VDEVID_GET(_info) \ |
| 5393 | (((_info) & HTT_RC_UPDATE_VDEVID_M) >> HTT_RC_UPDATE_VDEVID_S) |
| 5394 | |
| 5395 | #define HTT_RC_UPDATE_PEERID_SET(_info, _val) \ |
| 5396 | do { \ |
| 5397 | HTT_CHECK_SET_VAL(HTT_RC_UPDATE_PEERID, _val); \ |
| 5398 | ((_info) |= ((_val) << HTT_RC_UPDATE_PEERID_S)); \ |
| 5399 | } while (0) |
| 5400 | |
| 5401 | #define HTT_RC_UPDATE_PEERID_GET(_info) \ |
| 5402 | (((_info) & HTT_RC_UPDATE_PEERID_M) >> HTT_RC_UPDATE_PEERID_S) |
| 5403 | |
| 5404 | #define HTT_RC_UPDATE_NUM_ELEMS_SET(_info, _val) \ |
| 5405 | do { \ |
| 5406 | HTT_CHECK_SET_VAL(HTT_RC_UPDATE_NUM_ELEMS, _val); \ |
| 5407 | ((_info) |= ((_val) << HTT_RC_UPDATE_NUM_ELEMS_S)); \ |
| 5408 | } while (0) |
| 5409 | |
| 5410 | #define HTT_RC_UPDATE_NUM_ELEMS_GET(_info) \ |
| 5411 | (((_info) & HTT_RC_UPDATE_NUM_ELEMS_M) >> HTT_RC_UPDATE_NUM_ELEMS_S) |
| 5412 | |
| 5413 | /** |
| 5414 | * @brief target -> host rx fragment indication message definition |
| 5415 | * |
| 5416 | * @details |
| 5417 | * The following field definitions describe the format of the rx fragment |
| 5418 | * indication message sent from the target to the host. |
| 5419 | * The rx fragment indication message shares the format of the |
| 5420 | * rx indication message, but not all fields from the rx indication message |
| 5421 | * are relevant to the rx fragment indication message. |
| 5422 | * |
| 5423 | * |
| 5424 | * |31 24|23 18|17|16|15|14|13|12|11|10|9|8|7|6|5|4 0| |
| 5425 | * |-----------+-------------------+---------------------+-------------| |
| 5426 | * | peer ID | |FV| ext TID | msg type | |
| 5427 | * |-------------------------------------------------------------------| |
| 5428 | * | | flush | flush | |
| 5429 | * | | end | start | |
| 5430 | * | | seq num | seq num | |
| 5431 | * |-------------------------------------------------------------------| |
| 5432 | * | reserved | FW rx desc bytes | |
| 5433 | * |-------------------------------------------------------------------| |
| 5434 | * | | FW MSDU Rx | |
| 5435 | * | | desc B0 | |
| 5436 | * |-------------------------------------------------------------------| |
| 5437 | * Header fields: |
| 5438 | * - MSG_TYPE |
| 5439 | * Bits 7:0 |
| 5440 | * Purpose: identifies this as an rx fragment indication message |
| 5441 | * Value: 0xa |
| 5442 | * - EXT_TID |
| 5443 | * Bits 12:8 |
| 5444 | * Purpose: identify the traffic ID of the rx data, including |
| 5445 | * special "extended" TID values for multicast, broadcast, and |
| 5446 | * non-QoS data frames |
| 5447 | * Value: 0-15 for regular TIDs, or >= 16 for bcast/mcast/non-QoS |
| 5448 | * - FLUSH_VALID (FV) |
| 5449 | * Bit 13 |
| 5450 | * Purpose: indicate whether the flush IE (start/end sequence numbers) |
| 5451 | * is valid |
| 5452 | * Value: |
| 5453 | * 1 -> flush IE is valid and needs to be processed |
| 5454 | * 0 -> flush IE is not valid and should be ignored |
| 5455 | * - PEER_ID |
| 5456 | * Bits 31:16 |
| 5457 | * Purpose: Identify, by ID, which peer sent the rx data |
| 5458 | * Value: ID of the peer who sent the rx data |
| 5459 | * - FLUSH_SEQ_NUM_START |
| 5460 | * Bits 5:0 |
| 5461 | * Purpose: Indicate the start of a series of MPDUs to flush |
| 5462 | * Not all MPDUs within this series are necessarily valid - the host |
| 5463 | * must check each sequence number within this range to see if the |
| 5464 | * corresponding MPDU is actually present. |
| 5465 | * This field is only valid if the FV bit is set. |
| 5466 | * Value: |
| 5467 | * The sequence number for the first MPDUs to check to flush. |
| 5468 | * The sequence number is masked by 0x3f. |
| 5469 | * - FLUSH_SEQ_NUM_END |
| 5470 | * Bits 11:6 |
| 5471 | * Purpose: Indicate the end of a series of MPDUs to flush |
| 5472 | * Value: |
| 5473 | * The sequence number one larger than the sequence number of the |
| 5474 | * last MPDU to check to flush. |
| 5475 | * The sequence number is masked by 0x3f. |
| 5476 | * Not all MPDUs within this series are necessarily valid - the host |
| 5477 | * must check each sequence number within this range to see if the |
| 5478 | * corresponding MPDU is actually present. |
| 5479 | * This field is only valid if the FV bit is set. |
| 5480 | * Rx descriptor fields: |
| 5481 | * - FW_RX_DESC_BYTES |
| 5482 | * Bits 15:0 |
| 5483 | * Purpose: Indicate how many bytes in the Rx indication are used for |
| 5484 | * FW Rx descriptors |
| 5485 | * Value: 1 |
| 5486 | */ |
| 5487 | #define HTT_RX_FRAG_IND_HDR_PREFIX_SIZE32 2 |
| 5488 | |
| 5489 | #define HTT_RX_FRAG_IND_FW_DESC_BYTE_OFFSET 12 |
| 5490 | |
| 5491 | #define HTT_RX_FRAG_IND_EXT_TID_SET HTT_RX_IND_EXT_TID_SET |
| 5492 | #define HTT_RX_FRAG_IND_EXT_TID_GET HTT_RX_IND_EXT_TID_GET |
| 5493 | |
| 5494 | #define HTT_RX_FRAG_IND_PEER_ID_SET HTT_RX_IND_PEER_ID_SET |
| 5495 | #define HTT_RX_FRAG_IND_PEER_ID_GET HTT_RX_IND_PEER_ID_GET |
| 5496 | |
| 5497 | #define HTT_RX_FRAG_IND_FLUSH_VALID_SET HTT_RX_IND_FLUSH_VALID_SET |
| 5498 | #define HTT_RX_FRAG_IND_FLUSH_VALID_GET HTT_RX_IND_FLUSH_VALID_GET |
| 5499 | |
| 5500 | #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_SET \ |
| 5501 | HTT_RX_IND_FLUSH_SEQ_NUM_START_SET |
| 5502 | #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_START_GET \ |
| 5503 | HTT_RX_IND_FLUSH_SEQ_NUM_START_GET |
| 5504 | |
| 5505 | #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_SET \ |
| 5506 | HTT_RX_IND_FLUSH_SEQ_NUM_END_SET |
| 5507 | #define HTT_RX_FRAG_IND_FLUSH_SEQ_NUM_END_GET \ |
| 5508 | HTT_RX_IND_FLUSH_SEQ_NUM_END_GET |
| 5509 | |
| 5510 | #define HTT_RX_FRAG_IND_FW_RX_DESC_BYTES_GET HTT_RX_IND_FW_RX_DESC_BYTES_GET |
| 5511 | |
| 5512 | #define HTT_RX_FRAG_IND_BYTES \ |
| 5513 | (4 /* msg hdr */ + \ |
| 5514 | 4 /* flush spec */ + \ |
| 5515 | 4 /* (unused) FW rx desc bytes spec */ + \ |
| 5516 | 4 /* FW rx desc */) |
| 5517 | |
| 5518 | /** |
| 5519 | * @brief target -> host test message definition |
| 5520 | * |
| 5521 | * @details |
| 5522 | * The following field definitions describe the format of the test |
| 5523 | * message sent from the target to the host. |
| 5524 | * The message consists of a 4-octet header, followed by a variable |
| 5525 | * number of 32-bit integer values, followed by a variable number |
| 5526 | * of 8-bit character values. |
| 5527 | * |
| 5528 | * |31 16|15 8|7 0| |
| 5529 | * |-----------------------------------------------------------| |
| 5530 | * | num chars | num ints | msg type | |
| 5531 | * |-----------------------------------------------------------| |
| 5532 | * | int 0 | |
| 5533 | * |-----------------------------------------------------------| |
| 5534 | * | int 1 | |
| 5535 | * |-----------------------------------------------------------| |
| 5536 | * | ... | |
| 5537 | * |-----------------------------------------------------------| |
| 5538 | * | char 3 | char 2 | char 1 | char 0 | |
| 5539 | * |-----------------------------------------------------------| |
| 5540 | * | | | ... | char 4 | |
| 5541 | * |-----------------------------------------------------------| |
| 5542 | * - MSG_TYPE |
| 5543 | * Bits 7:0 |
| 5544 | * Purpose: identifies this as a test message |
| 5545 | * Value: HTT_MSG_TYPE_TEST |
| 5546 | * - NUM_INTS |
| 5547 | * Bits 15:8 |
| 5548 | * Purpose: indicate how many 32-bit integers follow the message header |
| 5549 | * - NUM_CHARS |
| 5550 | * Bits 31:16 |
| 5551 | * Purpose: indicate how many 8-bit charaters follow the series of integers |
| 5552 | */ |
| 5553 | #define HTT_RX_TEST_NUM_INTS_M 0xff00 |
| 5554 | #define HTT_RX_TEST_NUM_INTS_S 8 |
| 5555 | #define HTT_RX_TEST_NUM_CHARS_M 0xffff0000 |
| 5556 | #define HTT_RX_TEST_NUM_CHARS_S 16 |
| 5557 | |
| 5558 | #define HTT_RX_TEST_NUM_INTS_SET(word, value) \ |
| 5559 | do { \ |
| 5560 | HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_INTS, value); \ |
| 5561 | (word) |= (value) << HTT_RX_TEST_NUM_INTS_S; \ |
| 5562 | } while (0) |
| 5563 | #define HTT_RX_TEST_NUM_INTS_GET(word) \ |
| 5564 | (((word) & HTT_RX_TEST_NUM_INTS_M) >> HTT_RX_TEST_NUM_INTS_S) |
| 5565 | |
| 5566 | #define HTT_RX_TEST_NUM_CHARS_SET(word, value) \ |
| 5567 | do { \ |
| 5568 | HTT_CHECK_SET_VAL(HTT_RX_TEST_NUM_CHARS, value); \ |
| 5569 | (word) |= (value) << HTT_RX_TEST_NUM_CHARS_S; \ |
| 5570 | } while (0) |
| 5571 | #define HTT_RX_TEST_NUM_CHARS_GET(word) \ |
| 5572 | (((word) & HTT_RX_TEST_NUM_CHARS_M) >> HTT_RX_TEST_NUM_CHARS_S) |
| 5573 | |
| 5574 | /** |
| 5575 | * @brief target -> host packet log message |
| 5576 | * |
| 5577 | * @details |
| 5578 | * The following field definitions describe the format of the packet log |
| 5579 | * message sent from the target to the host. |
| 5580 | * The message consists of a 4-octet header,followed by a variable number |
| 5581 | * of 32-bit character values. |
| 5582 | * |
| 5583 | * |31 24|23 16|15 8|7 0| |
| 5584 | * |-----------------------------------------------------------| |
| 5585 | * | | | | msg type | |
| 5586 | * |-----------------------------------------------------------| |
| 5587 | * | payload | |
| 5588 | * |-----------------------------------------------------------| |
| 5589 | * - MSG_TYPE |
| 5590 | * Bits 7:0 |
| 5591 | * Purpose: identifies this as a test message |
| 5592 | * Value: HTT_MSG_TYPE_PACKETLOG |
| 5593 | */ |
| 5594 | PREPACK struct htt_pktlog_msg { |
| 5595 | A_UINT32 header; |
| 5596 | A_UINT32 payload[1 /* or more */]; |
| 5597 | } POSTPACK; |
| 5598 | |
| 5599 | |
| 5600 | /* |
| 5601 | * Rx reorder statistics |
| 5602 | * NB: all the fields must be defined in 4 octets size. |
| 5603 | */ |
| 5604 | struct rx_reorder_stats { |
| 5605 | /* Non QoS MPDUs received */ |
| 5606 | A_UINT32 deliver_non_qos; |
| 5607 | /* MPDUs received in-order */ |
| 5608 | A_UINT32 deliver_in_order; |
| 5609 | /* Flush due to reorder timer expired */ |
| 5610 | A_UINT32 deliver_flush_timeout; |
| 5611 | /* Flush due to move out of window */ |
| 5612 | A_UINT32 deliver_flush_oow; |
| 5613 | /* Flush due to DELBA */ |
| 5614 | A_UINT32 deliver_flush_delba; |
| 5615 | /* MPDUs dropped due to FCS error */ |
| 5616 | A_UINT32 fcs_error; |
| 5617 | /* MPDUs dropped due to monitor mode non-data packet */ |
| 5618 | A_UINT32 mgmt_ctrl; |
| 5619 | /* Unicast-data MPDUs dropped due to invalid peer */ |
| 5620 | A_UINT32 invalid_peer; |
| 5621 | /* MPDUs dropped due to duplication (non aggregation) */ |
| 5622 | A_UINT32 dup_non_aggr; |
| 5623 | /* MPDUs dropped due to processed before */ |
| 5624 | A_UINT32 dup_past; |
| 5625 | /* MPDUs dropped due to duplicate in reorder queue */ |
| 5626 | A_UINT32 dup_in_reorder; |
| 5627 | /* Reorder timeout happened */ |
| 5628 | A_UINT32 reorder_timeout; |
| 5629 | /* invalid bar ssn */ |
| 5630 | A_UINT32 invalid_bar_ssn; |
| 5631 | /* reorder reset due to bar ssn */ |
| 5632 | A_UINT32 ssn_reset; |
| 5633 | /* Flush due to delete peer */ |
| 5634 | A_UINT32 deliver_flush_delpeer; |
| 5635 | /* Flush due to offload */ |
| 5636 | A_UINT32 deliver_flush_offload; |
| 5637 | /* Flush due to out of buffer */ |
| 5638 | A_UINT32 deliver_flush_oob; |
| 5639 | /* MPDUs dropped due to PN check fail */ |
| 5640 | A_UINT32 pn_fail; |
| 5641 | /* MPDUs dropped due to unable to allocate memory */ |
| 5642 | A_UINT32 store_fail; |
| 5643 | /* Number of times the tid pool alloc succeeded */ |
| 5644 | A_UINT32 tid_pool_alloc_succ; |
| 5645 | /* Number of times the MPDU pool alloc succeeded */ |
| 5646 | A_UINT32 mpdu_pool_alloc_succ; |
| 5647 | /* Number of times the MSDU pool alloc succeeded */ |
| 5648 | A_UINT32 msdu_pool_alloc_succ; |
| 5649 | /* Number of times the tid pool alloc failed */ |
| 5650 | A_UINT32 tid_pool_alloc_fail; |
| 5651 | /* Number of times the MPDU pool alloc failed */ |
| 5652 | A_UINT32 mpdu_pool_alloc_fail; |
| 5653 | /* Number of times the MSDU pool alloc failed */ |
| 5654 | A_UINT32 msdu_pool_alloc_fail; |
| 5655 | /* Number of times the tid pool freed */ |
| 5656 | A_UINT32 tid_pool_free; |
| 5657 | /* Number of times the MPDU pool freed */ |
| 5658 | A_UINT32 mpdu_pool_free; |
| 5659 | /* Number of times the MSDU pool freed */ |
| 5660 | A_UINT32 msdu_pool_free; |
| 5661 | /* number of MSDUs undelivered to HTT and queued |
| 5662 | * to Data Rx MSDU free list */ |
| 5663 | A_UINT32 msdu_queued; |
| 5664 | /* Number of MSDUs released from Data Rx MSDU list to MAC ring */ |
| 5665 | A_UINT32 msdu_recycled; |
| 5666 | /* Number of MPDUs with invalid peer but A2 found in AST */ |
| 5667 | A_UINT32 invalid_peer_a2_in_ast; |
| 5668 | /* Number of MPDUs with invalid peer but A3 found in AST */ |
| 5669 | A_UINT32 invalid_peer_a3_in_ast; |
| 5670 | /* Number of MPDUs with invalid peer, Broadcast or Multicast frame */ |
| 5671 | A_UINT32 invalid_peer_bmc_mpdus; |
| 5672 | /* Number of MSDUs with err attention word */ |
| 5673 | A_UINT32 rxdesc_err_att; |
| 5674 | /* Number of MSDUs with flag of peer_idx_invalid */ |
| 5675 | A_UINT32 rxdesc_err_peer_idx_inv; |
| 5676 | /* Number of MSDUs with flag of peer_idx_timeout */ |
| 5677 | A_UINT32 rxdesc_err_peer_idx_to; |
| 5678 | /* Number of MSDUs with flag of overflow */ |
| 5679 | A_UINT32 rxdesc_err_ov; |
| 5680 | /* Number of MSDUs with flag of msdu_length_err */ |
| 5681 | A_UINT32 rxdesc_err_msdu_len; |
| 5682 | /* Number of MSDUs with flag of mpdu_length_err */ |
| 5683 | A_UINT32 rxdesc_err_mpdu_len; |
| 5684 | /* Number of MSDUs with flag of tkip_mic_err */ |
| 5685 | A_UINT32 rxdesc_err_tkip_mic; |
| 5686 | /* Number of MSDUs with flag of decrypt_err */ |
| 5687 | A_UINT32 rxdesc_err_decrypt; |
| 5688 | /* Number of MSDUs with flag of fcs_err */ |
| 5689 | A_UINT32 rxdesc_err_fcs; |
| 5690 | /* Number of Unicast (bc_mc bit is not set in attention word) |
| 5691 | * frames with invalid peer handler |
| 5692 | */ |
| 5693 | A_UINT32 rxdesc_uc_msdus_inv_peer; |
| 5694 | /* Number of unicast frame directly (direct bit is set in attention word) |
| 5695 | * to DUT with invalid peer handler |
| 5696 | */ |
| 5697 | A_UINT32 rxdesc_direct_msdus_inv_peer; |
| 5698 | /* Number of Broadcast/Multicast (bc_mc bit set in attention word) |
| 5699 | * frames with invalid peer handler |
| 5700 | */ |
| 5701 | A_UINT32 rxdesc_bmc_msdus_inv_peer; |
| 5702 | /* Number of MSDUs dropped due to no first MSDU flag */ |
| 5703 | A_UINT32 rxdesc_no_1st_msdu; |
| 5704 | /* Number of MSDUs droped due to ring overflow */ |
| 5705 | A_UINT32 msdu_drop_ring_ov; |
| 5706 | /* Number of MSDUs dropped due to FC mismatch */ |
| 5707 | A_UINT32 msdu_drop_fc_mismatch; |
| 5708 | /* Number of MSDUs dropped due to mgt frame in Remote ring */ |
| 5709 | A_UINT32 msdu_drop_mgmt_remote_ring; |
| 5710 | /* Number of MSDUs dropped due to errors not reported in attention word */ |
| 5711 | A_UINT32 msdu_drop_misc; |
| 5712 | /* Number of MSDUs go to offload before reorder */ |
| 5713 | A_UINT32 offload_msdu_wal; |
| 5714 | /* Number of data frame dropped by offload after reorder */ |
| 5715 | A_UINT32 offload_msdu_reorder; |
| 5716 | /* Number of MPDUs with sequence number in the past and within |
| 5717 | the BA window */ |
| 5718 | A_UINT32 dup_past_within_window; |
| 5719 | /* Number of MPDUs with sequence number in the past and |
| 5720 | * outside the BA window */ |
| 5721 | A_UINT32 dup_past_outside_window; |
| 5722 | /* Number of MSDUs with decrypt/MIC error */ |
| 5723 | A_UINT32 rxdesc_err_decrypt_mic; |
| 5724 | /* Number of data MSDUs received on both local and remote rings */ |
| 5725 | A_UINT32 data_msdus_on_both_rings; |
| 5726 | }; |
| 5727 | |
| 5728 | |
| 5729 | /* |
| 5730 | * Rx Remote buffer statistics |
| 5731 | * NB: all the fields must be defined in 4 octets size. |
| 5732 | */ |
| 5733 | struct rx_remote_buffer_mgmt_stats { |
| 5734 | /* Total number of MSDUs reaped for Rx processing */ |
| 5735 | A_UINT32 remote_reaped; |
| 5736 | /* MSDUs recycled within firmware */ |
| 5737 | A_UINT32 remote_recycled; |
| 5738 | /* MSDUs stored by Data Rx */ |
| 5739 | A_UINT32 data_rx_msdus_stored; |
| 5740 | /* Number of HTT indications from WAL Rx MSDU */ |
| 5741 | A_UINT32 wal_rx_ind; |
| 5742 | /* Number of unconsumed HTT indications from WAL Rx MSDU */ |
| 5743 | A_UINT32 wal_rx_ind_unconsumed; |
| 5744 | /* Number of HTT indications from Data Rx MSDU */ |
| 5745 | A_UINT32 data_rx_ind; |
| 5746 | /* Number of unconsumed HTT indications from Data Rx MSDU */ |
| 5747 | A_UINT32 data_rx_ind_unconsumed; |
| 5748 | /* Number of HTT indications from ATHBUF */ |
| 5749 | A_UINT32 athbuf_rx_ind; |
| 5750 | /* Number of remote buffers requested for refill */ |
| 5751 | A_UINT32 refill_buf_req; |
| 5752 | /* Number of remote buffers filled by the host */ |
| 5753 | A_UINT32 refill_buf_rsp; |
| 5754 | /* Number of times MAC hw_index = f/w write_index */ |
| 5755 | A_INT32 mac_no_bufs; |
| 5756 | /* Number of times f/w write_index = f/w read_index for MAC Rx ring */ |
| 5757 | A_INT32 fw_indices_equal; |
| 5758 | /* Number of times f/w finds no buffers to post */ |
| 5759 | A_INT32 host_no_bufs; |
| 5760 | }; |
| 5761 | |
| 5762 | /* |
| 5763 | * TXBF MU/SU packets and NDPA statistics |
| 5764 | * NB: all the fields must be defined in 4 octets size. |
| 5765 | */ |
| 5766 | struct rx_txbf_musu_ndpa_pkts_stats { |
| 5767 | /* number of TXBF MU packets received */ |
| 5768 | A_UINT32 number_mu_pkts; |
| 5769 | /* number of TXBF SU packets received */ |
| 5770 | A_UINT32 number_su_pkts; |
| 5771 | /* number of TXBF directed NDPA */ |
| 5772 | A_UINT32 txbf_directed_ndpa_count; |
| 5773 | /* number of TXBF retried NDPA */ |
| 5774 | A_UINT32 txbf_ndpa_retry_count; |
| 5775 | /* total number of TXBF NDPA */ |
| 5776 | A_UINT32 txbf_total_ndpa_count; |
| 5777 | /* must be set to 0x0 */ |
| 5778 | A_UINT32 reserved[3]; |
| 5779 | }; |
| 5780 | |
| 5781 | /* |
| 5782 | * htt_dbg_stats_status - |
| 5783 | * present - The requested stats have been delivered in full. |
| 5784 | * This indicates that either the stats information was contained |
| 5785 | * in its entirety within this message, or else this message |
| 5786 | * completes the delivery of the requested stats info that was |
| 5787 | * partially delivered through earlier STATS_CONF messages. |
| 5788 | * partial - The requested stats have been delivered in part. |
| 5789 | * One or more subsequent STATS_CONF messages with the same |
| 5790 | * cookie value will be sent to deliver the remainder of the |
| 5791 | * information. |
| 5792 | * error - The requested stats could not be delivered, for example due |
| 5793 | * to a shortage of memory to construct a message holding the |
| 5794 | * requested stats. |
| 5795 | * invalid - The requested stat type is either not recognized, or the |
| 5796 | * target is configured to not gather the stats type in question. |
| 5797 | * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| 5798 | * series_done - This special value indicates that no further stats info |
| 5799 | * elements are present within a series of stats info elems |
| 5800 | * (within a stats upload confirmation message). |
| 5801 | */ |
| 5802 | enum htt_dbg_stats_status { |
| 5803 | HTT_DBG_STATS_STATUS_PRESENT = 0, |
| 5804 | HTT_DBG_STATS_STATUS_PARTIAL = 1, |
| 5805 | HTT_DBG_STATS_STATUS_ERROR = 2, |
| 5806 | HTT_DBG_STATS_STATUS_INVALID = 3, |
| 5807 | |
| 5808 | |
| 5809 | HTT_DBG_STATS_STATUS_SERIES_DONE = 7 |
| 5810 | }; |
| 5811 | |
| 5812 | /** |
| 5813 | * @brief target -> host statistics upload |
| 5814 | * |
| 5815 | * @details |
| 5816 | * The following field definitions describe the format of the HTT target |
| 5817 | * to host stats upload confirmation message. |
| 5818 | * The message contains a cookie echoed from the HTT host->target stats |
| 5819 | * upload request, which identifies which request the confirmation is |
| 5820 | * for, and a series of tag-length-value stats information elements. |
| 5821 | * The tag-length header for each stats info element also includes a |
| 5822 | * status field, to indicate whether the request for the stat type in |
| 5823 | * question was fully met, partially met, unable to be met, or invalid |
| 5824 | * (if the stat type in question is disabled in the target). |
| 5825 | * A special value of all 1's in this status field is used to indicate |
| 5826 | * the end of the series of stats info elements. |
| 5827 | * |
| 5828 | * |
| 5829 | * |31 16|15 8|7 5|4 0| |
| 5830 | * |------------------------------------------------------------| |
| 5831 | * | reserved | msg type | |
| 5832 | * |------------------------------------------------------------| |
| 5833 | * | cookie LSBs | |
| 5834 | * |------------------------------------------------------------| |
| 5835 | * | cookie MSBs | |
| 5836 | * |------------------------------------------------------------| |
| 5837 | * | stats entry length | reserved | S |stat type| |
| 5838 | * |------------------------------------------------------------| |
| 5839 | * | | |
| 5840 | * | type-specific stats info | |
| 5841 | * | | |
| 5842 | * |------------------------------------------------------------| |
| 5843 | * | stats entry length | reserved | S |stat type| |
| 5844 | * |------------------------------------------------------------| |
| 5845 | * | | |
| 5846 | * | type-specific stats info | |
| 5847 | * | | |
| 5848 | * |------------------------------------------------------------| |
| 5849 | * | n/a | reserved | 111 | n/a | |
| 5850 | * |------------------------------------------------------------| |
| 5851 | * Header fields: |
| 5852 | * - MSG_TYPE |
| 5853 | * Bits 7:0 |
| 5854 | * Purpose: identifies this is a statistics upload confirmation message |
| 5855 | * Value: 0x9 |
| 5856 | * - COOKIE_LSBS |
| 5857 | * Bits 31:0 |
| 5858 | * Purpose: Provide a mechanism to match a target->host stats confirmation |
| 5859 | * message with its preceding host->target stats request message. |
| 5860 | * Value: LSBs of the opaque cookie specified by the host-side requestor |
| 5861 | * - COOKIE_MSBS |
| 5862 | * Bits 31:0 |
| 5863 | * Purpose: Provide a mechanism to match a target->host stats confirmation |
| 5864 | * message with its preceding host->target stats request message. |
| 5865 | * Value: MSBs of the opaque cookie specified by the host-side requestor |
| 5866 | * |
| 5867 | * Stats Information Element tag-length header fields: |
| 5868 | * - STAT_TYPE |
| 5869 | * Bits 4:0 |
| 5870 | * Purpose: identifies the type of statistics info held in the |
| 5871 | * following information element |
| 5872 | * Value: htt_dbg_stats_type |
| 5873 | * - STATUS |
| 5874 | * Bits 7:5 |
| 5875 | * Purpose: indicate whether the requested stats are present |
| 5876 | * Value: htt_dbg_stats_status, including a special value (0x7) to mark |
| 5877 | * the completion of the stats entry series |
| 5878 | * - LENGTH |
| 5879 | * Bits 31:16 |
| 5880 | * Purpose: indicate the stats information size |
| 5881 | * Value: This field specifies the number of bytes of stats information |
| 5882 | * that follows the element tag-length header. |
| 5883 | * It is expected but not required that this length is a multiple of |
| 5884 | * 4 bytes. Even if the length is not an integer multiple of 4, the |
| 5885 | * subsequent stats entry header will begin on a 4-byte aligned |
| 5886 | * boundary. |
| 5887 | */ |
| 5888 | #define HTT_T2H_STATS_COOKIE_SIZE 8 |
| 5889 | |
| 5890 | #define HTT_T2H_STATS_CONF_TAIL_SIZE 4 |
| 5891 | |
| 5892 | #define HTT_T2H_STATS_CONF_HDR_SIZE 4 |
| 5893 | |
| 5894 | #define HTT_T2H_STATS_CONF_TLV_HDR_SIZE 4 |
| 5895 | |
| 5896 | #define HTT_T2H_STATS_CONF_TLV_TYPE_M 0x0000001f |
| 5897 | #define HTT_T2H_STATS_CONF_TLV_TYPE_S 0 |
| 5898 | #define HTT_T2H_STATS_CONF_TLV_STATUS_M 0x000000e0 |
| 5899 | #define HTT_T2H_STATS_CONF_TLV_STATUS_S 5 |
| 5900 | #define HTT_T2H_STATS_CONF_TLV_LENGTH_M 0xffff0000 |
| 5901 | #define HTT_T2H_STATS_CONF_TLV_LENGTH_S 16 |
| 5902 | |
| 5903 | #define HTT_T2H_STATS_CONF_TLV_TYPE_SET(word, value) \ |
| 5904 | do { \ |
| 5905 | HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_TYPE, value); \ |
| 5906 | (word) |= (value) << HTT_T2H_STATS_CONF_TLV_TYPE_S; \ |
| 5907 | } while (0) |
| 5908 | #define HTT_T2H_STATS_CONF_TLV_TYPE_GET(word) \ |
| 5909 | (((word) & HTT_T2H_STATS_CONF_TLV_TYPE_M) >> \ |
| 5910 | HTT_T2H_STATS_CONF_TLV_TYPE_S) |
| 5911 | |
| 5912 | #define HTT_T2H_STATS_CONF_TLV_STATUS_SET(word, value) \ |
| 5913 | do { \ |
| 5914 | HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_STATUS, value); \ |
| 5915 | (word) |= (value) << HTT_T2H_STATS_CONF_TLV_STATUS_S; \ |
| 5916 | } while (0) |
| 5917 | #define HTT_T2H_STATS_CONF_TLV_STATUS_GET(word) \ |
| 5918 | (((word) & HTT_T2H_STATS_CONF_TLV_STATUS_M) >> \ |
| 5919 | HTT_T2H_STATS_CONF_TLV_STATUS_S) |
| 5920 | |
| 5921 | #define HTT_T2H_STATS_CONF_TLV_LENGTH_SET(word, value) \ |
| 5922 | do { \ |
| 5923 | HTT_CHECK_SET_VAL(HTT_T2H_STATS_CONF_TLV_LENGTH, value); \ |
| 5924 | (word) |= (value) << HTT_T2H_STATS_CONF_TLV_LENGTH_S; \ |
| 5925 | } while (0) |
| 5926 | #define HTT_T2H_STATS_CONF_TLV_LENGTH_GET(word) \ |
| 5927 | (((word) & HTT_T2H_STATS_CONF_TLV_LENGTH_M) >> \ |
| 5928 | HTT_T2H_STATS_CONF_TLV_LENGTH_S) |
| 5929 | |
| 5930 | #define HL_HTT_FW_RX_DESC_RSVD_SIZE 18 |
| 5931 | #define HTT_MAX_AGGR 64 |
| 5932 | #define HTT_HL_MAX_AGGR 18 |
| 5933 | |
| 5934 | /** |
| 5935 | * @brief host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank |
| 5936 | * |
| 5937 | * @details |
| 5938 | * The following field definitions describe the format of the HTT host |
| 5939 | * to target frag_desc/msdu_ext bank configuration message. |
| 5940 | * The message contains the based address and the min and max id of the |
| 5941 | * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and |
| 5942 | * MSDU_EXT/FRAG_DESC. |
| 5943 | * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. |
| 5944 | * In peregrine the firmware will use fragment_desc_ptr but in WIFI2.0 |
| 5945 | * the hardware does the mapping/translation. |
| 5946 | * |
| 5947 | * Total banks that can be configured is configured to 16. |
| 5948 | * |
| 5949 | * This should be called before any TX has be initiated by the HTT |
| 5950 | * |
| 5951 | * |31 16|15 8|7 5|4 0| |
| 5952 | * |------------------------------------------------------------| |
| 5953 | * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | |
| 5954 | * |------------------------------------------------------------| |
| 5955 | * | BANK0_BASE_ADDRESS (bits 31:0) | |
| 5956 | #if HTT_PADDR64 |
| 5957 | * | BANK0_BASE_ADDRESS (bits 63:32) | |
| 5958 | #endif |
| 5959 | * |------------------------------------------------------------| |
| 5960 | * | ... | |
| 5961 | * |------------------------------------------------------------| |
| 5962 | * | BANK15_BASE_ADDRESS (bits 31:0) | |
| 5963 | #if HTT_PADDR64 |
| 5964 | * | BANK15_BASE_ADDRESS (bits 63:32) | |
| 5965 | #endif |
| 5966 | * |------------------------------------------------------------| |
| 5967 | * | BANK0_MAX_ID | BANK0_MIN_ID | |
| 5968 | * |------------------------------------------------------------| |
| 5969 | * | ... | |
| 5970 | * |------------------------------------------------------------| |
| 5971 | * | BANK15_MAX_ID | BANK15_MIN_ID | |
| 5972 | * |------------------------------------------------------------| |
| 5973 | * Header fields: |
| 5974 | * - MSG_TYPE |
| 5975 | * Bits 7:0 |
| 5976 | * Value: 0x6 |
| 5977 | * for systems with 64-bit format for bus addresses: |
| 5978 | * - BANKx_BASE_ADDRESS_LO |
| 5979 | * Bits 31:0 |
| 5980 | * Purpose: Provide a mechanism to specify the base address of the |
| 5981 | * MSDU_EXT bank physical/bus address. |
| 5982 | * Value: lower 4 bytes of MSDU_EXT bank physical / bus address |
| 5983 | * - BANKx_BASE_ADDRESS_HI |
| 5984 | * Bits 31:0 |
| 5985 | * Purpose: Provide a mechanism to specify the base address of the |
| 5986 | * MSDU_EXT bank physical/bus address. |
| 5987 | * Value: higher 4 bytes of MSDU_EXT bank physical / bus address |
| 5988 | * for systems with 32-bit format for bus addresses: |
| 5989 | * - BANKx_BASE_ADDRESS |
| 5990 | * Bits 31:0 |
| 5991 | * Purpose: Provide a mechanism to specify the base address of the |
| 5992 | * MSDU_EXT bank physical/bus address. |
| 5993 | * Value: MSDU_EXT bank physical / bus address |
| 5994 | * - BANKx_MIN_ID |
| 5995 | * Bits 15:0 |
| 5996 | * Purpose: Provide a mechanism to specify the min index that needs to |
| 5997 | * mapped. |
| 5998 | * - BANKx_MAX_ID |
| 5999 | * Bits 31:16 |
| 6000 | * Purpose: Provide a mechanism to specify the max index that needs to |
| 6001 | * mapped. |
| 6002 | * |
| 6003 | */ |
| 6004 | |
| 6005 | /** @todo Compress the fields to fit MAX HTT Message size, until then |
| 6006 | * configure to a safe value. |
| 6007 | * @note MAX supported banks is 16. |
| 6008 | */ |
| 6009 | #define HTT_TX_MSDU_EXT_BANK_MAX 4 |
| 6010 | |
| 6011 | #define HTT_H2T_FRAG_DESC_BANK_PDEVID_M 0x300 |
| 6012 | #define HTT_H2T_FRAG_DESC_BANK_PDEVID_S 8 |
| 6013 | |
| 6014 | #define HTT_H2T_FRAG_DESC_BANK_SWAP_M 0x400 |
| 6015 | #define HTT_H2T_FRAG_DESC_BANK_SWAP_S 10 |
| 6016 | |
| 6017 | #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M 0xff0000 |
| 6018 | #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S 16 |
| 6019 | |
| 6020 | #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M 0xff000000 |
| 6021 | #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S 24 |
| 6022 | |
| 6023 | #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M 0xffff |
| 6024 | #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S 0 |
| 6025 | |
| 6026 | #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M 0xffff0000 |
| 6027 | #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S 16 |
| 6028 | |
| 6029 | #define HTT_H2T_FRAG_DESC_BANK_PDEVID_SET(word, value) \ |
| 6030 | do { \ |
| 6031 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_PDEVID, value); \ |
| 6032 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_PDEVID_S); \ |
| 6033 | } while (0) |
| 6034 | #define HTT_H2T_FRAG_DESC_BANK_PDEVID_GET(word) \ |
| 6035 | (((word) & HTT_H2T_FRAG_DESC_BANK_PDEVID_M) >> \ |
| 6036 | HTT_H2T_FRAG_DESC_BANK_PDEVID_S) |
| 6037 | |
| 6038 | #define HTT_H2T_FRAG_DESC_BANK_SWAP_SET(word, value) \ |
| 6039 | do { \ |
| 6040 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_SWAP, value);\ |
| 6041 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_SWAP_S);\ |
| 6042 | } while (0) |
| 6043 | #define HTT_H2T_FRAG_DESC_BANK_SWAP_GET(word) \ |
| 6044 | (((word) & HTT_H2T_FRAG_DESC_BANK_SWAP_M) >> \ |
| 6045 | HTT_H2T_FRAG_DESC_BANK_SWAP_S) |
| 6046 | |
| 6047 | #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_SET(word, value) \ |
| 6048 | do { \ |
| 6049 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_NUM_BANKS, value); \ |
| 6050 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S); \ |
| 6051 | } while (0) |
| 6052 | #define HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_GET(word) \ |
| 6053 | (((word) & HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_M) >> \ |
| 6054 | HTT_H2T_FRAG_DESC_BANK_NUM_BANKS_S) |
| 6055 | |
| 6056 | #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_SET(word, value) \ |
| 6057 | do { \ |
| 6058 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_DESC_SIZE, value); \ |
| 6059 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S); \ |
| 6060 | } while (0) |
| 6061 | #define HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_GET(word) \ |
| 6062 | (((word) & HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_M) >> \ |
| 6063 | HTT_H2T_FRAG_DESC_BANK_DESC_SIZE_S) |
| 6064 | |
| 6065 | #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_SET(word, value) \ |
| 6066 | do { \ |
| 6067 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MIN_IDX, value); \ |
| 6068 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S); \ |
| 6069 | } while (0) |
| 6070 | #define HTT_H2T_FRAG_DESC_BANK_MIN_IDX_GET(word) \ |
| 6071 | (((word) & HTT_H2T_FRAG_DESC_BANK_MIN_IDX_M) >> \ |
| 6072 | HTT_H2T_FRAG_DESC_BANK_MIN_IDX_S) |
| 6073 | |
| 6074 | #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_SET(word, value) \ |
| 6075 | do { \ |
| 6076 | HTT_CHECK_SET_VAL(HTT_H2T_FRAG_DESC_BANK_MAX_IDX, value); \ |
| 6077 | (word) |= ((value) << HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S); \ |
| 6078 | } while (0) |
| 6079 | #define HTT_H2T_FRAG_DESC_BANK_MAX_IDX_GET(word) \ |
| 6080 | (((word) & HTT_H2T_FRAG_DESC_BANK_MAX_IDX_M) >> \ |
| 6081 | HTT_H2T_FRAG_DESC_BANK_MAX_IDX_S) |
| 6082 | |
| 6083 | |
| 6084 | /* |
| 6085 | * TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T: |
| 6086 | * This macro defines a htt_tx_frag_descXXX_bank_cfg_t in which any physical |
| 6087 | * addresses are stored in a XXX-bit field. |
| 6088 | * This macro is used to define both htt_tx_frag_desc32_bank_cfg_t and |
| 6089 | * htt_tx_frag_desc64_bank_cfg_t structs. |
| 6090 | */ |
| 6091 | #define TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T( \ |
| 6092 | _paddr_bits_, \ |
| 6093 | _paddr__bank_base_address_) \ |
| 6094 | PREPACK struct htt_tx_frag_desc ## _paddr_bits_ ## _bank_cfg_t { \ |
| 6095 | /** word 0 \ |
| 6096 | * msg_type: 8, \ |
| 6097 | * pdev_id: 2, \ |
| 6098 | * swap: 1, \ |
| 6099 | * reserved0: 5, \ |
| 6100 | * num_banks: 8, \ |
| 6101 | * desc_size: 8; \ |
| 6102 | */ \ |
| 6103 | A_UINT32 word0; \ |
| 6104 | /* \ |
| 6105 | * If bank_base_address is 64 bits, the upper / lower |
| 6106 | * halves are stored \ |
| 6107 | * in little-endian order (bytes 0-3 in the first A_UINT32, |
| 6108 | * bytes 4-7 in the second A_UINT32). \ |
| 6109 | */ \ |
| 6110 | _paddr__bank_base_address_[HTT_TX_MSDU_EXT_BANK_MAX]; \ |
| 6111 | A_UINT32 bank_info[HTT_TX_MSDU_EXT_BANK_MAX]; \ |
| 6112 | } POSTPACK |
| 6113 | /* define htt_tx_frag_desc32_bank_cfg_t */ |
| 6114 | TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(32, HTT_VAR_PADDR32(bank_base_address)); |
| 6115 | /* define htt_tx_frag_desc64_bank_cfg_t */ |
| 6116 | TEMPLATE_HTT_TX_FRAG_DESC_BANK_CFG_T(64, HTT_VAR_PADDR64_LE(bank_base_address)); |
| 6117 | /* |
| 6118 | * Make htt_tx_frag_desc_bank_cfg_t be an alias for either |
| 6119 | * htt_tx_frag_desc32_bank_cfg_t or htt_tx_frag_desc64_bank_cfg_t |
| 6120 | */ |
| 6121 | #if HTT_PADDR64 |
| 6122 | #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc64_bank_cfg_t |
| 6123 | #else |
| 6124 | #define htt_tx_frag_desc_bank_cfg_t htt_tx_frag_desc32_bank_cfg_t |
| 6125 | #endif |
| 6126 | |
| 6127 | |
| 6128 | /** |
| 6129 | * @brief target -> host HTT TX Credit total count update message definition |
| 6130 | * |
| 6131 | *|31 16|15|14 9| 8 |7 0 | |
| 6132 | *|---------------------+--+----------+-------+----------| |
| 6133 | *|cur htt credit delta | Q| reserved | sign | msg type | |
| 6134 | *|------------------------------------------------------| |
| 6135 | * |
| 6136 | * Header fields: |
| 6137 | * - MSG_TYPE |
| 6138 | * Bits 7:0 |
| 6139 | * Purpose: identifies this as a htt tx credit delta update message |
| 6140 | * Value: 0xe |
| 6141 | * - SIGN |
| 6142 | * Bits 8 |
| 6143 | * identifies whether credit delta is positive or negative |
| 6144 | * Value: |
| 6145 | * - 0x0: credit delta is positive, rebalance in some buffers |
| 6146 | * - 0x1: credit delta is negative, rebalance out some buffers |
| 6147 | * - reserved |
| 6148 | * Bits 14:9 |
| 6149 | * Value: 0x0 |
| 6150 | * - TXQ_GRP |
| 6151 | * Bit 15 |
| 6152 | * Purpose: indicates whether any tx queue group information elements |
| 6153 | * are appended to the tx credit update message |
| 6154 | * Value: 0 -> no tx queue group information element is present |
| 6155 | * 1 -> a tx queue group information element immediately follows |
| 6156 | * - DELTA_COUNT |
| 6157 | * Bits 31:16 |
| 6158 | * Purpose: Specify current htt credit delta absolute count |
| 6159 | */ |
| 6160 | |
| 6161 | #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100 |
| 6162 | #define HTT_TX_CREDIT_SIGN_BIT_S 8 |
| 6163 | #define HTT_TX_CREDIT_TXQ_GRP_M 0x00008000 |
| 6164 | #define HTT_TX_CREDIT_TXQ_GRP_S 15 |
| 6165 | #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000 |
| 6166 | #define HTT_TX_CREDIT_DELTA_ABS_S 16 |
| 6167 | |
| 6168 | |
| 6169 | #define HTT_TX_CREDIT_SIGN_BIT_SET(word, value) \ |
| 6170 | do { \ |
| 6171 | HTT_CHECK_SET_VAL(HTT_TX_CREDIT_SIGN_BIT, value); \ |
| 6172 | (word) |= (value) << HTT_TX_CREDIT_SIGN_BIT_S; \ |
| 6173 | } while (0) |
| 6174 | |
| 6175 | #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \ |
| 6176 | (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S) |
| 6177 | |
| 6178 | #define HTT_TX_CREDIT_TXQ_GRP_SET(word, value) \ |
| 6179 | do { \ |
| 6180 | HTT_CHECK_SET_VAL(HTT_TX_CREDIT_TXQ_GRP, value); \ |
| 6181 | (word) |= (value) << HTT_TX_CREDIT_TXQ_GRP_S; \ |
| 6182 | } while (0) |
| 6183 | |
| 6184 | #define HTT_TX_CREDIT_TXQ_GRP_GET(word) \ |
| 6185 | (((word) & HTT_TX_CREDIT_TXQ_GRP_M) >> HTT_TX_CREDIT_TXQ_GRP_S) |
| 6186 | |
| 6187 | #define HTT_TX_CREDIT_DELTA_ABS_SET(word, value) \ |
| 6188 | do { \ |
| 6189 | HTT_CHECK_SET_VAL(HTT_TX_CREDIT_DELTA_ABS, value); \ |
| 6190 | (word) |= (value) << HTT_TX_CREDIT_DELTA_ABS_S; \ |
| 6191 | } while (0) |
| 6192 | |
| 6193 | #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \ |
| 6194 | (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S) |
| 6195 | |
| 6196 | |
| 6197 | #define HTT_TX_CREDIT_MSG_BYTES 4 |
| 6198 | |
| 6199 | #define HTT_TX_CREDIT_SIGN_BIT_POSITIVE 0x0 |
| 6200 | #define HTT_TX_CREDIT_SIGN_BIT_NEGATIVE 0x1 |
| 6201 | |
| 6202 | |
| 6203 | /** |
| 6204 | * @brief HTT WDI_IPA Operation Response Message |
| 6205 | * |
| 6206 | * @details |
| 6207 | * HTT WDI_IPA Operation Response message is sent by target |
| 6208 | * to host confirming suspend or resume operation. |
| 6209 | * |31 24|23 16|15 8|7 0| |
| 6210 | * |----------------+----------------+----------------+----------------| |
| 6211 | * | op_code | Rsvd | msg_type | |
| 6212 | * |-------------------------------------------------------------------| |
| 6213 | * | Rsvd | Response len | |
| 6214 | * |-------------------------------------------------------------------| |
| 6215 | * | | |
| 6216 | * | Response-type specific info | |
| 6217 | * | | |
| 6218 | * | | |
| 6219 | * |-------------------------------------------------------------------| |
| 6220 | * Header fields: |
| 6221 | * - MSG_TYPE |
| 6222 | * Bits 7:0 |
| 6223 | * Purpose: Identifies this as WDI_IPA Operation Response message |
| 6224 | * value: = 0x13 |
| 6225 | * - OP_CODE |
| 6226 | * Bits 31:16 |
| 6227 | * Purpose: Identifies the operation target is responding to |
| 6228 | * (e.g. TX suspend) |
| 6229 | * value: = enum htt_wdi_ipa_op_code |
| 6230 | * - RSP_LEN |
| 6231 | * Bits 16:0 |
| 6232 | * Purpose: length for the response-type specific info |
| 6233 | * value: = length in bytes for response-type specific info |
| 6234 | * For example, if OP_CODE == HTT_WDI_IPA_OPCODE_DBG_STATS, the |
| 6235 | * length value will be sizeof(struct wlan_wdi_ipa_dbg_stats_t). |
| 6236 | */ |
| 6237 | |
| 6238 | PREPACK struct htt_wdi_ipa_op_response_t { |
| 6239 | /* DWORD 0: flags and meta-data */ |
| 6240 | A_UINT32 |
| 6241 | msg_type:8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ |
| 6242 | reserved1:8, |
| 6243 | op_code:16; |
| 6244 | A_UINT32 |
| 6245 | rsp_len:16, |
| 6246 | reserved2:16; |
| 6247 | } POSTPACK; |
| 6248 | |
| 6249 | #define HTT_WDI_IPA_OP_RESPONSE_SZ 8 /* bytes */ |
| 6250 | |
| 6251 | #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M 0xffff0000 |
| 6252 | #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S 16 |
| 6253 | |
| 6254 | #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M 0x0000ffff |
| 6255 | #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S 0 |
| 6256 | |
| 6257 | #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_GET(_var) \ |
| 6258 | (((_var) & HTT_WDI_IPA_OP_RESPONSE_OP_CODE_M) >> \ |
| 6259 | HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S) |
| 6260 | #define HTT_WDI_IPA_OP_RESPONSE_OP_CODE_SET(_var, _val) \ |
| 6261 | do { \ |
| 6262 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_OP_CODE, _val); \ |
| 6263 | ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_OP_CODE_S)); \ |
| 6264 | } while (0) |
| 6265 | |
| 6266 | #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_GET(_var) \ |
| 6267 | (((_var) & HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_M) >> \ |
| 6268 | HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S) |
| 6269 | #define HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_SET(_var, _val) \ |
| 6270 | do { \ |
| 6271 | HTT_CHECK_SET_VAL(HTT_WDI_IPA_OP_RESPONSE_RSP_LEN, _val); \ |
| 6272 | ((_var) |= ((_val) << HTT_WDI_IPA_OP_RESPONSE_RSP_LEN_S)); \ |
| 6273 | } while (0) |
| 6274 | |
| 6275 | |
| 6276 | enum htt_phy_mode { |
| 6277 | htt_phy_mode_11a = 0, |
| 6278 | htt_phy_mode_11g = 1, |
| 6279 | htt_phy_mode_11b = 2, |
| 6280 | htt_phy_mode_11g_only = 3, |
| 6281 | htt_phy_mode_11na_ht20 = 4, |
| 6282 | htt_phy_mode_11ng_ht20 = 5, |
| 6283 | htt_phy_mode_11na_ht40 = 6, |
| 6284 | htt_phy_mode_11ng_ht40 = 7, |
| 6285 | htt_phy_mode_11ac_vht20 = 8, |
| 6286 | htt_phy_mode_11ac_vht40 = 9, |
| 6287 | htt_phy_mode_11ac_vht80 = 10, |
| 6288 | htt_phy_mode_11ac_vht20_2g = 11, |
| 6289 | htt_phy_mode_11ac_vht40_2g = 12, |
| 6290 | htt_phy_mode_11ac_vht80_2g = 13, |
| 6291 | htt_phy_mode_11ac_vht80_80 = 14, /* 80+80 */ |
| 6292 | htt_phy_mode_11ac_vht160 = 15, |
| 6293 | |
| 6294 | htt_phy_mode_max, |
| 6295 | }; |
| 6296 | |
| 6297 | /** |
| 6298 | * @brief target -> host HTT channel change indication |
| 6299 | * @details |
| 6300 | * Specify when a channel change occurs. |
| 6301 | * This allows the host to precisely determine which rx frames arrived |
| 6302 | * on the old channel and which rx frames arrived on the new channel. |
| 6303 | * |
| 6304 | *|31 |7 0 | |
| 6305 | *|-------------------------------------------+----------| |
| 6306 | *| reserved | msg type | |
| 6307 | *|------------------------------------------------------| |
| 6308 | *| primary_chan_center_freq_mhz | |
| 6309 | *|------------------------------------------------------| |
| 6310 | *| contiguous_chan1_center_freq_mhz | |
| 6311 | *|------------------------------------------------------| |
| 6312 | *| contiguous_chan2_center_freq_mhz | |
| 6313 | *|------------------------------------------------------| |
| 6314 | *| phy_mode | |
| 6315 | *|------------------------------------------------------| |
| 6316 | * |
| 6317 | * Header fields: |
| 6318 | * - MSG_TYPE |
| 6319 | * Bits 7:0 |
| 6320 | * Purpose: identifies this as a htt channel change indication message |
| 6321 | * Value: 0x15 |
| 6322 | * - PRIMARY_CHAN_CENTER_FREQ_MHZ |
| 6323 | * Bits 31:0 |
| 6324 | * Purpose: identify the (center of the) new 20 MHz primary channel |
| 6325 | * Value: center frequency of the 20 MHz primary channel, in MHz units |
| 6326 | * - CONTIG_CHAN1_CENTER_FREQ_MHZ |
| 6327 | * Bits 31:0 |
| 6328 | * Purpose: identify the (center of the) contiguous frequency range |
| 6329 | * comprising the new channel. |
| 6330 | * For example, if the new channel is a 80 MHz channel extending |
| 6331 | * 60 MHz beyond the primary channel, this field would be 30 larger |
| 6332 | * than the primary channel center frequency field. |
| 6333 | * Value: center frequency of the contiguous frequency range comprising |
| 6334 | * the full channel in MHz units |
| 6335 | * (80+80 channels also use the CONTIG_CHAN2 field) |
| 6336 | * - CONTIG_CHAN2_CENTER_FREQ_MHZ |
| 6337 | * Bits 31:0 |
| 6338 | * Purpose: Identify the (center of the) 80 MHz extension frequency range |
| 6339 | * within a VHT 80+80 channel. |
| 6340 | * This field is only relevant for VHT 80+80 channels. |
| 6341 | * Value: center frequency of the 80 MHz extension channel in a VHT 80+80 |
| 6342 | * channel (arbitrary value for cases besides VHT 80+80) |
| 6343 | * - PHY_MODE |
| 6344 | * Bits 31:0 |
| 6345 | * Purpose: specify the PHY channel's type (legacy vs. HT vs. VHT), width, |
| 6346 | * and band |
| 6347 | * Value: htt_phy_mode enum value |
| 6348 | */ |
| 6349 | |
| 6350 | PREPACK struct htt_chan_change_t { |
| 6351 | /* DWORD 0: flags and meta-data */ |
| 6352 | A_UINT32 msg_type:8, /* HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE */ |
| 6353 | reserved1:24; |
| 6354 | A_UINT32 primary_chan_center_freq_mhz; |
| 6355 | A_UINT32 contig_chan1_center_freq_mhz; |
| 6356 | A_UINT32 contig_chan2_center_freq_mhz; |
| 6357 | A_UINT32 phy_mode; |
| 6358 | } POSTPACK; |
| 6359 | |
| 6360 | #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M 0xffffffff |
| 6361 | #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S 0 |
| 6362 | #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M 0xffffffff |
| 6363 | #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S 0 |
| 6364 | #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M 0xffffffff |
| 6365 | #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S 0 |
| 6366 | #define HTT_CHAN_CHANGE_PHY_MODE_M 0xffffffff |
| 6367 | #define HTT_CHAN_CHANGE_PHY_MODE_S 0 |
| 6368 | |
| 6369 | |
| 6370 | #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_SET(word, value) \ |
| 6371 | do { \ |
| 6372 | HTT_CHECK_SET_VAL( \ |
| 6373 | HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ, value); \ |
| 6374 | (word) |= (value) << \ |
| 6375 | HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S; \ |
| 6376 | } while (0) |
| 6377 | #define HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_GET(word) \ |
| 6378 | (((word) & HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_M) \ |
| 6379 | >> HTT_CHAN_CHANGE_PRIMARY_CHAN_CENTER_FREQ_MHZ_S) |
| 6380 | |
| 6381 | #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_SET(word, value) \ |
| 6382 | do { \ |
| 6383 | HTT_CHECK_SET_VAL( \ |
| 6384 | HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ, value); \ |
| 6385 | (word) |= (value) << \ |
| 6386 | HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S; \ |
| 6387 | } while (0) |
| 6388 | #define HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_GET(word) \ |
| 6389 | (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_M) \ |
| 6390 | >> HTT_CHAN_CHANGE_CONTIG_CHAN1_CENTER_FREQ_MHZ_S) |
| 6391 | |
| 6392 | #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_SET(word, value) \ |
| 6393 | do { \ |
| 6394 | HTT_CHECK_SET_VAL( \ |
| 6395 | HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ, value); \ |
| 6396 | (word) |= (value) << \ |
| 6397 | HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S; \ |
| 6398 | } while (0) |
| 6399 | #define HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_GET(word) \ |
| 6400 | (((word) & HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_M) \ |
| 6401 | >> HTT_CHAN_CHANGE_CONTIG_CHAN2_CENTER_FREQ_MHZ_S) |
| 6402 | |
| 6403 | #define HTT_CHAN_CHANGE_PHY_MODE_SET(word, value) \ |
| 6404 | do { \ |
| 6405 | HTT_CHECK_SET_VAL(HTT_CHAN_CHANGE_PHY_MODE, value); \ |
| 6406 | (word) |= (value) << HTT_CHAN_CHANGE_PHY_MODE_S; \ |
| 6407 | } while (0) |
| 6408 | #define HTT_CHAN_CHANGE_PHY_MODE_GET(word) \ |
| 6409 | (((word) & HTT_CHAN_CHANGE_PHY_MODE_M) \ |
| 6410 | >> HTT_CHAN_CHANGE_PHY_MODE_S) |
| 6411 | |
| 6412 | #define HTT_CHAN_CHANGE_BYTES sizeof(struct htt_chan_change_t) |
| 6413 | |
| 6414 | |
| 6415 | /** |
| 6416 | * @brief rx offload packet error message |
| 6417 | * |
| 6418 | * @details |
| 6419 | * HTT_RX_OFLD_PKT_ERR message is sent by target to host to indicate err |
| 6420 | * of target payload like mic err. |
| 6421 | * |
| 6422 | * |31 24|23 16|15 8|7 0| |
| 6423 | * |----------------+----------------+----------------+----------------| |
| 6424 | * | tid | vdev_id | msg_sub_type | msg_type | |
| 6425 | * |-------------------------------------------------------------------| |
| 6426 | * : (sub-type dependent content) : |
| 6427 | * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: |
| 6428 | * Header fields: |
| 6429 | * - msg_type |
| 6430 | * Bits 7:0 |
| 6431 | * Purpose: Identifies this as HTT_RX_OFLD_PKT_ERR message |
| 6432 | * value: 0x16 (HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR) |
| 6433 | * - msg_sub_type |
| 6434 | * Bits 15:8 |
| 6435 | * Purpose: Identifies which type of rx error is reported by this message |
| 6436 | * value: htt_rx_ofld_pkt_err_type |
| 6437 | * - vdev_id |
| 6438 | * Bits 23:16 |
| 6439 | * Purpose: Identifies which vdev received the erroneous rx frame |
| 6440 | * value: |
| 6441 | * - tid |
| 6442 | * Bits 31:24 |
| 6443 | * Purpose: Identifies the traffic type of the rx frame |
| 6444 | * value: |
| 6445 | * |
| 6446 | * - The payload fields used if the sub-type == MIC error are shown below. |
| 6447 | * Note - MIC err is per MSDU, while PN is per MPDU. |
| 6448 | * The FW will discard the whole MPDU if any MSDU within the MPDU is marked |
| 6449 | * with MIC err in A-MSDU case, so FW will send only one HTT message |
| 6450 | * with the PN of this MPDU attached to indicate MIC err for one MPDU |
| 6451 | * instead of sending separate HTT messages for each wrong MSDU within |
| 6452 | * the MPDU. |
| 6453 | * |
| 6454 | * |31 24|23 16|15 8|7 0| |
| 6455 | * |----------------+----------------+----------------+----------------| |
| 6456 | * | Rsvd | key_id | peer_id | |
| 6457 | * |-------------------------------------------------------------------| |
| 6458 | * | receiver MAC addr 31:0 | |
| 6459 | * |-------------------------------------------------------------------| |
| 6460 | * | Rsvd | receiver MAC addr 47:32 | |
| 6461 | * |-------------------------------------------------------------------| |
| 6462 | * | transmitter MAC addr 31:0 | |
| 6463 | * |-------------------------------------------------------------------| |
| 6464 | * | Rsvd | transmitter MAC addr 47:32 | |
| 6465 | * |-------------------------------------------------------------------| |
| 6466 | * | PN 31:0 | |
| 6467 | * |-------------------------------------------------------------------| |
| 6468 | * | Rsvd | PN 47:32 | |
| 6469 | * |-------------------------------------------------------------------| |
| 6470 | * - peer_id |
| 6471 | * Bits 15:0 |
| 6472 | * Purpose: identifies which peer is frame is from |
| 6473 | * value: |
| 6474 | * - key_id |
| 6475 | * Bits 23:16 |
| 6476 | * Purpose: identifies key_id of rx frame |
| 6477 | * value: |
| 6478 | * - RA_31_0 (receiver MAC addr 31:0) |
| 6479 | * Bits 31:0 |
| 6480 | * Purpose: identifies by MAC address which vdev received the frame |
| 6481 | * value: MAC address lower 4 bytes |
| 6482 | * - RA_47_32 (receiver MAC addr 47:32) |
| 6483 | * Bits 15:0 |
| 6484 | * Purpose: identifies by MAC address which vdev received the frame |
| 6485 | * value: MAC address upper 2 bytes |
| 6486 | * - TA_31_0 (transmitter MAC addr 31:0) |
| 6487 | * Bits 31:0 |
| 6488 | * Purpose: identifies by MAC address which peer transmitted the frame |
| 6489 | * value: MAC address lower 4 bytes |
| 6490 | * - TA_47_32 (transmitter MAC addr 47:32) |
| 6491 | * Bits 15:0 |
| 6492 | * Purpose: identifies by MAC address which peer transmitted the frame |
| 6493 | * value: MAC address upper 2 bytes |
| 6494 | * - PN_31_0 |
| 6495 | * Bits 31:0 |
| 6496 | * Purpose: Identifies pn of rx frame |
| 6497 | * value: PN lower 4 bytes |
| 6498 | * - PN_47_32 |
| 6499 | * Bits 15:0 |
| 6500 | * Purpose: Identifies pn of rx frame |
| 6501 | * value: |
| 6502 | * TKIP or CCMP: PN upper 2 bytes |
| 6503 | * WAPI: PN bytes 6:5 (bytes 15:7 not included in this message) |
| 6504 | */ |
| 6505 | |
| 6506 | enum htt_rx_ofld_pkt_err_type { |
| 6507 | HTT_RX_OFLD_PKT_ERR_TYPE_NONE = 0, |
| 6508 | HTT_RX_OFLD_PKT_ERR_TYPE_MIC_ERR, |
| 6509 | }; |
| 6510 | |
| 6511 | /* definition for HTT_RX_OFLD_PKT_ERR msg hdr */ |
| 6512 | #define HTT_RX_OFLD_PKT_ERR_HDR_BYTES 4 |
| 6513 | |
| 6514 | #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M 0x0000ff00 |
| 6515 | #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S 8 |
| 6516 | |
| 6517 | #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_M 0x00ff0000 |
| 6518 | #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_S 16 |
| 6519 | |
| 6520 | #define HTT_RX_OFLD_PKT_ERR_TID_M 0xff000000 |
| 6521 | #define HTT_RX_OFLD_PKT_ERR_TID_S 24 |
| 6522 | |
| 6523 | #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_GET(_var) \ |
| 6524 | (((_var) & HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_M) \ |
| 6525 | >> HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S) |
| 6526 | #define HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_SET(_var, _val) \ |
| 6527 | do { \ |
| 6528 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE, _val); \ |
| 6529 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MSG_SUB_TYPE_S)); \ |
| 6530 | } while (0) |
| 6531 | |
| 6532 | #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_GET(_var) \ |
| 6533 | (((_var) & HTT_RX_OFLD_PKT_ERR_VDEV_ID_M) >> \ |
| 6534 | HTT_RX_OFLD_PKT_ERR_VDEV_ID_S) |
| 6535 | #define HTT_RX_OFLD_PKT_ERR_VDEV_ID_SET(_var, _val) \ |
| 6536 | do { \ |
| 6537 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_VDEV_ID, _val); \ |
| 6538 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_VDEV_ID_S)); \ |
| 6539 | } while (0) |
| 6540 | |
| 6541 | #define HTT_RX_OFLD_PKT_ERR_TID_GET(_var) \ |
| 6542 | (((_var) & HTT_RX_OFLD_PKT_ERR_TID_M) >> HTT_RX_OFLD_PKT_ERR_TID_S) |
| 6543 | #define HTT_RX_OFLD_PKT_ERR_TID_SET(_var, _val) \ |
| 6544 | do { \ |
| 6545 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_TID, _val); \ |
| 6546 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_TID_S)); \ |
| 6547 | } while (0) |
| 6548 | |
| 6549 | /* definition for HTT_RX_OFLD_PKT_ERR_MIC_ERR msg sub-type payload */ |
| 6550 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_BYTES 28 |
| 6551 | |
| 6552 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M 0x0000ffff |
| 6553 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S 0 |
| 6554 | |
| 6555 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M 0x00ff0000 |
| 6556 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S 16 |
| 6557 | |
| 6558 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M 0xffffffff |
| 6559 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S 0 |
| 6560 | |
| 6561 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M 0x0000ffff |
| 6562 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S 0 |
| 6563 | |
| 6564 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M 0xffffffff |
| 6565 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S 0 |
| 6566 | |
| 6567 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M 0x0000ffff |
| 6568 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S 0 |
| 6569 | |
| 6570 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M 0xffffffff |
| 6571 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S 0 |
| 6572 | |
| 6573 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M 0x0000ffff |
| 6574 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S 0 |
| 6575 | |
| 6576 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_GET(_var) \ |
| 6577 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_M) >> \ |
| 6578 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S) |
| 6579 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_SET(_var, _val) \ |
| 6580 | do { \ |
| 6581 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID, _val); \ |
| 6582 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PEER_ID_S)); \ |
| 6583 | } while (0) |
| 6584 | |
| 6585 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_GET(_var) \ |
| 6586 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_M) >> \ |
| 6587 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S) |
| 6588 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_SET(_var, _val) \ |
| 6589 | do { \ |
| 6590 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID, _val); \ |
| 6591 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_KEYID_S)); \ |
| 6592 | } while (0) |
| 6593 | |
| 6594 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_GET(_var) \ |
| 6595 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_M) >> \ |
| 6596 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S) |
| 6597 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_SET(_var, _val) \ |
| 6598 | do { \ |
| 6599 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0, _val); \ |
| 6600 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_31_0_S)); \ |
| 6601 | } while (0) |
| 6602 | |
| 6603 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_GET(_var) \ |
| 6604 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_M) >> \ |
| 6605 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S) |
| 6606 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_SET(_var, _val) \ |
| 6607 | do { \ |
| 6608 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32, _val); \ |
| 6609 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_RA_47_32_S)); \ |
| 6610 | } while (0) |
| 6611 | |
| 6612 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_GET(_var) \ |
| 6613 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_M) >> \ |
| 6614 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S) |
| 6615 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_SET(_var, _val) \ |
| 6616 | do { \ |
| 6617 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0, _val); \ |
| 6618 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_31_0_S)); \ |
| 6619 | } while (0) |
| 6620 | |
| 6621 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_GET(_var) \ |
| 6622 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_M) >> \ |
| 6623 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S) |
| 6624 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_SET(_var, _val) \ |
| 6625 | do { \ |
| 6626 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32, _val); \ |
| 6627 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_TA_47_32_S)); \ |
| 6628 | } while (0) |
| 6629 | |
| 6630 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_GET(_var) \ |
| 6631 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_M) >> \ |
| 6632 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S) |
| 6633 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_SET(_var, _val) \ |
| 6634 | do { \ |
| 6635 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0, _val); \ |
| 6636 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_31_0_S)); \ |
| 6637 | } while (0) |
| 6638 | |
| 6639 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_GET(_var) \ |
| 6640 | (((_var) & HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_M) >> \ |
| 6641 | HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S) |
| 6642 | #define HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_SET(_var, _val) \ |
| 6643 | do { \ |
| 6644 | HTT_CHECK_SET_VAL(HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32, _val); \ |
| 6645 | ((_var) |= ((_val) << HTT_RX_OFLD_PKT_ERR_MIC_ERR_PN_47_32_S)); \ |
| 6646 | } while (0) |
| 6647 | |
| 6648 | /** |
| 6649 | * @brief peer rate report message |
| 6650 | * |
| 6651 | * @details |
| 6652 | * HTT_T2H_MSG_TYPE_RATE_REPORT message is sent by target to host to indicate the |
| 6653 | * justified rate of all the peers. |
| 6654 | * |
| 6655 | * |31 24|23 16|15 8|7 0| |
| 6656 | * |----------------+----------------+----------------+----------------| |
| 6657 | * | peer_count | | msg_type | |
| 6658 | * |-------------------------------------------------------------------| |
| 6659 | * : Payload (variant number of peer rate report) : |
| 6660 | * :- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -: |
| 6661 | * Header fields: |
| 6662 | * - msg_type |
| 6663 | * Bits 7:0 |
| 6664 | * Purpose: Identifies this as HTT_T2H_MSG_TYPE_RATE_REPORT message. |
| 6665 | * value: 0x17 (HTT_T2H_MSG_TYPE_RATE_REPORT) |
| 6666 | * - reserved |
| 6667 | * Bits 15:8 |
| 6668 | * Purpose: |
| 6669 | * value: |
| 6670 | * - peer_count |
| 6671 | * Bits 31:16 |
| 6672 | * Purpose: Specify how many peer rate report elements are present in the payload. |
| 6673 | * value: |
| 6674 | * |
| 6675 | * Payload: |
| 6676 | * There are variant number of peer rate report follow the first 32 bits. |
| 6677 | * The peer rate report is defined as follows. |
| 6678 | * |
| 6679 | * |31 20|19 16|15 0| |
| 6680 | * |-----------------------+---------+---------------------------------|- |
| 6681 | * | reserved | phy | peer_id | \ |
| 6682 | * |-------------------------------------------------------------------| -> report #0 |
| 6683 | * | rate | / |
| 6684 | * |-----------------------+---------+---------------------------------|- |
| 6685 | * | reserved | phy | peer_id | \ |
| 6686 | * |-------------------------------------------------------------------| -> report #1 |
| 6687 | * | rate | / |
| 6688 | * |-----------------------+---------+---------------------------------|- |
| 6689 | * | reserved | phy | peer_id | \ |
| 6690 | * |-------------------------------------------------------------------| -> report #2 |
| 6691 | * | rate | / |
| 6692 | * |-------------------------------------------------------------------|- |
| 6693 | * : : |
| 6694 | * : : |
| 6695 | * : : |
| 6696 | * :-------------------------------------------------------------------: |
| 6697 | * |
| 6698 | * - peer_id |
| 6699 | * Bits 15:0 |
| 6700 | * Purpose: identify the peer |
| 6701 | * value: |
| 6702 | * - phy |
| 6703 | * Bits 19:16 |
| 6704 | * Purpose: identify which phy is in use |
| 6705 | * value: 0=11b, 1=11a/g, 2=11n, 3=11ac. |
| 6706 | * Please see enum htt_peer_report_phy_type for detail. |
| 6707 | * - reserved |
| 6708 | * Bits 31:20 |
| 6709 | * Purpose: |
| 6710 | * value: |
| 6711 | * - rate |
| 6712 | * Bits 31:0 |
| 6713 | * Purpose: represent the justified rate of the peer specified by peer_id |
| 6714 | * value: |
| 6715 | */ |
| 6716 | |
| 6717 | enum htt_peer_rate_report_phy_type { |
| 6718 | HTT_PEER_RATE_REPORT_11B = 0, |
| 6719 | HTT_PEER_RATE_REPORT_11A_G, |
| 6720 | HTT_PEER_RATE_REPORT_11N, |
| 6721 | HTT_PEER_RATE_REPORT_11AC, |
| 6722 | }; |
| 6723 | |
| 6724 | #define HTT_PEER_RATE_REPORT_SIZE 8 |
| 6725 | |
| 6726 | #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M 0xffff0000 |
| 6727 | #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S 16 |
| 6728 | |
| 6729 | #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_M 0x0000ffff |
| 6730 | #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_S 0 |
| 6731 | |
| 6732 | #define HTT_PEER_RATE_REPORT_MSG_PHY_M 0x000f0000 |
| 6733 | #define HTT_PEER_RATE_REPORT_MSG_PHY_S 16 |
| 6734 | |
| 6735 | #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_GET(_var) \ |
| 6736 | (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_M) \ |
| 6737 | >> HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S) |
| 6738 | #define HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_SET(_var, _val) \ |
| 6739 | do { \ |
| 6740 | HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_COUNT, _val); \ |
| 6741 | ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_COUNT_S)); \ |
| 6742 | } while (0) |
| 6743 | |
| 6744 | #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_GET(_var) \ |
| 6745 | (((_var) & HTT_PEER_RATE_REPORT_MSG_PEER_ID_M) \ |
| 6746 | >> HTT_PEER_RATE_REPORT_MSG_PEER_ID_S) |
| 6747 | #define HTT_PEER_RATE_REPORT_MSG_PEER_ID_SET(_var, _val) \ |
| 6748 | do { \ |
| 6749 | HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PEER_ID, _val); \ |
| 6750 | ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PEER_ID_S)); \ |
| 6751 | } while (0) |
| 6752 | |
| 6753 | #define HTT_PEER_RATE_REPORT_MSG_PHY_GET(_var) \ |
| 6754 | (((_var) & HTT_PEER_RATE_REPORT_MSG_PHY_M) \ |
| 6755 | >> HTT_PEER_RATE_REPORT_MSG_PHY_S) |
| 6756 | #define HTT_PEER_RATE_REPORT_MSG_PHY_SET(_var, _val) \ |
| 6757 | do { \ |
| 6758 | HTT_CHECK_SET_VAL(HTT_PEER_RATE_REPORT_MSG_PHY, _val); \ |
| 6759 | ((_var) |= ((_val) << HTT_PEER_RATE_REPORT_MSG_PHY_S)); \ |
| 6760 | } while (0) |
| 6761 | |
| 6762 | /** |
| 6763 | * @brief HTT_T2H_MSG_TYPE_FLOW_POOL_MAP Message |
| 6764 | * |
| 6765 | * @details |
| 6766 | * HTT_T2H_MSG_TYPE_FLOW_POOL_MAP message is sent by the target when setting up |
| 6767 | * a flow of descriptors. |
| 6768 | * |
| 6769 | * This message is in TLV format and indicates the parameters to be setup a |
| 6770 | * flow in the host. Each entry indicates that a particular flow ID is ready to |
| 6771 | * receive descriptors from a specified pool. |
| 6772 | * |
| 6773 | * The message would appear as follows: |
| 6774 | * |
| 6775 | * |31 24|23 16|15 8|7 0| |
| 6776 | * |----------------+----------------+----------------+----------------| |
| 6777 | * header | reserved | num_flows | msg_type | |
| 6778 | * |-------------------------------------------------------------------| |
| 6779 | * | | |
| 6780 | * : payload : |
| 6781 | * | | |
| 6782 | * |-------------------------------------------------------------------| |
| 6783 | * |
| 6784 | * The header field is one DWORD long and is interpreted as follows: |
| 6785 | * b'0:7 - msg_type: This will be set to HTT_T2H_MSG_TYPE_FLOW_POOL_MAP |
| 6786 | * b'8-15 - num_flows: This will indicate the number of flows being setup in |
| 6787 | * this message |
| 6788 | * b'16-31 - reserved: These bits are reserved for future use |
| 6789 | * |
| 6790 | * Payload: |
| 6791 | * The payload would contain multiple objects of the following structure. Each |
| 6792 | * object represents a flow. |
| 6793 | * |
| 6794 | * |31 24|23 16|15 8|7 0| |
| 6795 | * |----------------+----------------+----------------+----------------| |
| 6796 | * header | reserved | num_flows | msg_type | |
| 6797 | * |-------------------------------------------------------------------| |
| 6798 | * payload0| flow_type | |
| 6799 | * |-------------------------------------------------------------------| |
| 6800 | * | flow_id | |
| 6801 | * |-------------------------------------------------------------------| |
| 6802 | * | reserved0 | flow_pool_id | |
| 6803 | * |-------------------------------------------------------------------| |
| 6804 | * | reserved1 | flow_pool_size | |
| 6805 | * |-------------------------------------------------------------------| |
| 6806 | * | reserved2 | |
| 6807 | * |-------------------------------------------------------------------| |
| 6808 | * payload1| flow_type | |
| 6809 | * |-------------------------------------------------------------------| |
| 6810 | * | flow_id | |
| 6811 | * |-------------------------------------------------------------------| |
| 6812 | * | reserved0 | flow_pool_id | |
| 6813 | * |-------------------------------------------------------------------| |
| 6814 | * | reserved1 | flow_pool_size | |
| 6815 | * |-------------------------------------------------------------------| |
| 6816 | * | reserved2 | |
| 6817 | * |-------------------------------------------------------------------| |
| 6818 | * | . | |
| 6819 | * | . | |
| 6820 | * | . | |
| 6821 | * |-------------------------------------------------------------------| |
| 6822 | * |
| 6823 | * Each payload is 5 DWORDS long and is interpreted as follows: |
| 6824 | * dword0 - b'0:31 - flow_type: This indicates the type of the entity to which |
| 6825 | * this flow is associated. It can be VDEV, peer, |
| 6826 | * or tid (AC). Based on enum htt_flow_type. |
| 6827 | * |
| 6828 | * dword1 - b'0:31 - flow_id: Identifier for the flow corresponding to this |
| 6829 | * object. For flow_type vdev it is set to the |
| 6830 | * vdevid, for peer it is peerid and for tid, it is |
| 6831 | * tid_num. |
| 6832 | * |
| 6833 | * dword2 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being used |
| 6834 | * in the host for this flow |
| 6835 | * b'16:31 - reserved0: This field in reserved for the future. In case |
| 6836 | * we have a hierarchical implementation (HCM) of |
| 6837 | * pools, it can be used to indicate the ID of the |
| 6838 | * parent-pool. |
| 6839 | * |
| 6840 | * dword3 - b'0:15 - flow_pool_size: Size of the pool in number of descriptors. |
| 6841 | * Descriptors for this flow will be |
| 6842 | * allocated from this pool in the host. |
| 6843 | * b'16:31 - reserved1: This field in reserved for the future. In case |
| 6844 | * we have a hierarchical implementation of pools, |
| 6845 | * it can be used to indicate the max number of |
| 6846 | * descriptors in the pool. The b'0:15 can be used |
| 6847 | * to indicate min number of descriptors in the |
| 6848 | * HCM scheme. |
| 6849 | * |
| 6850 | * dword4 - b'0:31 - reserved2: This field in reserved for the future. In case |
| 6851 | * we have a hierarchical implementation of pools, |
| 6852 | * b'0:15 can be used to indicate the |
| 6853 | * priority-based borrowing (PBB) threshold of |
| 6854 | * the flow's pool. The b'16:31 are still left |
| 6855 | * reserved. |
| 6856 | */ |
| 6857 | |
| 6858 | enum htt_flow_type { |
| 6859 | FLOW_TYPE_VDEV = 0, |
| 6860 | /* Insert new flow types above this line */ |
| 6861 | }; |
| 6862 | |
| 6863 | PREPACK struct htt_flow_pool_map_payload_t { |
| 6864 | A_UINT32 flow_type; |
| 6865 | A_UINT32 flow_id; |
| 6866 | A_UINT32 flow_pool_id:16, |
| 6867 | reserved0:16; |
| 6868 | A_UINT32 flow_pool_size:16, |
| 6869 | reserved1:16; |
| 6870 | A_UINT32 reserved2; |
| 6871 | } POSTPACK; |
| 6872 | |
| 6873 | #define HTT_FLOW_POOL_MAP_HEADER_SZ (sizeof(A_UINT32)) |
| 6874 | |
| 6875 | #define HTT_FLOW_POOL_MAP_PAYLOAD_SZ \ |
| 6876 | (sizeof(struct htt_flow_pool_map_payload_t)) |
| 6877 | |
| 6878 | #define HTT_FLOW_POOL_MAP_NUM_FLOWS_M 0x0000ff00 |
| 6879 | #define HTT_FLOW_POOL_MAP_NUM_FLOWS_S 8 |
| 6880 | |
| 6881 | #define HTT_FLOW_POOL_MAP_FLOW_TYPE_M 0xffffffff |
| 6882 | #define HTT_FLOW_POOL_MAP_FLOW_TYPE_S 0 |
| 6883 | |
| 6884 | #define HTT_FLOW_POOL_MAP_FLOW_ID_M 0xffffffff |
| 6885 | #define HTT_FLOW_POOL_MAP_FLOW_ID_S 0 |
| 6886 | |
| 6887 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M 0x0000ffff |
| 6888 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S 0 |
| 6889 | |
| 6890 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M 0x0000ffff |
| 6891 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S 0 |
| 6892 | |
| 6893 | #define HTT_FLOW_POOL_MAP_NUM_FLOWS_GET(_var) \ |
| 6894 | (((_var) & HTT_FLOW_POOL_MAP_NUM_FLOWS_M) >> HTT_FLOW_POOL_MAP_NUM_FLOWS_S) |
| 6895 | |
| 6896 | #define HTT_FLOW_POOL_MAP_FLOW_TYPE_GET(_var) \ |
| 6897 | (((_var) & HTT_FLOW_POOL_MAP_FLOW_TYPE_M) >> HTT_FLOW_POOL_MAP_FLOW_TYPE_S) |
| 6898 | |
| 6899 | #define HTT_FLOW_POOL_MAP_FLOW_ID_GET(_var) \ |
| 6900 | (((_var) & HTT_FLOW_POOL_MAP_FLOW_ID_M) >> HTT_FLOW_POOL_MAP_FLOW_ID_S) |
| 6901 | |
| 6902 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_GET(_var) \ |
| 6903 | (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_ID_M) >> \ |
| 6904 | HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S) |
| 6905 | |
| 6906 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_GET(_var) \ |
| 6907 | (((_var) & HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_M) >> \ |
| 6908 | HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S) |
| 6909 | |
| 6910 | #define HTT_FLOW_POOL_MAP_NUM_FLOWS_SET(_var, _val) \ |
| 6911 | do { \ |
| 6912 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_NUM_FLOWS, _val); \ |
| 6913 | ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_NUM_FLOWS_S)); \ |
| 6914 | } while (0) |
| 6915 | |
| 6916 | #define HTT_FLOW_POOL_MAP_FLOW_TYPE_SET(_var, _val) \ |
| 6917 | do { \ |
| 6918 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_TYPE, _val); \ |
| 6919 | ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_TYPE_S)); \ |
| 6920 | } while (0) |
| 6921 | |
| 6922 | #define HTT_FLOW_POOL_MAP_FLOW_ID_SET(_var, _val) \ |
| 6923 | do { \ |
| 6924 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_ID, _val); \ |
| 6925 | ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_ID_S)); \ |
| 6926 | } while (0) |
| 6927 | |
| 6928 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_ID_SET(_var, _val) \ |
| 6929 | do { \ |
| 6930 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_ID, _val); \ |
| 6931 | ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_ID_S)); \ |
| 6932 | } while (0) |
| 6933 | |
| 6934 | #define HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_SET(_var, _val) \ |
| 6935 | do { \ |
| 6936 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE, _val); \ |
| 6937 | ((_var) |= ((_val) << HTT_FLOW_POOL_MAP_FLOW_POOL_SIZE_S)); \ |
| 6938 | } while (0) |
| 6939 | |
| 6940 | /** |
| 6941 | * @brief HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP Message |
| 6942 | * |
| 6943 | * @details |
| 6944 | * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP message is sent by the target when tearing |
| 6945 | * down a flow of descriptors. |
| 6946 | * This message indicates that for the flow (whose ID is provided) is wanting |
| 6947 | * to stop receiving descriptors. This flow ID corresponds to the ID of the |
| 6948 | * pool of descriptors from where descriptors are being allocated for this |
| 6949 | * flow. When a flow (and its pool) are unmapped, all the child-pools will also |
| 6950 | * be unmapped by the host. |
| 6951 | * |
| 6952 | * The message would appear as follows: |
| 6953 | * |
| 6954 | * |31 24|23 16|15 8|7 0| |
| 6955 | * |----------------+----------------+----------------+----------------| |
| 6956 | * | reserved0 | msg_type | |
| 6957 | * |-------------------------------------------------------------------| |
| 6958 | * | flow_type | |
| 6959 | * |-------------------------------------------------------------------| |
| 6960 | * | flow_id | |
| 6961 | * |-------------------------------------------------------------------| |
| 6962 | * | reserved1 | flow_pool_id | |
| 6963 | * |-------------------------------------------------------------------| |
| 6964 | * |
| 6965 | * The message is interpreted as follows: |
| 6966 | * dword0 - b'0:7 - msg_type: This will be set to |
| 6967 | * HTT_T2H_MSG_TYPE_FLOW_POOL_UNMAP |
| 6968 | * b'8:31 - reserved0: Reserved for future use |
| 6969 | * |
| 6970 | * dword1 - b'0:31 - flow_type: This indicates the type of the entity to which |
| 6971 | * this flow is associated. It can be VDEV, peer, |
| 6972 | * or tid (AC). Based on enum htt_flow_type. |
| 6973 | * |
| 6974 | * dword2 - b'0:31 - flow_id: Identifier for the flow corresponding to this |
| 6975 | * object. For flow_type vdev it is set to the |
| 6976 | * vdevid, for peer it is peerid and for tid, it is |
| 6977 | * tid_num. |
| 6978 | * |
| 6979 | * dword3 - b'0:15 - flow_pool_id: Identifier of the descriptor-pool being |
| 6980 | * used in the host for this flow |
| 6981 | * b'16:31 - reserved0: This field in reserved for the future. |
| 6982 | * |
| 6983 | */ |
| 6984 | |
| 6985 | PREPACK struct htt_flow_pool_unmap_t { |
| 6986 | A_UINT32 msg_type:8, |
| 6987 | reserved0:24; |
| 6988 | A_UINT32 flow_type; |
| 6989 | A_UINT32 flow_id; |
| 6990 | A_UINT32 flow_pool_id:16, |
| 6991 | reserved1:16; |
| 6992 | } POSTPACK; |
| 6993 | |
| 6994 | #define HTT_FLOW_POOL_UNMAP_SZ (sizeof(struct htt_flow_pool_unmap_t)) |
| 6995 | |
| 6996 | #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M 0xffffffff |
| 6997 | #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S 0 |
| 6998 | |
| 6999 | #define HTT_FLOW_POOL_UNMAP_FLOW_ID_M 0xffffffff |
| 7000 | #define HTT_FLOW_POOL_UNMAP_FLOW_ID_S 0 |
| 7001 | |
| 7002 | #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M 0x0000ffff |
| 7003 | #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S 0 |
| 7004 | |
| 7005 | #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_GET(_var) \ |
| 7006 | (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_TYPE_M) >> \ |
| 7007 | HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S) |
| 7008 | |
| 7009 | #define HTT_FLOW_POOL_UNMAP_FLOW_ID_GET(_var) \ |
| 7010 | (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_ID_M) >> HTT_FLOW_POOL_UNMAP_FLOW_ID_S) |
| 7011 | |
| 7012 | #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_GET(_var) \ |
| 7013 | (((_var) & HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_M) >> \ |
| 7014 | HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S) |
| 7015 | |
| 7016 | #define HTT_FLOW_POOL_UNMAP_FLOW_TYPE_SET(_var, _val) \ |
| 7017 | do { \ |
| 7018 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_TYPE, _val); \ |
| 7019 | ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_TYPE_S)); \ |
| 7020 | } while (0) |
| 7021 | |
| 7022 | #define HTT_FLOW_POOL_UNMAP_FLOW_ID_SET(_var, _val) \ |
| 7023 | do { \ |
| 7024 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_ID, _val); \ |
| 7025 | ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_ID_S)); \ |
| 7026 | } while (0) |
| 7027 | |
| 7028 | #define HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_SET(_var, _val) \ |
| 7029 | do { \ |
| 7030 | HTT_CHECK_SET_VAL(HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID, _val); \ |
| 7031 | ((_var) |= ((_val) << HTT_FLOW_POOL_UNMAP_FLOW_POOL_ID_S)); \ |
| 7032 | } while (0) |
| 7033 | |
| 7034 | #endif |