Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __TARGADDRS_H__ |
| 29 | #define __TARGADDRS_H__ |
| 30 | |
| 31 | #if defined(ATH_TARGET) |
| 32 | #include "soc_addrs.h" |
| 33 | #endif |
| 34 | |
| 35 | #if !defined(ATH_TARGET) |
| 36 | #include "athstartpack.h" |
| 37 | #endif |
| 38 | |
| 39 | /* |
| 40 | * SOC option bits, to enable/disable various features. |
| 41 | * By default, all option bits are 0. |
| 42 | * AR6004: These bits can be set in LOCAL_SCRATCH register 0. |
| 43 | * AR9888: These bits can be set in soc_core register SCRATCH_0. |
| 44 | */ |
| 45 | #define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */ |
| 46 | #define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */ |
| 47 | #define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */ |
| 48 | #define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */ |
| 49 | #define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */ |
| 50 | #define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */ |
| 51 | #define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */ |
| 52 | #define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */ |
| 53 | |
| 54 | /* |
| 55 | * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the |
| 56 | * host_interest structure. It must match the address of the _host_interest |
| 57 | * symbol (see linker script). |
| 58 | * |
| 59 | * Host Interest is shared between Host and Target in order to coordinate |
| 60 | * between the two, and is intended to remain constant (with additions only |
| 61 | * at the end) across software releases. |
| 62 | * |
| 63 | * All addresses are available here so that it's possible to |
| 64 | * write a single binary that works with all Target Types. |
| 65 | * May be used in assembler code as well as C. |
| 66 | */ |
| 67 | #define AR6002_HOST_INTEREST_ADDRESS 0x00500400 |
| 68 | #define AR6003_HOST_INTEREST_ADDRESS 0x00540600 |
| 69 | #define AR6004_HOST_INTEREST_ADDRESS 0x00400800 |
| 70 | #define AR9888_HOST_INTEREST_ADDRESS 0x00400800 |
| 71 | #define AR900B_HOST_INTEREST_ADDRESS 0x00400800 |
| 72 | #define AR6320_HOST_INTEREST_ADDRESS 0x00400800 |
| 73 | #define QCA6180_HOST_INTEREST_ADDRESS 0x005d96a0 |
| 74 | #define AR6004_SOC_RESET_ADDRESS 0X00004000 |
| 75 | #define AR6004_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800 |
| 76 | #if defined(AR6006_MEMORY_NEW_ARCH) |
| 77 | #define AR6006_HOST_INTEREST_ADDRESS 0x00428800 |
| 78 | #else |
| 79 | #define AR6006_HOST_INTEREST_ADDRESS 0x00400800 |
| 80 | #endif |
| 81 | #define AR6006_SOC_RESET_ADDRESS 0X00004000 |
| 82 | #define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800 |
| 83 | |
| 84 | #define HOST_INTEREST_MAX_SIZE 0x200 |
| 85 | |
| 86 | #if !defined(__ASSEMBLER__) |
| 87 | struct register_dump_s; |
| 88 | struct dbglog_hdr_s; |
| 89 | |
| 90 | /* |
| 91 | * These are items that the Host may need to access |
| 92 | * via BMI or via the Diagnostic Window. The position |
| 93 | * of items in this structure must remain constant |
| 94 | * across firmware revisions! |
| 95 | * |
| 96 | * Types for each item must be fixed size across |
| 97 | * target and host platforms. |
| 98 | * |
| 99 | * More items may be added at the end. |
| 100 | */ |
| 101 | PREPACK64 struct host_interest_s { |
| 102 | /* |
| 103 | * Pointer to application-defined area, if any. |
| 104 | * Set by Target application during startup. |
| 105 | */ |
| 106 | A_UINT32 hi_app_host_interest; /* 0x00 */ |
| 107 | |
| 108 | /* Pointer to register dump area, valid after Target crash. */ |
| 109 | A_UINT32 hi_failure_state; /* 0x04 */ |
| 110 | |
| 111 | /* Pointer to debug logging header */ |
| 112 | A_UINT32 hi_dbglog_hdr; /* 0x08 */ |
| 113 | |
| 114 | /* Save SW ROM version */ |
| 115 | A_UINT32 hi_sw_rom_version; /* 0x0c */ |
| 116 | |
| 117 | /* |
| 118 | * General-purpose flag bits, similar to SOC_OPTION_* flags. |
| 119 | * Can be used by application rather than by OS. |
| 120 | */ |
| 121 | A_UINT32 hi_option_flag; /* 0x10 */ |
| 122 | |
| 123 | /* |
| 124 | * Boolean that determines whether or not to |
| 125 | * display messages on the serial port. |
| 126 | */ |
| 127 | A_UINT32 hi_serial_enable; /* 0x14 */ |
| 128 | |
| 129 | /* Start address of DataSet index, if any */ |
| 130 | A_UINT32 hi_dset_list_head; /* 0x18 */ |
| 131 | |
| 132 | /* Override Target application start address */ |
| 133 | A_UINT32 hi_app_start; /* 0x1c */ |
| 134 | |
| 135 | /* Clock and voltage tuning */ |
| 136 | A_UINT32 hi_skip_clock_init; /* 0x20 */ |
| 137 | A_UINT32 hi_core_clock_setting; /* 0x24 */ |
| 138 | A_UINT32 hi_cpu_clock_setting; /* 0x28 */ |
| 139 | A_UINT32 hi_system_sleep_setting; /* 0x2c */ |
| 140 | A_UINT32 hi_xtal_control_setting; /* 0x30 */ |
| 141 | A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */ |
| 142 | A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */ |
| 143 | A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */ |
| 144 | A_UINT32 hi_clock_info; /* 0x40 */ |
| 145 | |
| 146 | /* Host uses BE CPU or not */ |
| 147 | A_UINT32 hi_be; /* 0x44 */ |
| 148 | |
| 149 | A_UINT32 hi_stack; /* normal stack *//* 0x48 */ |
| 150 | A_UINT32 hi_err_stack; /* error stack *//* 0x4c */ |
| 151 | A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */ |
| 152 | |
| 153 | /* Pointer to Board Data */ |
| 154 | A_UINT32 hi_board_data; /* 0x54 */ |
| 155 | |
| 156 | /* |
| 157 | * Indication of Board Data state: |
| 158 | * 0: board data is not yet initialized. |
| 159 | * 1: board data is initialized; unknown size |
| 160 | * >1: number of bytes of initialized board data (varies with board type) |
| 161 | */ |
| 162 | A_UINT32 hi_board_data_initialized; /* 0x58 */ |
| 163 | |
| 164 | A_UINT32 hi_dset_RAM_index_table; /* 0x5c */ |
| 165 | |
| 166 | A_UINT32 hi_desired_baud_rate; /* 0x60 */ |
| 167 | A_UINT32 hi_dbglog_config; /* 0x64 */ |
| 168 | A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */ |
| 169 | A_UINT32 hi_mbox_io_block_sz; /* 0x6c */ |
| 170 | |
| 171 | A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */ |
| 172 | A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */ |
| 173 | |
| 174 | A_UINT32 hi_refclk_hz; /* 0x78 */ |
| 175 | A_UINT32 hi_ext_clk_detected; /* 0x7c */ |
| 176 | A_UINT32 hi_dbg_uart_txpin; /* 0x80 */ |
| 177 | A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */ |
| 178 | A_UINT32 hi_hci_uart_baud; /* 0x88 */ |
| 179 | A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */ |
| 180 | /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */ |
| 181 | A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */ |
| 182 | A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */ |
| 183 | |
| 184 | A_UINT32 hi_allocram_start; /* 0x98 */ |
| 185 | A_UINT32 hi_allocram_sz; /* 0x9c */ |
| 186 | A_UINT32 hi_hci_bridge_flags; /* 0xa0 */ |
| 187 | A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */ |
| 188 | /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */ |
| 189 | A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */ |
| 190 | /* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high |
| 191 | * [31:16]: wakeup timeout in ms |
| 192 | */ |
| 193 | /* Pointer to extended board Data */ |
| 194 | A_UINT32 hi_board_ext_data; /* 0xac */ |
| 195 | A_UINT32 hi_board_ext_data_config; /* 0xb0 */ |
| 196 | /* |
| 197 | * Bit [0] : valid |
| 198 | * Bit[31:16: size |
| 199 | */ |
| 200 | /* |
| 201 | * hi_reset_flag is used to do some stuff when target reset. |
| 202 | * such as restore app_start after warm reset or |
| 203 | * preserve host Interest area, or preserve ROM data, literals etc. |
| 204 | */ |
| 205 | A_UINT32 hi_reset_flag; /* 0xb4 */ |
| 206 | /* indicate hi_reset_flag is valid */ |
| 207 | A_UINT32 hi_reset_flag_valid; /* 0xb8 */ |
| 208 | A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */ |
| 209 | /* 0xbc - [31:0]: idle timeout in ms |
| 210 | */ |
| 211 | /* ACS flags */ |
| 212 | A_UINT32 hi_acs_flags; /* 0xc0 */ |
| 213 | A_UINT32 hi_console_flags; /* 0xc4 */ |
| 214 | A_UINT32 hi_nvram_state; /* 0xc8 */ |
| 215 | A_UINT32 hi_option_flag2; /* 0xcc */ |
| 216 | |
| 217 | /* If non-zero, override values sent to Host in WMI_READY event. */ |
| 218 | A_UINT32 hi_sw_version_override; /* 0xd0 */ |
| 219 | A_UINT32 hi_abi_version_override; /* 0xd4 */ |
| 220 | |
| 221 | /* Percentage of high priority RX traffic to total expected RX traffic - |
| 222 | * applicable only to ar6004 */ |
| 223 | A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */ |
| 224 | |
| 225 | /* test applications flags */ |
| 226 | A_UINT32 hi_test_apps_related; /* 0xdc */ |
| 227 | /* location of test script */ |
| 228 | A_UINT32 hi_ota_testscript; /* 0xe0 */ |
| 229 | /* location of CAL data */ |
| 230 | A_UINT32 hi_cal_data; /* 0xe4 */ |
| 231 | |
| 232 | /* Number of packet log buffers */ |
| 233 | A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */ |
| 234 | |
| 235 | /* wow extension configuration */ |
| 236 | A_UINT32 hi_wow_ext_config; /* 0xec */ |
| 237 | A_UINT32 hi_pwr_save_flags; /* 0xf0 */ |
| 238 | |
| 239 | /* Spatial Multiplexing Power Save (SMPS) options */ |
| 240 | A_UINT32 hi_smps_options; /* 0xf4 */ |
| 241 | |
| 242 | /* Interconnect-specific state */ |
| 243 | A_UINT32 hi_interconnect_state; /* 0xf8 */ |
| 244 | |
| 245 | /* Coex configuration flags */ |
| 246 | A_UINT32 hi_coex_config; /* 0xfc */ |
| 247 | |
| 248 | /* Early allocation support */ |
| 249 | A_UINT32 hi_early_alloc; /* 0x100 */ |
| 250 | |
| 251 | /* FW swap field */ |
| 252 | /* Bits of this 32bit word will be used to pass specific swap |
| 253 | instruction to FW */ |
| 254 | /* Bit 0 -- AP Nart descriptor no swap. When this bit is set |
| 255 | FW will not swap TX descriptor. Meaning packets are formed |
| 256 | on the target processor. */ |
| 257 | /* Bit 1 -- TBD */ |
| 258 | |
| 259 | A_UINT32 hi_fw_swap; /* 0x104 */ |
| 260 | |
| 261 | /* global arenas pointer address, used by host driver debug */ |
| 262 | A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */ |
| 263 | |
| 264 | /* allocated bytes of DRAM use by allocated */ |
| 265 | A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */ |
| 266 | |
| 267 | /* remaining bytes of DRAM */ |
| 268 | A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */ |
| 269 | |
| 270 | /* memory track count, configured by host */ |
| 271 | A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */ |
| 272 | |
| 273 | /* minidump buffer */ |
| 274 | A_UINT32 hi_minidump; /* 0x118 */ |
| 275 | |
| 276 | /* bdata's sig and key addr */ |
| 277 | A_UINT32 hi_bd_sig_key; /* 0x11c */ |
| 278 | |
| 279 | } POSTPACK64; |
| 280 | |
| 281 | /* bitmap for hi_test_apps_related */ |
| 282 | #define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001 |
| 283 | #define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002 |
| 284 | |
| 285 | /* Bits defined in hi_option_flag */ |
| 286 | #define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */ |
| 287 | #define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */ |
| 288 | #define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */ |
| 289 | #define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */ |
| 290 | #define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */ |
| 291 | #define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */ |
| 292 | #define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */ |
| 293 | #define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */ |
| 294 | #define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */ |
| 295 | #define HI_OPTION_NUM_DEV_LSB 0x200 |
| 296 | #define HI_OPTION_NUM_DEV_MSB 0x800 |
| 297 | #define HI_OPTION_DEV_MODE_LSB 0x1000 |
| 298 | #define HI_OPTION_DEV_MODE_MSB 0x8000000 |
| 299 | #define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */ |
| 300 | #define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */ |
| 301 | #define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before |
| 302 | * sending WMI ready event to host */ |
| 303 | #define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */ |
| 304 | |
| 305 | #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3 |
| 306 | |
| 307 | /* 2 bits of hi_option_flag are used to represent 3 modes */ |
| 308 | #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */ |
| 309 | #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */ |
| 310 | #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */ |
| 311 | #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */ |
| 312 | |
| 313 | /* 2 bits of hi_option flag are usedto represent 4 submodes */ |
| 314 | #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */ |
| 315 | #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */ |
| 316 | #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */ |
| 317 | #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */ |
| 318 | |
| 319 | /* Num dev Mask */ |
| 320 | #define HI_OPTION_NUM_DEV_MASK 0x7 |
| 321 | #define HI_OPTION_NUM_DEV_SHIFT 0x9 |
| 322 | |
| 323 | /* firmware bridging */ |
| 324 | #define HI_OPTION_FW_BRIDGE_SHIFT 0x04 |
| 325 | |
| 326 | /* Fw Mode/SubMode Mask |
| 327 | |-------------------------------------------------------------------------------| |
| 328 | | SUB | SUB | SUB | SUB | | | | | |
| 329 | | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] | |
| 330 | | (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) | |
| 331 | |||-------------------------------------------------------------------------------| |
| 332 | */ |
| 333 | #define HI_OPTION_FW_MODE_BITS 0x2 |
| 334 | #define HI_OPTION_FW_MODE_MASK 0x3 |
| 335 | #define HI_OPTION_FW_MODE_SHIFT 0xC |
| 336 | #define HI_OPTION_ALL_FW_MODE_MASK 0xFF |
| 337 | |
| 338 | #define HI_OPTION_FW_SUBMODE_BITS 0x2 |
| 339 | #define HI_OPTION_FW_SUBMODE_MASK 0x3 |
| 340 | #define HI_OPTION_FW_SUBMODE_SHIFT 0x14 |
| 341 | #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00 |
| 342 | #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8 |
| 343 | |
| 344 | /* hi_option_flag2 options */ |
| 345 | #define HI_OPTION_OFFLOAD_AMSDU 0x01 |
| 346 | #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */ |
| 347 | #define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */ |
| 348 | #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */ |
| 349 | #define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */ |
| 350 | |
| 351 | #define HI_OPTION_RF_KILL_SHIFT 0x2 |
| 352 | #define HI_OPTION_RF_KILL_MASK 0x1 |
| 353 | |
| 354 | /* AR9888 1.0 only. Enable/disable CDC max perf support from host */ |
| 355 | #define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20 |
| 356 | #define CDC_MAX_PERF_WAR_ENABLED() \ |
| 357 | (!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR)) |
| 358 | |
| 359 | #define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU */ |
| 360 | #define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */ |
| 361 | #define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */ |
| 362 | #define GPIO_WAKEUP_ENABLED() \ |
| 363 | (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT) |
| 364 | |
| 365 | /* hi_reset_flag */ |
| 366 | #define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */ |
| 367 | #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */ |
| 368 | #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */ |
| 369 | #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08 |
| 370 | #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10 |
| 371 | #define HI_RESET_FLAG_WARM_RESET 0x20 |
| 372 | |
| 373 | /* define hi_fw_swap bits */ |
| 374 | #define HI_DESC_IN_FW_BIT 0x01 |
| 375 | |
| 376 | #define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */ |
| 377 | |
| 378 | #define ON_RESET_FLAGS_VALID() \ |
| 379 | (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID) |
| 380 | |
| 381 | #define RESET_FLAGS_VALIDATE() \ |
| 382 | (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID) |
| 383 | |
| 384 | #define RESET_FLAGS_INVALIDATE() \ |
| 385 | (HOST_INTEREST->hi_reset_flag_valid = 0) |
| 386 | |
| 387 | #define ON_RESET_PRESERVE_APP_START() \ |
| 388 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START) |
| 389 | |
| 390 | #define ON_RESET_PRESERVE_NVRAM_STATE() \ |
| 391 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE) |
| 392 | |
| 393 | #define ON_RESET_PRESERVE_HOST_INTEREST() \ |
| 394 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST) |
| 395 | |
| 396 | #define ON_RESET_PRESERVE_ROMDATA() \ |
| 397 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA) |
| 398 | |
| 399 | #define ON_RESET_PRESERVE_BOOT_INFO() \ |
| 400 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO) |
| 401 | |
| 402 | #define ON_RESET_WARM_RESET() \ |
| 403 | (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET) |
| 404 | |
| 405 | /* host CPU endianness */ |
| 406 | #define HOST_ON_BE_CPU() \ |
| 407 | (HOST_INTEREST->hi_be) |
| 408 | |
| 409 | /* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */ |
| 410 | #define DESC_IN_FW() \ |
| 411 | (HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT) |
| 412 | |
| 413 | #define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */ |
| 414 | #define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */ |
| 415 | #define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */ |
| 416 | |
| 417 | /* CONSOLE FLAGS |
| 418 | * |
| 419 | * Bit Range Meaning |
| 420 | * --------- -------------------------------- |
| 421 | * 2..0 UART ID (0 = Default) |
| 422 | * 3 Baud Select (0 = 9600, 1 = 115200) |
| 423 | * 30..4 Reserved |
| 424 | * 31 Enable Console |
| 425 | * |
| 426 | * */ |
| 427 | |
| 428 | #define HI_CONSOLE_FLAGS_ENABLE (1 << 31) |
| 429 | #define HI_CONSOLE_FLAGS_UART_MASK (0x7) |
| 430 | #define HI_CONSOLE_FLAGS_UART_SHIFT 0 |
| 431 | #define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3) |
| 432 | |
| 433 | /* SM power save options */ |
| 434 | #define HI_SMPS_ALLOW_MASK (0x00000001) |
| 435 | #define HI_SMPS_MODE_MASK (0x00000002) |
| 436 | #define HI_SMPS_MODE_STATIC (0x00000000) |
| 437 | #define HI_SMPS_MODE_DYNAMIC (0x00000002) |
| 438 | #define HI_SMPS_DISABLE_AUTO_MODE (0x00000004) |
| 439 | #define HI_SMPS_DATA_THRESH_MASK (0x000007f8) |
| 440 | #define HI_SMPS_DATA_THRESH_SHIFT (3) |
| 441 | #define HI_SMPS_RSSI_THRESH_MASK (0x0007f800) |
| 442 | #define HI_SMPS_RSSI_THRESH_SHIFT (11) |
| 443 | #define HI_SMPS_LOWPWR_CM_MASK (0x00380000) |
| 444 | #define HI_SMPS_LOWPWR_CM_SHIFT (15) |
| 445 | #define HI_SMPS_HIPWR_CM_MASK (0x03c00000) |
| 446 | #define HI_SMPS_HIPWR_CM_SHIFT (19) |
| 447 | |
| 448 | #define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK) |
| 449 | #define HOST_INTEREST_SMPS_GET_DATA_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT) |
| 450 | #define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK) |
| 451 | #define HOST_INTEREST_SMPS_GET_RSSI_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT) |
| 452 | #define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK) |
| 453 | #define HOST_INTEREST_SMPS_SET_LOWPWR_CM() ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT) |
| 454 | #define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT) |
| 455 | #define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE) |
| 456 | |
| 457 | /* WOW Extension configuration |
| 458 | * |
| 459 | * Bit Range Meaning |
| 460 | * --------- -------------------------------- |
| 461 | * 8..0 Size of each WOW pattern (max 511) |
| 462 | * 15..9 Number of patterns per list (max 127) |
| 463 | * 17..16 Number of lists (max 4) |
| 464 | * 30..18 Reserved |
| 465 | * 31 Enabled |
| 466 | * |
| 467 | * set values (except enable) to zeros for default settings |
| 468 | * |
| 469 | * */ |
| 470 | |
| 471 | #define HI_WOW_EXT_ENABLED_MASK (1 << 31) |
| 472 | #define HI_WOW_EXT_NUM_LIST_SHIFT 16 |
| 473 | #define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT) |
| 474 | #define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9 |
| 475 | #define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT) |
| 476 | #define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0 |
| 477 | #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT) |
| 478 | |
| 479 | #define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \ |
| 480 | ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \ |
| 481 | (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \ |
| 482 | (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK)) |
| 483 | |
| 484 | #define HI_WOW_EXT_GET_NUM_LISTS(config) \ |
| 485 | (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT) |
| 486 | #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \ |
| 487 | (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT) |
| 488 | #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \ |
| 489 | (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT) |
| 490 | |
| 491 | /* |
| 492 | * Early allocation configuration |
| 493 | * Support RAM bank configuration before BMI done and this eases the memory |
| 494 | * allocation at very early stage |
| 495 | * Bit Range Meaning |
| 496 | * --------- ---------------------------------- |
| 497 | * [0:3] number of bank assigned to be IRAM |
| 498 | * [4:15] reserved |
| 499 | * [16:31] magic number |
| 500 | * |
| 501 | * Note: |
| 502 | * 1. target firmware would check magic number and if it's a match, firmware |
| 503 | * would consider the bits[0:15] are valid and base on that to calculate |
| 504 | * the end of DRAM. Early allocation would be located at that area and |
| 505 | * may be reclaimed when necesary |
| 506 | * 2. if no magic number is found, early allocation would happen at "_end" |
| 507 | * symbol of ROM which is located before the app-data and might NOT be |
| 508 | * re-claimable. If this is adopted, link script should keep this in |
| 509 | * mind to avoid data corruption. |
| 510 | */ |
| 511 | #define HI_EARLY_ALLOC_MAGIC 0x6d8a |
| 512 | #define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000 |
| 513 | #define HI_EARLY_ALLOC_MAGIC_SHIFT 16 |
| 514 | #define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f |
| 515 | #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0 |
| 516 | |
| 517 | #define HI_EARLY_ALLOC_VALID() \ |
| 518 | ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \ |
| 519 | == (HI_EARLY_ALLOC_MAGIC)) |
| 520 | #define HI_EARLY_ALLOC_GET_IRAM_BANKS() \ |
| 521 | (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT) |
| 522 | |
| 523 | /* |
| 524 | * Intended for use by Host software, this macro returns the Target RAM |
| 525 | * address of any item in the host_interest structure. |
| 526 | * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data); |
| 527 | */ |
| 528 | #define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 529 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item))) |
| 530 | |
| 531 | #define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 532 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item))) |
| 533 | |
| 534 | #define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 535 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item))) |
| 536 | |
| 537 | #define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 538 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item))) |
| 539 | |
| 540 | #define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 541 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item))) |
| 542 | |
| 543 | #define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 544 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item))) |
| 545 | |
| 546 | #define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \ |
| 547 | (A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item))) |
| 548 | |
| 549 | #define HOST_INTEREST_DBGLOG_IS_ENABLED() \ |
| 550 | (!((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG)) |
| 551 | |
| 552 | #define HOST_INTEREST_PKTLOG_IS_ENABLED() \ |
| 553 | (((volatile A_UINT32)HOST_INTEREST->hi_pktlog_num_buffers)) |
| 554 | |
| 555 | #define HOST_INTEREST_PROFILE_IS_ENABLED() \ |
| 556 | ((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE) |
| 557 | |
| 558 | #define LF_TIMER_STABILIZATION_IS_ENABLED() \ |
| 559 | (!((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL)) |
| 560 | |
| 561 | #define IS_AMSDU_OFFLAOD_ENABLED() \ |
| 562 | (((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU)) |
| 563 | |
| 564 | #define HOST_INTEREST_DFS_IS_ENABLED() \ |
| 565 | (((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT)) |
| 566 | |
| 567 | #define HOST_INTEREST_EARLY_CFG_DONE() \ |
| 568 | (((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE)) |
| 569 | |
| 570 | /*power save flag bit definitions*/ |
| 571 | #define HI_PWR_SAVE_LPL_ENABLED 0x1 |
| 572 | /*b1-b3 reserved*/ |
| 573 | /*b4-b5 : dev0 LPL type : 0 - none |
| 574 | 1- Reduce Pwr Search |
| 575 | 2- Reduce Pwr Listen*/ |
| 576 | /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/ |
| 577 | #define HI_PWR_SAVE_LPL_DEV0_LSB 4 |
| 578 | #define HI_PWR_SAVE_LPL_DEV_MASK 0x3 |
| 579 | /*power save related utility macros*/ |
| 580 | #define HI_LPL_ENABLED() \ |
| 581 | ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED)) |
| 582 | #define HI_DEV_LPL_TYPE_GET(_devix) \ |
| 583 | (HOST_INTEREST->hi_pwr_save_flags & \ |
| 584 | ((HI_PWR_SAVE_LPL_DEV_MASK) << \ |
| 585 | (HI_PWR_SAVE_LPL_DEV0_LSB + \ |
| 586 | (_devix)*2))) |
| 587 | |
| 588 | #define HOST_INTEREST_SMPS_IS_ALLOWED() \ |
| 589 | ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK)) |
| 590 | |
| 591 | /* Convert a Target virtual address into a Target physical address */ |
| 592 | #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff) |
| 593 | #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff) |
| 594 | #define AR6004_VTOP(vaddr) (vaddr) |
| 595 | #define AR6006_VTOP(vaddr) (vaddr) |
| 596 | #define AR9888_VTOP(vaddr) (vaddr) |
| 597 | #define AR6320_VTOP(vaddr) (vaddr) |
| 598 | #define AR900B_VTOP(vaddr) (vaddr) |
| 599 | #define TARG_VTOP(TargetType, vaddr) \ |
| 600 | (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \ |
| 601 | (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \ |
| 602 | (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \ |
| 603 | (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \ |
| 604 | (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \ |
| 605 | (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \ |
| 606 | (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \ |
| 607 | 0))))))) |
| 608 | |
| 609 | #define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \ |
| 610 | (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 611 | (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 612 | (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 613 | (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 614 | (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 615 | (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 616 | (((TargetType) == TARGET_TYPE_AR6320V2) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 617 | (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \ |
| 618 | 0)))))))) |
| 619 | |
| 620 | #define AR6002_BOARD_DATA_SZ 768 |
| 621 | #define AR6002_BOARD_EXT_DATA_SZ 0 |
| 622 | #define AR6003_BOARD_DATA_SZ 1024 |
| 623 | /* Reserve 1024 bytes for extended board data */ |
| 624 | #if defined(AR6002_REV43) |
| 625 | #define AR6003_BOARD_EXT_DATA_SZ 1024 |
| 626 | #else |
| 627 | #define AR6003_BOARD_EXT_DATA_SZ 768 |
| 628 | #endif |
| 629 | #define AR6004_BOARD_DATA_SZ 7168 |
| 630 | #define AR6004_BOARD_EXT_DATA_SZ 0 |
| 631 | #define AR9888_BOARD_DATA_SZ 7168 |
| 632 | #define AR9888_BOARD_EXT_DATA_SZ 0 |
| 633 | #define AR6320_BOARD_DATA_SZ 8192 |
| 634 | #define AR6320_BOARD_EXT_DATA_SZ 0 |
| 635 | #define AR900B_BOARD_DATA_SZ 7168 |
| 636 | #define AR900B_BOARD_EXT_DATA_SZ 0 |
| 637 | |
| 638 | #define AR6003_REV3_APP_START_OVERRIDE 0x946100 |
| 639 | #define AR6003_REV3_APP_LOAD_ADDRESS 0x545000 |
| 640 | #define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330 |
| 641 | #define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74 |
| 642 | #define AR6003_REV3_RAM_RESERVE_SIZE 4096 |
| 643 | |
| 644 | #define AR6004_REV1_BOARD_DATA_ADDRESS 0x423900 |
| 645 | #define AR6004_REV1_RAM_RESERVE_SIZE 19456 |
| 646 | #define AR6004_REV1_DATASET_PATCH_ADDRESS 0x425294 |
| 647 | |
| 648 | #define AR6004_REV2_BOARD_DATA_ADDRESS 0x426400 |
| 649 | #define AR6004_REV2_RAM_RESERVE_SIZE 7168 |
| 650 | #define AR6004_REV2_DATASET_PATCH_ADDRESS 0x435294 |
| 651 | |
| 652 | #define AR6004_REV5_BOARD_DATA_ADDRESS 0x436400 |
| 653 | #define AR6004_REV5_RAM_RESERVE_SIZE 7168 |
| 654 | #define AR6004_REV5_DATASET_PATCH_ADDRESS 0x437860 |
| 655 | |
| 656 | /* Reserve 4K for OTA test script */ |
| 657 | #define AR6004_REV1_RAM_RESERVE_SIZE_FOR_TEST_SCRIPT 4096 |
| 658 | #define AR6004_REV1_TEST_SCRIPT_ADDRESS 0x422900 |
| 659 | |
| 660 | /* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */ |
| 661 | #define AR6003_FETCH_TARG_REGS_COUNT 64 |
| 662 | #define AR6004_FETCH_TARG_REGS_COUNT 64 |
| 663 | #define AR9888_FETCH_TARG_REGS_COUNT 64 |
| 664 | #define AR6320_FETCH_TARG_REGS_COUNT 64 |
| 665 | #define AR900B_FETCH_TARG_REGS_COUNT 64 |
| 666 | |
| 667 | #endif /* !__ASSEMBLER__ */ |
| 668 | |
| 669 | #ifndef ATH_TARGET |
| 670 | #include "athendpack.h" |
| 671 | #endif |
| 672 | |
| 673 | #endif /* __TARGADDRS_H__ */ |