Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1 | /* |
Dhanashri Atre | 83d373d | 2015-07-28 16:45:59 -0700 | [diff] [blame] | 2 | * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved. |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef _HTT_TYPES__H_ |
| 29 | #define _HTT_TYPES__H_ |
| 30 | |
| 31 | #include <osdep.h> /* uint16_t, dma_addr_t */ |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 32 | #include <qdf_types.h> /* qdf_device_t */ |
Anurag Chouhan | a37b5b7 | 2016-02-21 14:53:42 +0530 | [diff] [blame] | 33 | #include <qdf_lock.h> /* qdf_spinlock_t */ |
Anurag Chouhan | 754fbd8 | 2016-02-19 17:00:08 +0530 | [diff] [blame] | 34 | #include <qdf_timer.h> /* qdf_timer_t */ |
Anurag Chouhan | 8e0ccd3 | 2016-02-19 15:30:20 +0530 | [diff] [blame] | 35 | #include <qdf_atomic.h> /* qdf_atomic_inc */ |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 36 | #include <qdf_nbuf.h> /* qdf_nbuf_t */ |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 37 | #include <htc_api.h> /* HTC_PACKET */ |
| 38 | |
| 39 | #include <ol_ctrl_api.h> /* ol_pdev_handle */ |
| 40 | #include <ol_txrx_api.h> /* ol_txrx_pdev_handle */ |
| 41 | |
| 42 | #define DEBUG_DMA_DONE |
| 43 | |
Anurag Chouhan | a37b5b7 | 2016-02-21 14:53:42 +0530 | [diff] [blame] | 44 | #define HTT_TX_MUTEX_TYPE qdf_spinlock_t |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 45 | |
| 46 | #ifdef QCA_TX_HTT2_SUPPORT |
| 47 | #ifndef HTC_TX_HTT2_MAX_SIZE |
| 48 | /* Should sync to the target's implementation. */ |
| 49 | #define HTC_TX_HTT2_MAX_SIZE (120) |
| 50 | #endif |
| 51 | #endif /* QCA_TX_HTT2_SUPPORT */ |
| 52 | |
| 53 | |
| 54 | struct htt_htc_pkt { |
| 55 | void *pdev_ctxt; |
| 56 | dma_addr_t nbuf_paddr; |
| 57 | HTC_PACKET htc_pkt; |
| 58 | uint16_t msdu_id; |
| 59 | }; |
| 60 | |
| 61 | struct htt_htc_pkt_union { |
| 62 | union { |
| 63 | struct htt_htc_pkt pkt; |
| 64 | struct htt_htc_pkt_union *next; |
| 65 | } u; |
| 66 | }; |
| 67 | |
| 68 | /* |
| 69 | * HTT host descriptor: |
| 70 | * Include the htt_tx_msdu_desc that gets downloaded to the target, |
| 71 | * but also include the HTC_FRAME_HDR and alignment padding that |
| 72 | * precede the htt_tx_msdu_desc. |
| 73 | * htc_send_data_pkt expects this header space at the front of the |
| 74 | * initial fragment (i.e. tx descriptor) that is downloaded. |
| 75 | */ |
| 76 | struct htt_host_tx_desc_t { |
| 77 | uint8_t htc_header[HTC_HEADER_LEN]; |
| 78 | /* force the tx_desc field to begin on a 4-byte boundary */ |
| 79 | union { |
| 80 | uint32_t dummy_force_align; |
| 81 | struct htt_tx_msdu_desc_t tx_desc; |
| 82 | } align32; |
| 83 | }; |
| 84 | |
| 85 | struct htt_tx_mgmt_desc_buf { |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 86 | qdf_nbuf_t msg_buf; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 87 | A_BOOL is_inuse; |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 88 | qdf_nbuf_t mgmt_frm; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 89 | }; |
| 90 | |
| 91 | struct htt_tx_mgmt_desc_ctxt { |
| 92 | struct htt_tx_mgmt_desc_buf *pool; |
| 93 | A_UINT32 pending_cnt; |
| 94 | }; |
| 95 | |
| 96 | struct htt_list_node { |
| 97 | struct htt_list_node *prev; |
| 98 | struct htt_list_node *next; |
| 99 | }; |
| 100 | |
| 101 | struct htt_rx_hash_entry { |
| 102 | A_UINT32 paddr; |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 103 | qdf_nbuf_t netbuf; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 104 | A_UINT8 fromlist; |
| 105 | struct htt_list_node listnode; |
| 106 | #ifdef RX_HASH_DEBUG |
| 107 | A_UINT32 cookie; |
| 108 | #endif |
| 109 | }; |
| 110 | |
| 111 | struct htt_rx_hash_bucket { |
| 112 | struct htt_list_node listhead; |
| 113 | struct htt_rx_hash_entry *entries; |
| 114 | struct htt_list_node freepool; |
| 115 | #ifdef RX_HASH_DEBUG |
| 116 | A_UINT32 count; |
| 117 | #endif |
| 118 | }; |
| 119 | |
| 120 | /* IPA micro controller |
| 121 | wlan host driver |
| 122 | firmware shared memory structure */ |
| 123 | struct uc_shared_mem_t { |
| 124 | uint32_t *vaddr; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 125 | qdf_dma_addr_t paddr; |
| 126 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 127 | }; |
| 128 | |
| 129 | /* Micro controller datapath offload |
| 130 | * WLAN TX resources */ |
| 131 | struct htt_ipa_uc_tx_resource_t { |
| 132 | struct uc_shared_mem_t tx_ce_idx; |
| 133 | struct uc_shared_mem_t tx_comp_base; |
| 134 | |
| 135 | uint32_t tx_comp_idx_paddr; |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 136 | qdf_nbuf_t *tx_buf_pool_vaddr_strg; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 137 | uint32_t alloc_tx_buf_cnt; |
| 138 | }; |
| 139 | |
Leo Chang | 8e07361 | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 140 | /** |
| 141 | * struct htt_ipa_uc_rx_resource_t |
| 142 | * @rx_rdy_idx_paddr: rx ready index physical address |
| 143 | * @rx_ind_ring_base: rx indication ring base memory info |
| 144 | * @rx_ipa_prc_done_idx: rx process done index memory info |
| 145 | * @rx_ind_ring_size: rx process done ring size |
| 146 | * @rx2_rdy_idx_paddr: rx process done index physical address |
| 147 | * @rx2_ind_ring_base: rx process done indication ring base memory info |
| 148 | * @rx2_ipa_prc_done_idx: rx process done index memory info |
| 149 | * @rx2_ind_ring_size: rx process done ring size |
| 150 | */ |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 151 | struct htt_ipa_uc_rx_resource_t { |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 152 | qdf_dma_addr_t rx_rdy_idx_paddr; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 153 | struct uc_shared_mem_t rx_ind_ring_base; |
| 154 | struct uc_shared_mem_t rx_ipa_prc_done_idx; |
| 155 | uint32_t rx_ind_ring_size; |
| 156 | |
| 157 | /* 2nd RX ring */ |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 158 | qdf_dma_addr_t rx2_rdy_idx_paddr; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 159 | struct uc_shared_mem_t rx2_ind_ring_base; |
| 160 | struct uc_shared_mem_t rx2_ipa_prc_done_idx; |
| 161 | uint32_t rx2_ind_ring_size; |
| 162 | }; |
| 163 | |
Leo Chang | 8e07361 | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 164 | /** |
| 165 | * struct ipa_uc_rx_ring_elem_t |
| 166 | * @rx_packet_paddr: rx packet physical address |
| 167 | * @vdev_id: virtual interface id |
| 168 | * @rx_packet_leng: packet length |
| 169 | */ |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 170 | struct ipa_uc_rx_ring_elem_t { |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 171 | qdf_dma_addr_t rx_packet_paddr; |
Leo Chang | 8e07361 | 2015-11-13 10:55:34 -0800 | [diff] [blame] | 172 | uint32_t vdev_id; |
| 173 | uint32_t rx_packet_leng; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 174 | }; |
| 175 | |
| 176 | #if defined(HELIUMPLUS_PADDR64) |
Houston Hoffman | 43d47fa | 2016-02-24 16:34:30 -0800 | [diff] [blame] | 177 | /** |
| 178 | * msdu_ext_frag_desc: |
| 179 | * semantically, this is an array of 6 of 2-tuples of |
| 180 | * a 48-bit physical address and a 16 bit len field |
| 181 | * with the following layout: |
| 182 | * 31 16 8 0 |
| 183 | * | p t r - l o w 3 2 | |
| 184 | * | len | ptr-7/16 | |
| 185 | */ |
| 186 | struct msdu_ext_frag_desc { |
| 187 | union { |
| 188 | uint64_t desc64; |
| 189 | struct { |
| 190 | uint32_t ptr_low; |
| 191 | uint32_t ptr_hi:16, |
| 192 | len:16; |
| 193 | } frag32; |
| 194 | } u; |
| 195 | }; |
| 196 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 197 | struct msdu_ext_desc_t { |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 198 | struct cdf_tso_flags_t tso_flags; |
Houston Hoffman | 43d47fa | 2016-02-24 16:34:30 -0800 | [diff] [blame] | 199 | struct msdu_ext_frag_desc frags[6]; |
| 200 | /* |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 201 | u_int32_t frag_ptr0; |
| 202 | u_int32_t frag_len0; |
| 203 | u_int32_t frag_ptr1; |
| 204 | u_int32_t frag_len1; |
| 205 | u_int32_t frag_ptr2; |
| 206 | u_int32_t frag_len2; |
| 207 | u_int32_t frag_ptr3; |
| 208 | u_int32_t frag_len3; |
| 209 | u_int32_t frag_ptr4; |
| 210 | u_int32_t frag_len4; |
| 211 | u_int32_t frag_ptr5; |
| 212 | u_int32_t frag_len5; |
Houston Hoffman | 43d47fa | 2016-02-24 16:34:30 -0800 | [diff] [blame] | 213 | */ |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 214 | }; |
| 215 | #endif /* defined(HELIUMPLUS_PADDR64) */ |
| 216 | |
| 217 | struct htt_pdev_t { |
| 218 | ol_pdev_handle ctrl_pdev; |
| 219 | ol_txrx_pdev_handle txrx_pdev; |
| 220 | HTC_HANDLE htc_pdev; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 221 | qdf_device_t osdev; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 222 | |
| 223 | HTC_ENDPOINT_ID htc_endpoint; |
| 224 | |
| 225 | #ifdef QCA_TX_HTT2_SUPPORT |
| 226 | HTC_ENDPOINT_ID htc_tx_htt2_endpoint; |
| 227 | uint16_t htc_tx_htt2_max_size; |
| 228 | #endif /* QCA_TX_HTT2_SUPPORT */ |
| 229 | |
| 230 | #ifdef ATH_11AC_TXCOMPACT |
| 231 | HTT_TX_MUTEX_TYPE txnbufq_mutex; |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 232 | qdf_nbuf_queue_t txnbufq; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 233 | struct htt_htc_pkt_union *htt_htc_pkt_misclist; |
| 234 | #endif |
| 235 | |
| 236 | struct htt_htc_pkt_union *htt_htc_pkt_freelist; |
| 237 | struct { |
| 238 | int is_full_reorder_offload; |
| 239 | int default_tx_comp_req; |
| 240 | int ce_classify_enabled; |
| 241 | } cfg; |
| 242 | struct { |
| 243 | uint8_t major; |
| 244 | uint8_t minor; |
| 245 | } tgt_ver; |
| 246 | #if defined(HELIUMPLUS_PADDR64) |
| 247 | struct { |
| 248 | u_int8_t major; |
| 249 | u_int8_t minor; |
| 250 | } wifi_ip_ver; |
| 251 | #endif /* defined(HELIUMPLUS_PADDR64) */ |
| 252 | struct { |
| 253 | struct { |
| 254 | /* |
| 255 | * Ring of network buffer objects - |
| 256 | * This ring is used exclusively by the host SW. |
| 257 | * This ring mirrors the dev_addrs_ring that is shared |
| 258 | * between the host SW and the MAC HW. |
| 259 | * The host SW uses this netbufs ring to locate the nw |
| 260 | * buffer objects whose data buffers the HW has filled. |
| 261 | */ |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 262 | qdf_nbuf_t *netbufs_ring; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 263 | /* |
| 264 | * Ring of buffer addresses - |
| 265 | * This ring holds the "physical" device address of the |
| 266 | * rx buffers the host SW provides for MAC HW to fill. |
| 267 | */ |
| 268 | #if HTT_PADDR64 |
| 269 | uint64_t *paddrs_ring; |
| 270 | #else /* ! HTT_PADDR64 */ |
| 271 | uint32_t *paddrs_ring; |
| 272 | #endif |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 273 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 274 | } buf; |
| 275 | /* |
| 276 | * Base address of ring, as a "physical" device address rather |
| 277 | * than a CPU address. |
| 278 | */ |
| 279 | uint32_t base_paddr; |
| 280 | int size; /* how many elems in the ring (power of 2) */ |
| 281 | unsigned size_mask; /* size - 1 */ |
| 282 | |
| 283 | int fill_level; /* how many rx buffers to keep in the ring */ |
| 284 | int fill_cnt; /* # of rx buffers (full+empty) in the ring */ |
| 285 | |
| 286 | /* |
| 287 | * target_idx - |
| 288 | * Without reorder offload: |
| 289 | * not used |
| 290 | * With reorder offload: |
| 291 | * points to the location in the rx ring from which rx buffers |
| 292 | * are available to copy into the MAC DMA ring |
| 293 | */ |
| 294 | struct { |
| 295 | uint32_t *vaddr; |
| 296 | uint32_t paddr; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 297 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 298 | } target_idx; |
| 299 | |
| 300 | /* |
| 301 | * alloc_idx/host_idx - |
| 302 | * Without reorder offload: |
| 303 | * where HTT SW has deposited empty buffers |
| 304 | * This is allocated in consistent mem, so that the FW can read |
| 305 | * this variable, and program the HW's FW_IDX reg with the value |
| 306 | * of this shadow register |
| 307 | * With reorder offload: |
| 308 | * points to the end of the available free rx buffers |
| 309 | */ |
| 310 | struct { |
| 311 | uint32_t *vaddr; |
| 312 | uint32_t paddr; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 313 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 314 | } alloc_idx; |
| 315 | |
| 316 | /* sw_rd_idx - |
| 317 | * where HTT SW has processed bufs filled by rx MAC DMA */ |
| 318 | struct { |
| 319 | unsigned msdu_desc; |
| 320 | unsigned msdu_payld; |
| 321 | } sw_rd_idx; |
| 322 | |
| 323 | /* |
| 324 | * refill_retry_timer - timer triggered when the ring is not |
| 325 | * refilled to the level expected |
| 326 | */ |
Anurag Chouhan | 754fbd8 | 2016-02-19 17:00:08 +0530 | [diff] [blame] | 327 | qdf_timer_t refill_retry_timer; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 328 | |
| 329 | /* |
| 330 | * refill_ref_cnt - ref cnt for Rx buffer replenishment - this |
| 331 | * variable is used to guarantee that only one thread tries |
| 332 | * to replenish Rx ring. |
| 333 | */ |
Anurag Chouhan | 8e0ccd3 | 2016-02-19 15:30:20 +0530 | [diff] [blame] | 334 | qdf_atomic_t refill_ref_cnt; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 335 | #ifdef DEBUG_DMA_DONE |
| 336 | uint32_t dbg_initial_msdu_payld; |
| 337 | uint32_t dbg_mpdu_range; |
| 338 | uint32_t dbg_mpdu_count; |
| 339 | uint32_t dbg_ring_idx; |
| 340 | uint32_t dbg_refill_cnt; |
| 341 | uint32_t dbg_sync_success; |
| 342 | #endif |
| 343 | #ifdef HTT_RX_RESTORE |
| 344 | int rx_reset; |
| 345 | uint8_t htt_rx_restore; |
| 346 | #endif |
| 347 | struct htt_rx_hash_bucket *hash_table; |
| 348 | uint32_t listnode_offset; |
| 349 | } rx_ring; |
| 350 | long rx_fw_desc_offset; |
| 351 | int rx_mpdu_range_offset_words; |
| 352 | int rx_ind_msdu_byte_idx; |
| 353 | |
| 354 | struct { |
| 355 | int size; /* of each HTT tx desc */ |
Leo Chang | 376398b | 2015-10-23 14:19:02 -0700 | [diff] [blame] | 356 | uint16_t pool_elems; |
| 357 | uint16_t alloc_cnt; |
Anurag Chouhan | 600c3a0 | 2016-03-01 10:33:54 +0530 | [diff] [blame] | 358 | struct qdf_mem_multi_page_t desc_pages; |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 359 | uint32_t *freelist; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 360 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 361 | } tx_descs; |
| 362 | #if defined(HELIUMPLUS_PADDR64) |
| 363 | struct { |
| 364 | int size; /* of each Fragment/MSDU-Ext descriptor */ |
| 365 | int pool_elems; |
Anurag Chouhan | 600c3a0 | 2016-03-01 10:33:54 +0530 | [diff] [blame] | 366 | struct qdf_mem_multi_page_t desc_pages; |
Anurag Chouhan | 6d76066 | 2016-02-20 16:05:43 +0530 | [diff] [blame] | 367 | qdf_dma_mem_context(memctx); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 368 | } frag_descs; |
| 369 | #endif /* defined(HELIUMPLUS_PADDR64) */ |
| 370 | |
| 371 | int download_len; |
| 372 | void (*tx_send_complete_part2)(void *pdev, A_STATUS status, |
Nirav Shah | cbc6d72 | 2016-03-01 16:24:53 +0530 | [diff] [blame^] | 373 | qdf_nbuf_t msdu, uint16_t msdu_id); |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 374 | |
| 375 | HTT_TX_MUTEX_TYPE htt_tx_mutex; |
| 376 | |
| 377 | struct { |
| 378 | int htc_err_cnt; |
| 379 | } stats; |
| 380 | |
| 381 | struct htt_tx_mgmt_desc_ctxt tx_mgmt_desc_ctxt; |
| 382 | struct targetdef_s *targetdef; |
| 383 | struct ce_reg_def *target_ce_def; |
| 384 | |
| 385 | struct htt_ipa_uc_tx_resource_t ipa_uc_tx_rsc; |
| 386 | struct htt_ipa_uc_rx_resource_t ipa_uc_rx_rsc; |
Govind Singh | d79e134 | 2015-11-03 16:20:02 +0530 | [diff] [blame] | 387 | #ifdef DEBUG_RX_RING_BUFFER |
| 388 | struct rx_buf_debug *rx_buff_list; |
| 389 | int rx_buff_index; |
| 390 | #endif |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | #define HTT_EPID_GET(_htt_pdev_hdl) \ |
| 394 | (((struct htt_pdev_t *)(_htt_pdev_hdl))->htc_endpoint) |
| 395 | |
| 396 | #if defined(HELIUMPLUS_PADDR64) |
| 397 | #define HTT_WIFI_IP(pdev, x, y) (((pdev)->wifi_ip_ver.major == (x)) && \ |
| 398 | ((pdev)->wifi_ip_ver.minor == (y))) |
| 399 | |
| 400 | #define HTT_SET_WIFI_IP(pdev, x, y) (((pdev)->wifi_ip_ver.major = (x)) && \ |
| 401 | ((pdev)->wifi_ip_ver.minor = (y))) |
| 402 | #endif /* defined(HELIUMPLUS_PADDR64) */ |
| 403 | |
| 404 | #endif /* _HTT_TYPES__H_ */ |