Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1 | /* |
Hong Shi | 417824f | 2017-01-12 02:31:14 +0800 | [diff] [blame] | 2 | * Copyright (c) 2011-2017 The Linux Foundation. All rights reserved. |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
| 28 | #ifndef __WNICFG_H |
| 29 | #define __WNICFG_H |
| 30 | |
| 31 | /* |
| 32 | * Configuration Parameter ID for STA |
| 33 | */ |
| 34 | |
| 35 | enum { |
| 36 | WNI_CFG_STA_ID, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 37 | WNI_CFG_CFP_PERIOD, |
| 38 | WNI_CFG_CFP_MAX_DURATION, |
| 39 | WNI_CFG_SSID, |
| 40 | WNI_CFG_BEACON_INTERVAL, |
| 41 | WNI_CFG_DTIM_PERIOD, |
| 42 | WNI_CFG_WEP_KEY_LENGTH, |
| 43 | WNI_CFG_WEP_DEFAULT_KEY_1, |
| 44 | WNI_CFG_WEP_DEFAULT_KEY_2, |
| 45 | WNI_CFG_WEP_DEFAULT_KEY_3, |
| 46 | WNI_CFG_WEP_DEFAULT_KEY_4, |
| 47 | WNI_CFG_WEP_DEFAULT_KEYID, |
| 48 | WNI_CFG_EXCLUDE_UNENCRYPTED, |
| 49 | WNI_CFG_RTS_THRESHOLD, |
| 50 | WNI_CFG_SHORT_RETRY_LIMIT, |
| 51 | WNI_CFG_LONG_RETRY_LIMIT, |
| 52 | WNI_CFG_FRAGMENTATION_THRESHOLD, |
| 53 | WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME, |
| 54 | WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME, |
| 55 | WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME, |
| 56 | WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME, |
| 57 | WNI_CFG_JOIN_FAILURE_TIMEOUT, |
| 58 | WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT, |
| 59 | WNI_CFG_AUTHENTICATE_RSP_TIMEOUT, |
| 60 | WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT, |
| 61 | WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 62 | WNI_CFG_PS_ENABLE_BCN_FILTER, |
| 63 | WNI_CFG_PS_ENABLE_HEART_BEAT, |
| 64 | WNI_CFG_PS_ENABLE_RSSI_MONITOR, |
| 65 | WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT, |
| 66 | WNI_CFG_RF_SETTLING_TIME_CLK, |
| 67 | WNI_CFG_SUPPORTED_RATES_11B, |
| 68 | WNI_CFG_SUPPORTED_RATES_11A, |
| 69 | WNI_CFG_PHY_MODE, |
| 70 | WNI_CFG_DOT11_MODE, |
| 71 | WNI_CFG_OPERATIONAL_RATE_SET, |
| 72 | WNI_CFG_EXTENDED_OPERATIONAL_RATE_SET, |
| 73 | WNI_CFG_PROPRIETARY_OPERATIONAL_RATE_SET, |
| 74 | WNI_CFG_LISTEN_INTERVAL, |
| 75 | WNI_CFG_VALID_CHANNEL_LIST, |
| 76 | WNI_CFG_CURRENT_CHANNEL, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 77 | WNI_CFG_DEFAULT_RATE_INDEX_24GHZ, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 78 | WNI_CFG_FIXED_RATE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 79 | WNI_CFG_APSD_ENABLED, |
| 80 | WNI_CFG_SHARED_KEY_AUTH_ENABLE, |
| 81 | WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE, |
| 82 | WNI_CFG_AUTHENTICATION_TYPE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 83 | WNI_CFG_PRIVACY_ENABLED, |
| 84 | WNI_CFG_SHORT_PREAMBLE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 85 | WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY, |
| 86 | WNI_CFG_QOS_ENABLED, |
| 87 | WNI_CFG_HCF_ENABLED, |
| 88 | WNI_CFG_RSN_ENABLED, |
| 89 | WNI_CFG_MAX_NUM_PRE_AUTH, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 90 | WNI_CFG_HEART_BEAT_THRESHOLD, |
| 91 | WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 92 | WNI_CFG_MANUFACTURER_NAME, |
| 93 | WNI_CFG_MODEL_NUMBER, |
| 94 | WNI_CFG_MODEL_NAME, |
| 95 | WNI_CFG_MANUFACTURER_PRODUCT_NAME, |
| 96 | WNI_CFG_MANUFACTURER_PRODUCT_VERSION, |
| 97 | WNI_CFG_11D_ENABLED, |
| 98 | WNI_CFG_MAX_TX_POWER_2_4, |
| 99 | WNI_CFG_MAX_TX_POWER_5, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 100 | WNI_CFG_CURRENT_TX_POWER_LEVEL, |
| 101 | WNI_CFG_NEW_BSS_FOUND_IND, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 102 | WNI_CFG_COUNTRY_CODE, |
| 103 | WNI_CFG_11H_ENABLED, |
| 104 | WNI_CFG_WT_CNF_TIMEOUT, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 105 | WNI_CFG_LOG_LEVEL, |
| 106 | WNI_CFG_OLBC_DETECT_TIMEOUT, |
| 107 | WNI_CFG_PROTECTION_ENABLED, |
| 108 | WNI_CFG_11G_PROTECTION_ALWAYS, |
| 109 | WNI_CFG_FORCE_POLICY_PROTECTION, |
| 110 | WNI_CFG_11G_SHORT_PREAMBLE_ENABLED, |
| 111 | WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED, |
| 112 | WNI_CFG_11G_ONLY_POLICY, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 113 | WNI_CFG_WME_ENABLED, |
| 114 | WNI_CFG_ADDTS_RSP_TIMEOUT, |
| 115 | WNI_CFG_MAX_SP_LENGTH, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 116 | WNI_CFG_WSM_ENABLED, |
| 117 | WNI_CFG_EDCA_PROFILE, |
| 118 | WNI_CFG_EDCA_ANI_ACBK_LOCAL, |
| 119 | WNI_CFG_EDCA_ANI_ACBE_LOCAL, |
| 120 | WNI_CFG_EDCA_ANI_ACVI_LOCAL, |
| 121 | WNI_CFG_EDCA_ANI_ACVO_LOCAL, |
| 122 | WNI_CFG_EDCA_ANI_ACBK, |
| 123 | WNI_CFG_EDCA_ANI_ACBE, |
| 124 | WNI_CFG_EDCA_ANI_ACVI, |
| 125 | WNI_CFG_EDCA_ANI_ACVO, |
| 126 | WNI_CFG_EDCA_WME_ACBK_LOCAL, |
| 127 | WNI_CFG_EDCA_WME_ACBE_LOCAL, |
| 128 | WNI_CFG_EDCA_WME_ACVI_LOCAL, |
| 129 | WNI_CFG_EDCA_WME_ACVO_LOCAL, |
| 130 | WNI_CFG_EDCA_WME_ACBK, |
| 131 | WNI_CFG_EDCA_WME_ACBE, |
| 132 | WNI_CFG_EDCA_WME_ACVI, |
| 133 | WNI_CFG_EDCA_WME_ACVO, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 134 | WNI_CFG_LOCAL_POWER_CONSTRAINT, |
| 135 | WNI_CFG_ADMIT_POLICY, |
| 136 | WNI_CFG_ADMIT_BWFACTOR, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 137 | WNI_CFG_CHANNEL_BONDING_MODE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 138 | WNI_CFG_DYNAMIC_THRESHOLD_ZERO, |
| 139 | WNI_CFG_DYNAMIC_THRESHOLD_ONE, |
| 140 | WNI_CFG_DYNAMIC_THRESHOLD_TWO, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 141 | WNI_CFG_SCAN_CONTROL_LIST, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 142 | WNI_CFG_BLOCK_ACK_ENABLED, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 143 | WNI_CFG_HT_CAP_INFO, |
| 144 | WNI_CFG_HT_AMPDU_PARAMS, |
| 145 | WNI_CFG_SUPPORTED_MCS_SET, |
| 146 | WNI_CFG_EXT_HT_CAP_INFO, |
| 147 | WNI_CFG_TX_BF_CAP, |
| 148 | WNI_CFG_AS_CAP, |
| 149 | WNI_CFG_HT_INFO_FIELD1, |
| 150 | WNI_CFG_HT_INFO_FIELD2, |
| 151 | WNI_CFG_HT_INFO_FIELD3, |
| 152 | WNI_CFG_BASIC_MCS_SET, |
| 153 | WNI_CFG_CURRENT_MCS_SET, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 154 | WNI_CFG_VHT_MAX_MPDU_LENGTH, |
| 155 | WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET, |
| 156 | WNI_CFG_VHT_LDPC_CODING_CAP, |
| 157 | WNI_CFG_VHT_SHORT_GI_80MHZ, |
| 158 | WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ, |
| 159 | WNI_CFG_VHT_TXSTBC, |
| 160 | WNI_CFG_VHT_RXSTBC, |
| 161 | WNI_CFG_VHT_SU_BEAMFORMER_CAP, |
| 162 | WNI_CFG_VHT_SU_BEAMFORMEE_CAP, |
| 163 | WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED, |
| 164 | WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS, |
| 165 | WNI_CFG_VHT_MU_BEAMFORMER_CAP, |
| 166 | WNI_CFG_VHT_MU_BEAMFORMEE_CAP, |
| 167 | WNI_CFG_VHT_TXOP_PS, |
| 168 | WNI_CFG_VHT_HTC_VHTC_CAP, |
| 169 | WNI_CFG_VHT_AMPDU_LEN_EXPONENT, |
| 170 | WNI_CFG_VHT_LINK_ADAPTATION_CAP, |
| 171 | WNI_CFG_VHT_RX_ANT_PATTERN, |
| 172 | WNI_CFG_VHT_TX_ANT_PATTERN, |
| 173 | WNI_CFG_VHT_RX_MCS_MAP, |
| 174 | WNI_CFG_VHT_TX_MCS_MAP, |
| 175 | WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE, |
| 176 | WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 177 | WNI_CFG_VHT_BASIC_MCS_SET, |
| 178 | WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT, |
| 179 | WNI_CFG_VHT_SS_UNDER_UTIL, |
| 180 | WNI_CFG_VHT_40MHZ_UTILIZATION, |
| 181 | WNI_CFG_VHT_80MHZ_UTILIZATION, |
| 182 | WNI_CFG_VHT_160MHZ_UTILIZATION, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 183 | WNI_CFG_MPDU_DENSITY, |
| 184 | WNI_CFG_MAX_RX_AMPDU_FACTOR, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 185 | WNI_CFG_MAX_PS_POLL, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 186 | WNI_CFG_RSSI_FILTER_PERIOD, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 187 | WNI_CFG_SCAN_IN_POWERSAVE, |
| 188 | WNI_CFG_IGNORE_DTIM, |
| 189 | WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE, |
| 190 | WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE, |
| 191 | WNI_CFG_WOWLAN_DEAUTH_ENABLE, |
| 192 | WNI_CFG_WOWLAN_DISASSOC_ENABLE, |
| 193 | WNI_CFG_WOWLAN_MAX_MISSED_BEACON, |
| 194 | WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 195 | WNI_CFG_MAX_MEDIUM_TIME, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 196 | WNI_CFG_IBSS_AUTO_BSSID, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 197 | WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 198 | WNI_CFG_WPS_ENABLE, |
| 199 | WNI_CFG_WPS_STATE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 200 | WNI_CFG_WPS_VERSION, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 201 | WNI_CFG_WPS_CFG_METHOD, |
| 202 | WNI_CFG_WPS_UUID, |
| 203 | WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY, |
| 204 | WNI_CFG_WPS_PIMARY_DEVICE_OUI, |
| 205 | WNI_CFG_WPS_DEVICE_SUB_CATEGORY, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 206 | WNI_CFG_WPS_DEVICE_PASSWORD_ID, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 207 | WNI_CFG_LOW_GAIN_OVERRIDE, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 208 | WNI_CFG_SINGLE_TID_RC, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 209 | WNI_CFG_MCAST_BCAST_FILTER_SETTING, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 210 | WNI_CFG_DYNAMIC_PS_POLL_VALUE, |
| 211 | WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT, |
| 212 | WNI_CFG_TELE_BCN_WAKEUP_EN, |
| 213 | WNI_CFG_TELE_BCN_TRANS_LI, |
| 214 | WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS, |
| 215 | WNI_CFG_TELE_BCN_MAX_LI, |
| 216 | WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 217 | WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD, |
| 218 | WNI_CFG_ASSOC_STA_LIMIT, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 219 | WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 220 | WNI_CFG_ENABLE_LTE_COEX, |
| 221 | WNI_CFG_AP_KEEP_ALIVE_TIMEOUT, |
| 222 | WNI_CFG_GO_KEEP_ALIVE_TIMEOUT, |
| 223 | WNI_CFG_ENABLE_MC_ADDR_LIST, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 224 | WNI_CFG_ENABLE_LPWR_IMG_TRANSITION, |
| 225 | WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED, |
| 226 | WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP, |
| 227 | WNI_CFG_AP_LINK_MONITOR_TIMEOUT, |
| 228 | WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK, |
| 229 | WNI_CFG_TDLS_BUF_STA_ENABLED, |
| 230 | WNI_CFG_TDLS_PUAPSD_INACT_TIME, |
| 231 | WNI_CFG_TDLS_RX_FRAME_THRESHOLD, |
| 232 | WNI_CFG_PMF_SA_QUERY_MAX_RETRIES, |
| 233 | WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL, |
| 234 | WNI_CFG_ENABLE_ADAPT_RX_DRAIN, |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 235 | WNI_CFG_ANTENNA_DIVESITY, |
| 236 | WNI_CFG_GO_LINK_MONITOR_TIMEOUT, |
| 237 | WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY, |
| 238 | WNI_CFG_CURRENT_RSSI, |
| 239 | WNI_CFG_RTT3_ENABLE, |
| 240 | WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL, |
| 241 | WNI_CFG_TDLS_OFF_CHANNEL_ENABLED, |
| 242 | WNI_CFG_IBSS_ATIM_WIN_SIZE, |
| 243 | WNI_CFG_DFS_MASTER_ENABLED, |
| 244 | WNI_CFG_VHT_ENABLE_TXBF_20MHZ, |
Sandeep Puligilla | e087566 | 2016-02-12 16:09:21 -0800 | [diff] [blame] | 245 | WNI_CFG_TDLS_WMM_MODE_ENABLED, |
| 246 | WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME, |
| 247 | WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME, |
| 248 | WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL, |
| 249 | WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL, |
| 250 | WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL, |
| 251 | WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY, |
Varun Reddy Yeturu | 986cd65 | 2016-05-11 16:36:45 -0700 | [diff] [blame] | 252 | WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD, |
Rajeev Kumar Sirasanagandla | af47474 | 2016-09-06 17:54:50 +0530 | [diff] [blame] | 253 | WNI_CFG_TGT_GTX_USR_CFG, |
Hong Shi | 417824f | 2017-01-12 02:31:14 +0800 | [diff] [blame] | 254 | WNI_CFG_MAX_HT_MCS_TX_DATA, |
Hong Shi | a9ef871 | 2017-02-19 21:54:02 +0800 | [diff] [blame] | 255 | WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA, |
Hong Shi | b90718f | 2017-02-20 00:57:22 +0800 | [diff] [blame] | 256 | WNI_CFG_RATE_FOR_TX_MGMT, |
Krishna Kumaar Natarajan | ed1efd9 | 2016-09-24 18:05:47 -0700 | [diff] [blame^] | 257 | WNI_CFG_HE_CONTROL, |
| 258 | WNI_CFG_HE_TWT_REQUESTOR, |
| 259 | WNI_CFG_HE_TWT_RESPONDER, |
| 260 | WNI_CFG_HE_FRAGMENTATION, |
| 261 | WNI_CFG_HE_MAX_FRAG_MSDU, |
| 262 | WNI_CFG_HE_MIN_FRAG_SIZE, |
| 263 | WNI_CFG_HE_TRIG_PAD, |
| 264 | WNI_CFG_HE_MTID_AGGR, |
| 265 | WNI_CFG_HE_LINK_ADAPTATION, |
| 266 | WNI_CFG_HE_ALL_ACK, |
| 267 | WNI_CFG_HE_UL_MU_RSP_SCHEDULING, |
| 268 | WNI_CFG_HE_BUFFER_STATUS_RPT, |
| 269 | WNI_CFG_HE_BCAST_TWT, |
| 270 | WNI_CFG_HE_BA_32BIT, |
| 271 | WNI_CFG_HE_MU_CASCADING, |
| 272 | WNI_CFG_HE_MULTI_TID, |
| 273 | WNI_CFG_HE_DL_MU_BA, |
| 274 | WNI_CFG_HE_OMI, |
| 275 | WNI_CFG_HE_OFDMA_RA, |
| 276 | WNI_CFG_HE_MAX_AMPDU_LEN, |
| 277 | WNI_CFG_HE_AMSDU_FRAG, |
| 278 | WNI_CFG_HE_FLEX_TWT_SCHED, |
| 279 | WNI_CFG_HE_RX_CTRL, |
| 280 | WNI_CFG_HE_BSRP_AMPDU_AGGR, |
| 281 | WNI_CFG_HE_QTP, |
| 282 | WNI_CFG_HE_A_BQR, |
| 283 | WNI_CFG_HE_DUAL_BAND, |
| 284 | WNI_CFG_HE_CHAN_WIDTH, |
| 285 | WNI_CFG_HE_RX_PREAM_PUNC, |
| 286 | WNI_CFG_HE_CLASS_OF_DEVICE, |
| 287 | WNI_CFG_HE_LDPC, |
| 288 | WNI_CFG_HE_LTF_PPDU, |
| 289 | WNI_CFG_HE_LTF_NDP, |
| 290 | WNI_CFG_HE_STBC, |
| 291 | WNI_CFG_HE_DOPPLER, |
| 292 | WNI_CFG_HE_UL_MUMIMO, |
| 293 | WNI_CFG_HE_DCM_TX, |
| 294 | WNI_CFG_HE_DCM_RX, |
| 295 | WNI_CFG_HE_MU_PPDU, |
| 296 | WNI_CFG_HE_SU_BEAMFORMER, |
| 297 | WNI_CFG_HE_SU_BEAMFORMEE, |
| 298 | WNI_CFG_HE_MU_BEAMFORMER, |
| 299 | WNI_CFG_HE_BFEE_STS_LT80, |
| 300 | WNI_CFG_HE_NSTS_TOT_LT80, |
| 301 | WNI_CFG_HE_BFEE_STS_GT80, |
| 302 | WNI_CFG_HE_NSTS_TOT_GT80, |
| 303 | WNI_CFG_HE_NUM_SOUND_LT80, |
| 304 | WNI_CFG_HE_NUM_SOUND_GT80, |
| 305 | WNI_CFG_HE_SU_FEED_TONE16, |
| 306 | WNI_CFG_HE_MU_FEED_TONE16, |
| 307 | WNI_CFG_HE_CODEBOOK_SU, |
| 308 | WNI_CFG_HE_CODEBOOK_MU, |
| 309 | WNI_CFG_HE_BFRM_FEED, |
| 310 | WNI_CFG_HE_ER_SU_PPDU, |
| 311 | WNI_CFG_HE_DL_PART_BW, |
| 312 | WNI_CFG_HE_PPET_PRESENT, |
| 313 | WNI_CFG_HE_SRP, |
| 314 | WNI_CFG_HE_POWER_BOOST, |
| 315 | WNI_CFG_HE_4x_LTF_GI, |
| 316 | WNI_CFG_HE_NSS, |
| 317 | WNI_CFG_HE_MCS, |
| 318 | WNI_CFG_HE_PPET, |
Varun Reddy Yeturu | 986cd65 | 2016-05-11 16:36:45 -0700 | [diff] [blame] | 319 | /* Any new items to be added should be above this strictly */ |
| 320 | CFG_PARAM_MAX_NUM |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 321 | }; |
| 322 | /* |
| 323 | * String parameter lengths |
| 324 | */ |
| 325 | |
| 326 | #define WNI_CFG_STA_ID_LEN 6 |
| 327 | #define WNI_CFG_SSID_LEN 32 |
| 328 | #define WNI_CFG_WEP_DEFAULT_KEY_1_LEN 13 |
| 329 | #define WNI_CFG_WEP_DEFAULT_KEY_2_LEN 13 |
| 330 | #define WNI_CFG_WEP_DEFAULT_KEY_3_LEN 13 |
| 331 | #define WNI_CFG_WEP_DEFAULT_KEY_4_LEN 13 |
| 332 | #define WNI_CFG_SUPPORTED_RATES_11B_LEN 4 |
| 333 | #define WNI_CFG_SUPPORTED_RATES_11A_LEN 8 |
| 334 | #define WNI_CFG_OPERATIONAL_RATE_SET_LEN 12 |
| 335 | #define WNI_CFG_EXTENDED_OPERATIONAL_RATE_SET_LEN 8 |
| 336 | #define WNI_CFG_PROPRIETARY_OPERATIONAL_RATE_SET_LEN 4 |
| 337 | #define WNI_CFG_VALID_CHANNEL_LIST_LEN 100 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 338 | #define WNI_CFG_MANUFACTURER_NAME_LEN 64 |
| 339 | #define WNI_CFG_MODEL_NUMBER_LEN 32 |
| 340 | #define WNI_CFG_MODEL_NAME_LEN 32 |
| 341 | #define WNI_CFG_MANUFACTURER_PRODUCT_NAME_LEN 32 |
| 342 | #define WNI_CFG_MANUFACTURER_PRODUCT_VERSION_LEN 32 |
| 343 | #define WNI_CFG_MAX_TX_POWER_2_4_LEN 128 |
| 344 | #define WNI_CFG_MAX_TX_POWER_5_LEN 128 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 345 | #define WNI_CFG_COUNTRY_CODE_LEN 3 |
| 346 | #define WNI_CFG_EDCA_ANI_ACBK_LOCAL_LEN 20 |
| 347 | #define WNI_CFG_EDCA_ANI_ACBE_LOCAL_LEN 20 |
| 348 | #define WNI_CFG_EDCA_ANI_ACVI_LOCAL_LEN 20 |
| 349 | #define WNI_CFG_EDCA_ANI_ACVO_LOCAL_LEN 20 |
| 350 | #define WNI_CFG_EDCA_ANI_ACBK_LEN 20 |
| 351 | #define WNI_CFG_EDCA_ANI_ACBE_LEN 20 |
| 352 | #define WNI_CFG_EDCA_ANI_ACVI_LEN 20 |
| 353 | #define WNI_CFG_EDCA_ANI_ACVO_LEN 20 |
| 354 | #define WNI_CFG_EDCA_WME_ACBK_LOCAL_LEN 20 |
| 355 | #define WNI_CFG_EDCA_WME_ACBE_LOCAL_LEN 20 |
| 356 | #define WNI_CFG_EDCA_WME_ACVI_LOCAL_LEN 20 |
| 357 | #define WNI_CFG_EDCA_WME_ACVO_LOCAL_LEN 20 |
| 358 | #define WNI_CFG_EDCA_WME_ACBK_LEN 20 |
| 359 | #define WNI_CFG_EDCA_WME_ACBE_LEN 20 |
| 360 | #define WNI_CFG_EDCA_WME_ACVI_LEN 20 |
| 361 | #define WNI_CFG_EDCA_WME_ACVO_LEN 20 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 362 | #define WNI_CFG_SCAN_CONTROL_LIST_LEN 128 |
| 363 | #define WNI_CFG_SUPPORTED_MCS_SET_LEN 16 |
| 364 | #define WNI_CFG_BASIC_MCS_SET_LEN 16 |
| 365 | #define WNI_CFG_CURRENT_MCS_SET_LEN 16 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 366 | #define WNI_CFG_PROBE_RSP_ADDNIE_DATA1_LEN 255 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 367 | #define WNI_CFG_ASSOC_RSP_ADDNIE_DATA_LEN 255 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 368 | #define WNI_CFG_PROBE_RSP_BCN_ADDNIE_DATA_LEN 255 |
| 369 | #define WNI_CFG_WPS_UUID_LEN 16 |
Krishna Kumaar Natarajan | ed1efd9 | 2016-09-24 18:05:47 -0700 | [diff] [blame^] | 370 | #define WNI_CFG_HE_PPET_LEN 27 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 371 | |
| 372 | /* |
| 373 | * Integer parameter min/max/default values |
| 374 | */ |
| 375 | |
| 376 | #define WNI_CFG_CFP_PERIOD_STAMIN 0 |
| 377 | #define WNI_CFG_CFP_PERIOD_STAMAX 255 |
| 378 | #define WNI_CFG_CFP_PERIOD_STADEF 1 |
| 379 | |
| 380 | #define WNI_CFG_CFP_MAX_DURATION_STAMIN 0 |
| 381 | #define WNI_CFG_CFP_MAX_DURATION_STAMAX 65535 |
| 382 | #define WNI_CFG_CFP_MAX_DURATION_STADEF 30000 |
| 383 | |
| 384 | #define WNI_CFG_BEACON_INTERVAL_STAMIN 0 |
| 385 | #define WNI_CFG_BEACON_INTERVAL_STAMAX 65535 |
| 386 | #define WNI_CFG_BEACON_INTERVAL_STADEF 100 |
| 387 | |
| 388 | #define WNI_CFG_DTIM_PERIOD_STAMIN 0 |
| 389 | #define WNI_CFG_DTIM_PERIOD_STAMAX 65535 |
| 390 | #define WNI_CFG_DTIM_PERIOD_STADEF 1 |
| 391 | |
| 392 | #define WNI_CFG_WEP_KEY_LENGTH_STAMIN 5 |
| 393 | #define WNI_CFG_WEP_KEY_LENGTH_STAMAX 13 |
| 394 | #define WNI_CFG_WEP_KEY_LENGTH_STADEF 5 |
| 395 | |
| 396 | #define WNI_CFG_WEP_KEY_LENGTH_5 5 |
| 397 | #define WNI_CFG_WEP_KEY_LENGTH_13 13 |
| 398 | |
| 399 | #define WNI_CFG_WEP_DEFAULT_KEYID_STAMIN 0 |
| 400 | #define WNI_CFG_WEP_DEFAULT_KEYID_STAMAX 3 |
| 401 | #define WNI_CFG_WEP_DEFAULT_KEYID_STADEF 0 |
| 402 | |
| 403 | #define WNI_CFG_WEP_DEFAULT_KEYID_0 0 |
| 404 | #define WNI_CFG_WEP_DEFAULT_KEYID_1 1 |
| 405 | #define WNI_CFG_WEP_DEFAULT_KEYID_2 2 |
| 406 | #define WNI_CFG_WEP_DEFAULT_KEYID_3 3 |
| 407 | |
| 408 | #define WNI_CFG_EXCLUDE_UNENCRYPTED_STAMIN 0 |
| 409 | #define WNI_CFG_EXCLUDE_UNENCRYPTED_STAMAX 1 |
| 410 | #define WNI_CFG_EXCLUDE_UNENCRYPTED_STADEF 0 |
| 411 | |
| 412 | #define WNI_CFG_RTS_THRESHOLD_STAMIN 0 |
| 413 | #define WNI_CFG_RTS_THRESHOLD_STAMAX 1048576 |
| 414 | #define WNI_CFG_RTS_THRESHOLD_STADEF 2347 |
| 415 | |
| 416 | #define WNI_CFG_SHORT_RETRY_LIMIT_STAMIN 0 |
| 417 | #define WNI_CFG_SHORT_RETRY_LIMIT_STAMAX 255 |
| 418 | #define WNI_CFG_SHORT_RETRY_LIMIT_STADEF 6 |
| 419 | |
| 420 | #define WNI_CFG_LONG_RETRY_LIMIT_STAMIN 0 |
| 421 | #define WNI_CFG_LONG_RETRY_LIMIT_STAMAX 255 |
| 422 | #define WNI_CFG_LONG_RETRY_LIMIT_STADEF 6 |
| 423 | |
| 424 | #define WNI_CFG_FRAGMENTATION_THRESHOLD_STAMIN 256 |
| 425 | #define WNI_CFG_FRAGMENTATION_THRESHOLD_STAMAX 8000 |
| 426 | #define WNI_CFG_FRAGMENTATION_THRESHOLD_STADEF 8000 |
| 427 | |
| 428 | #define WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STAMIN 0 |
| 429 | #define WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STAMAX 65535 |
| 430 | #define WNI_CFG_ACTIVE_MINIMUM_CHANNEL_TIME_STADEF 20 |
| 431 | |
| 432 | #define WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STAMIN 0 |
| 433 | #define WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STAMAX 65535 |
| 434 | #define WNI_CFG_ACTIVE_MAXIMUM_CHANNEL_TIME_STADEF 40 |
| 435 | |
| 436 | #define WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STAMIN 0 |
| 437 | #define WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STAMAX 65535 |
| 438 | #define WNI_CFG_PASSIVE_MINIMUM_CHANNEL_TIME_STADEF 60 |
| 439 | |
| 440 | #define WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STAMIN 0 |
| 441 | #define WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STAMAX 65535 |
| 442 | #define WNI_CFG_PASSIVE_MAXIMUM_CHANNEL_TIME_STADEF 110 |
| 443 | |
| 444 | #define WNI_CFG_JOIN_FAILURE_TIMEOUT_STAMIN 0 |
| 445 | #define WNI_CFG_JOIN_FAILURE_TIMEOUT_STAMAX 65535 |
| 446 | #define WNI_CFG_JOIN_FAILURE_TIMEOUT_STADEF 3000 |
| 447 | |
| 448 | #define WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STAMIN 0 |
| 449 | #define WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STAMAX 65535 |
| 450 | #define WNI_CFG_AUTHENTICATE_FAILURE_TIMEOUT_STADEF 1000 |
| 451 | |
| 452 | #define WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STAMIN 0 |
| 453 | #define WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STAMAX 65535 |
| 454 | #define WNI_CFG_AUTHENTICATE_RSP_TIMEOUT_STADEF 1000 |
| 455 | |
| 456 | #define WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STAMIN 0 |
| 457 | #define WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STAMAX 65535 |
| 458 | #define WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT_STADEF 2000 |
| 459 | |
| 460 | #define WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STAMIN 0 |
| 461 | #define WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STAMAX 65535 |
| 462 | #define WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT_STADEF 1000 |
| 463 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 464 | #define WNI_CFG_PS_ENABLE_BCN_FILTER_STAMIN 0 |
| 465 | #define WNI_CFG_PS_ENABLE_BCN_FILTER_STAMAX 1 |
| 466 | #define WNI_CFG_PS_ENABLE_BCN_FILTER_STADEF 1 |
| 467 | |
| 468 | #define WNI_CFG_PS_ENABLE_HEART_BEAT_STAMIN 0 |
| 469 | #define WNI_CFG_PS_ENABLE_HEART_BEAT_STAMAX 1 |
| 470 | #define WNI_CFG_PS_ENABLE_HEART_BEAT_STADEF 1 |
| 471 | |
| 472 | #define WNI_CFG_PS_ENABLE_RSSI_MONITOR_STAMIN 0 |
| 473 | #define WNI_CFG_PS_ENABLE_RSSI_MONITOR_STAMAX 1 |
| 474 | #define WNI_CFG_PS_ENABLE_RSSI_MONITOR_STADEF 0 |
| 475 | |
| 476 | #define WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STAMIN 1 |
| 477 | #define WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STAMAX 255 |
Jeff Johnson | 9c9be71 | 2016-09-02 14:02:31 -0700 | [diff] [blame] | 478 | #define WNI_CFG_PS_DATA_INACTIVITY_TIMEOUT_STADEF 200 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 479 | |
| 480 | #define WNI_CFG_RF_SETTLING_TIME_CLK_STAMIN 0 |
| 481 | #define WNI_CFG_RF_SETTLING_TIME_CLK_STAMAX 60000 |
| 482 | #define WNI_CFG_RF_SETTLING_TIME_CLK_STADEF 1500 |
| 483 | |
| 484 | #define WNI_CFG_PHY_MODE_STAMIN 0 |
| 485 | #define WNI_CFG_PHY_MODE_STAMAX 3 |
| 486 | #define WNI_CFG_PHY_MODE_STADEF 0 |
| 487 | |
| 488 | #define WNI_CFG_PHY_MODE_11A 0 |
| 489 | #define WNI_CFG_PHY_MODE_11B 1 |
| 490 | #define WNI_CFG_PHY_MODE_11G 2 |
| 491 | #define WNI_CFG_PHY_MODE_NONE 3 |
| 492 | |
| 493 | #define WNI_CFG_DOT11_MODE_STAMIN 0 |
| 494 | #define WNI_CFG_DOT11_MODE_STAMAX 11 |
| 495 | #define WNI_CFG_DOT11_MODE_STADEF 0 |
| 496 | |
| 497 | #define WNI_CFG_DOT11_MODE_ALL 0 |
| 498 | #define WNI_CFG_DOT11_MODE_11A 1 |
| 499 | #define WNI_CFG_DOT11_MODE_11B 2 |
| 500 | #define WNI_CFG_DOT11_MODE_11G 3 |
| 501 | #define WNI_CFG_DOT11_MODE_11N 4 |
| 502 | #define WNI_CFG_DOT11_MODE_11G_ONLY 5 |
| 503 | #define WNI_CFG_DOT11_MODE_11N_ONLY 6 |
| 504 | #define WNI_CFG_DOT11_MODE_11AC 7 |
| 505 | #define WNI_CFG_DOT11_MODE_11AC_ONLY 8 |
| 506 | |
| 507 | #define WNI_CFG_LISTEN_INTERVAL_STAMIN 0 |
| 508 | #define WNI_CFG_LISTEN_INTERVAL_STAMAX 65535 |
| 509 | #define WNI_CFG_LISTEN_INTERVAL_STADEF 1 |
| 510 | |
| 511 | #define WNI_CFG_CURRENT_CHANNEL_STAMIN 0 |
| 512 | #define WNI_CFG_CURRENT_CHANNEL_STAMAX 165 |
| 513 | #define WNI_CFG_CURRENT_CHANNEL_STADEF 1 |
| 514 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 515 | #define WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STAMIN 0 |
| 516 | #define WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STAMAX 31 |
| 517 | #define WNI_CFG_DEFAULT_RATE_INDEX_24GHZ_STADEF 1 |
| 518 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 519 | #define WNI_CFG_RATE_ADAPTATION_TYPE_FIXED 0 |
| 520 | #define WNI_CFG_RATE_ADAPTATION_TYPE_AUTO 1 |
| 521 | #define WNI_CFG_RATE_ADAPTATION_TYPE_SNR_BASED 2 |
| 522 | |
| 523 | #define WNI_CFG_FIXED_RATE_STAMIN 0 |
| 524 | #define WNI_CFG_FIXED_RATE_STAMAX 44 |
| 525 | #define WNI_CFG_FIXED_RATE_STADEF 0 |
| 526 | |
| 527 | #define WNI_CFG_FIXED_RATE_AUTO 0 |
| 528 | #define WNI_CFG_FIXED_RATE_1MBPS 1 |
| 529 | #define WNI_CFG_FIXED_RATE_2MBPS 2 |
| 530 | #define WNI_CFG_FIXED_RATE_5_5MBPS 3 |
| 531 | #define WNI_CFG_FIXED_RATE_11MBPS 4 |
| 532 | #define WNI_CFG_FIXED_RATE_6MBPS 5 |
| 533 | #define WNI_CFG_FIXED_RATE_9MBPS 6 |
| 534 | #define WNI_CFG_FIXED_RATE_12MBPS 7 |
| 535 | #define WNI_CFG_FIXED_RATE_18MBPS 8 |
| 536 | #define WNI_CFG_FIXED_RATE_24MBPS 9 |
| 537 | #define WNI_CFG_FIXED_RATE_36MBPS 10 |
| 538 | #define WNI_CFG_FIXED_RATE_48MBPS 11 |
| 539 | #define WNI_CFG_FIXED_RATE_54MBPS 12 |
| 540 | #define WNI_CFG_FIXED_RATE_6_5MBPS_MCS0_20MHZ_SIMO 13 |
| 541 | #define WNI_CFG_FIXED_RATE_13MBPS_MCS1_20MHZ_SIMO 14 |
| 542 | #define WNI_CFG_FIXED_RATE_19_5MBPS_MCS2_20MHZ_SIMO 15 |
| 543 | #define WNI_CFG_FIXED_RATE_26MBPS_MCS3_20MHZ_SIMO 16 |
| 544 | #define WNI_CFG_FIXED_RATE_39MBPS_MCS4_20MHZ_SIMO 17 |
| 545 | #define WNI_CFG_FIXED_RATE_52MBPS_MCS5_20MHZ_SIMO 18 |
| 546 | #define WNI_CFG_FIXED_RATE_58_5MBPS_MCS6_20MHZ_SIMO 19 |
| 547 | #define WNI_CFG_FIXED_RATE_65MBPS_MCS7_20MHZ_SIMO 20 |
| 548 | #define WNI_CFG_FIXED_RATE_7_2MBPS_MCS0_20MHZ_SIMO_SGI 21 |
| 549 | #define WNI_CFG_FIXED_RATE_14_4MBPS_MCS1_20MHZ_SIMO_SGI 22 |
| 550 | #define WNI_CFG_FIXED_RATE_21_7MBPS_MCS2_20MHZ_SIMO_SGI 23 |
| 551 | #define WNI_CFG_FIXED_RATE_28_9MBPS_MCS3_20MHZ_SIMO_SGI 24 |
| 552 | #define WNI_CFG_FIXED_RATE_43_3MBPS_MCS4_20MHZ_SIMO_SGI 25 |
| 553 | #define WNI_CFG_FIXED_RATE_57_8MBPS_MCS5_20MHZ_SIMO_SGI 26 |
| 554 | #define WNI_CFG_FIXED_RATE_65MBPS_MCS6_20MHZ_SIMO_SGI 27 |
| 555 | #define WNI_CFG_FIXED_RATE_72_2MBPS_MCS7_20MHZ_SIMO_SGI 28 |
| 556 | #define WNI_CFG_FIXED_RATE_0_25MBPS_SLR_20MHZ_SIMO 29 |
| 557 | #define WNI_CFG_FIXED_RATE_0_5MBPS_SLR_20MHZ_SIMO 30 |
| 558 | #define WNI_CFG_FIXED_RATE_68_25MBPS_QC_PROP_20MHZ_SIMO 31 |
| 559 | #define WNI_CFG_FIXED_RATE_54MBPS_MCS3_40MHZ_SIMO 32 |
| 560 | #define WNI_CFG_FIXED_RATE_81MBPS_MCS4_40MHZ_SIMO 33 |
| 561 | #define WNI_CFG_FIXED_RATE_108MBPS_MCS5_40MHZ_SIMO 34 |
| 562 | #define WNI_CFG_FIXED_RATE_121_5MBPS_MCS6_40MHZ_SIMO 35 |
| 563 | #define WNI_CFG_FIXED_RATE_135MBPS_MCS7_40MHZ_SIMO 36 |
| 564 | #define WNI_CFG_FIXED_RATE_15MBPS_MCS0_40MHZ_SIMO_SGI 37 |
| 565 | #define WNI_CFG_FIXED_RATE_30MBPS_MCS1_40MHZ_SIMO_SGI 38 |
| 566 | #define WNI_CFG_FIXED_RATE_45MBPS_MCS2_40MHZ_SIMO_SGI 39 |
| 567 | #define WNI_CFG_FIXED_RATE_60MBPS_MCS3_40MHZ_SIMO_SGI 40 |
| 568 | #define WNI_CFG_FIXED_RATE_90MBPS_MCS4_40MHZ_SIMO_SGI 41 |
| 569 | #define WNI_CFG_FIXED_RATE_120MBPS_MCS5_40MHZ_SIMO_SGI 42 |
| 570 | #define WNI_CFG_FIXED_RATE_135MBPS_MCS6_40MHZ_SIMO_SGI 43 |
| 571 | #define WNI_CFG_FIXED_RATE_150MBPS_MCS7_40MHZ_SIMO_SGI 44 |
| 572 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 573 | #define WNI_CFG_RETRYRATE_POLICY_MIN_SUPPORTED 0 |
| 574 | #define WNI_CFG_RETRYRATE_POLICY_PRIMARY 1 |
| 575 | #define WNI_CFG_RETRYRATE_POLICY_RESERVED 2 |
| 576 | #define WNI_CFG_RETRYRATE_POLICY_CLOSEST 3 |
| 577 | #define WNI_CFG_RETRYRATE_POLICY_AUTOSELECT 4 |
| 578 | #define WNI_CFG_RETRYRATE_POLICY_MAX 5 |
| 579 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 580 | #define WNI_CFG_APSD_ENABLED_STAMIN 0 |
| 581 | #define WNI_CFG_APSD_ENABLED_STAMAX 1 |
| 582 | #define WNI_CFG_APSD_ENABLED_STADEF 0 |
| 583 | |
| 584 | #define WNI_CFG_SHARED_KEY_AUTH_ENABLE_STAMIN 0 |
| 585 | #define WNI_CFG_SHARED_KEY_AUTH_ENABLE_STAMAX 1 |
| 586 | #define WNI_CFG_SHARED_KEY_AUTH_ENABLE_STADEF 1 |
| 587 | |
| 588 | #define WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STAMIN 0 |
| 589 | #define WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STAMAX 1 |
| 590 | #define WNI_CFG_OPEN_SYSTEM_AUTH_ENABLE_STADEF 1 |
| 591 | |
| 592 | #define WNI_CFG_AUTHENTICATION_TYPE_STAMIN 0 |
| 593 | #define WNI_CFG_AUTHENTICATION_TYPE_STAMAX 65535 |
| 594 | #define WNI_CFG_AUTHENTICATION_TYPE_STADEF 0 |
| 595 | |
| 596 | #define WNI_CFG_PRIVACY_ENABLED_STAMIN 0 |
| 597 | #define WNI_CFG_PRIVACY_ENABLED_STAMAX 1 |
| 598 | #define WNI_CFG_PRIVACY_ENABLED_STADEF 0 |
| 599 | |
| 600 | #define WNI_CFG_SHORT_PREAMBLE_STAMIN 0 |
| 601 | #define WNI_CFG_SHORT_PREAMBLE_STAMAX 1 |
| 602 | #define WNI_CFG_SHORT_PREAMBLE_STADEF 1 |
| 603 | |
| 604 | #define WNI_CFG_SHORT_SLOT_TIME_STAMIN 0 |
| 605 | #define WNI_CFG_SHORT_SLOT_TIME_STAMAX 1 |
| 606 | #define WNI_CFG_SHORT_SLOT_TIME_STADEF 1 |
| 607 | |
| 608 | #define WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STAMIN 0 |
| 609 | #define WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STAMAX 1 |
| 610 | #define WNI_CFG_ACCEPT_SHORT_SLOT_ASSOC_ONLY_STADEF 0 |
| 611 | |
| 612 | #define WNI_CFG_QOS_ENABLED_STAMIN 0 |
| 613 | #define WNI_CFG_QOS_ENABLED_STAMAX 1 |
| 614 | #define WNI_CFG_QOS_ENABLED_STADEF 0 |
| 615 | |
| 616 | #define WNI_CFG_HCF_ENABLED_STAMIN 0 |
| 617 | #define WNI_CFG_HCF_ENABLED_STAMAX 1 |
| 618 | #define WNI_CFG_HCF_ENABLED_STADEF 0 |
| 619 | |
| 620 | #define WNI_CFG_RSN_ENABLED_STAMIN 0 |
| 621 | #define WNI_CFG_RSN_ENABLED_STAMAX 1 |
| 622 | #define WNI_CFG_RSN_ENABLED_STADEF 0 |
| 623 | |
| 624 | #define WNI_CFG_BACKGROUND_SCAN_PERIOD_STAMIN 0 |
| 625 | #define WNI_CFG_BACKGROUND_SCAN_PERIOD_STAMAX 180000 |
| 626 | #define WNI_CFG_BACKGROUND_SCAN_PERIOD_STADEF 5000 |
| 627 | |
| 628 | #define WNI_CFG_MAX_NUM_PRE_AUTH_STAMIN 0 |
| 629 | #define WNI_CFG_MAX_NUM_PRE_AUTH_STAMAX 256 |
| 630 | #define WNI_CFG_MAX_NUM_PRE_AUTH_STADEF 64 |
| 631 | |
| 632 | #define WNI_CFG_HEART_BEAT_THRESHOLD_STAMIN 0 |
| 633 | #define WNI_CFG_HEART_BEAT_THRESHOLD_STAMAX 65535 |
| 634 | #define WNI_CFG_HEART_BEAT_THRESHOLD_STADEF 40 |
| 635 | |
| 636 | #define WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STAMIN 10 |
| 637 | #define WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STAMAX 10000 |
| 638 | #define WNI_CFG_PROBE_AFTER_HB_FAIL_TIMEOUT_STADEF 40 |
| 639 | |
| 640 | #define WNI_CFG_11D_ENABLED_STAMIN 0 |
| 641 | #define WNI_CFG_11D_ENABLED_STAMAX 1 |
| 642 | #define WNI_CFG_11D_ENABLED_STADEF 1 |
| 643 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 644 | #define WNI_CFG_NETWORK_DENSITY_LOW 0 |
| 645 | #define WNI_CFG_NETWORK_DENSITY_MEDIUM 1 |
| 646 | #define WNI_CFG_NETWORK_DENSITY_HIGH 2 |
| 647 | #define WNI_CFG_NETWORK_DENSITY_ADAPTIVE 3 |
| 648 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 649 | #define WNI_CFG_ADAPTIVE_THRESHOLD_ALGORITHM_CARRIER 1 |
| 650 | #define WNI_CFG_ADAPTIVE_THRESHOLD_ALGORITHM_CORRELATION 2 |
| 651 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 652 | #define WNI_CFG_CURRENT_TX_POWER_LEVEL_STAMIN 0 |
| 653 | #define WNI_CFG_CURRENT_TX_POWER_LEVEL_STAMAX 128 |
| 654 | #define WNI_CFG_CURRENT_TX_POWER_LEVEL_STADEF 27 |
| 655 | |
| 656 | |
| 657 | |
| 658 | #define WNI_CFG_NEW_BSS_FOUND_IND_STAMIN 0 |
| 659 | #define WNI_CFG_NEW_BSS_FOUND_IND_STAMAX 1 |
| 660 | #define WNI_CFG_NEW_BSS_FOUND_IND_STADEF 0 |
| 661 | |
| 662 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 663 | #define WNI_CFG_11H_ENABLED_STAMIN 0 |
| 664 | #define WNI_CFG_11H_ENABLED_STAMAX 1 |
| 665 | #define WNI_CFG_11H_ENABLED_STADEF 1 |
| 666 | |
| 667 | #define WNI_CFG_WT_CNF_TIMEOUT_STAMIN 10 |
| 668 | #define WNI_CFG_WT_CNF_TIMEOUT_STAMAX 3000 |
| 669 | #define WNI_CFG_WT_CNF_TIMEOUT_STADEF 1000 |
| 670 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 671 | #define WNI_CFG_LOG_LEVEL_STAMIN 0 |
| 672 | #define WNI_CFG_LOG_LEVEL_STAMAX 7 |
| 673 | #define WNI_CFG_LOG_LEVEL_STADEF 4 |
| 674 | |
| 675 | #define WNI_CFG_OLBC_DETECT_TIMEOUT_STAMIN 1000 |
| 676 | #define WNI_CFG_OLBC_DETECT_TIMEOUT_STAMAX 30000 |
| 677 | #define WNI_CFG_OLBC_DETECT_TIMEOUT_STADEF 10000 |
| 678 | |
| 679 | #define WNI_CFG_PROTECTION_ENABLED_STAMIN 0 |
| 680 | #define WNI_CFG_PROTECTION_ENABLED_STAMAX 65535 |
| 681 | #define WNI_CFG_PROTECTION_ENABLED_STADEF 65535 |
| 682 | |
| 683 | #define WNI_CFG_PROTECTION_ENABLED_FROM_llA 0 |
| 684 | #define WNI_CFG_PROTECTION_ENABLED_FROM_llB 1 |
| 685 | #define WNI_CFG_PROTECTION_ENABLED_FROM_llG 2 |
| 686 | #define WNI_CFG_PROTECTION_ENABLED_HT_20 3 |
| 687 | #define WNI_CFG_PROTECTION_ENABLED_NON_GF 4 |
| 688 | #define WNI_CFG_PROTECTION_ENABLED_LSIG_TXOP 5 |
| 689 | #define WNI_CFG_PROTECTION_ENABLED_RIFS 6 |
| 690 | #define WNI_CFG_PROTECTION_ENABLED_OBSS 7 |
| 691 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_FROM_llA 8 |
| 692 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_FROM_llB 9 |
| 693 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_FROM_llG 10 |
| 694 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_HT20 11 |
| 695 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_NON_GF 12 |
| 696 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_LSIG_TXOP 13 |
| 697 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_RIFS 14 |
| 698 | #define WNI_CFG_PROTECTION_ENABLED_OLBC_OBSS 15 |
| 699 | |
| 700 | #define WNI_CFG_11G_PROTECTION_ALWAYS_STAMIN 0 |
| 701 | #define WNI_CFG_11G_PROTECTION_ALWAYS_STAMAX 1 |
| 702 | #define WNI_CFG_11G_PROTECTION_ALWAYS_STADEF 0 |
| 703 | |
| 704 | #define WNI_CFG_FORCE_POLICY_PROTECTION_STAMIN 0 |
| 705 | #define WNI_CFG_FORCE_POLICY_PROTECTION_STAMAX 5 |
| 706 | #define WNI_CFG_FORCE_POLICY_PROTECTION_STADEF 5 |
| 707 | |
| 708 | #define WNI_CFG_FORCE_POLICY_PROTECTION_DISABLE 0 |
| 709 | #define WNI_CFG_FORCE_POLICY_PROTECTION_CTS 1 |
| 710 | #define WNI_CFG_FORCE_POLICY_PROTECTION_RTS 2 |
| 711 | #define WNI_CFG_FORCE_POLICY_PROTECTION_DUAL_CTS 3 |
| 712 | #define WNI_CFG_FORCE_POLICY_PROTECTION_RTS_ALWAYS 4 |
| 713 | #define WNI_CFG_FORCE_POLICY_PROTECTION_AUTO 5 |
| 714 | |
| 715 | #define WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STAMIN 0 |
| 716 | #define WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STAMAX 1 |
| 717 | #define WNI_CFG_11G_SHORT_PREAMBLE_ENABLED_STADEF 0 |
| 718 | |
| 719 | #define WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STAMIN 0 |
| 720 | #define WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STAMAX 1 |
| 721 | #define WNI_CFG_11G_SHORT_SLOT_TIME_ENABLED_STADEF 1 |
| 722 | |
| 723 | #define WNI_CFG_11G_ONLY_POLICY_STAMIN 0 |
| 724 | #define WNI_CFG_11G_ONLY_POLICY_STAMAX 1 |
| 725 | #define WNI_CFG_11G_ONLY_POLICY_STADEF 0 |
| 726 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 727 | #define WNI_CFG_WME_ENABLED_STAMIN 0 |
| 728 | #define WNI_CFG_WME_ENABLED_STAMAX 1 |
| 729 | #define WNI_CFG_WME_ENABLED_STADEF 1 |
| 730 | |
| 731 | #define WNI_CFG_ADDTS_RSP_TIMEOUT_STAMIN 0 |
| 732 | #define WNI_CFG_ADDTS_RSP_TIMEOUT_STAMAX 65535 |
| 733 | #define WNI_CFG_ADDTS_RSP_TIMEOUT_STADEF 1000 |
| 734 | |
| 735 | #define WNI_CFG_MAX_SP_LENGTH_STAMIN 0 |
| 736 | #define WNI_CFG_MAX_SP_LENGTH_STAMAX 3 |
| 737 | #define WNI_CFG_MAX_SP_LENGTH_STADEF 0 |
| 738 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 739 | #define WNI_CFG_WSM_ENABLED_STAMIN 0 |
| 740 | #define WNI_CFG_WSM_ENABLED_STAMAX 1 |
| 741 | #define WNI_CFG_WSM_ENABLED_STADEF 0 |
| 742 | |
| 743 | #define WNI_CFG_EDCA_PROFILE_STAMIN 0 |
| 744 | #define WNI_CFG_EDCA_PROFILE_STAMAX 255 |
| 745 | #define WNI_CFG_EDCA_PROFILE_STADEF 1 |
| 746 | |
| 747 | #define WNI_CFG_EDCA_PROFILE_ANI 0 |
| 748 | #define WNI_CFG_EDCA_PROFILE_WMM 1 |
| 749 | #define WNI_CFG_EDCA_PROFILE_TIT_DEMO 2 |
| 750 | #define WNI_CFG_EDCA_PROFILE_MAX 3 |
| 751 | #define WNI_CFG_EDCA_PROFILE_ACM_IDX 0 |
| 752 | #define WNI_CFG_EDCA_PROFILE_AIFSN_IDX 1 |
| 753 | #define WNI_CFG_EDCA_PROFILE_CWMINA_IDX 2 |
| 754 | #define WNI_CFG_EDCA_PROFILE_CWMAXA_IDX 4 |
| 755 | #define WNI_CFG_EDCA_PROFILE_TXOPA_IDX 6 |
| 756 | #define WNI_CFG_EDCA_PROFILE_CWMINB_IDX 7 |
| 757 | #define WNI_CFG_EDCA_PROFILE_CWMAXB_IDX 9 |
| 758 | #define WNI_CFG_EDCA_PROFILE_TXOPB_IDX 11 |
| 759 | #define WNI_CFG_EDCA_PROFILE_CWMING_IDX 12 |
| 760 | #define WNI_CFG_EDCA_PROFILE_CWMAXG_IDX 14 |
| 761 | #define WNI_CFG_EDCA_PROFILE_TXOPG_IDX 16 |
| 762 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 763 | #define WNI_CFG_LOCAL_POWER_CONSTRAINT_STAMIN 0 |
| 764 | #define WNI_CFG_LOCAL_POWER_CONSTRAINT_STAMAX 255 |
| 765 | #define WNI_CFG_LOCAL_POWER_CONSTRAINT_STADEF 0 |
| 766 | |
| 767 | #define WNI_CFG_ADMIT_POLICY_STAMIN 0 |
| 768 | #define WNI_CFG_ADMIT_POLICY_STAMAX 2 |
| 769 | #define WNI_CFG_ADMIT_POLICY_STADEF 0 |
| 770 | |
| 771 | #define WNI_CFG_ADMIT_POLICY_ADMIT_ALL 0 |
| 772 | #define WNI_CFG_ADMIT_POLICY_REJECT_ALL 1 |
| 773 | #define WNI_CFG_ADMIT_POLICY_BW_FACTOR 2 |
| 774 | |
| 775 | #define WNI_CFG_ADMIT_BWFACTOR_STAMIN 0 |
| 776 | #define WNI_CFG_ADMIT_BWFACTOR_STAMAX 100 |
| 777 | #define WNI_CFG_ADMIT_BWFACTOR_STADEF 20 |
| 778 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 779 | #define WNI_CFG_CHANNEL_BONDING_MODE_STAMIN 0 |
| 780 | #define WNI_CFG_CHANNEL_BONDING_MODE_STAMAX 10 |
| 781 | #define WNI_CFG_CHANNEL_BONDING_MODE_STADEF 0 |
| 782 | |
| 783 | #define WNI_CFG_CHANNEL_BONDING_MODE_DISABLE 0 |
| 784 | #define WNI_CFG_CHANNEL_BONDING_MODE_ENABLE 1 |
| 785 | #define WNI_CFG_CHANNEL_BONDING_MODE_IF_NO_LEGACY_BSS 2 |
| 786 | #define WNI_CFG_CHANNEL_BONDING_MODE_IF_NO_LEGACY_ALL 3 |
| 787 | #define WNI_CFG_CHANNEL_BONDING_MODE_INTELLIGENT 4 |
| 788 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 789 | #define WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STAMIN 0 |
| 790 | #define WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STAMAX 255 |
| 791 | #define WNI_CFG_DYNAMIC_THRESHOLD_ZERO_STADEF 2 |
| 792 | |
| 793 | #define WNI_CFG_DYNAMIC_THRESHOLD_ONE_STAMIN 0 |
| 794 | #define WNI_CFG_DYNAMIC_THRESHOLD_ONE_STAMAX 255 |
| 795 | #define WNI_CFG_DYNAMIC_THRESHOLD_ONE_STADEF 4 |
| 796 | |
| 797 | #define WNI_CFG_DYNAMIC_THRESHOLD_TWO_STAMIN 0 |
| 798 | #define WNI_CFG_DYNAMIC_THRESHOLD_TWO_STAMAX 255 |
| 799 | #define WNI_CFG_DYNAMIC_THRESHOLD_TWO_STADEF 6 |
| 800 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 801 | #define WNI_CFG_BLOCK_ACK_ENABLED_STAMIN 0 |
| 802 | #define WNI_CFG_BLOCK_ACK_ENABLED_STAMAX 3 |
| 803 | #define WNI_CFG_BLOCK_ACK_ENABLED_STADEF 0 |
| 804 | |
| 805 | #define WNI_CFG_BLOCK_ACK_ENABLED_DELAYED 0 |
| 806 | #define WNI_CFG_BLOCK_ACK_ENABLED_IMMEDIATE 1 |
| 807 | |
| 808 | #define WNI_CFG_HT_RX_STBC_STAMIN 0 |
| 809 | #define WNI_CFG_HT_RX_STBC_STAMAX 3 |
| 810 | #define WNI_CFG_HT_RX_STBC_STADEF 1 |
| 811 | |
| 812 | #define WNI_CFG_HT_CAP_INFO_STAMIN 0 |
| 813 | #define WNI_CFG_HT_CAP_INFO_STAMAX 65535 |
| 814 | #define WNI_CFG_HT_CAP_INFO_STADEF 364 |
| 815 | |
| 816 | #define WNI_CFG_HT_CAP_INFO_ADVANCE_CODING 0 |
| 817 | #define WNI_CFG_HT_CAP_INFO_SUPPORTED_CHAN_WIDTH_SET 1 |
| 818 | #define WNI_CFG_HT_CAP_INFO_SM_POWER_SAVE 2 |
| 819 | #define WNI_CFG_HT_CAP_INFO_GREEN_FIELD 4 |
| 820 | #define WNI_CFG_HT_CAP_INFO_SHORT_GI_20MHZ 5 |
| 821 | #define WNI_CFG_HT_CAP_INFO_SHORT_GI_40MHZ 6 |
| 822 | #define WNI_CFG_HT_CAP_INFO_TX_STBC 7 |
| 823 | #define WNI_CFG_HT_CAP_INFO_RX_STBC 8 |
| 824 | #define WNI_CFG_HT_CAP_INFO_DELAYED_BA 10 |
| 825 | #define WNI_CFG_HT_CAP_INFO_MAX_AMSDU_SIZE 11 |
| 826 | #define WNI_CFG_HT_CAP_INFO_DSSS_CCK_MODE_40MHZ 12 |
| 827 | #define WNI_CFG_HT_CAP_INFO_PSMP 13 |
| 828 | #define WNI_CFG_HT_CAP_INFO_STBC_CONTROL_FRAME 14 |
| 829 | #define WNI_CFG_HT_CAP_INFO_LSIG_TXOP_PROTECTION 15 |
| 830 | |
| 831 | #define WNI_CFG_HT_AMPDU_PARAMS_STAMIN 0 |
| 832 | #define WNI_CFG_HT_AMPDU_PARAMS_STAMAX 255 |
| 833 | #define WNI_CFG_HT_AMPDU_PARAMS_STADEF 0 |
| 834 | |
| 835 | #define WNI_CFG_HT_AMPDU_PARAMS_MAX_RX_AMPDU_FACTOR 0 |
| 836 | #define WNI_CFG_HT_AMPDU_PARAMS_MPDU_DENSITY 2 |
| 837 | #define WNI_CFG_HT_AMPDU_PARAMS_RESERVED 5 |
| 838 | |
| 839 | #define WNI_CFG_EXT_HT_CAP_INFO_STAMIN 0 |
| 840 | #define WNI_CFG_EXT_HT_CAP_INFO_STAMAX 65535 |
| 841 | #define WNI_CFG_EXT_HT_CAP_INFO_STADEF 1024 |
| 842 | |
| 843 | #define WNI_CFG_EXT_HT_CAP_INFO_PCO 0 |
| 844 | #define WNI_CFG_EXT_HT_CAP_INFO_TRANSITION_TIME 1 |
| 845 | #define WNI_CFG_EXT_HT_CAP_INFO_RESERVED1 3 |
| 846 | #define WNI_CFG_EXT_HT_CAP_INFO_MCS_FEEDBACK 8 |
| 847 | #define WNI_CFG_EXT_HT_CAP_INFO_HTC_SUPPORT 10 |
| 848 | #define WNI_CFG_EXT_HT_CAP_INFO_RD_RESPONDER 11 |
| 849 | #define WNI_CFG_EXT_HT_CAP_INFO_RESERVED2 12 |
| 850 | |
| 851 | #define WNI_CFG_TX_BF_CAP_STAMIN 0 |
| 852 | #define WNI_CFG_TX_BF_CAP_STAMAX 4294967295 |
| 853 | #define WNI_CFG_TX_BF_CAP_STADEF 0 |
| 854 | |
| 855 | #define WNI_CFG_AS_CAP_STAMIN 0 |
| 856 | #define WNI_CFG_AS_CAP_STAMAX 255 |
| 857 | #define WNI_CFG_AS_CAP_STADEF 0 |
| 858 | |
| 859 | #define WNI_CFG_AS_CAP_ANTENNA_SELECTION 0 |
| 860 | #define WNI_CFG_AS_CAP_EXPLICIT_CSI_FEEDBACK_TX 1 |
| 861 | #define WNI_CFG_AS_CAP_ANTENNA_INDICES_FEEDBACK_TX 2 |
| 862 | #define WNI_CFG_AS_CAP_EXPLICIT_CSI_FEEDBACK 3 |
| 863 | #define WNI_CFG_AS_CAP_ANTENNA_INDICES_FEEDBACK 4 |
| 864 | #define WNI_CFG_AS_CAP_RX_AS 5 |
| 865 | #define WNI_CFG_AS_CAP_TX_SOUNDING_PPDUS 6 |
| 866 | #define WNI_CFG_AS_CAP_RESERVED 7 |
| 867 | |
| 868 | #define WNI_CFG_HT_INFO_FIELD1_STAMIN 0 |
| 869 | #define WNI_CFG_HT_INFO_FIELD1_STAMAX 255 |
| 870 | #define WNI_CFG_HT_INFO_FIELD1_STADEF 15 |
| 871 | |
| 872 | #define WNI_CFG_HT_INFO_FIELD1_SECONDARY_CHANNEL_OFFSET 0 |
| 873 | #define WNI_CFG_HT_INFO_FIELD1_RECOMMENDED_CHANNEL_WIDTH 2 |
| 874 | #define WNI_CFG_HT_INFO_FIELD1_RIFS_MODE 3 |
| 875 | #define WNI_CFG_HT_INFO_FIELD1_PSMP_ACCESS_ONLY 4 |
| 876 | #define WNI_CFG_HT_INFO_FIELD1_SERVICE_INTERVAL_GRANULARITY 5 |
| 877 | |
| 878 | #define WNI_CFG_HT_INFO_FIELD2_STAMIN 0 |
| 879 | #define WNI_CFG_HT_INFO_FIELD2_STAMAX 65535 |
| 880 | #define WNI_CFG_HT_INFO_FIELD2_STADEF 0 |
| 881 | |
| 882 | #define WNI_CFG_HT_INFO_FIELD2_OP_MODE 0 |
| 883 | #define WNI_CFG_HT_INFO_FIELD2_NON_GF_DEVICES_PRESENT 2 |
| 884 | #define WNI_CFG_HT_INFO_FIELD2_RESERVED 3 |
| 885 | |
| 886 | #define WNI_CFG_HT_INFO_FIELD3_STAMIN 0 |
| 887 | #define WNI_CFG_HT_INFO_FIELD3_STAMAX 65535 |
| 888 | #define WNI_CFG_HT_INFO_FIELD3_STADEF 0 |
| 889 | |
| 890 | #define WNI_CFG_HT_INFO_FIELD3_BASIC_STBC_MCS 0 |
| 891 | #define WNI_CFG_HT_INFO_FIELD3_DUAL_STBC_PROTECTION 7 |
| 892 | #define WNI_CFG_HT_INFO_FIELD3_SECONDARY_BEACON 8 |
| 893 | #define WNI_CFG_HT_INFO_FIELD3_LSIG_TXOP_PROTECTION_FULL_SUPPORT 9 |
| 894 | #define WNI_CFG_HT_INFO_FIELD3_PCO_ACTIVE 10 |
| 895 | #define WNI_CFG_HT_INFO_FIELD3_PCO_PHASE 11 |
| 896 | #define WNI_CFG_HT_INFO_FIELD3_RESERVED 12 |
| 897 | |
| 898 | #define WNI_CFG_GREENFIELD_CAPABILITY_STAMIN 0 |
| 899 | #define WNI_CFG_GREENFIELD_CAPABILITY_STAMAX 1 |
| 900 | #define WNI_CFG_GREENFIELD_CAPABILITY_STADEF 0 |
| 901 | |
| 902 | #define WNI_CFG_GREENFIELD_CAPABILITY_ENABLE 1 |
| 903 | #define WNI_CFG_GREENFIELD_CAPABILITY_DISABLE 0 |
| 904 | |
| 905 | #define WNI_CFG_VHT_MAX_MPDU_LENGTH_STAMIN 0 |
| 906 | #define WNI_CFG_VHT_MAX_MPDU_LENGTH_STAMAX 2 |
| 907 | #define WNI_CFG_VHT_MAX_MPDU_LENGTH_STADEF 0 |
| 908 | |
| 909 | #define WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STAMIN 0 |
| 910 | #define WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STAMAX 2 |
Kiran Kumar Lokere | 4bbbd0d | 2017-02-07 00:06:43 -0800 | [diff] [blame] | 911 | #define WNI_CFG_VHT_SUPPORTED_CHAN_WIDTH_SET_STADEF 0 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 912 | |
| 913 | #define WNI_CFG_VHT_LDPC_CODING_CAP_STAMIN 0 |
| 914 | #define WNI_CFG_VHT_LDPC_CODING_CAP_STAMAX 1 |
| 915 | #define WNI_CFG_VHT_LDPC_CODING_CAP_STADEF 0 |
| 916 | |
| 917 | #define WNI_CFG_VHT_SHORT_GI_80MHZ_STAMIN 0 |
| 918 | #define WNI_CFG_VHT_SHORT_GI_80MHZ_STAMAX 1 |
| 919 | #define WNI_CFG_VHT_SHORT_GI_80MHZ_STADEF 1 |
| 920 | |
| 921 | #define WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STAMIN 0 |
| 922 | #define WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STAMAX 1 |
Kiran Kumar Lokere | 4bbbd0d | 2017-02-07 00:06:43 -0800 | [diff] [blame] | 923 | #define WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ_STADEF 0 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 924 | |
| 925 | #define WNI_CFG_VHT_TXSTBC_STAMIN 0 |
| 926 | #define WNI_CFG_VHT_TXSTBC_STAMAX 1 |
| 927 | #define WNI_CFG_VHT_TXSTBC_STADEF 0 |
| 928 | |
| 929 | #define WNI_CFG_VHT_RXSTBC_STAMIN 0 |
| 930 | #define WNI_CFG_VHT_RXSTBC_STAMAX 1 |
| 931 | #define WNI_CFG_VHT_RXSTBC_STADEF 1 |
| 932 | |
| 933 | #define WNI_CFG_VHT_SU_BEAMFORMER_CAP_STAMIN 0 |
| 934 | #define WNI_CFG_VHT_SU_BEAMFORMER_CAP_STAMAX 1 |
| 935 | #define WNI_CFG_VHT_SU_BEAMFORMER_CAP_STADEF 0 |
| 936 | |
| 937 | #define WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STAMIN 0 |
| 938 | #define WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STAMAX 1 |
Sushant Kaushik | f217d95 | 2015-11-02 11:38:25 +0530 | [diff] [blame] | 939 | #define WNI_CFG_VHT_SU_BEAMFORMEE_CAP_STADEF 1 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 940 | |
| 941 | #define WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STAMIN 0 |
| 942 | #define WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STAMAX 4 |
| 943 | #define WNI_CFG_VHT_CSN_BEAMFORMEE_ANT_SUPPORTED_STADEF 0 |
| 944 | |
| 945 | #define WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STAMIN 0 |
| 946 | #define WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STAMAX 3 |
| 947 | #define WNI_CFG_VHT_NUM_SOUNDING_DIMENSIONS_STADEF 0 |
| 948 | |
| 949 | #define WNI_CFG_VHT_MU_BEAMFORMER_CAP_STAMIN 0 |
| 950 | #define WNI_CFG_VHT_MU_BEAMFORMER_CAP_STAMAX 1 |
| 951 | #define WNI_CFG_VHT_MU_BEAMFORMER_CAP_STADEF 0 |
| 952 | |
| 953 | #define WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STAMIN 0 |
| 954 | #define WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STAMAX 1 |
| 955 | #define WNI_CFG_VHT_MU_BEAMFORMEE_CAP_STADEF 0 |
| 956 | |
| 957 | #define WNI_CFG_VHT_TXOP_PS_STAMIN 0 |
| 958 | #define WNI_CFG_VHT_TXOP_PS_STAMAX 1 |
| 959 | #define WNI_CFG_VHT_TXOP_PS_STADEF 0 |
| 960 | |
| 961 | #define WNI_CFG_VHT_HTC_VHTC_CAP_STAMIN 0 |
| 962 | #define WNI_CFG_VHT_HTC_VHTC_CAP_STAMAX 1 |
| 963 | #define WNI_CFG_VHT_HTC_VHTC_CAP_STADEF 0 |
| 964 | |
| 965 | #define WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STAMIN 0 |
| 966 | #define WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STAMAX 7 |
| 967 | #define WNI_CFG_VHT_AMPDU_LEN_EXPONENT_STADEF 3 |
| 968 | |
| 969 | #define WNI_CFG_VHT_LINK_ADAPTATION_CAP_STAMIN 0 |
| 970 | #define WNI_CFG_VHT_LINK_ADAPTATION_CAP_STAMAX 3 |
| 971 | #define WNI_CFG_VHT_LINK_ADAPTATION_CAP_STADEF 0 |
| 972 | |
| 973 | #define WNI_CFG_VHT_RX_ANT_PATTERN_STAMIN 0 |
| 974 | #define WNI_CFG_VHT_RX_ANT_PATTERN_STAMAX 1 |
| 975 | #define WNI_CFG_VHT_RX_ANT_PATTERN_STADEF 1 |
| 976 | |
| 977 | #define WNI_CFG_VHT_TX_ANT_PATTERN_STAMIN 0 |
| 978 | #define WNI_CFG_VHT_TX_ANT_PATTERN_STAMAX 1 |
| 979 | #define WNI_CFG_VHT_TX_ANT_PATTERN_STADEF 1 |
| 980 | |
| 981 | #define WNI_CFG_VHT_RX_MCS_MAP_STAMIN 0 |
| 982 | #define WNI_CFG_VHT_RX_MCS_MAP_STAMAX 65535 |
| 983 | #define WNI_CFG_VHT_RX_MCS_MAP_STADEF 65534 |
| 984 | |
| 985 | #define WNI_CFG_VHT_TX_MCS_MAP_STAMIN 0 |
| 986 | #define WNI_CFG_VHT_TX_MCS_MAP_STAMAX 65535 |
| 987 | #define WNI_CFG_VHT_TX_MCS_MAP_STADEF 65534 |
| 988 | |
| 989 | #define WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STAMIN 0 |
| 990 | #define WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STAMAX 780 |
| 991 | #define WNI_CFG_VHT_RX_HIGHEST_SUPPORTED_DATA_RATE_STADEF 780 |
| 992 | |
| 993 | #define WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STAMIN 0 |
| 994 | #define WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STAMAX 780 |
| 995 | #define WNI_CFG_VHT_TX_HIGHEST_SUPPORTED_DATA_RATE_STADEF 780 |
| 996 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 997 | #define WNI_CFG_VHT_BASIC_MCS_SET_STAMIN 0 |
| 998 | #define WNI_CFG_VHT_BASIC_MCS_SET_STAMAX 65535 |
| 999 | #define WNI_CFG_VHT_BASIC_MCS_SET_STADEF 65534 |
| 1000 | |
| 1001 | #define WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STAMIN 0 |
| 1002 | #define WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STAMAX 4 |
| 1003 | #define WNI_CFG_VHT_MU_MIMO_CAP_STA_COUNT_STADEF 0 |
| 1004 | |
| 1005 | #define WNI_CFG_VHT_SS_UNDER_UTIL_STAMIN 0 |
| 1006 | #define WNI_CFG_VHT_SS_UNDER_UTIL_STAMAX 0 |
| 1007 | #define WNI_CFG_VHT_SS_UNDER_UTIL_STADEF 0 |
| 1008 | |
| 1009 | #define WNI_CFG_VHT_40MHZ_UTILIZATION_STAMIN 0 |
| 1010 | #define WNI_CFG_VHT_40MHZ_UTILIZATION_STAMAX 0 |
| 1011 | #define WNI_CFG_VHT_40MHZ_UTILIZATION_STADEF 0 |
| 1012 | |
| 1013 | #define WNI_CFG_VHT_80MHZ_UTILIZATION_STAMIN 0 |
| 1014 | #define WNI_CFG_VHT_80MHZ_UTILIZATION_STAMAX 0 |
| 1015 | #define WNI_CFG_VHT_80MHZ_UTILIZATION_STADEF 0 |
| 1016 | |
| 1017 | #define WNI_CFG_VHT_160MHZ_UTILIZATION_STAMIN 0 |
| 1018 | #define WNI_CFG_VHT_160MHZ_UTILIZATION_STAMAX 0 |
| 1019 | #define WNI_CFG_VHT_160MHZ_UTILIZATION_STADEF 0 |
| 1020 | |
| 1021 | #define WNI_CFG_MAX_AMSDU_LENGTH_STAMIN 0 |
| 1022 | #define WNI_CFG_MAX_AMSDU_LENGTH_STAMAX 1 |
| 1023 | #define WNI_CFG_MAX_AMSDU_LENGTH_STADEF 0 |
| 1024 | |
| 1025 | #define WNI_CFG_MAX_AMSDU_LENGTH_SHORT_3839_BYTES 0 |
| 1026 | #define WNI_CFG_MAX_AMSDU_LENGTH_LONG_7935__BYTES 1 |
| 1027 | |
| 1028 | #define WNI_CFG_MPDU_DENSITY_STAMIN 0 |
| 1029 | #define WNI_CFG_MPDU_DENSITY_STAMAX 7 |
Krishna Kumaar Natarajan | 22b59a7 | 2015-11-23 18:54:58 -0800 | [diff] [blame] | 1030 | #define WNI_CFG_MPDU_DENSITY_STADEF 7 |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1031 | |
| 1032 | #define WNI_CFG_NUM_BUFF_ADVERT_STAMIN 0 |
| 1033 | #define WNI_CFG_NUM_BUFF_ADVERT_STAMAX 128 |
| 1034 | #define WNI_CFG_NUM_BUFF_ADVERT_STADEF 64 |
| 1035 | |
| 1036 | #define WNI_CFG_MAX_RX_AMPDU_FACTOR_STAMIN 0 |
| 1037 | #define WNI_CFG_MAX_RX_AMPDU_FACTOR_STAMAX 3 |
| 1038 | #define WNI_CFG_MAX_RX_AMPDU_FACTOR_STADEF 3 |
| 1039 | |
| 1040 | #define WNI_CFG_SHORT_GI_20MHZ_STAMIN 0 |
| 1041 | #define WNI_CFG_SHORT_GI_20MHZ_STAMAX 1 |
| 1042 | #define WNI_CFG_SHORT_GI_20MHZ_STADEF 1 |
| 1043 | |
| 1044 | #define WNI_CFG_SHORT_GI_20MHZ_ENABLE 1 |
| 1045 | #define WNI_CFG_SHORT_GI_20MHZ_DISABLE 0 |
| 1046 | |
| 1047 | #define WNI_CFG_SHORT_GI_40MHZ_STAMIN 0 |
| 1048 | #define WNI_CFG_SHORT_GI_40MHZ_STAMAX 1 |
| 1049 | #define WNI_CFG_SHORT_GI_40MHZ_STADEF 0 |
| 1050 | |
| 1051 | #define WNI_CFG_SHORT_GI_40MHZ_ENABLE 1 |
| 1052 | #define WNI_CFG_SHORT_GI_40MHZ_DISABLE 0 |
| 1053 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1054 | #define WNI_CFG_MAX_PS_POLL_STAMIN 0 |
| 1055 | #define WNI_CFG_MAX_PS_POLL_STAMAX 255 |
| 1056 | #define WNI_CFG_MAX_PS_POLL_STADEF 0 |
| 1057 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1058 | #define WNI_CFG_RSSI_FILTER_PERIOD_STAMIN 0 |
| 1059 | #define WNI_CFG_RSSI_FILTER_PERIOD_STAMAX 255 |
| 1060 | #define WNI_CFG_RSSI_FILTER_PERIOD_STADEF 5 |
| 1061 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1062 | #define WNI_CFG_SCAN_IN_POWERSAVE_STAMIN 0 |
| 1063 | #define WNI_CFG_SCAN_IN_POWERSAVE_STAMAX 1 |
| 1064 | #define WNI_CFG_SCAN_IN_POWERSAVE_STADEF 1 |
| 1065 | |
| 1066 | #define WNI_CFG_IGNORE_DTIM_STAMIN 0 |
| 1067 | #define WNI_CFG_IGNORE_DTIM_STAMAX 1 |
| 1068 | #define WNI_CFG_IGNORE_DTIM_STADEF 0 |
| 1069 | |
| 1070 | #define WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STAMIN 0 |
| 1071 | #define WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STAMAX 1 |
| 1072 | #define WNI_CFG_WOWLAN_UCAST_PATTERN_FILTER_ENABLE_STADEF 1 |
| 1073 | |
| 1074 | #define WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STAMIN 0 |
| 1075 | #define WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STAMAX 1 |
| 1076 | #define WNI_CFG_WOWLAN_CHANNEL_SWITCH_ENABLE_STADEF 1 |
| 1077 | |
| 1078 | #define WNI_CFG_WOWLAN_DEAUTH_ENABLE_STAMIN 0 |
| 1079 | #define WNI_CFG_WOWLAN_DEAUTH_ENABLE_STAMAX 1 |
| 1080 | #define WNI_CFG_WOWLAN_DEAUTH_ENABLE_STADEF 1 |
| 1081 | |
| 1082 | #define WNI_CFG_WOWLAN_DISASSOC_ENABLE_STAMIN 0 |
| 1083 | #define WNI_CFG_WOWLAN_DISASSOC_ENABLE_STAMAX 1 |
| 1084 | #define WNI_CFG_WOWLAN_DISASSOC_ENABLE_STADEF 1 |
| 1085 | |
| 1086 | #define WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STAMIN 0 |
| 1087 | #define WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STAMAX 65535 |
| 1088 | #define WNI_CFG_WOWLAN_MAX_MISSED_BEACON_STADEF 40 |
| 1089 | |
| 1090 | #define WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STAMIN 0 |
| 1091 | #define WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STAMAX 65535 |
| 1092 | #define WNI_CFG_WOWLAN_MAX_SLEEP_PERIOD_STADEF 65535 |
| 1093 | |
| 1094 | #define WNI_CFG_MAX_MEDIUM_TIME_STAMIN 0 |
| 1095 | #define WNI_CFG_MAX_MEDIUM_TIME_STAMAX 65535 |
| 1096 | #define WNI_CFG_MAX_MEDIUM_TIME_STADEF 2048 |
| 1097 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1098 | #define WNI_CFG_IBSS_AUTO_BSSID_STAMIN 0 |
| 1099 | #define WNI_CFG_IBSS_AUTO_BSSID_STAMAX 1 |
| 1100 | #define WNI_CFG_IBSS_AUTO_BSSID_STADEF 1 |
| 1101 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1102 | #define WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STAMIN 0 |
| 1103 | #define WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STAMAX 1 |
| 1104 | #define WNI_CFG_PROBE_RSP_BCN_ADDNIE_FLAG_STADEF 0 |
| 1105 | |
| 1106 | #define WNI_CFG_WPS_ENABLE_STAMIN 0 |
| 1107 | #define WNI_CFG_WPS_ENABLE_STAMAX 255 |
| 1108 | #define WNI_CFG_WPS_ENABLE_STADEF 0 |
| 1109 | |
| 1110 | #define WNI_CFG_WPS_ENABLE_AP 1 |
| 1111 | #define WNI_CFG_WPS_ENABLE_STA 2 |
| 1112 | |
| 1113 | #define WNI_CFG_WPS_STATE_STAMIN 0 |
| 1114 | #define WNI_CFG_WPS_STATE_STAMAX 255 |
| 1115 | #define WNI_CFG_WPS_STATE_STADEF 1 |
| 1116 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1117 | #define WNI_CFG_WPS_VERSION_STAMIN 0 |
| 1118 | #define WNI_CFG_WPS_VERSION_STAMAX 255 |
| 1119 | #define WNI_CFG_WPS_VERSION_STADEF 16 |
| 1120 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1121 | #define WNI_CFG_WPS_CFG_METHOD_STAMIN 0 |
| 1122 | #define WNI_CFG_WPS_CFG_METHOD_STAMAX 4294967295 |
| 1123 | #define WNI_CFG_WPS_CFG_METHOD_STADEF 8 |
| 1124 | |
| 1125 | #define WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STAMIN 0 |
| 1126 | #define WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STAMAX 65535 |
| 1127 | #define WNI_CFG_WPS_PRIMARY_DEVICE_CATEGORY_STADEF 1 |
| 1128 | |
| 1129 | #define WNI_CFG_WPS_PIMARY_DEVICE_OUI_STAMIN 0 |
| 1130 | #define WNI_CFG_WPS_PIMARY_DEVICE_OUI_STAMAX 4294967295 |
| 1131 | #define WNI_CFG_WPS_PIMARY_DEVICE_OUI_STADEF 5304836 |
| 1132 | |
| 1133 | #define WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STAMIN 0 |
| 1134 | #define WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STAMAX 65535 |
| 1135 | #define WNI_CFG_WPS_DEVICE_SUB_CATEGORY_STADEF 1 |
| 1136 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1137 | #define WNI_CFG_WPS_DEVICE_PASSWORD_ID_STAMIN 0 |
| 1138 | #define WNI_CFG_WPS_DEVICE_PASSWORD_ID_STAMAX 4294967295 |
| 1139 | #define WNI_CFG_WPS_DEVICE_PASSWORD_ID_STADEF 0 |
| 1140 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1141 | #define WNI_CFG_LOW_GAIN_OVERRIDE_STAMIN 0 |
| 1142 | #define WNI_CFG_LOW_GAIN_OVERRIDE_STAMAX 1 |
| 1143 | #define WNI_CFG_LOW_GAIN_OVERRIDE_STADEF 0 |
| 1144 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1145 | #define WNI_CFG_SINGLE_TID_RC_STAMIN 0 |
| 1146 | #define WNI_CFG_SINGLE_TID_RC_STAMAX 1 |
| 1147 | #define WNI_CFG_SINGLE_TID_RC_STADEF 1 |
| 1148 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1149 | #define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMIN 0 |
| 1150 | #define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STAMAX 3 |
| 1151 | #define WNI_CFG_MCAST_BCAST_FILTER_SETTING_STADEF 0 |
| 1152 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1153 | #define WNI_CFG_DYNAMIC_PS_POLL_VALUE_STAMIN 0 |
| 1154 | #define WNI_CFG_DYNAMIC_PS_POLL_VALUE_STAMAX 255 |
| 1155 | #define WNI_CFG_DYNAMIC_PS_POLL_VALUE_STADEF 0 |
| 1156 | |
| 1157 | #define WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STAMIN 0 |
| 1158 | #define WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STAMAX 80 |
| 1159 | #define WNI_CFG_PS_NULLDATA_AP_RESP_TIMEOUT_STADEF 0 |
| 1160 | |
| 1161 | #define WNI_CFG_TELE_BCN_WAKEUP_EN_STAMIN 0 |
| 1162 | #define WNI_CFG_TELE_BCN_WAKEUP_EN_STAMAX 1 |
| 1163 | #define WNI_CFG_TELE_BCN_WAKEUP_EN_STADEF 0 |
| 1164 | |
| 1165 | #define WNI_CFG_TELE_BCN_TRANS_LI_STAMIN 0 |
| 1166 | #define WNI_CFG_TELE_BCN_TRANS_LI_STAMAX 7 |
| 1167 | #define WNI_CFG_TELE_BCN_TRANS_LI_STADEF 3 |
| 1168 | |
| 1169 | #define WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STAMIN 5 |
| 1170 | #define WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STAMAX 255 |
| 1171 | #define WNI_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS_STADEF 10 |
| 1172 | |
| 1173 | #define WNI_CFG_TELE_BCN_MAX_LI_STAMIN 0 |
| 1174 | #define WNI_CFG_TELE_BCN_MAX_LI_STAMAX 7 |
| 1175 | #define WNI_CFG_TELE_BCN_MAX_LI_STADEF 5 |
| 1176 | |
| 1177 | #define WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STAMIN 5 |
| 1178 | #define WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STAMAX 255 |
| 1179 | #define WNI_CFG_TELE_BCN_MAX_LI_IDLE_BCNS_STADEF 15 |
| 1180 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1181 | #define WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STAMIN 0 |
| 1182 | #define WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STAMAX 1000 |
| 1183 | #define WNI_CFG_INFRA_STA_KEEP_ALIVE_PERIOD_STADEF 0 |
| 1184 | |
| 1185 | #define WNI_CFG_ASSOC_STA_LIMIT_STAMIN 1 |
| 1186 | #define WNI_CFG_ASSOC_STA_LIMIT_STAMAX 32 |
| 1187 | #define WNI_CFG_ASSOC_STA_LIMIT_STADEF 10 |
| 1188 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1189 | #define WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STAMIN 0 |
| 1190 | #define WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STAMAX 65535 |
| 1191 | #define WNI_CFG_AP_DATA_AVAIL_POLL_PERIOD_STADEF 5 |
| 1192 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1193 | #define WNI_CFG_ENABLE_LTE_COEX_STAMIN 0 |
| 1194 | #define WNI_CFG_ENABLE_LTE_COEX_STAMAX 1 |
| 1195 | #define WNI_CFG_ENABLE_LTE_COEX_STADEF 0 |
| 1196 | |
| 1197 | #define WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STAMIN 1 |
| 1198 | #define WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STAMAX 65535 |
| 1199 | #define WNI_CFG_AP_KEEP_ALIVE_TIMEOUT_STADEF 20 |
| 1200 | |
| 1201 | #define WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STAMIN 1 |
| 1202 | #define WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STAMAX 65535 |
| 1203 | #define WNI_CFG_GO_KEEP_ALIVE_TIMEOUT_STADEF 20 |
| 1204 | |
| 1205 | #define WNI_CFG_ENABLE_MC_ADDR_LIST_STAMIN 0 |
| 1206 | #define WNI_CFG_ENABLE_MC_ADDR_LIST_STAMAX 1 |
| 1207 | #define WNI_CFG_ENABLE_MC_ADDR_LIST_STADEF 0 |
| 1208 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1209 | #define WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STAMIN 0 |
| 1210 | #define WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STAMAX 1 |
| 1211 | #define WNI_CFG_ENABLE_LPWR_IMG_TRANSITION_STADEF 0 |
| 1212 | |
| 1213 | #define WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STAMIN 0 |
| 1214 | #define WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STAMAX 1 |
| 1215 | #define WNI_CFG_ENABLE_MCC_ADAPTIVE_SCHED_STADEF 0 |
| 1216 | |
| 1217 | #define WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STAMIN 0 |
| 1218 | #define WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STAMAX 1 |
| 1219 | #define WNI_CFG_DISABLE_LDPC_WITH_TXBF_AP_STADEF 0 |
| 1220 | |
| 1221 | #define WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STAMIN 1 |
| 1222 | #define WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STAMAX 255 |
| 1223 | #define WNI_CFG_AP_LINK_MONITOR_TIMEOUT_STADEF 3 |
| 1224 | |
| 1225 | #define WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STAMIN 0 |
| 1226 | #define WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STAMAX 15 |
| 1227 | #define WNI_CFG_TDLS_QOS_WMM_UAPSD_MASK_STADEF 0 |
| 1228 | |
| 1229 | #define WNI_CFG_TDLS_BUF_STA_ENABLED_STAMIN 0 |
| 1230 | #define WNI_CFG_TDLS_BUF_STA_ENABLED_STAMAX 1 |
| 1231 | #define WNI_CFG_TDLS_BUF_STA_ENABLED_STADEF 0 |
| 1232 | |
| 1233 | #define WNI_CFG_TDLS_PUAPSD_INACT_TIME_STAMIN 0 |
| 1234 | #define WNI_CFG_TDLS_PUAPSD_INACT_TIME_STAMAX 10 |
| 1235 | #define WNI_CFG_TDLS_PUAPSD_INACT_TIME_STADEF 0 |
| 1236 | |
| 1237 | #define WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STAMIN 10 |
| 1238 | #define WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STAMAX 20 |
| 1239 | #define WNI_CFG_TDLS_RX_FRAME_THRESHOLD_STADEF 10 |
| 1240 | |
| 1241 | #define WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STAMIN 0 |
| 1242 | #define WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STAMAX 20 |
| 1243 | #define WNI_CFG_PMF_SA_QUERY_MAX_RETRIES_STADEF 5 |
| 1244 | |
| 1245 | #define WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STAMIN 10 |
| 1246 | #define WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STAMAX 2000 |
| 1247 | #define WNI_CFG_PMF_SA_QUERY_RETRY_INTERVAL_STADEF 200 |
| 1248 | |
| 1249 | #define WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STAMIN 0 |
| 1250 | #define WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STAMAX 1 |
| 1251 | #define WNI_CFG_ENABLE_ADAPT_RX_DRAIN_STADEF 1 |
| 1252 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1253 | #define WNI_CFG_ANTENNA_DIVESITY_STAMIN 0 |
| 1254 | #define WNI_CFG_ANTENNA_DIVESITY_STAMAX 3 |
| 1255 | #define WNI_CFG_ANTENNA_DIVESITY_STADEF 0 |
| 1256 | |
| 1257 | #define WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STAMIN 3 |
| 1258 | #define WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STAMAX 50 |
| 1259 | #define WNI_CFG_GO_LINK_MONITOR_TIMEOUT_STADEF 10 |
| 1260 | |
| 1261 | #define WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STAMIN 100 |
| 1262 | #define WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STAMAX 1000 |
| 1263 | #define WNI_CFG_RMC_ACTION_PERIOD_FREQUENCY_STADEF 300 |
| 1264 | |
| 1265 | #define WNI_CFG_CURRENT_RSSI_STAMIN 0 |
| 1266 | #define WNI_CFG_CURRENT_RSSI_STAMAX 127 |
| 1267 | #define WNI_CFG_CURRENT_RSSI_STADEF 0 |
| 1268 | |
| 1269 | #define WNI_CFG_RTT3_ENABLE_STAMIN 0 |
| 1270 | #define WNI_CFG_RTT3_ENABLE_STAMAX 1 |
| 1271 | #define WNI_CFG_RTT3_ENABLE_STADEF 1 |
| 1272 | |
| 1273 | #define WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STAMIN 0 |
| 1274 | #define WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STAMAX 1 |
| 1275 | #define WNI_CFG_DEBUG_P2P_REMAIN_ON_CHANNEL_STADEF 0 |
| 1276 | |
| 1277 | #define WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STAMIN 0 |
| 1278 | #define WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STAMAX 1 |
| 1279 | #define WNI_CFG_TDLS_OFF_CHANNEL_ENABLED_STADEF 0 |
| 1280 | |
| 1281 | #define WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMIN 0 |
| 1282 | #define WNI_CFG_IBSS_ATIM_WIN_SIZE_STAMAX 100 |
| 1283 | #define WNI_CFG_IBSS_ATIM_WIN_SIZE_STADEF 0 |
| 1284 | |
| 1285 | #define WNI_CFG_DFS_MASTER_ENABLED_STAMIN 0 |
| 1286 | #define WNI_CFG_DFS_MASTER_ENABLED_STAMAX 1 |
| 1287 | #define WNI_CFG_DFS_MASTER_ENABLED_STADEF 0 |
| 1288 | |
| 1289 | #define WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STAMIN 0 |
| 1290 | #define WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STAMAX 1 |
| 1291 | #define WNI_CFG_VHT_ENABLE_TXBF_20MHZ_STADEF 0 |
| 1292 | |
| 1293 | #define WNI_CFG_TDLS_WMM_MODE_ENABLED_STAMIN 0 |
| 1294 | #define WNI_CFG_TDLS_WMM_MODE_ENABLED_STAMAX 1 |
| 1295 | #define WNI_CFG_TDLS_WMM_MODE_ENABLED_STADEF 0 |
| 1296 | |
Sandeep Puligilla | e087566 | 2016-02-12 16:09:21 -0800 | [diff] [blame] | 1297 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STAMIN 5 |
| 1298 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STAMAX 1000 |
| 1299 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_DWELL_TIME_STADEF 20 |
| 1300 | |
| 1301 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STAMIN 10 |
| 1302 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STAMAX 1000 |
| 1303 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_DWELL_TIME_STADEF 10 |
| 1304 | |
| 1305 | #define WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STAMIN 10 |
| 1306 | #define WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STAMAX 900 |
| 1307 | #define WNI_CFG_OBSS_HT40_SCAN_WIDTH_TRIGGER_INTERVAL_STADEF 200 |
| 1308 | |
| 1309 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STAMIN 200 |
| 1310 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STAMAX 10000 |
| 1311 | #define WNI_CFG_OBSS_HT40_SCAN_PASSIVE_TOTAL_PER_CHANNEL_STADEF 200 |
| 1312 | |
| 1313 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STAMIN 20 |
| 1314 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STAMAX 10000 |
| 1315 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVE_TOTAL_PER_CHANNEL_STADEF 20 |
| 1316 | |
| 1317 | #define WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STAMIN 5 |
| 1318 | #define WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STAMAX 100 |
| 1319 | #define WNI_CFG_OBSS_HT40_WIDTH_CH_TRANSITION_DELAY_STADEF 5 |
| 1320 | |
| 1321 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMIN 0 |
| 1322 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STAMAX 100 |
| 1323 | #define WNI_CFG_OBSS_HT40_SCAN_ACTIVITY_THRESHOLD_STADEF 25 |
| 1324 | |
Rajeev Kumar Sirasanagandla | af47474 | 2016-09-06 17:54:50 +0530 | [diff] [blame] | 1325 | #define WNI_CFG_TGT_GTX_USR_CFG_STAMIN 0 |
| 1326 | #define WNI_CFG_TGT_GTX_USR_CFG_STAMAX 32 |
| 1327 | #define WNI_CFG_TGT_GTX_USR_CFG_STADEF 32 |
| 1328 | |
Hong Shi | 417824f | 2017-01-12 02:31:14 +0800 | [diff] [blame] | 1329 | #define WNI_CFG_MAX_HT_MCS_TX_DATA_STAMIN 0x0 |
| 1330 | #define WNI_CFG_MAX_HT_MCS_TX_DATA_STAMAX 0x17f |
| 1331 | #define WNI_CFG_MAX_HT_MCS_TX_DATA_STADEF 0x0 |
| 1332 | |
Hong Shi | a9ef871 | 2017-02-19 21:54:02 +0800 | [diff] [blame] | 1333 | #define WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STAMIN 0 |
| 1334 | #define WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STAMAX 1 |
| 1335 | #define WNI_CFG_DISABLE_ABG_RATE_FOR_TX_DATA_STADEF 0 |
| 1336 | |
Hong Shi | b90718f | 2017-02-20 00:57:22 +0800 | [diff] [blame] | 1337 | #define WNI_CFG_RATE_FOR_TX_MGMT_STAMIN 0x0 |
| 1338 | #define WNI_CFG_RATE_FOR_TX_MGMT_STAMAX 0xFF |
| 1339 | #define WNI_CFG_RATE_FOR_TX_MGMT_STADEF 0xFF |
| 1340 | |
Krishna Kumaar Natarajan | ed1efd9 | 2016-09-24 18:05:47 -0700 | [diff] [blame^] | 1341 | #define WNI_CFG_HE_CONTROL_STAMIN 0 |
| 1342 | #define WNI_CFG_HE_CONTROL_STAMAX 1 |
| 1343 | #define WNI_CFG_HE_CONTROL_STADEF 0 |
| 1344 | |
| 1345 | #define WNI_CFG_HE_TWT_REQUESTOR_STAMIN 0 |
| 1346 | #define WNI_CFG_HE_TWT_REQUESTOR_STAMAX 1 |
| 1347 | #define WNI_CFG_HE_TWT_REQUESTOR_STADEF 0 |
| 1348 | |
| 1349 | #define WNI_CFG_HE_TWT_RESPONDER_STAMIN 0 |
| 1350 | #define WNI_CFG_HE_TWT_RESPONDER_STAMAX 1 |
| 1351 | #define WNI_CFG_HE_TWT_RESPONDER_STADEF 0 |
| 1352 | |
| 1353 | #define WNI_CFG_HE_FRAGMENTATION_STAMIN 0 |
| 1354 | #define WNI_CFG_HE_FRAGMENTATION_STAMAX 0x3 |
| 1355 | #define WNI_CFG_HE_FRAGMENTATION_STADEF 0 |
| 1356 | |
| 1357 | #define WNI_CFG_HE_MAX_FRAG_MSDU_STAMIN 0 |
| 1358 | #define WNI_CFG_HE_MAX_FRAG_MSDU_STAMAX 0x7 |
| 1359 | #define WNI_CFG_HE_MAX_FRAG_MSDU_STADEF 0 |
| 1360 | |
| 1361 | #define WNI_CFG_HE_MIN_FRAG_SIZE_STAMIN 0 |
| 1362 | #define WNI_CFG_HE_MIN_FRAG_SIZE_STAMAX 0x3 |
| 1363 | #define WNI_CFG_HE_MIN_FRAG_SIZE_STADEF 0 |
| 1364 | |
| 1365 | #define WNI_CFG_HE_TRIG_PAD_STAMIN 0 |
| 1366 | #define WNI_CFG_HE_TRIG_PAD_STAMAX 2 |
| 1367 | #define WNI_CFG_HE_TRIG_PAD_STADEF 0 |
| 1368 | |
| 1369 | #define WNI_CFG_HE_MTID_AGGR_STAMIN 0 |
| 1370 | #define WNI_CFG_HE_MTID_AGGR_STAMAX 0x7 |
| 1371 | #define WNI_CFG_HE_MTID_AGGR_STADEF 0 |
| 1372 | |
| 1373 | #define WNI_CFG_HE_LINK_ADAPTATION_STAMIN 0 |
| 1374 | #define WNI_CFG_HE_LINK_ADAPTATION_STAMAX 0x3 |
| 1375 | #define WNI_CFG_HE_LINK_ADAPTATION_STADEF 0 |
| 1376 | |
| 1377 | #define WNI_CFG_HE_ALL_ACK_STAMIN 0 |
| 1378 | #define WNI_CFG_HE_ALL_ACK_STAMAX 1 |
| 1379 | #define WNI_CFG_HE_ALL_ACK_STADEF 0 |
| 1380 | |
| 1381 | #define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMIN 0 |
| 1382 | #define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STAMAX 1 |
| 1383 | #define WNI_CFG_HE_UL_MU_RSP_SCHEDULING_STADEF 0 |
| 1384 | |
| 1385 | #define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMIN 0 |
| 1386 | #define WNI_CFG_HE_BUFFER_STATUS_RPT_STAMAX 1 |
| 1387 | #define WNI_CFG_HE_BUFFER_STATUS_RPT_STADEF 0 |
| 1388 | |
| 1389 | #define WNI_CFG_HE_BCAST_TWT_STAMIN 0 |
| 1390 | #define WNI_CFG_HE_BCAST_TWT_STAMAX 1 |
| 1391 | #define WNI_CFG_HE_BCAST_TWT_STADEF 0 |
| 1392 | |
| 1393 | #define WNI_CFG_HE_BA_32BIT_STAMIN 0 |
| 1394 | #define WNI_CFG_HE_BA_32BIT_STAMAX 1 |
| 1395 | #define WNI_CFG_HE_BA_32BIT_STADEF 0 |
| 1396 | |
| 1397 | #define WNI_CFG_HE_MU_CASCADING_STAMIN 0 |
| 1398 | #define WNI_CFG_HE_MU_CASCADING_STAMAX 1 |
| 1399 | #define WNI_CFG_HE_MU_CASCADING_STADEF 0 |
| 1400 | |
| 1401 | #define WNI_CFG_HE_MULTI_TID_STAMIN 0 |
| 1402 | #define WNI_CFG_HE_MULTI_TID_STAMAX 1 |
| 1403 | #define WNI_CFG_HE_MULTI_TID_STADEF 0 |
| 1404 | |
| 1405 | #define WNI_CFG_HE_DL_MU_BA_STAMIN 0 |
| 1406 | #define WNI_CFG_HE_DL_MU_BA_STAMAX 1 |
| 1407 | #define WNI_CFG_HE_DL_MU_BA_STADEF 0 |
| 1408 | |
| 1409 | #define WNI_CFG_HE_OMI_STAMIN 0 |
| 1410 | #define WNI_CFG_HE_OMI_STAMAX 1 |
| 1411 | #define WNI_CFG_HE_OMI_STADEF 0 |
| 1412 | |
| 1413 | #define WNI_CFG_HE_OFDMA_RA_STAMIN 0 |
| 1414 | #define WNI_CFG_HE_OFDMA_RA_STAMAX 1 |
| 1415 | #define WNI_CFG_HE_OFDMA_RA_STADEF 0 |
| 1416 | |
| 1417 | #define WNI_CFG_HE_MAX_AMPDU_LEN_STAMIN 0 |
| 1418 | #define WNI_CFG_HE_MAX_AMPDU_LEN_STAMAX 0x3 |
| 1419 | #define WNI_CFG_HE_MAX_AMPDU_LEN_STADEF 0 |
| 1420 | |
| 1421 | #define WNI_CFG_HE_AMSDU_FRAG_STAMIN 0 |
| 1422 | #define WNI_CFG_HE_AMSDU_FRAG_STAMAX 1 |
| 1423 | #define WNI_CFG_HE_AMSDU_FRAG_STADEF 0 |
| 1424 | |
| 1425 | #define WNI_CFG_HE_FLEX_TWT_SCHED_STAMIN 0 |
| 1426 | #define WNI_CFG_HE_FLEX_TWT_SCHED_STAMAX 1 |
| 1427 | #define WNI_CFG_HE_FLEX_TWT_SCHED_STADEF 0 |
| 1428 | |
| 1429 | #define WNI_CFG_HE_RX_CTRL_STAMIN 0 |
| 1430 | #define WNI_CFG_HE_RX_CTRL_STAMAX 1 |
| 1431 | #define WNI_CFG_HE_RX_CTRL_STADEF 0 |
| 1432 | |
| 1433 | #define WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMIN 0 |
| 1434 | #define WNI_CFG_HE_BSRP_AMPDU_AGGR_STAMAX 1 |
| 1435 | #define WNI_CFG_HE_BSRP_AMPDU_AGGR_STADEF 0 |
| 1436 | |
| 1437 | #define WNI_CFG_HE_QTP_STAMIN 0 |
| 1438 | #define WNI_CFG_HE_QTP_STAMAX 1 |
| 1439 | #define WNI_CFG_HE_QTP_STADEF 0 |
| 1440 | |
| 1441 | #define WNI_CFG_HE_A_BQR_STAMIN 0 |
| 1442 | #define WNI_CFG_HE_A_BQR_STAMAX 1 |
| 1443 | #define WNI_CFG_HE_A_BQR_STADEF 0 |
| 1444 | |
| 1445 | #define WNI_CFG_HE_DUAL_BAND_STAMIN 0 |
| 1446 | #define WNI_CFG_HE_DUAL_BAND_STAMAX 1 |
| 1447 | #define WNI_CFG_HE_DUAL_BAND_STADEF 0 |
| 1448 | |
| 1449 | #define WNI_CFG_HE_CHAN_WIDTH_STAMIN 0 |
| 1450 | #define WNI_CFG_HE_CHAN_WIDTH_STAMAX 0x3F |
| 1451 | #define WNI_CFG_HE_CHAN_WIDTH_STADEF 0 |
| 1452 | |
| 1453 | #define WNI_CFG_HE_RX_PREAM_PUNC_STAMIN 0 |
| 1454 | #define WNI_CFG_HE_RX_PREAM_PUNC_STAMAX 0xF |
| 1455 | #define WNI_CFG_HE_RX_PREAM_PUNC_STADEF 0 |
| 1456 | |
| 1457 | #define WNI_CFG_HE_CLASS_OF_DEVICE_STAMIN 0 |
| 1458 | #define WNI_CFG_HE_CLASS_OF_DEVICE_STAMAX 1 |
| 1459 | #define WNI_CFG_HE_CLASS_OF_DEVICE_STADEF 0 |
| 1460 | |
| 1461 | #define WNI_CFG_HE_LDPC_STAMIN 0 |
| 1462 | #define WNI_CFG_HE_LDPC_STAMAX 1 |
| 1463 | #define WNI_CFG_HE_LDPC_STADEF 0 |
| 1464 | |
| 1465 | #define WNI_CFG_HE_LTF_PPDU_STAMIN 0 |
| 1466 | #define WNI_CFG_HE_LTF_PPDU_STAMAX 0x3 |
| 1467 | #define WNI_CFG_HE_LTF_PPDU_STADEF 0 |
| 1468 | |
| 1469 | #define WNI_CFG_HE_LTF_NDP_STAMIN 0 |
| 1470 | #define WNI_CFG_HE_LTF_NDP_STAMAX 0x3 |
| 1471 | #define WNI_CFG_HE_LTF_NDP_STADEF 0 |
| 1472 | |
| 1473 | #define WNI_CFG_HE_STBC_STAMIN 0 |
| 1474 | #define WNI_CFG_HE_STBC_STAMAX 0x3 |
| 1475 | #define WNI_CFG_HE_STBC_STADEF 0 |
| 1476 | |
| 1477 | #define WNI_CFG_HE_DOPPLER_STAMIN 0 |
| 1478 | #define WNI_CFG_HE_DOPPLER_STAMAX 0x3 |
| 1479 | #define WNI_CFG_HE_DOPPLER_STADEF 0 |
| 1480 | |
| 1481 | #define WNI_CFG_HE_UL_MUMIMO_STAMIN 0 |
| 1482 | #define WNI_CFG_HE_UL_MUMIMO_STAMAX 0x3 |
| 1483 | #define WNI_CFG_HE_UL_MUMIMO_STADEF 0 |
| 1484 | |
| 1485 | #define WNI_CFG_HE_DCM_TX_STAMIN 0 |
| 1486 | #define WNI_CFG_HE_DCM_TX_STAMAX 0x7 |
| 1487 | #define WNI_CFG_HE_DCM_TX_STADEF 0 |
| 1488 | |
| 1489 | #define WNI_CFG_HE_DCM_RX_STAMIN 0 |
| 1490 | #define WNI_CFG_HE_DCM_RX_STAMAX 0x7 |
| 1491 | #define WNI_CFG_HE_DCM_RX_STADEF 0 |
| 1492 | |
| 1493 | #define WNI_CFG_HE_MU_PPDU_STAMIN 0 |
| 1494 | #define WNI_CFG_HE_MU_PPDU_STAMAX 1 |
| 1495 | #define WNI_CFG_HE_MU_PPDU_STADEF 0 |
| 1496 | |
| 1497 | #define WNI_CFG_HE_SU_BEAMFORMER_STAMIN 0 |
| 1498 | #define WNI_CFG_HE_SU_BEAMFORMER_STAMAX 1 |
| 1499 | #define WNI_CFG_HE_SU_BEAMFORMER_STADEF 0 |
| 1500 | |
| 1501 | #define WNI_CFG_HE_SU_BEAMFORMEE_STAMIN 0 |
| 1502 | #define WNI_CFG_HE_SU_BEAMFORMEE_STAMAX 1 |
| 1503 | #define WNI_CFG_HE_SU_BEAMFORMEE_STADEF 0 |
| 1504 | |
| 1505 | #define WNI_CFG_HE_MU_BEAMFORMER_STAMIN 0 |
| 1506 | #define WNI_CFG_HE_MU_BEAMFORMER_STAMAX 1 |
| 1507 | #define WNI_CFG_HE_MU_BEAMFORMER_STADEF 0 |
| 1508 | |
| 1509 | #define WNI_CFG_HE_BFEE_STS_LT80_STAMIN 0x3 |
| 1510 | #define WNI_CFG_HE_BFEE_STS_LT80_STAMAX 0x7 |
| 1511 | #define WNI_CFG_HE_BFEE_STS_LT80_STADEF 0 |
| 1512 | |
| 1513 | #define WNI_CFG_HE_NSTS_TOT_LT80_STAMIN 0x3 |
| 1514 | #define WNI_CFG_HE_NSTS_TOT_LT80_STAMAX 0x7 |
| 1515 | #define WNI_CFG_HE_NSTS_TOT_LT80_STADEF 0 |
| 1516 | |
| 1517 | #define WNI_CFG_HE_BFEE_STS_GT80_STAMIN 0x3 |
| 1518 | #define WNI_CFG_HE_BFEE_STS_GT80_STAMAX 0x7 |
| 1519 | #define WNI_CFG_HE_BFEE_STS_GT80_STADEF 0 |
| 1520 | |
| 1521 | #define WNI_CFG_HE_NSTS_TOT_GT80_STAMIN 0x3 |
| 1522 | #define WNI_CFG_HE_NSTS_TOT_GT80_STAMAX 0x7 |
| 1523 | #define WNI_CFG_HE_NSTS_TOT_GT80_STADEF 0 |
| 1524 | |
| 1525 | #define WNI_CFG_HE_NUM_SOUND_LT80_STAMIN 0 |
| 1526 | #define WNI_CFG_HE_NUM_SOUND_LT80_STAMAX 0x7 |
| 1527 | #define WNI_CFG_HE_NUM_SOUND_LT80_STADEF 0 |
| 1528 | |
| 1529 | #define WNI_CFG_HE_NUM_SOUND_GT80_STAMIN 0 |
| 1530 | #define WNI_CFG_HE_NUM_SOUND_GT80_STAMAX 0x7 |
| 1531 | #define WNI_CFG_HE_NUM_SOUND_GT80_STADEF 0 |
| 1532 | |
| 1533 | #define WNI_CFG_HE_SU_FEED_TONE16_STAMIN 0 |
| 1534 | #define WNI_CFG_HE_SU_FEED_TONE16_STAMAX 1 |
| 1535 | #define WNI_CFG_HE_SU_FEED_TONE16_STADEF 0 |
| 1536 | |
| 1537 | #define WNI_CFG_HE_MU_FEED_TONE16_STAMIN 0 |
| 1538 | #define WNI_CFG_HE_MU_FEED_TONE16_STAMAX 1 |
| 1539 | #define WNI_CFG_HE_MU_FEED_TONE16_STADEF 0 |
| 1540 | |
| 1541 | #define WNI_CFG_HE_CODEBOOK_SU_STAMIN 0 |
| 1542 | #define WNI_CFG_HE_CODEBOOK_SU_STAMAX 1 |
| 1543 | #define WNI_CFG_HE_CODEBOOK_SU_STADEF 0 |
| 1544 | |
| 1545 | #define WNI_CFG_HE_CODEBOOK_MU_STAMIN 0 |
| 1546 | #define WNI_CFG_HE_CODEBOOK_MU_STAMAX 1 |
| 1547 | #define WNI_CFG_HE_CODEBOOK_MU_STADEF 0 |
| 1548 | |
| 1549 | #define WNI_CFG_HE_BFRM_FEED_STAMIN 0 |
| 1550 | #define WNI_CFG_HE_BFRM_FEED_STAMAX 0x7 |
| 1551 | #define WNI_CFG_HE_BFRM_FEED_STADEF 0 |
| 1552 | |
| 1553 | #define WNI_CFG_HE_ER_SU_PPDU_STAMIN 0 |
| 1554 | #define WNI_CFG_HE_ER_SU_PPDU_STAMAX 1 |
| 1555 | #define WNI_CFG_HE_ER_SU_PPDU_STADEF 0 |
| 1556 | |
| 1557 | #define WNI_CFG_HE_DL_PART_BW_STAMIN 0 |
| 1558 | #define WNI_CFG_HE_DL_PART_BW_STAMAX 1 |
| 1559 | #define WNI_CFG_HE_DL_PART_BW_STADEF 0 |
| 1560 | |
| 1561 | #define WNI_CFG_HE_PPET_PRESENT_STAMIN 0 |
| 1562 | #define WNI_CFG_HE_PPET_PRESENT_STAMAX 1 |
| 1563 | #define WNI_CFG_HE_PPET_PRESENT_STADEF 0 |
| 1564 | |
| 1565 | #define WNI_CFG_HE_SRP_STAMIN 0 |
| 1566 | #define WNI_CFG_HE_SRP_STAMAX 1 |
| 1567 | #define WNI_CFG_HE_SRP_STADEF 0 |
| 1568 | |
| 1569 | #define WNI_CFG_HE_POWER_BOOST_STAMIN 0 |
| 1570 | #define WNI_CFG_HE_POWER_BOOST_STAMAX 1 |
| 1571 | #define WNI_CFG_HE_POWER_BOOST_STADEF 0 |
| 1572 | |
| 1573 | #define WNI_CFG_HE_4x_LTF_GI_STAMIN 0 |
| 1574 | #define WNI_CFG_HE_4x_LTF_GI_STAMAX 1 |
| 1575 | #define WNI_CFG_HE_4x_LTF_GI_STADEF 0 |
| 1576 | |
| 1577 | #define WNI_CFG_HE_NSS_STAMIN 0 |
| 1578 | #define WNI_CFG_HE_NSS_STAMAX 0x7 |
| 1579 | #define WNI_CFG_HE_NSS_STADEF 0 |
| 1580 | |
| 1581 | #define WNI_CFG_HE_MCS_STAMIN 0 |
| 1582 | #define WNI_CFG_HE_MCS_STAMAX 0x7 |
| 1583 | #define WNI_CFG_HE_MCS_STADEF 0 |
| 1584 | |
Prakash Dhavali | 7090c5f | 2015-11-02 17:55:19 -0800 | [diff] [blame] | 1585 | #define CFG_STA_MAGIC_DWORD 0xbeefbeef |
| 1586 | |
| 1587 | #endif |